Shockley’s Model
Vgs = Gate to Source Voltage, V
Vds = Drain to Source Voltage, V
Vtn = Threshold Voltage, V
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Shockley’s Model
n = (n ox/tox) (W/L)
A/V2
MOS Transistor Gain Factor
n = Mobility of electrons, cm2/V-Sec
ox = Oxide Permittivity, F/cm,
tox = Oxide thickness, cm
W = Width of the transistor, microns
L = Length of the transistor, microns
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Shockley’s Model

The drain to source current of an nMOS device is
given by
Ids = 0 ; Cut-off region; Vgs<Vtn
Ids = n/2 [2(Vgs – Vtn)Vds - Vds2 ] ;
Linear Region; Vds < (Vgs – Vtn)
Ids = n/2 (Vgs – Vtn)2 ;
Saturation Region; Vds  (Vgs – Vtn);
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V-I Characteristics
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V-I Characteristics
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MOSFET Scaling
SCALING - refers to ordered reduction in dimensions of the
MOSFET and other VLSI features
Reduce
Size of VLSI chips.
Change
operational characteristics of MOSFETs and parasitic.
Physical
limits restrict degree of scaling that can be achieved.
 Constant Field Scaling
 Constant Voltage Scaling
 Lateral Scaling
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Constant Field Scaling
 The electric field E is kept constant, and the scaled device
is obtained by applying a dimensionless scale-factor a
(such that E is unchanged):

all dimensions, including those vertical to the
surface (1/a)

device voltages (1/a)

the concentration densities (a).
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Constant Voltage Scaling
 Vdd is kept constant.
 All dimensions, including those vertical to the surface
are scaled.
 Concentration densities are scaled.
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Lateral Scaling
 Only the gate length is scaled L = 1/a (gate-shrink).
 Year
Feature Size(m)
1980
5.0
1983
3.5
1985
2.5
1987
1.75
1989
1.25
1991
1.0
1993
0.8
1995
0.6
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PARAMETER
Length (L)
Width (W)
Supply Voltage (V)
Gate Oxide thickness (tox)
Junction depth (Xj)
Current (I)
Power Dissipation (P)
Electric Field
Load Capacitance (C)
Gate Delay (T)
Digital Integrated Circuits
SCALING MODEL
Constant
Field
1/a
1/a
1/a
1/a
1/a
1/a
1/a2
1
1/a
1/a
Devices
Constant
Voltage
1/a
1/a
1
1/a
1/a
a
a
a
1/a
1/a2
Lateral
1/a
1
1
1
1
a
a
1
1/a
1/a2
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MOS Capacitances
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What’s a short channel device?
Short Channel Device
Channel Length is of the same order as
Depletion region thickness.
Leff = xj
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Transistor in Saturation
VGS
V DS > VGS - V T
G
D
S
n+
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-
VGS - VT
Devices
+
n+
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Case 3: VG positive and larger than a certain
threshold voltage.
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NMOS Structure





P-type substrate (“Bulk”, “Body”)
D and S heavily doped (n+) n-regions
Gate is heavily doped polysilicon (amorphous non-crystal)
Thin layer of SiO2 to insulate Gate from Substrate
A p+ region at the Silicon-Dioxide/Substrate interface (to create a
positive threshold voltage)
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Gate Dimensions


L = Length
W = Width
During fabrication S and D
“side diffuse”: Actual L is
slightly less than the drawn
layout L.
» LD = Amount of side
diffusion
» LDrawn = Layout intention of L
» Leff = Effective Length
» Then: Leff = LDrawn - 2 LD

We shall use L but
we’ll always mean
Leff
Typically W>>L so we shall
not mention Weff
Gate Oxide thickness = tox
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Technology Trends

The principal thrust in MOS technology is to reduce
both L and tox

Typical values (as of Year 2000):
L eff  0 . 15  m
t ox  5 nm
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CMOS



PMOS fabricated in a “local substrate” called “well”
All NMOS devices on a chip share the same
substrate
Each PMOS device on a chip has an independent nwell
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MOS Symbols



Symbols (a) are the most general, allowing B to be
connected anywhere.
Symbols (b) will be used most frequently: Whenever
B of NMOS is tied to GND, or B of PMOS is tied to
VDD
Symbols (c) used in digital circuits.
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Saturation Mode
iD 
Digital Integrated Circuits
1
2
(  n C ox )
W
L
Devices
( v GS  V TH )
2
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Digital Integrated Circuits
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MOS Capacitances
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Cross-Section of CMOS
Technology
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MOS transistors
Types and Symbols
D
D
G
G
S
S
NMOS Enhancement NMOS Depletion
D
D
G
G
S
S
PMOS Enhancement
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B
Devices
NMOS with
Bulk Contact
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MOS Structure –
p substrate
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MOS Structure – n
substrate
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