Pei-Ci Wu
Martin D. F. Wong
DAC’14

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Introduction
Preliminaries
Linear Programming Based
Optimization
Bottom-up Buffer Insertion
Experimental Results
Concluding Remarks

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Timing closure, which is to satisfy the timing constraints, is a key problem in the physical design
Setup (long-path) constraints
 ensure that the signal transitions do not arrive too late hold-time (short-path) constraints
 ensure that the signal transitions do not arrive too early

 Typically, hold violations are addressed after setup optimization has been performed.
 Discrete cell sizes (i.e. discrete buffer sizes for hold optimization) in modern industrial designs

 Cell libraries specified for the setup constraints and the hold-time constraints are usually different in modern industrial designs

 Negative setup slacks and negative hold slacks indicate setup violations and hold violations

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TNS
 the absolute value of the total negative setup slacks of all the pins in PO
THS
 the absolute value of the total negative hold slacks of all the pins in PO
TNS must not be worsen during holdviolation removal

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Given:
 a design and a buffer library, find a buffering solution such that:
 THS and the cost of buffering (i.e. area and power consumption) are both minimized while
TNS is not worsen.

 Inserting delay into wires to remove hold violations
 A linear programming formulation
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Extend such formulation for the complex timing constraints
Graph-reduction approach

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Input
 Combinational circuit C* s.t. for any pin p of C* , hold_slack p
< 0 and setup_slack p
> 0
C* can then be represented as a directed acyclic graph G(V,E)
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V is the pins of C*
( i, j )
∈ E represents an edge

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I : the zero in-degree pins
O : the zero out-degree pins for each pin i in V
 three real-value variables, x i
(delays inserted at pin i for hold-time constraints), ha i
, and sa i

 Hold-time constraints

 For buffer library characterization is necessary in order to get an empirical ratio such that
 we assume that the buffer only affects the driver cell and the sink cells of the buffer

 Delays introduced by inserting the buffer is
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(a)
(b)

 Setup constraints
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 Objective :
 The setup constraints limit the delays that can be inserted
 r i is only necessary when there is no feasible solution

 Some pins with positive setup slacks and positive hold slacks that are not included

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Given:
 a pin i , hold delay D
H and setup delay D
S
Find a buffering solution at pin i from a buffer library B:
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 hold delays introduced by the chosen buffers are as close to D
H setup delays introduced by the chosen buffers are not larger than D
S
Minimize the area of the chosen buffers

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DP based algorithm
A set of buffering candidates C(L, d h
, d s
, A) is kept during the process
For each buffer in B, we insert it to any of the existing candidates

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New buffering candidates
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(1) if d′ s
> D
S
, C′ is removed immediately
(2) if d′ h
<= d h
, C′ is removed as well
 d′ h
> D
H
+ margin where margin is a parameter, then C′ is removed too
(3) C′ is dominated by any existing candidate
C*(I*, d* h
, d* s
, A*) if d′ h
< d* h and A′ > A*
Chose the candidate that has the largest ratio of d h
/A as the buffering solution

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Bottom-up Methodology
 process the pins by the bottom-up topological ordering (i.e. from PO to PI)
DP algorithm cannot realize the exact amount of hold delays/setup delays by inserting buffers(extra delays)

 Suppose now we are processing pin p , collected extra delays
 cur_setup_req p
= setup_req p
− ds_delay
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 extra delays = cur_setup_req p
– sa p
D s
= x p
+ cur_setup_req p
− sa p
 Similarly to get D h

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First propose a linear programming based approach that minimizes the number of inserted delays
A bottom-up buffer insertion and the flow of optimizing are presented