Chapter 1
An Introduction to Processor
Design
부산대학교
컴퓨터공학과
1.1 Processor Architecture &
Organization

All modern general-purpose computers employ
“stored program concept”
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IAS computer by von Neumann at Princeton Institute
for Advanced Studies (in 1946)
First implemented in ‘Baby Machine’ at Univ. of
Manchester, England (in 1948)
[Figure 1.1] The state in a stored-program digital
computer
FF.. FF16
ins truc tions
regis ters
addres s
dat a
processor
ins truc tions
and data
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memory
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1.1 Processor Architecture &
Organization

50 years of development:
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performance of processors h
cost i
 cost-effective computers (principles of operation not
changed much)
Most of improvements:
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Advances in technology of electronics
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New insights:
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Vacuum tubes -> transistors -> ICs -> VLSI
Virtual memory (early 1960s)
Cache memory
Pipelining
RISC
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1.2 Abstraction in Hardware Design
Transistors (elementary component)
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Logically act as inverters
Logic gates
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CMOS NAND gate (using 4 trs)
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If A = B = Vdd, output = Vss
If either A or B (or both) = Vss, output =Vdd
=> output = not(A.B)
Transistor circuit, logic symbol, truth table
Vdd
A
A.B
A
B
out put
A
B
Output
0
0
1
0
1
1
1
0
1
1
1
0
B
Vss
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Logic sy mbol
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Truth table
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1.2 Abstraction in Hardware Design

The gate abstraction
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Simplify the process of designing circuits with great number of trs
Removes the need to know that the gate is built from trs
Free from implementation technology in function level
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Eg. Field effect tr, bipolar tr, etc.
However, performance difference exists
Levels of abstraction
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Trs
Gates, memory cells
Adder, MUX, decoder, registers
ALUs, shifters, memory blocks
Processors, peripherals, memories
ICs
PCBs
PCs, controllers, mobile phones
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1.3 MU0 – a simple processor

A simple form of processor can be built from a few
basic components
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PC (program counter)
ACC (accumulator)
ALU (arithmetic-logic unit)
IR (instruction register)
Instruction decoder, control logic
The MU0 instruction set
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A 16-bit machine with a 12-bit address space (4K x 2 bytes:
8K bytes memory)
Instructions: 16 bits long (op: 4 bits, address field: 12 bits)
4 bits
opcode
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12 bits
S
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1.3 MU0 – a simple processor

[Table 1.1] The MU0 instruction set
Instruction
Opcode
Effect
LDA S
0000
ACC := mem 16[S]
STO S
0001
mem 16[S] := ACC
ADD S
0010
ACC := ACC + mem 16[S]
SUB S
0011
ACC := ACC - mem 16[S]
JMP S
0100
PC := S
JGE S
0101
if ACC >= 0 PC := S
JNE S
0110
if ACC !=0 PC := S
STP
0111
stop
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1.3 MU0 – a simple processor

Datapath
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A register transfer level (RTL) design style based on
registers, MUXs, and so on
[Figure 1.5] MU0 datapath example
address bus
PC
control
IR
memory
ALU
ACC
data bus
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RTL level design
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[Figure 1.6] MU0 register transfer level organization
Control signals:
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enables on all of regs
function select lines to ALU
select control lines for two MUXs
control for a tri-state driver
to send ACC value to memory
MEMrq (memory request)
RnW (read/write control lines)
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1.4 Instruction set design
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To build a high-performance processor (beyond MU0
inst. set), inst. set design is important.
4 address insts (the most general form)
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Ex) add d, s1, s2, next_i; d := s1 + s2
f bits
n bits
f unc tion op 1 addr.
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n bits
op 2 addr.
n bits
n bits
des t. addr. nex t_i addr.
3 address insts
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Make address of the next inst. implicit using PC (except for
branch)
Ex) add d, s1, s2; d := s1 + s2
f bits
n bits
f unction op 1 addr.
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n bits
op 2 addr.
n bits
dest. addr.
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1.4 Instruction set design
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2 address insts
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Make destination reg. the same as one of source reg.
Ex) add d, s1; d := d + s1
f bits
n bits
f unct ion op 1 addr.

n bits
des t. addr.
1 address insts
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AC is used as destination
Ex) add s1; AC := AC + s1
f bits
n bits
f unction op 1 addr.
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0 address insts (using a stack)
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Ex) add; tos := tos + next on stack
f bits
f unc tion
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1.4 Instruction set design
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Addressing modes
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Immediate addressing: immediate data
Absolute addressing: inst. contains full address for data
Indirect addressing: inst. contains address of location that
contains address of data
Register addressing: data is in a reg.
Register indirect addressing
Index addressing
Stack addressing
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1.4 Instruction set design
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Control flow instructions
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Subroutine calls & returns
System calls
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Branch, jump
Conditional branch
Branch to an operating system routine
Exceptions
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Error handling
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1.5 Processor design trade-offs
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CISC vs RISC
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CISC
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To reduce semantic gap b/w high level language & machine
instruction
Complex sequence of operations
Make compiler’s job easy
RISC
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ARM’s middle name: from RISC
Reducing semantic gap is not the right way to make an efficient
computer
[Table 1.3] Typical dynamic instruction usage
Instruction type
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Dynamic usage
Data movement
Control flow
43%
23%
Arithmetic operations
15%
Comparisons
13%
Logical operations
5%
Other
1%
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1.5 Processor design trade-offs
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Data movement b/w regs and memory:
almost half
Control flow such as branches & procedure
calls: almost quarter
Arithmetic operations: only 15%
 Complex arithmetic insts do not help much
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The most important tech: pipelining, cache
memory
 To make processors go faster
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1.5 Processor design trade-offs
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Pipelines
1.
2.
3.
4.
5.
6.
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Fetch
Decode
REG: get operands from register bank
ALU
MEM: access memory for an operand, if necessary
RES: write result back to register bank
[Figure 1.13] Pipelined instruction execution
1
f et ch dec
2
3
instruction
reg
f et ch dec
ALU mem res
reg
f et ch dec
ALU mem res
reg
ALU mem res
time
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1.5 Processor design trade-offs
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Pipeline hazards
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Read after write hazard (data hazard)
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1
Result from one inst is used as an operand by the next inst =>
inst2 must stall until the result is available
[Figure 1.14] Read-after-write pipeline hazard
f etch dec
2
reg ALU mem res
f etch dec
stall
reg ALU mem res
instruction
time
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1.5 Processor design trade-offs
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Branch hazard
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Solution:
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Compute branch target earlier (if possible)
The target may be computed speculatively
Delayed branch
[Figure 1.15] Pipelined branch behavior
1 (branch) f et ch dec
2
reg
f et ch dec
3
ALU mem res
reg
f et ch dec
4
5 (br anch tar get)
ALU mem res
reg
f et ch dec
ALU mem res
reg
f et ch dec
ALU mem res
reg
ALU mem res
instruction
time
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Pipeline efficiency
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The deeper the pipeline, the worse the problems get: RISC approach is
better
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1.6 RISC
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In 1980, Patterson: RISCI project
RISCI arch
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Fixed (32-bit) inst size with few formats
Load-store arch:
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RISCI organization
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Insts that process data operate only on regs
Separate insts to access memory
A large register bank (32 32-bit regs) to allow load-store arch to
operate efficiently
Hard-wired inst decode logic
Pipelined execution
Single cycle execution
RISCI advantages
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A smaller die size
A shorter development time
A higher performance (controversial)
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