ECE 2560 - Lecture 04 The Instruction Set

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ECE 2560
The MSP430 Instruction Set
Department of Electrical and
Computer Engineering
The Ohio State University
ECE 3561 - Lecture 1
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The MSP 430 Instruction Set
What is an Instruction Set
 The MSP 430 Instruction Set
 Instruction Formats
 Assemblers
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ECE 3561 - Lecture 1
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Assembly Language
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Assembler Language Instructions
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The core instruction set of a processor
Allow programming in pneumonics and symbols versus direct
machine language.
Assembler language instruction
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Machine language instruction
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MOV R4,R3
$9A42
1 Assembler Instr  1 Machine Instr
A machine instruction specifies exactly what functions will
be taken by the processor.
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Example – move the contents of R1 to R2
Decoded and causes generation of control signals that cause
the movement of data
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The MSP430 Instruction Set
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Consists of 27 core instructions and 24
emulated instructions.
Core instructions have unique op-codes
Emulated instructions – instructions made
easier to write and read. When assembled
they are replaced by the assembler with an
equivalent core instruction.
Note: There is no code or performance
penalty for using emulated instructions.
See manual for instructions
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What is an assembler?
It is a software program that has, as
input, assembler language code and
produces, as output, the machine
language for a specific processor, i.e.,
the binary coding of instrcutions.
 Typically assemblers work with a group
of processor targets in the same family.
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Core Instruction Formats
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Single operand
Dual operand
Jump
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Single and dual operand instructions can be byte or
word instructions by using the .B or .W extension.
 Byte instructions – used for byte data or byte
peripherals
 Word instructions – used for word data or word
peripherals
 No .B or .W ? – defaults to a word instruction
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Notation
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In instruction description
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src – The source operand – As and S-reg
dst – The destination operand – Ad and D-reg
As – The addressing bits responsible for the
addressing mode used for the source
S-reg – The register used for the source
Ad – The addressing bits used for the destination
D-reg – The register used for the destination
Note on destination

Destination addresses can be anywhere in the
memory map, but they must be writeable to be
effective.
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Double Operand Instructions

The format of the two operand instruction
is
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The fields are almost self explanatory
The assembler language instruction
looks like
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MOV src,dst
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Single Operand Instruction

The format of the single operand
instruction is

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Again, the fields are self explanatory
Example

SXT dst
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Jump Instruction

The format of jump instructions is
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Modifies the Program Counter, PC, to alter
control flow.
 Example
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JNE label
label represents an address
Action is to transfer execution to label if zero bit of
condition code register set. Otherwise execution
continues with the next instruction.
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The Program Counter
The Program Counter always points to
the memory location of the next
instruction word to be fetched.
 Instructions are 1 to 3 words in length.
 As the PC points to words, the lsb is
always 0.

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The instruction set
The full instruction
set is shown to the
right.
 How to learn
instruction set?

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Break down into
groups
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Data movement

The MOV instruction
Moves data to and from memory (or an I/O
port) to a destination.
 The source can use any addressing mode
 The destination can use any addressing
mode.
 Addressing modes
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Register, immediate, absolute, indexed,
symbolic, indirect register, indirect
autoincrement
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The MOV instruction

Examples of the move instruction
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Load a specific value into a register
src – use immediate mode
 dst – use register mode
 MOV #024h,R9
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MOV #6511h,R2
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Set the contents of R9 to $0024
Set the contents of R2 to $6511
MOV(.B) is the only instruction for
movement of data
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Arithmetic instructions

ADC dst Add C to destination
ADD src,dst Add source to destination
ADDC src,dst Add source and C to destination
DADC dst Add C to decimally to dst
DADD src,dst Add src and C decimally to dst
DEC dst Decrement destination
DECD dst Double-decrement destination
INC dst Increment destination
INCD dst Double-increment destination
SUB src,dst Subtract source from destination
SUBC src,dst Subtract source and not(C) from dst
SBC dst Subtract not(C) from destination
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All have .B mode for byte data
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Logical Instructions
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AND src,dst Logical AND source and destination
INV dst Logical invert destination
RLA dst Rotate left arithmetically
RLC dst Rotate left through C
RRA dst Rotate right arithmetically
RRC dst Rotate right through C
XOR src,dst Exclusive OR source and destination
CLR dst Clear the destination to 0’s
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ALL ABOVE HAVE .B to operate on byte data
SWPB dst Swap bytes
SXT dst Sign extend low byte through high byte
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Compare and Test
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CMP(.B) src,dst Compare source and destination
TST(.B) dst Test destination
BIT(.B) src,dst src and dst are logically ANDed

N is msb, Z set if 0, C is NOT Z, V reset
These instructions do not modify the
contents of src or dst.
 They do however, set the bits of the
condition code register (CC)
 Used to set bits for branching
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Set and clear bits
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Masked set and clear - data
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BIC(.B) src,dst Clear bits in destination
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BIS(.B) src,dst Set bits in destination
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Result: NOT.src AND dst -> dst
Result: src OR dst -> dst
Set and clear bits of CC register
CLRC Clear C
 CLRN Clear N
 CLRZ
Clear Z
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SETC Set C
SETN Set N
SETZ Set Z
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Transfer of control flow
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Normal operation has the next instruction in memory executed
next (PC+2 or 3)
Control flow instructions can modify were the next instruction is
fetched from.
The Jump instructions (conditional)
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JC/JHS label Jump if C set/Jump if higher or same
JEQ/JZ label Jump if equal/Jump if Z set
JGE label Jump if greater or equal
JL
label Jump if less
JN label Jump is N set
JNC/JLO label Jump if C not set/Jump if lower
JNE/JNZ label Jump if not equal/Jump if Z not set
Unconditional
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JMP label
BR dst
This is an unconditional jump ( (label)->PC )
Branch to destination (dst-> PC)
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Subroutine support
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Support for subroutine instrcutions
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CALL dst
Call destintion
ACTION:
 SP-2 -> SP,
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RET
PC+2-> @SP,
dst->PC
Return from subroutine
ACTION:
 @SP-> PC, SP+2 -> SP
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Stacks

The stack –
an area of
memory for
storage of
data
accessed
through the
PUSH and
POP
instructions
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StacK instructions
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Two instructions
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PUSH(.B) src Push the source onto stack
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Action is SP-2-> SP
POP(.B) dst
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src->@SP
Pop item from stack to destination
Action is @SP-> dst
SP+2 -> SP
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Convention is that the stack grows down in
memory
 The MSP430s : SP points to TOS and valid data

NOTE: in some processor chips (microcontrollers
and processors) the SP points to a free location
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ACTIONS to push and pop?
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Interrupts
A pin on the MSP430 is the NonMaskable Interrupt (NMI) input pin.
 Interrupts allow an external device to call
for attention.
 The current instruction is completed and
then the device is “serviced”.
 There are 3 instructions for managing
this pin.
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Interrupt instructions
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Permitting and not permitting interrupts
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EINT
DINT
Enable interrupts
Disable interrupts
When an interrupt occurs, control flow is
automatically transferred to the program
that will deal with it. But first the PC and
status register are pushed to the Stack.
How to get back to where your program
was at the time the interrupt occurred?
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RETI
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Return from interrupt
Will pop the status register and PC from the Stack.
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The last instruction
The final instruction in the instruction set
is
 NOP
No Operation
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Summary - Assignment

The MSP 430 Users Guide has been added to the
course webpage.
 The information in this lecture is a summary of the
information of Table 3-17.
 Next – Using CCS for assembler language
programming. If you want to get a jump on this you
can watch Dr. Khan’s 2560 screencast 07 and 08.

Quiz – see web page
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Will cover some initial aspects of instruction
Example: Write the assembler instruction that will copy
the contents of R4 to R8.
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