Machine Structures
Lecture 27 – Virtual Memory II
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L27 Virtual Memory II (1)
Another View of the Memory Hierarchy
Thus far
{
{
Next:
Virtual
Memory
Regs
Instr. Operands
Cache
Blocks
Faster
L2 Cache
Blocks
Memory
Pages
Disk
Files
Tape
L27 Virtual Memory II (2)
Upper Level
Larger
Lower Level
Review
• Manage memory to disk? Treat as cache
• Included protection as bonus, now critical
• Use Page Table of mappings for each
process vs. tag/data in cache
• TLB is cache of VirtualPhysical addr trans
• Virtual Memory allows protected sharing
of memory between processes
• Spatial Locality means Working Set of
Pages is all that must be in memory for
process to run fairly well
L27 Virtual Memory II (3)
Translation Look-Aside Buffers (TLBs)
•TLBs usually small, typically 128 - 256 entries
• Like any other cache, the TLB can be direct
mapped, set associative, or fully associative
VA
Processor
hit
TLB
Lookup
miss
Page
Table
PA
Cache miss
hit
Main
Memory
data
On TLB miss, get page table entry from main memory
L27 Virtual Memory II (4)
Address Mapping: Page Table
Virtual Address:
page no. offset
Page Table
Base Reg
index
into
page
table
Page Table
...
V
A.R. P. P. A.
+
Val Access Physical
-id Rights Page
Address Physical
Memory
Address
.
...
Page Table located in physical memory
L27 Virtual Memory II (5)
Address Translation
Virtual Address
VPN
INDEX
Offset
TLB
...
V. P. N.
Virtual
Page
Number
V. P. N.
Data Cache
Tag Data
Tag Data
L27 Virtual Memory II (6)
P. P. N.
Physical
Page
Number
P. P. N.
PPN
Offset
Physical Address
TAG
INDEX Offset
Typical TLB Format
Virtual Physical Dirty Ref Valid Access
Address Address
Rights
• TLB 是 page table映射的Cache
• TLB 访问时间同cache可比 (比内存访问时间要少很
多)
• Dirty: 由于使用write back, 需要知道当替换时，是否
要把页写到磁盘上
•Ref: 用于在替换时，帮助计算LRU
• 由OS定期清除, 然后再检查页是否被referenced
L27 Virtual Memory II (7)
What if not in TLB?
• Option 1: 硬件检查page table，并把新
的 Page Table Entry装入TLB
• Option 2: 硬件激发OS,由 OS决定做什么
• MIPS follows Option 2: Hardware knows
nothing about page table
L27 Virtual Memory II (8)
What if the data is on disk?
• 从磁盘中将页装入内存的空余块, 使用
DMA传送(Direct Memory Access – 特别
的硬件用于支持不用处理器的传送)
• 其间会切换到其他等待运行的进程
• 当DMA完成时, 得到一个中断(interrupt)
此时进程page table已经更新
• 因此当切换回本任务时, 所需的数据已经在内
存中
L27 Virtual Memory II (9)
What if we don’t have enough memory?
• 选定属于某个程序的其他页，如果该页是
dirty的，将该页复制到硬盘
• 如果是干净的 (磁盘中的备份是最新的),直接
覆盖内存中的数据
• 选择剔除的页面遵循一定更新策略 (如, LRU)
• 更新该程序的page table，以反映其内存
数据已经移到其他某个地方
• 如果不断在磁盘和内存中进行交换, 称为
Thrashing（翻来覆去）
L27 Virtual Memory II (10)
We’re done with new material
Let’s now review w/Questions
L27 Virtual Memory II (11)
Question (1/3)
• 40-bit virtual address, 16 KB page
Virtual Page Number (? bits)
Page Offset (? bits)
• 36-bit physical address
Physical Page Number (? bits)
Page Offset (? bits)
• Number of bits in Virtual Page Number/ Page
offset, Physical Page Number/Page offset?
1:
2:
3:
4:
5:
22/18 (VPN/PO), 22/14 (PPN/PO)
24/16, 20/16
26/14, 22/14
26/14, 26/10
28/12, 24/12
L27 Virtual Memory II (12)
(1/3) Answer
• 40- bit virtual address, 16 KB (214 B)
Virtual Page Number (26 bits)
Page Offset (14 bits)
• 36- bit virtual address, 16 KB (214 B)
Physical Page Number (22 bits)
Page Offset (14 bits)
• Number of bits in Virtual Page Number/ Page
offset, Physical Page Number/Page offset?
1:
2:
3:
4:
5:
22/18 (VPN/PO), 22/14 (PPN/PO)
24/16, 20/16
26/14, 22/14
26/14, 26/10
28/12, 24/12
L27 Virtual Memory II (13)
Question (2/3): 40b VA, 36b PA
• 2-way set-assoc. TLB, 512 entries, 40b VA:
TLB Tag (? bits)
TLB Index (? bits)
Page Offset (14 bits)
• TLB Entry: Valid bit, Dirty bit,
Access Control (say 2 bits),
Virtual Page Number, Physical Page Number
V D Access (2 bits)
TLB Tag (? bits)
Physical Page No. (? bits)
• Number of bits in TLB Tag / Index / Entry?
1:
2:
3:
4:
12 / 14 / 38 (TLB Tag / Index / Entry)
14 / 12 / 40
18 / 8 / 44
18 / 8 / 58
L27 Virtual Memory II (14)
(2/3) Answer
• 2-way set-assoc data cache, 256 (28) “sets”, 2
TLB entries per set => 8 bit index
TLB Tag (18 bits)
TLB Index (8 bits)
Page Offset (14 bits)
Virtual Page Number (26 bits)
• TLB Entry: Valid bit, Dirty bit,
Access Control (2 bits),
Virtual Page Number, Physical Page Number
V D Access (2 bits)
1:
2:
3:
4:
TLB Tag (18 bits) Physical Page No. (22 bits)
12 / 14 / 38 (TLB Tag / Index / Entry)
14 / 12 / 40
18 / 8 / 44
18 / 8 / 58
L27 Virtual Memory II (15)
Question (3/3)
• 2-way set-assoc, 64KB data cache, 64B block
Cache Tag (? bits) Cache Index (? bits)
Block Offset (? bits)
Physical Page Address (36 bits)
• Data Cache Entry: Valid bit, Dirty bit, Cache
tag + ? bits of Data
V D
Cache Tag (? bits)
Cache Data (? bits)
• Number of bits in Data cache Tag / Index /
Offset / Entry?
1:
2:
3:
4:
5:
12 / 9 / 14 / 87 (Tag/Index/Offset/Entry)
20 / 10 / 6 / 86
20 / 10 / 6 / 534
21 / 9 / 6 / 87
21 / 9 / 6 / 535
L27 Virtual Memory II (16)
(3/3) Answer
• 2-way set-assoc data cache, 64K/1K (210)
“sets”, 2 entries per sets => 9 bit index
Cache Tag (21 bits) Cache Index (9 bits)
Block Offset (6 bits)
Physical Page Address (36 bits)
• Data Cache Entry: Valid bit, Dirty bit, Cache
tag + 64 Bytes of Data
V D
1:
2:
3:
4:
5:
Cache Tag (21 bits)
Cache Data (64 Bytes =
512 bits)
12 / 9 / 14 / 87 (Tag/Index/Offset/Entry)
20 / 10 / 6 / 86
20 / 10 / 6 / 534
21 / 9 / 6 / 87
21 / 9 / 6 / 535
L27 Virtual Memory II (17)
4 Qs for any Memory Hierarchy
• Q1: Where can a block be placed?
• One place (direct mapped)
• A few places (set associative)
• Any place (fully associative)
• Q2: How is a block found?
•
•
•
•
Indexing (as in a direct-mapped cache)
Limited search (as in a set-associative cache)
Full search (as in a fully associative cache)
Separate lookup table (as in a page table)
• Q3: Which block is replaced on a miss?
• Least recently used (LRU)
• Random
• Q4: How are writes handled?
• Write through (Level never inconsistent w/lower)
• Write back (Could be “dirty”, must have dirty bit)
L27 Virtual Memory II (18)
Q1: Where block placed in upper level?
• Block #12 placed in 8 block cache:
• Fully associative
• Direct mapped
• 2-way set associative
 Set Associative Mapping = Block # Mod # of Sets
Block
no.
01234567
Fully associative:
block 12 can go
anywhere
L27 Virtual Memory II (19)
Block
no.
01234567
Direct mapped:
block 12 can go
only into block 4
(12 mod 8)
Block
no.
01234567
Set Set Set Set
0 1 2 3
Set associative:
block 12 can go
anywhere in set 0
(12 mod 4)
Q2: How is a block found in upper level?
Block Address
Tag
Block
offset
Index
Set Select
Data Select
• Direct indexing (using index and block
offset), tag compares, or combination
• Increasing associativity shrinks index,
expands tag
L27 Virtual Memory II (20)
Q3: Which block replaced on a miss?
•Easy for Direct Mapped
•Set Associative or Fully Associative:
• Random
• LRU (Least Recently Used)
Miss Rates
Associativity:2-way
4-way
Size
LRU Ran LRU
16 KB
64 KB
8-way
Ran
LRU
Ran
5.2% 5.7%
4.7% 5.3%
4.4%
5.0%
1.9% 2.0%
1.5% 1.7%
1.4%
1.5%
256 KB 1.15% 1.17% 1.13% 1.13% 1.12% 1.12%
L27 Virtual Memory II (21)
Q4: What to do on a write hit?
• Write-through
• update the word in cache block and
corresponding word in memory
• Write-back
• update word in cache block
• allow memory word to be “stale”
=> add ‘dirty’ bit to each line indicating that
memory be updated when block is replaced
=> OS flushes cache before I/O !!!
• Performance trade-offs?
• WT: read misses cannot result in writes
• WB: no writes of repeated writes
L27 Virtual Memory II (22)
Three Advantages of Virtual Memory
1) 变换:
• 程序在内存中看起来是连续的, 即使物理内存是杂
乱的
• 使多进程成为可能
• 只有程序最重要的部分 (“工作集Working Set”) 必
须驻留在物理内存中
• 连续数据结构(如栈)需要多少使用多少，当然后来
会逐渐增加
L27 Virtual Memory II (23)
Three Advantages of Virtual Memory
2) 保护:
• 不同进程互不干扰
• 不同的页可以有自己专门的特性
 (只读, 用户程序看不见等).
• 用户程序看不见核数据（Kernel data）
• 可以免受“邪恶”程序的侵害  Far more
“viruses” under Microsoft Windows
• 进程的特殊模式 (“Kernel mode”) 允许进程改变
page table/TLB
3) 共享:
• 可以将同一物理页映射给多个用户(“共享内存”)
L27 Virtual Memory II (24)
Why Translation Lookaside Buffer (TLB)?
• 分页是最著名的虚拟内存实现(另一方式是
base/bounds)
• 每个分页的虚拟内存访问都必须通过在内
存中的Page Table行来进行检查和访问，
从而提供了保护/ indirection
• Page Table Entries (TLB)的Cache使得
不通过内存访问就能进行地址变换，从而
在多数情况下加速了该过程
L27 Virtual Memory II (25)
And in Conclusion…
• Virtual memory to Physical Memory
Translation too slow?
• Add a cache of Virtual to Physical Address
Translations, called a TLB
• Spatial Locality means Working Set of
Pages is all that must be in memory for
process to run fairly well
• Virtual Memory allows protected
sharing of memory between processes
with less swapping to disk
L27 Virtual Memory II (26)