Institute for Applied Microelectronics
IUMA - ULPGC
Universidad de Las Palmas de Gran Canaria
Programa de doctorado Sistemas Inteligentes y
Aplicaciones Numéricas en Ingeniería
System Level Design Space Exploration for MPSoC:
Methods, Algorithms and New Infrastructure
European Doctorate
Institute for Applied Microelectronics (IUMA)
PhD student:
Zai Jian Jia Li
Supervisors:
Prof. Antonio Núñez
Assist. prof. Tomás Bautista
Las Palmas de Gran Canaria, January 25, 2011
Institute for Applied Microelectronics
IUMA - ULPGC
OUTLINE
• Introduction and context
• Motivation, challenges and goals
• Approaches and contributions
• Results
• Conclusions and future work
2
INTRODUCTION
Institute for Applied Microelectronics
IUMA - ULPGC
• Systems-on-Chip design challenges
– The continuous technology progress is leading to a major
capacity of integration on chip.
– System composted of a big number and variety of
components: processing elements (PEs), network elements
(NEs), storages elements (SEs); I/O devices…
– As a result, this Increasing level of integration is leading to
more complex embedded Systems-on-Chip (SoC).
– This issue also represents several challenges for the
system designers.
3
INTRODUCTION
Institute for Applied Microelectronics
IUMA - ULPGC
• Challenges (I)
 Heterogeneous architectural components: SoC
composed of multiple and different types of PEs, SEs,
NEs… Example: Multiprocessor System-on-Chip (MPSoC).
=> Flexible and reusable platform for a family of product
and easily modified for the market needs.
 Exploration of a large number of design decisions:
designers have to make decisions about a large amount of
design decisions or design options. Example: number and
types, mapping, architectural topology, HW/SW partition,
allocation of the components in the architecture…
=> The more flexible and complex the platform is, the larger
number of design options should be taken into account.
4
INTRODUCTION
Institute for Applied Microelectronics
IUMA - ULPGC
• Challenges (II)
 Multiple design constraints: in addition to the huge number
of design decisions that should be explored, designers also
have to take into account many design objectives. Example:
performance, cost/area, power consumptions…
=> Optimal solution inside the design space that satisfy the
design constraints: efficiency and without over-dimensioning.
 New techniques and generic framework: to assist to
designers in the exploration and design process. We would
need flexible and reusable approaches, without resorting to
ad-hoc strategies designed for particular cases.
=> Strategies to carry out the design process in a time
efficient way, as well as to reduce significantly the effort of
designers.
5
INTRODUCTION
Institute for Applied Microelectronics
IUMA - ULPGC
• System level design (SLD)
– SLD has been proposed as a complement to the traditional
design methods at Register Transfer Level (RTL), as well
as to improve the productivity of system designers.
– Essential difference between SLD and RTL: SLD works at a
higher abstraction level => elements with a higher
granularity level and less implementation details.
– Working at a higher abstraction level implies to trade off
certain accuracy with respect to RTL design.
– System level design indeed presents important benefits to
the system designers.
6
INTRODUCTION
Institute for Applied Microelectronics
IUMA - ULPGC
• Some benefits of System level design
 Simplify significantly the design effort: new design or
modification of a previous design can be obtained in an
easier way than if using a lower abstraction level.
 Speed up the simulation time: as consequence of
working with less implementation details, system level
simulations can run 2 and 3 orders of magnitude faster than
RTL simulations => rapid exploration of large number of
design points or design solutions.
 Making decisions at an earlier stage of design process:
allow designers to have a clear overview and the impacts of
different design decisions on system behaviours => without
building or developing a full-detailed system design.
7
Institute for Applied Microelectronics
IUMA - ULPGC
OUTLINE
 Introduction and context
• Motivation, challenges and goals
• Approaches and contributions
• Results
• Conclusions and future work
8
MOTIVATION AND GOALS
Institute for Applied Microelectronics
IUMA - ULPGC
Context of this work: Design Space Exploration at System Level.
Design space
dimension 3
Design point C
Design space
Dd3 B
Design point B
Dd3 A
Design point A
Dd2 A
Dd2 B
Design space
dimension 2
Dd1 B
Dd1 A
Design point D
Design point E
Design space
dimension 1
9
MOTIVATION AND GOALS
Institute for Applied Microelectronics
IUMA - ULPGC
Context of this work: Design Space Exploration at System Level.
Design space
dimension 3
Design objective 1
Design point C
Design space
Dd3 B
Design point B
Solution(s) or
candidate
solution(s)
Dd3 A
Design objective 3
Design point A
Dd2 A
Dd2 B
Design space
dimension 2
Dd1 B
Dd1 A
Design point D
Design point E
Design space
dimension 1
Design objective 2
10
Institute for Applied Microelectronics
IUMA - ULPGC
MOTIVATION AND GOALS
• Design Space Exploration (DSE) for
MPSoC at System level
 System-level DSE for MPSoC often can be seen as a
multiobjective optimization design problem.
 The more design options, the larger the resulting design
space is => and the more effort and time is needed to carry
out the DSE.
• Components of the DSE process
Search methods, evaluation techniques and generator of
system design description.
11
MOTIVATION AND GOALS
Institute for Applied Microelectronics
IUMA - ULPGC
Components of system-level DSE process
• The search method is used to travel
systematically through the design space.
Search
method
Design
space
• Goal: identify and select design points
(from the design space) that are analyzed
further by the evaluation techniques.
• Different strategies: exhaustive search,
random sampling, incorporating
knowledge of design space (e.g., genetic
algorithms), heuristic-based algorithms…
12
MOTIVATION AND GOALS
Institute for Applied Microelectronics
IUMA - ULPGC
Components of system-level DSE process
• Evaluation technique assess the quality of each design
point selected by the search method.
• The quality of solutions is measured in terms of different
system metrics: packets/data processed per second,
system traffic, number of each type of components actually
used in the architecture…
• The search method is used to travel
systematically
•System-level simulation and analytical methods
(formal through the design space.
rules, mathematical formulations…)
Search
method
• Goal: identify and select design points
Evaluation
(from the design space) that are analyzed
technique
further by the evaluation techniques.
System
•metrics
Different strategies: exhaustive search,
Design
space
power,
random sampling, Performace,
incorporating
cost…
knowledge of design space (e.g., genetic
algorithms), heuristic-based algorithms…
13
MOTIVATION AND GOALS
Institute for Applied Microelectronics
IUMA - ULPGC
Components of system-level DSE process
• Evaluation technique assess the quality of each design
point selected by the search method.
• The quality of solutions is measured in terms of different
system metrics: packets/data processed perGenerator
second, of
system description
system traffic, number of each type of components
actually
Application model
used in the architecture…
•System-level simulation and analytical methods (formal
Mapping
rules, mathematical
formulations…)
Design points
model
descriptions
Search
method
Architecture model
System
model
Evaluation
technique
System
metrics
Design
space
Performace, power,
cost…
14
MOTIVATION AND GOALS
Institute for Applied Microelectronics
IUMA - ULPGC
Components of system-level DSE process
• In the practice, many efforts are based
on ad-hoc approaches: create
manually, or use customized control
scripts…
• Rewrite these control scripts for
different DSE => labour intensive, errorprone, bottlenecks of productivity…
Generator of
system description
Application model
Mapping
model
Design points
descriptions
Search
method
Architecture model
System
model
Evaluation
technique
System
metrics
Design
space
Performace, power,
cost…
15
MOTIVATION AND GOALS
Institute for Applied Microelectronics
IUMA - ULPGC
Components of system-level DSE process
• In the practice, many efforts are based
on ad-hoc approaches: create
manually, or use customized control
User
scripts…
specifications
• Rewrite these control scripts for
different DSE => labour intensive, errorprone, bottlenecks of productivity…
DSE infrastructure
Generator of
system description
Application model
Mapping
model
Design points
descriptions
Search
method
Architecture model
System
model
Evaluation
technique
System
metrics
Design
space
Performace, power,
cost…
16
MOTIVATION AND GOALS
Institute for Applied Microelectronics
IUMA - ULPGC
• Goals
 An approach to handle the increasing level of design
options.
 Strategies and algorithms to solve the multiobjective
optimization design problem in a time and effort
efficient way.
 A framework that allows for incorporating different
combinations of search strategies and evaluation
techniques in an automatic and fast way.
 A single and generic infrastructure for system-level
DSE experiments, which provides a flexible and
reusable environment to systematically explore the
design space without resorting to ad-hoc efforts.
17
Institute for Applied Microelectronics
IUMA - ULPGC
OUTLINE
 Introduction and context
 Motivation, challenges and goals
• Approaches and contributions
• Results
• Conclusions and future work
18
APPROACHES AND CONTRIBUTIONS
Institute for Applied Microelectronics
IUMA - ULPGC
• “Dimension-oriented DSE approach”
– A novel concept and methodology for system-level MPSoC DSE.
– A large design space defined by a huge number of design options
can be explicitly separated and hierarchically organized into
dimensions or exploration levels.
Platform dimension
Design options or design decisions
Topology of the platform
Arch. component dimension
Number and type of components
Tasks migration
HW/SW partition
Resources allocation and organization
Tasks clustering
Mapping dimension
Storage capacity
Different clock domains
Scheduling policy
…
…
19
APPROACHES AND CONTRIBUTIONS
Institute for Applied Microelectronics
IUMA - ULPGC
• Dimension-oriented DSE approach: benefits
 Extensibility: remove and add new exploration levels with
additional design options.
 Flexibility: explore simultaneously all dimensions of the design
space or to fix one or more of these dimensions (e.g., a fixed
architecture) and focus the exploration within other dimensions.
Use a single search methods for exploring the whole design space,
or use a separate and different search method to co-explore the
design space => not perform the DSE as multiple independent
explorations, but the results from all dimensions are
simultaneously taken into account.
20
APPROACHES AND CONTRIBUTIONS
Institute for Applied Microelectronics
IUMA - ULPGC
• Dimension-oriented DSE approach
If no information is exchanged between different search methods in
the co-exploration process, we can have an under-exploration
problem and/or even worse, we cannot ensure the convergence.
A  {d , d , d
B  {d
A
pla
A
arc
A
map
B
pla
B
arc
B
map
,d ,d
}
}
Result after a single
evaluation: A is
better than B
A
B
is better than d pla ?
¿d pla
=
or
A
¿d arc
is better than
B
d arc
?
Solution: Establish explicit relationships between different search
methods used in the co-exploration process. There are many ways,
e.g., by means of hierarchical fitness functions => the search
methods that work at higher abstraction dimensions require more
information for a better overview of the design space.
21
APPROACHES AND CONTRIBUTIONS
Institute for Applied Microelectronics
IUMA - ULPGC
• “NASA framework”
– NASA (Non Ad-hoc Search Algorithm) is a modular infrastructure
for system-level MPSoC DSE experiments.
– A software environment that allows designers to deploy our
dimension-oriented approach, as well as to integrate a generator of
system design description.
– A single and generic framework that allows for integrating
different combinations of search methods and evaluation
techniques in a plug & play fashion.
– A flexible and reusable infrastructure to carry out system-level
multidimensional DSE experiments in a fast and automatic way.
22
APPROACHES AND CONTRIBUTIONS
Institute for Applied Microelectronics
IUMA - ULPGC
• NASA framework
User
specifications
Search
Feasibility
Checker
Platform
Connectivity
Architectural
components
Arch. Platform
Generator
Platform
instance
Architecture
instance
Components
Application
specifications
Modules
configuration
Architecture
constraints
Design-options
files (checked)
Tasks and
channels
Mapping
Design-options
files
Architectural
intermediate
file
Design-options
files (checked)
Architecture
model
Mapping
model
Fitness
files
Components
specifications
Application
model
Translator
Fitness function
Platform
Architectural
Components
Evaluator
Mapping
Metrics
reader
Simulator
System
model
23
Institute for Applied Microelectronics
IUMA - ULPGC
APPROACHES AND CONTRIBUTIONS
#define
#define
#define
NUMBER_SEARCH
TYPE_SEARCH_1
SOURCE_SEARCH_1
3
//Type PE
PE1=ARM
“GA”
PE2=MIPS
“../search/GA/”
PE3=PPC
#define
#define
#define
MAX_NUMBER_PE
MAX_NUMBER_SE
MAX_NUMBER_NE
3
2
3
…
//Type NE
NE1=BUS
NE2=XBA
TYPE_PE_1
“ARM”
NE3=P2P
PARAMETER_FILE_PE1 “../library/PE/arm.txt”
…
#define
#define
…
#define
#define
…
#define
#define
#define
#define
//Type SE
SE1=SDR
SE2=DDR
User
specifications
Application
specifications
Modules
configuration
Architecture
constraints
Components
specifications
Num. NE=3
Num. SE=2
TYPE_SE_1
“SDR”
Num. PE=3
PARAMETER_FILE_SE1 “../library/SE/sdr.txt”
…
…
NUMBER_TASKS
NUMBER_CHANNLES
TASK1
TASK1_SOURCE
7
12
“RGB2YCrCb”
“../app/rgb2ycrcb/”
…
24
APPROACHES AND CONTRIBUTIONS
Institute for Applied Microelectronics
IUMA - ULPGC
BTU 1
1
2
3
4
//Type PE
PE1=ARM
PE2=MIPS
PE3=PPC
Meta-platform
5
Network 1
BTU 2
1
2
3
4
BTU 3
1
5
Network 2
2
2
3
4
4
//Type SE
SE1=SDR
SE2=DDR
5
Network 3
BTU 4
1
3
BTU 5
1
5
Network 4
2
3
BTU 6
4
1
5
Network 5
2
3
4
Network 6
5
//Type NE
NE1=BUS
NE2=XBA
NE3=P2P
User
specifications
Application
specifications
Modules
configuration
Architecture
constraints
Components
specifications
Num. NE=3
Num. SE=2
Num. PE=3
Element container
1
2
3
4
5
…
…
Network container
2
3
7
BTU
1
4
6
5
Basic Topology Unit is a
logical pattern composed of a
number of the element
containers and a network
container
25
APPROACHES AND CONTRIBUTIONS
Institute for Applied Microelectronics
IUMA - ULPGC
BTU 1
1
2
3
4
Network 1
Meta-platform
5
2
3
4
BTU 3
Platform
1
5
2
Network 2
1
2
4
3
4
5
BTU 5
2
Network 4
3
1
5
Network 5
files
Fitness function
3
1
6
5
2
3
4
Network 6
5
Design-options
files (checked)
Tasks and
channels
Design-options
files
Fitness
Element
container
Architecture
BTU 6
Components
4
Mapping
2
Platform
//Type
SE
instance
SE1=SDR
SE2=DDR
Connectivity
5
Network 3
BTU 4 Architectural
components
1
3
Feasibility
Checker
Search
BTU 2
1
//Type PE
PE1=ARM
PE2=MIPS
Arch. Platform
PE3=PPC
Generator
1
2
…
Architecture
…
model
model
BTU
Architectural
4
Components
Evaluator
Mapping
Metrics
reader
Modules
configuration
Architecture
constraints
Components
specifications
intermediate
3 Mapping
4 5
7
Platform
Application
specifications
Num. file
NE=3
Num. SE=2
Num. PE=3
Design-options
files (checked)
Network container
instance
//Type
NE
NE1=BUS
NE2=XBA
NE3=P2P
Architectural
User
specifications
Application
model
Translator
Basic Topology Unit is a System
Simulator
logical pattern composedmodel
of a
number of the element
containers and a network
container
26
APPROACHES AND CONTRIBUTIONS
Institute for Applied Microelectronics
IUMA - ULPGC
Search
Search
Platform
Architectural
components
Mapping
SA
Dimension-oriented
DSE approach:
Platform
1) Multiple Search
Algorithms
2) Different (tailored)
search algorithm per
dimension
SA
Architectural components
3) Fixe one dimension
SA
Mapping
1 Search Algorithm (SA)
Adaptor
in
SA
Adaptor
out
27
APPROACHES AND CONTRIBUTIONS
Institute for Applied Microelectronics
IUMA - ULPGC
Design-options file
dpla1
Platform string
…
…
sub-string
Search
…
…
Networks Architectural elements
dplak
Architectural components string
darc1
Platform
Architectural
components
…
…
…
…
Processors
darck
Memories
Mapping
dmap1
Mapping string
…
…
…
…
Tasks
Design point (dpk)
dmapk
Channels
dpla1
…
dplaj
…
dplak
darc1
…
darcj
…
darck
dmap1
…
dmapj
…
dmapk
28
Institute for Applied Microelectronics
IUMA - ULPGC
APPROACHES AND CONTRIBUTIONS
User
specifications
Search
Feasibility
Checker
Platform
Connectivity
Architectural
components
Arch. Platform
Generator
Platform
instance
Architecture
instance
Components
Application
specifications
Modules
configuration
Architecture
constraints
Design-options
files (checked)
Tasks and
channels
Mapping
Design-options
files
Architectural
intermediate
file
Design-options
files (checked)
Architecture
model
Mapping
model
Fitness
files
Components
specifications
Application
model
Translator
Fitness function
Platform
Architectural
Components
Evaluator
Mapping
Metrics
reader
Simulator
System
model
29
APPROACHES AND CONTRIBUTIONS
Institute for Applied Microelectronics
IUMA - ULPGC
Users specification
NE1 = Bus
NE2 = XBA
Infeasible platform string
0
0
2
0
0
Feasible platform string
Connectivity
NE1 NE2 NE3 NE4 NE5 NE6 …
1
Feasibility
Checker
…
NE1 NE2 NE3 NE4 NE5 NE6
…
1
…
2
0
0
0
0
Checked
design-options
file
Components
Tasks and
channels
BTU 1
BTU 1
1
2
3
4
Infeasible platform
(isolate BTU)
5
1
3
4
Feasible platform
5
bus
bus
BTU 2
2
BTU 3
BTU 2
BTU 3
1
2
3
4
5
xba
BTU 4
1
2
3
4
BTU 5
BTU 6
BTU 4
BTU 5
BTU 6
5
xba
30
APPROACHES AND CONTRIBUTIONS
Institute for Applied Microelectronics
IUMA - ULPGC
Users specification
User
specifications
NE1 = Bus
NE2 = XBA
Infeasible platform string
Platform
Connectivity
NE1 NE2 NE3 NE4 NE5 NE6 …
1
0
0
2
0
0
Arch. Platform
Generator
Feasible platform string
Platform
NE1 NE2
NE3 NE4 NE5 NE6
…
instance
Feasibility
Checker
Search
…
1
Architectural
components
2
0
0
0
0
Application
specifications
Modules
configuration
…
Checked
Architecture
instance
Components
Architecture
design-options
constraints
file
Design-options
files (checked)
Tasks and
channels
Mapping
Design-options
files
2
3
bus
Infeasible platform
Mapping
(isolate BTU)
4 5
Fitness
files
BTU 2
Design-options
files (checked)
BTU 1
BTU 1
1
1
Architectural
Components
Mapping
2
3
4
Evaluator
BTU 5
2
4 5
Architecture
model
bus
Translator
Fitness function
BTU 3
BTU 4
1
model
Platform
1
Components
specifications
Architectural
intermediate
file
Metrics
reader BTU 6
3
BTU 3
BTU 2
2
3
4
Feasible platform
Application
model
5
xba
BTU 4
Simulator
BTU 5 System
model
BTU 6
5
xba
31
Institute for Applied Microelectronics
IUMA - ULPGC
APPROACHES AND CONTRIBUTIONS
•
Translator module converts NASA’s internal format of a
design point to the specific format required by each
evaluation technique.
•
For example, integration of a new simulator in NASA only
requires the adaptation of the Translator module.
Different
system-level
simulators
Architectural intermediate file
Sesame
Translator
YML-basad
architecture model
CASSE
Translator
Translator module
Command lines based
architecture model
32
Institute for Applied Microelectronics
IUMA - ULPGC
APPROACHES AND CONTRIBUTIONS
User
specifications
Search
Feasibility
Checker
Platform
Connectivity
Architectural
components
Arch. Platform
Generator
Platform
instance
Architecture
instance
Components
Application
specifications
Modules
configuration
Architecture
constraints
Design-options
files (checked)
Tasks and
channels
Mapping
Design-options
files
Architectural
intermediate
file
Design-options
files (checked)
Architecture
model
Mapping
model
Fitness
files
Components
specifications
Application
model
Translator
Fitness function
Platform
Architectural
Components
Evaluator
Mapping
Metrics
reader
Simulator
System
model
33
APPROACHES AND CONTRIBUTIONS
Institute for Applied Microelectronics
IUMA - ULPGC
• “Heuristic-based mapping algorithms”
– DSE experiments: using a single genetic algorithm vs multiple
genetic algorithms.
– Hierarchical DSE strategy with heuristic-based mapping algorithms
=> Fixed platform, variable architectural components and mappings.
– Objective: multi-objective optimization mapping problem =>
optimal configuration of a target platform for the mapping of a realtime application, while achieving real-time constraint, minimizing
system traffic load, maximizing resource usage as well as the load
balancing.
34
APPROACHES AND CONTRIBUTIONS
Institute for Applied Microelectronics
IUMA - ULPGC
• Heuristic-based mapping algorithms
 Estimation phase:
– Heuristic algorithms and analytical estimation function => exploring
and pruning the design space.
– Map a minimum number of logical clusters onto the components of
the MPSoC platform => constraints: real-time, system traffic load,
load balancing and resource usage.
 Simulation phase:
– Candidate solutions obtained in estimation phase are assessed with
a system-level simulator.
– Analytical estimation usually focuses on the relevance of subset of
design decisions, as well as often fail to consider non-linear
system behaviours => make an accurate evaluation difficult without
the use of simulation.
35
APPROACHES AND CONTRIBUTIONS
Institute for Applied Microelectronics
IUMA - ULPGC
• Heuristic-based mapping algorithms
NASA configuration
Estimation phase
Tasks
clustering
HW/SW
partitioning
Assignment
Search
Static performance estimation
Application
specification
Real-time
constraint
Architectural
template
Feasibility checker
Potential mappings
Arc. Platform Gen.
Component
s library
Simulation phase
Select mapping
Application
task graph
Translator
system model
generator
Simulator
System-level
simulator
No
satisfied
Evaluator
Constraints
Satisfied
Best mapping
36
Institute for Applied Microelectronics
IUMA - ULPGC
OUTLINE
 Introduction and context
 Motivation, challenges and goals
 Approaches and contributions
• Results
• Conclusions and future work
37
RESULTS
Institute for Applied Microelectronics
IUMA - ULPGC
• Co-exploration vs traditional exploration
DSE with multiple genetic algorithms (3GA) vs a single genetic algorithm
(1GA).
Parameter
PE
SE
NE
Dimensions (β)
Search algs. (SA)
GA Selection (S)
GA Crossover (C)
C probability (pc)
GA Mutation (M)
M probability (pm)
Search iterations (I)
Population size (N)
Nr.
≤6
≤3
≤4
3
1 or 3
1
1
5
1
5
41
10
Types
3
2
3
1
1
2
2
-
Values
ARM, PPC, MIPS
DDR, SDR
Bus, Fully-connected, Customized-network
Platform, architectural components and mapping
Genetic algorithms
Proportional with elitism
1-point and 2-point
[0.1,0.3,0.5,0.8,1.0]
Simultaneous (M=1) and Independent (M=6)
[0.1,0.3,0.5,0.8,1.0]
Nr. of individuals per iteration
Target application: Visual tracking algorithm (ULPGC)
System level simulator: CASSE (ULPGC)
38
RESULTS
20 iterations
1400
1400
1350
1350
1300
Best fitness value
(packets/s)
Best fitness value
(packets/s)
10 iterations
1250
1200
1150
1GA1x6
1100
1GA2x1
1050
3GA1x6
1000
1300
1250
1200
1150
1GA1x6
1100
1GA2x1
1050
3GA1x6
1000
3GA2x6
950
3GA2x6
950
20
70
120
170
220
270
320
370
420
20
70
120
Accumulated diversity
1350
1350
Best fitness value
(packets/s)
1400
3GA
1300
1250
1200
1150
1GA1x6
1GA
1050
220
270
320
370
40 iterations
1400
1100
170
420
Accumulated diversity
30 iterations
Best fitness value
(packets/s)
Institute for Applied Microelectronics
IUMA - ULPGC
• Co-exploration vs traditional exploration
1GA2x1
3GA1x6
1000
pc0.8pm0.3
1300
1250
1200
1150
1100
1GA1x6
1GA
1050
1GA2x1
3GA1x6
1000
3GA2x6
950
3GA
3GA2x6
950
20
70
120
170
220
270
Accumulated diversity
320
370
420
20
70
120
170
220
270
320
370
420
Accumulated diversity
39
RESULTS
Iterations
0
5
10
15
20
25
30
35
40
1400
Fitness values (packets/s)
Institute for Applied Microelectronics
IUMA - ULPGC
• Co-exploration vs traditional exploration
Metrics to compare the quality
of different DSE approaches:
1200
-Convergence
1000
1GA1x6
800
-Diversity
1GA2x1
3GA1x6
600
3GA2x6
Real time
400
0
100
200
300
-Coverage
400
Explored design points
40
RESULTS
– In this set of experiments: fitness values=> performance (packets/s).
– 3GA can converge progressively to solutions with a higher fitness
value, while 1GA often cannot converge to solutions with higher
fitness value (e.g., cannot achieve to the real-time constraint).
Real-time
constraint
0
5
10
Iterations
15
20
25
30
3GA
35
40
1400
Fitness values (packets/s)
Institute for Applied Microelectronics
IUMA - ULPGC
• Co-exploration vs traditional exploration
1200
Local
optima
solutions
1GA
1000
3GA can achieve to solutions
satisfying the real-time constraint
after 15~19 iterations.
800
1GA1x6
1GA2x1
3GA1x6
600
3GA2x6
Real time
400
0
100
200
300
400
Explored design points
41
RESULTS
Institute for Applied Microelectronics
IUMA - ULPGC
• Co-exploration vs traditional exploration
1GA: after 40 iterations
42
RESULTS
Institute for Applied Microelectronics
IUMA - ULPGC
• Co-exploration vs traditional exploration
3GA: after 40 iterations
43
RESULTS
Institute for Applied Microelectronics
IUMA - ULPGC
• Co-exploration vs traditional exploration
3GA: after 40
10 iterations
20
30
These solutions still need to be
refined for their validations
44
RESULTS
Institute for Applied Microelectronics
IUMA - ULPGC
• Hierarchical strategy vs Co-exploration
– DSE using our heuristic algorithms to explore and prune the design
space vs Co-exploration using 2GA.
– Target MPSoC platform, and variable architectural components and
mappings.
– Quality of DSE in term of the average runtime of DSE experiments:
• Co-exploration: 60 simulations x 30 second per simulation = 1800 s.
• Hierarchical: 30 ~ 90 s => 2 orders of magnitude more efficient.
– Quality of design solutions in term of four design objectives:
(1) Number of resources actually used; (2) resources usage;
(3) Minimize PE load unbalancing; (4) Minimize system traffic load.
45
RESULTS
Institute for Applied Microelectronics
IUMA - ULPGC
• Hierarchical strategy vs Co-exploration
(1) Number of resources actually used; (2) resources usage;
(3) Minimize PE load unbalancing; (4) Minimize system traffic load.
Higher
quality
solutions
25
28
RTC (frames/s)
(1)*
(2)
(3)
(4)
Hierarchical
3 (0)
88.875 %
11.533 %
49.045 %
Co-exploration
4 (3)
66.656 %
29.066 %
87.308 %
Hierarchical
4 (2)
71.655 %
18.427 %
58.903 %
Co-exploration
5 (3)
57.324 %
30.026 %
97.124 %
After 20
iterations
* Number of PE (SE) used in the solution.
– Co-exploration approach also can achieve these optimal solutions or
even better solutions => running more iterations.
– Co-exploration with 2GA can provide a set of Pareto Optima
solutions => designers decide which strategy to used according to
their need.
46
Institute for Applied Microelectronics
IUMA - ULPGC
OUTLINE
 Introduction and context
 Motivation, challenges and goals
 Approaches and contributions
 Results
• Conclusions and future work
47
Institute for Applied Microelectronics
IUMA - ULPGC
CONCLUSIONS AND FUTURE WORK
•
The main goal pursues new approaches that facilitate the
system-level design space exploration process =>
concepts, infrastructure, methods and algorithms.
•
It is important to stress that system-level design has been
proposed as a complement of the traditional design
methods => candidates solutions have to be refined for
their validation.
•
As future work, it would be interesting to link our
approaches to a design flow at lower abstraction level.
•
Develop more DSE experiments, integrating other search
techniques, simulation tools and application domains, etc,
in order to prove progressively the full capability of our
approaches.
48
Institute for Applied Microelectronics
IUMA - ULPGC
Universidad de Las Palmas de Gran Canaria
THANKS YOU VERY MUCH FOR
YOUR ATTENTION!
Las Palmas de Gran Canaria, January 25, 2011
Institute for Applied Microelectronics
IUMA - ULPGC
Universidad de Las Palmas de Gran Canaria
Programa de doctorado Sistemas Inteligentes y
Aplicaciones Numéricas en Ingeniería
System Level Design Space Exploration for MPSoC:
Methods, Algorithms and New Infrastructure
European Doctorate
Institute for Applied Microelectronics (IUMA)
PhD student:
Zai Jian Jia Li
Supervisors:
Prof. Antonio Núñez
Assist. prof. Tomás Bautista
Las Palmas de Gran Canaria, January 25, 2011