DSP C 5000
Chapter 8
Direct Memory Access (DMA)
Copyright © 2003 Texas Instruments. All rights reserved.
Direct Memory Access
In a real-time system, DMA is used to transfer data
from peripheral/memory and memory/peripheral
without burdening the CPU :
Input Data
Memory
DMA
serial or parallel
Let’s see how the
DMA performs
its tasks...
ESIEE, Slide 2
ESIEE
internal/external
C54x
C55x
Copyright © 2003 Texas Instruments. All rights reserved.
C54x Direct Memory Access (DMA)
Performs data transfers without CPU intervention
SRC address
SOURCE
DEST
Element 1
Element 2
Element 3
Element 4
Frame 1
Frame 2
Frame 3
Frame 4
DST address
Terminology
- Element: basic unit of transfer (1, 2 words)
- Frame: multiple elements (1-64K)
- Block: multiple frames (1-256)
Max Speed: One 16-bit word per 4 CPU cycles (all channels combined)
Transfer dependent upon:
- Source/destination address
- Rotating priority between channels
- Event sync (different events can be selected)
- Element/Frame count
- Index (can select: no modification, inc/dec by 1 and element/frame index)
ESIEE, Slide 3
ESIEE
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Registers and Resources
DMA Channels 0-5
EHPI
Source
DMA “Resources”
Destination
DARAM
EHPI
Auxiliary
Channel
15
Elem Count
Frame Count
SARAM
Elem Index
Frame Index
Ext’l Mem
Control
Status
14
13
8
Free AUTOIX DPRC[5:0]
DE[5:0]
INTSEL
DPRC
AUTOIX
Free
7
DMA
Bus
6
INTSEL
Peripherals
5
0
DE[5:0]
DMPREC Register
Enable/disable channels
Interrupt Multiplex Control
Channel Priority (Hi or Low)
Extended reload mode
Emulation Control
Only the ‘C5409, ‘10, ‘16, ‘21 and ‘41 support external DMA accesses
ESIEE, Slide 4
ESIEE
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Registers
12
15
DSYN[3:0]
11
DBLW
10
8 7
rsvd
0
Frame Count
DMSFCn (Sync Event and Frame Count)
Frame Count:
N-1 (N is desired # of frames)
DBLW:
Double-word mode (0: 16-bit, 1: 32-bit)
DSYN:
DMA sync event
15
14
13
12
11
10
8
AUTOINIT DINM IMOD CTMOD SLAXS SIND
7
6
5
4
2
DMS DLAXS DIND
1
0
DMD
DMMCRn (Transfer Mode Control)
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DMD:
Destination Address Space (Program, Data, I/O)
DIND:
Destination Index (none, +, -, element/frame index)
DLAXS:
Internal/External Access (0/1)
DMS:
Source Address Space (Program, Data, I/O)
SIND:
Source Index (none, +, -, element/frame index)
SLAXS:
Internal/External Access (0/1)
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Registers - Synchronisation Example
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Index and Frame offset are 16 bits signed
Example: data sorting
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Registers – ABU Mode
Implements circular buffering.
Indefinite number of transfers.
Base address must be a power of two, 2r >N,
with N being the buffer size.
One side must be without address modification
and the other can only use an indexing mode.
3000h
McBSP
DRR
ESIEE, Slide 7
ESIEE
DMSRC1=DRR
DMDST1
DMCTR1
DMSFC1
30FFh
1E57
2089
F57B
...
DEAD
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Registers – Interrupt Mode
DINM, IMOD and CTMOD specify
interrupt mode:
DINM: no interrupt on transfer completion if 0.
CTMOD: multiframe mode if 0, ABU mode if 1.
IMOD: depend on CTMOD
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Multiframe mode: interrupt occurs at end of block
transfer if 0, else at the end of each frame and at the
end of block transfer.
ABU mode: interrupt occurs when buffer is full if 0,
else at half buffer full and at buffer full condition.
Copyright © 2003 Texas Instruments. All rights reserved.
Writing to the DMA Registers
Writing to DMA registers is a multi-step process using
sub-bank addressing
MMR Regs
Sub-bank Address
DMSA
Data Register
DMSDN
Data Register
with auto-increment DMSDI
Sub-bank Regs
DMSRCn Source Address
DMDSTn Destination Address
DMCTRn Element Count
DMSFCn Sync Event, Frame Count
DMMCRn Transfer Mode Control
Using sub-bank addressing with auto-increment
DMSRC0 .set 00h
STM
DMSRC0,DMSA
;init DMSA to pt to DMSRC0
STM
#1000h,DMSDI
;write 1000h to DMSRC0
STM
#2000h,DMSDI
;write 2000h to DMDST0
…etc.
Another example
ESIEE, Slide 9
ESIEE
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Throughput
DPRC[5:0]: determines DMA bus priority between channels
- (hi-1, low-0) Affects access to the 16-bit DMA bus only
- Can select high or low rotating priority (per element transfer):
High
Ch-3
Low
Ch-0
Ch-2
Priority Access to
Data Buses:
ESIEE, Slide 10
ESIEE
Ch-5
Ch-1
Low serviced when high:
- waiting for event sync
- transfers are complete
Ch-4
EHPI
DMA (Hi)
DMA (Lo)
CPU
highest
lowest
Copyright © 2003 Texas Instruments. All rights reserved.
Example: Auto-Init and Sync Events
McBSP
A/D
DRR
Global Reload Regs
DMGSA=DRR
DMGDA=80h
DMGCR=15
DMGFR0=00h
DMA Ch0
DMSRC0=DRR
DMDST0=80h
DMCTR0=15
DMSFC0=00h
Sync event
RRDY = 1
80h
8Fh
1E57
2089
F57B
...
DEAD
Int to CPU
Selected sync event (e.g. RRDY=1) triggers element transfer
(e.g. from DRR to 80h)
Interrupt can occur at end of block or end of frame/block
DMA channel registers reloaded from reload registers at
end of block transfer IF auto-init enabled.
Example shown transfers 16 values from DRR to the same
memory locations every frame
Refer to the documentation for a complete list of the DMA registers
ESIEE, Slide 11
ESIEE
Copyright © 2003 Texas Instruments. All rights reserved.
Example: Interfacing PCM3002 with DMA
McBSP2
A/D
DMA4
DMA5
DRR
McBSP2
DXR
PING
IN
D/A
PING
PROCES-
OUT
SING
ESIEE, Slide 12
ESIEE
PONG
PONG
IN
OUT
Copyright © 2003 Texas Instruments. All rights reserved.
Overview
Create a new project
Retrieve audioIO.cdb
(McBSP2 configuration already done) and
save it in the project directory as
audioIODma.cdb
Specify buffer declaration (circular
addressing constraint).
Configure DMA channels with GUI
interface.
Interrupt configuration for input DMA
channel
ESIEE, Slide 13
ESIEE
Copyright © 2003 Texas Instruments. All rights reserved.
Create Source File
ESIEE, Slide 14
ESIEE
Take the file audioIODma.c and add it to
the project.
Copyright © 2003 Texas Instruments. All rights reserved.
Buffer Declaration
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ESIEE
Because of constraints on buffer address in
ABU mode, the buffer must declared and
handled in a special way during linking.
Add this file audioIODma.cmd
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Configurations
ESIEE, Slide 16
ESIEE
Open file audioIODma.cdb and go to CSL
Add a DMA configuration named
« DmaAudioRx ».
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Configuration
ESIEE, Slide 17
ESIEE
Select ABU for circular buffer
Interrupt on half and full buffer to
implement Ping-Pong buffering
Synchronisation on receive event from AD
converter through McBSP2.
Copyright © 2003 Texas Instruments. All rights reserved.
DMA configurations
source and destinatation
ESIEE, Slide 18
ESIEE
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Configuration
ESIEE, Slide 19
ESIEE
Add a new DMA configuration
« DmaAudioTx ».
Copyright © 2003 Texas Instruments. All rights reserved.
DMA configurations
source and destinatation
ESIEE, Slide 20
ESIEE
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Settings
ESIEE, Slide 21
ESIEE
Select DMA4 for receive channel
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DMA Settings
ESIEE, Slide 22
ESIEE
Select DMA5 for transmit channel
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Handling
ESIEE, Slide 23
ESIEE
Declare handle to DMA channels in source file
and start transfer using CSL functions call.
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Interrupt Handling
ESIEE, Slide 24
ESIEE
Connect IRQ event from DMA4 to a function
called RxBuffer
Unmask this interrupt and globally enable
interrupts (INTM)
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Interrupt Handler
Add the DMA interrupt service routine « RxBuffer »
Build and run the application
ESIEE, Slide 25
ESIEE
Copyright © 2003 Texas Instruments. All rights reserved.
Other DMA Issues
Auto-Initialization:
- At end of block, DMA copies reload registers to channel registers
- Reload registers can be altered at any time
- Every channel can select to use auto-init and reload registers
- Allows user to provide “continuous” or “repetitious” operation
ESIEE, Slide 26
ESIEE
Copyright © 2003 Texas Instruments. All rights reserved.
‘C55x Direct Memory Access (DMA)
Performs data transfers without CPU intervention
SRC addr
SOURCE
DEST
Element 1
Element 2
Element 3
Element 4
Frame 1
Frame 2
Frame 3
Frame 4
DST addr
Terminology
- Element: basic unit of transfer (1, 2, or 4 bytes)
- Frame: a group of 1 to 64K elements
- Block: a group of 1 to 64K frames
Max Throughput: Two 16-bit transfers (R/W) per cycle (2 different Ch’s)
Transfer dependent upon:
- Source/destination address
- Priority (rotating priority between channels, also Ch vs. CPU)
- Event sync (20 different events can be selected for ‘C5510)
- Element/Frame count
- Index (can select: constant, increment, element/frame index)
ESIEE, Slide 27
ESIEE
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Registers, Resources
DMA Channels 0-5
Source
Destination
DMA “Ports”
Read
Bus
32
Elem Index
Frame Index
Elem Count
Frame Count
16-bit FIFO
Control
Status
32
EHPI
Auxiliary
Channel
ESIEE, Slide 28
ESIEE
32
DARAM
32
SARAM
32
EMIF
16
Peripherals
16
EHPI
Write
Bus
Each CHx has: 2 32-bit buses (R/W) + 16-bit FIFO + 8 DMA regs shown
DMA Channels 0-5 have access to all ports except EHPI port
EHPI Auxiliary Channel has access to all ports except Peripherals port
EHPI share the auxiliary port with USB module
Copyright © 2003 Texas Instruments. All rights reserved.
DMA vs EHPI
Global Control Register (DMA_GCR)
If EXCL 0 all ports are connected.
If EXCL 1 ports in red are disconnected and EHPI
have exclusive access to DARAM and SARAM
ESIEE, Slide 29
ESIEE
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Throughput
DMA throughput is affected by the combination of:
1
CPU has FIXED priority over the DMA
- Affects access to: RHEA, EMIF, SARAM, DARAM
2
PRIO bits: (DMA_CCRn:6) sets priority(hi/low) for DMA channel n
EHPI PRIO bit: (DMA_GCR:0) sets priority for EHPI Aux. channel
- Affects access to the two 16-bit DMA buses
- Can select high or low priority round robin (per element transfer)
High
Ch-3
Ch-0
Ch-2
3
Low
Ch-5
Ch-1
Low serviced when high:
- waiting for event sync
- transfers are complete
Ch-4
EHPI EXCL bit: (DMA_GCR:1)
- Affects access to internal/external memory
- EXCL=1: EHPI accesses internal RAM only, DMA external RAM only
ESIEE, Slide 30
ESIEE
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Service Chain
ESIEE, Slide 31
ESIEE
Scenario
Service chain example
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DMA Interrupt
Interrupts can be generated from multiple events for
each channel (DMA_CICR), all interrupts are Ored :
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ESIEE
Timeout : each resource access can be supervised thanks to a
counter.
Drop : Synchronisation not serviced.
Half frame : At half of each frame.
Frame : At the end of each frame.
Last Frame : At the beginning of the last frame transfer.
Block : At the end of the block transfer.
Read DMA_CSR to determine source of interrupt
Copyright © 2003 Texas Instruments. All rights reserved.
Setting Up a DMA Transfer (SARAMD/A)
Problem: - Transfer a block of pixels from SARAM to a D/A
- Output via McBSP/DMA and sync transfer to D/A (ready)
16-bit pixels
(SARAM)
Src: mem_8
15
14
McBSP
DXR
8 9 10 11
14 15 16 17
20 21 22 23
13
12
DMA
D
D/A
Dest: DXR
Ready
EXT_INT4
9
8
7
6
5
2
1
0
DST BEN DST PACK DST SRC BEN SRC PACK SRC DATA TYPE
DMA Channel n Source Destination Parameters Register (DMA_CSDPn)
Field
Description
DATA TYPE
SRC/DST
Element size
Port select
Options
Answer?
2
1, 2, or 4 bytes
SA/DARAM, EMIF, Periph SARAM/Periph
DST/SRC PACK Data packing packed or non-packed
non-packed
DST/SRC BEN
no burst
Burst enable
no burst, 4 element burst
There’s more to set up for the DMA channel ...
ESIEE, Slide 33
ESIEE
Copyright © 2003 Texas Instruments. All rights reserved.
Setting Up a DMA Transfer (SARAMD/A)
Problem: - Transfer a block of pixels from SARAM to a D/A
- Output via McBSP/DMA and sync transfer to D/A (ready)
16-bit pixels
(SARAM)
Src: mem_8
15
14
McBSP
DXR
8 9 10 11
14 15 16 17
20 21 22 23
13
DMA
D
D/A
Dest: DXR
Ready
EXT_INT4
11
10
9
8
7
6
5
4
0
DST AMODE SRC AMODE
AUTO INIT EN PRIO FS SYNC
DMA Channel n Control Register (DMA_CCRn)
Field
Description
Options
SYNC
Sync Event 20 options (plus no sync)
FS
Frame Sync 0: elem sync, 1: frame sync
PRIO
Priority
0: low, 1: hi
EN
Ch enable
0: disable, 1: enable
AUTO INIT
Auto init
0: none, 1: auto init
SRC/DST AMODE Addr index none, +, elem indx, frm indx
What other registers need to be set up?
ESIEE, Slide 34
ESIEE
Answer?
EXT_INT4
0
0 (or 1)
1
0
frm indx/ none
Copyright © 2003 Texas Instruments. All rights reserved.
DMA Transfer - Example
Problem: - Transfer a block of pixels from SARAM to a D/A
- Output via McBSP/DMA and sync transfer to D/A (ready)
16-bit pixels
(SARAM)
8 9 10 11
14 15 16 17
20 21 22 23
Src: mem_8
DMA_CSSA_Un DMA_CSSA_Ln
mem_8[23:16] mem_8[15:0]
SRC starting BYTE Address
McBSP
DXR
DMA
D
D/A
Dest: DXR
Ready
EXT_INT4
DMA_CDSA_Un DMA_CDSA_Ln
DXR[23:16]
DXR[15:0]
DEST starting BYTE Address
Note: data labels, e.g. mem_8 must be <<1 to form byte address
DMA_CENn
4
DMA_CFNn
3
# of Elements
# of Frames
ESIEE, Slide 35
ESIEE
DMA_CEIn
2
DMA_CFIn
6
Element Index
(in bytes)
Frame Index
(in bytes)
Copyright © 2003 Texas Instruments. All rights reserved.
Other DMA Issues
Auto-Initialization:
- Each channel contains “config” and “working” register sets. When
auto-init is enabled, the “working registers” are reloaded from the
“config” registers (which you can access via I/O memory)
- Continuous operation: can change init/reload registers during current
block transfer. Next transfer uses new values. Does not stop DMA.
- Repetitive Operation: same init/reload registers used every time
Refer to the documentation for a complete list of the DMA registers
ESIEE, Slide 36
ESIEE
Copyright © 2003 Texas Instruments. All rights reserved.
