Synthesis of False Target Radar Images
Using a Reconfigurable Computer
Dr. Douglas J. Fouts
LT Kendrick R. Macklin
Daniel P. Zulaica
Department of Electrical
and Computer Engineering
U.S. Naval Postgraduate School
Monterey, California
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Using a Reconfigurable Computer
Outline
1.
2.
3.
4.
5.
6.
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High resolution imaging inverse synthetic aperture radar (ISAR).
Digital synthesis of realistic false target images.
The SRC-6E reconfigurable computer.
Synthesis of false target images on the SRC-6E.
Testing results.
Conclusions
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Synthesis of False Target Radar Images
Using a Reconfigurable Computer
The USS Crockett, a typical target for a potential adversary.
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Using a Reconfigurable Computer
Target appearance on the screen of a
typical surface search and navigation radar.
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Using a Reconfigurable Computer
Appearance of USS Crockett on U.S. Navy AN/APS-137
http://radar-www.nrl.navy.mil/Areas/ISAR
imaging
Inverse Synthetic Aperture Radar (ISAR).
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Using a Reconfigurable Computer
Block diagram of electronic warfare system
with false target image synthesis capability.
Digital Image
Synthesis
Hardware
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Using a Reconfigurable Computer
Dividing a target into range bins.
Range Bins
Interrogating Radar Signal
Reflected Radar Signal
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Block diagram of digital image synthesis hardware.
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To synthesize a false target image,
the math must be done very fast.
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Using a Reconfigurable Computer
RTL diagram of
Range Bin Processor
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Using a Reconfigurable Computer
The SRC-6E Reconfigurable Computer
•
•
LINUX cluster of two PCs
Each PC has
– Two 1000 MHz Intel XEON® processors
– Common memory
– Snap port to Multi Adaptive Processor (MAP)
•
Each MAP has
–
–
–
–
–
•
Two user-programmable Xilinx Virtex-II FPGAs (6 M gates each)
One Xilinx Virtex-II Control FPGA (not user programmable)
On-board memory
Snap port to PC
Two 96-bit wide chain ports to other MAP
Programs written in C or Fortran.
– User identifies which part(s) of program are converted to FPGA circuitry for
(hopefully) increased execution speed
– FPGA code can also be written in VHDL OR Verilog
– FPGA can also be programmed schematically or with IP cores
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SRC-6E Architecture (half)
μP Board
Intel®
μP
Intel®
μP
315/195
MB/s
(peak)
MAP
Controller
L2
L2
6x 800 MB/s
MIOC
PCI
Common
Memory
On-Board Memory
(24 MB)
S
N
A
P
6x 800 MB/s
Chain Port
To/From
Other MAP
800 MB/s
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FPGA
FPGA
Chain Port
To/From
Other MAP
800 MB/s
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Synthesis of False Target Radar Images
Using a Reconfigurable Computer
MAP Software Development
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•
•
•
•
•
Code for FPGAs is isolated in external function
SRC compiler translates C source code into FPGA programming file.
MAP can also be programmed with Verilog, VHDL, IP cores, or schematically
FPGA circuitry deeply pipelined with 100 MHz clock (10 ns period)
Large pipeline fill time (large latency)
Calls are inserted in the main program to
– Initialize the MAP
– Transfer input data from common memory to on-board memory
– Call the external function
– Transfer output data from on-board memory to common memory
– Release the MAP (optional)
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Programming Steps Used in This Research
•
Describe range bin processor using VHDL in the Aldec Active-HDL 5.2
environment
–
–
–
–
•
•
•
Code the individual logic blocks
Combine to build a single range bin processor
Instance the range bin processor the required number of times
Test code using Aldec Active-HDL simulator
Create support and interface files for SRC-6E
Create “main” part of program in C for execution on PCs in SRC-6E
Compile and link
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Benchmarks
1. VHDL macro on the SRC-6E MAP
2. C program on the SRC-6E
– 1 GHz Xeon P3
– 1.5 Gigabytes of RAM
– Linux OS
3. C program on Pentium 4 system
– 3 GHz P4
– 2 Gigabytes of RAM
– Windows XP Professional OS
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Usage (%)
FPGA Usage
100.00
90.00
80.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.00
y = 1.9449x2 - 10.003x + 19.02
y = 4.693e
1
2
4
8
16
32
64
128
256
0.2978x
512
Number of Bins
Usage
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Expon. (Usage)
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Poly. (Usage)
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Synthesis of False Target Radar Images
Using a Reconfigurable Computer
Average Total Time (4 Bins)
Time (Seconds)
5
4.5
4
3.5
3
2.5
2
1.5
00
50
00
44
72
26
21
6
13
10
65
53
4
8
32
76
16
38
81
92
40
96
20
48
10
24
51
2
25
6
12
8
64
32
1
0.5
0
Number of Samples
Fouts
SRC Macro MAP Call
SRC Macro Total
Windows XP C Program
SRC C Program
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00
44
50
00
26
21
72
6
13
10
65
53
8
32
76
4
16
38
81
92
40
96
20
48
10
24
51
2
25
6
12
8
64
10
9
8
7
6
5
4
3
2
1
0
32
Time (Seconds)
Average Total Time (64 Bins)
Number of Samples
Fouts
SRC Macro MAP Call
SRC Macro Total
Windows XP C Program
SRC C Program
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Average Total Time (128 Bins)
Time (Seconds)
18
16
14
12
10
8
6
4
2
00
50
00
44
26
21
72
6
13
10
65
53
4
8
32
76
16
38
81
92
40
96
20
48
10
24
51
2
25
6
12
8
64
32
0
Number of Samples
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SRC Macro MAP Call
SRC Macro Total
Windows XP C Program
SRC C Program
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SRC MAP Call Average Time
0.15
Time (Seconds)
0.14
0.13
0.12
0.11
0.1
00
50
00
44
72
26
21
8
6
13
10
65
53
32
76
4
16
38
81
92
40
96
20
48
10
24
51
2
25
6
12
8
64
32
0.09
Number of Samples
Old 4 Bins
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4 Bins
8 Bins
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16 Bins
64 Bins
128 Bins
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Synthesis of False Target Radar Images
Using a Reconfigurable Computer
Average Percentage of Total Time (4 Bins)
00
44
50
00
72
26
21
8
6
13
10
65
53
4
32
76
16
38
81
92
40
96
20
48
10
24
51
2
25
6
12
8
64
70%
60%
50%
40%
30%
20%
10%
0%
32
Percentage
100%
90%
80%
Number of Samples
I/O Overhead
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MAP Overhead
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MAP Call
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Synthesis of False Target Radar Images
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I/O Overhead Percentage of Total Time (Semi-Log)
Percentage (Log)
00
44
50
00
72
26
21
6
13
10
4
8
65
53
32
76
10.00%
16
38
81
92
40
96
20
48
10
24
51
2
25
6
12
8
64
32
100.00%
1.00%
0.10%
0.01%
Number of Samples
4 Bins
Fouts
8 Bins
16 Bins
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64 Bins
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Conclusions
1. The SRC-6E compiler allows C programmers to utilize the MAP without
having to become circuit designers.
2. Porting code to the MAP requires basic knowledge of the hardware.
3. Programming an SRC-6E requires less time and effort than developing
FPGA designs using COTS FPGA development systems.
4. Overall performance of SRC-6E can be limited by transfer time
between common memory and on-board memory.
5. Use of large data sets amortizes MAP overhead and pipeline latency
across many calculations.
6. Applications performing a large number of calculations on each data
set derive the largest performance boost from using the MAP.
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