Lecture 3 - 68HC11 Memory

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ECE265
ECE 265 – LECTURE 3
68HC11 Address Space, Memory, Registers, and
data transfers
3/29/2011
1
Lecture Overview
2





How is the address space broken out in the 68HC11
RAM and ROM memories
Structure and Logical organization memory
Registers
Material from Chapter 2 and a 68HC11 reference
manual
 Joanne E. DeGroat, OSU
ECE265
3/29/2011
What is the difference – RAM and ROM
3

RAM = Random Access Memory
 Joanne E. DeGroat, OSU
ECE265
3/29/2011
What is the difference – RAM and ROM
4

RAM = Random Access Memory




As the name implies any location of the memory can
be accessed in any order, i.e., randomly.
Given an address, the data is stored at that address, or
the data at that address is retrieved, depending on the
mode of access (read or write).
RAM is the memory where data is stored.
ROM = Read Only Memory
 Memory
that can only be read.
 Joanne E. DeGroat, OSU
ECE265
3/29/2011
What is the difference – RAM and ROM
5

RAM = Random Access Memory



As the name implies any location of the memory can be
accessed in any order, i.e., randomly.
This is the memory where data is stored.
ROM = Read Only Memory


This is memory that can only be read.
There are different types


One time programmable, UV erasable, EEPROM – electrically
erasable
ROM will maintain the contents even when power is off.
 Joanne E. DeGroat, OSU
ECE265
3/29/2011
Different flavors of the 68HC11
6

Different flavors of the chip have different amounts



MC68HC11A8 – 256 bytes of RAM and 8K of ROM
MC68HC11E9 – 512 bytes RAM, 12K ROM
MC68HC11D3 – 192 bytes RAM, 4K ROM

The different amounts allow choice of a chip
tailored to the embedded system.

Note: There is also a 192 byte ROM on board for
use in testing that has a bootstrap loading program.
This ROM is also used for security.
 Joanne E. DeGroat, OSU
ECE265
3/29/2011
The RAM
7

The entire memory space – 16 bit address (65,536)
RAM is in the first 256 loactions - $0000 to $00FF
 These locations are available using direct addressing mode.
 Direct addressing mode assumes the upper byte of the
address is $00

Saves space in program memory – only 8 bits for address and a 1
word instruction versus 2
 Saves a cycle of execution as only one fetch to load the
instruction


By using the INIT register, 4-bits, RAM can be moved to
the start of any 4K partition within the memory space as the
INIT register specifies the upper 4-bits when direct
addressing modes is used. INIT starts with 0000
 Joanne E. DeGroat, OSU
ECE265
3/29/2011
Power and RAM
8


The contents in RAM are lost if power is lost.
The design is fully static RAM so the data is not
lost if the clocks are halted.
DRAM – Dynamic RAM – clocks are needed to
keep the data refreshed as the contents are not static.
The charge that determines the value of that bit will
bleed off if not refreshed.
 In
 Joanne E. DeGroat, OSU
ECE265
3/29/2011
The memory map
9




The complete 64K
memory space
Note that EEPROM
is located at $B600 to
$B7FF
The map also
supports add-on
RAM – another chip
in the system.
There is also a
monitor EPROM
 Joanne E. DeGroat, OSU
ECE265
3/29/2011
The Registers
10

Within the CPU
The 68HC11 is an accumulator based architecture
 What is an accumulator based architecture?


First consider the programmers model of the architecture.
The programmers model is what the programmer see, i.e., what
the programmer has direct access to. Allows the programmer to
visualize how data is transferred between registers.
 In may cases there are other registers within a processor
architecture that required for operation but are not directly visible
to the programmer. An example is the Instruction Register.

 Joanne E. DeGroat, OSU
ECE265
3/29/2011
The Registers
11

Within the CPU
The 68HC11 is an accumulator based architecture
 What is an accumulator based architecture?



An architecture in which all data operations require the data to be
loaded in or interact with the accumulator.
First consider the programmers model of the architecture.
The programmers model is what the programmer see, i.e., what
the programmer has direct access to. Allows the programmer to
visualize how data is transferred between registers.
 In most cases, there are other registers within a processor
architecture that are required for operation but are not directly
visible to the programmer. An example is the Instruction
Register.

 Joanne E. DeGroat, OSU
ECE265
3/29/2011
The 68HC11 Programmer Model
12


7 registers in total
2 are index registers
 Used




in addressing data
A stack pointer register
The PC
A CC register
The accumulator
 Joanne E. DeGroat, OSU
ECE265
3/29/2011
The Accumulator
13

Actually have 2–Accumulator A &Accumulator B

Can be combined to form Accumulator D
For the most part they can be used to perform the same
operations.
EXCEPT –


Decimal arithmetic – BDC operation must use A
 CC register can only be transferred to A
 Certain operations put the result in A

 Joanne E. DeGroat, OSU
ECE265
3/29/2011
Example of Accumulator Use
14

The ABA instruction
 Add
accumulators
 Result is loaded into Accumulator A
 Joanne E. DeGroat, OSU
ECE265
3/29/2011
Accumulator D
15

Can perform a Load Double Accumulator
Instruction
 Loads
both the A and B accumulators from Memory

Can also perform add and subtract operations on D
Can use the D accumulator in shift operations

The D accumulator is not a separate accumulator

 If
you use the D accumulator for an operation it will
replace the contents of the A and B accumulators as it
is the same physical register.
 Joanne E. DeGroat, OSU
ECE265
3/29/2011
Lecture summary
16

Have covered
 The
pin configuration on the M68HC11
 The organization of the pins
 The basic interface capabilities of the pins
 Joanne E. DeGroat, OSU
ECE265
3/29/2011
Assignment
17


Read Chapter 2
Look at Chapter 2, Problems: 2, 4, 5, 6, 7, 8, 9, 10
 Joanne E. DeGroat, OSU
ECE265
3/29/2011
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