Memory • Memory technologies • Static RAM (SRAM): Flip-Flops – Fast, expensive, used for caches • Dynamic RAM (DRAM): Charge stored in capacitor – Leackage requires periodic refreshing (< 2ms), slower – High density, cheap and used for main memory. • EPROM, EEPROM: Charge stored in an isolated gate • Storage of charge with high voltage • Erase: via ultraviolet light (EPROM), or electrically (EEPROM, Flash ROM) • Non-volatile memory • PROM: Burning of fuses • ROM: contents inserted during production DRAM cell • Architecture of a DRAM cell • Read destroys information, therefore it has to be written back. • Cycle time (time between two accesses) is larger than access time. Architecture of a DRAM Chip Memory Organization of PCs • SDRAM (Synchronous DRAM) • Synchron: All signals (RAS, Adresse …) are combined with a fixed clock cycle (PC100, PC133 …). • Access via North Bridge or an integrated memory controller Frontside Bus Chip Select • Data width is 64 Bit oder 8 Bytes • Chip Select determines the row • The row provides 8 Bytes Address Data Control DIMM 1 or 2 rows (North Bridge) DIMM 1 or 2 rows Prozessor Chip Satz Memory Organization of PCs • Each row of a DIMM has 8 chips. • To provide 1 GB per row we use eight 1 Gbit SDRAM chips. • Each chip • 8 data wires • internally organized in 4 banks with 256 Mbit. Each bank is organized in eight memory arrays. Internal Organization of a GBit DRAM • 1 GBit or 128 MByte chips • 128 M = 227 • 27 adress lines • 11 (2K) column • 14 (16K) row • 2 (4) memory field 8 Bit width 1 Bit width 16K rows, 2K columns Access to DDR-SDRAM • Read , Burst length=8 • Burst Mode: transmission of 8 Bytes • DDR (Double Data Rate): Transmission with rising and falling edge of the clock signal • RAS-to-CAS-Delay (tRCD), CAS latency (tCL), RAS-to-PrechargeLatency (tRAS), Read-Cycle-time (tRC) • Precharge necessary because of differential lines Access to DDR-SDRAM, Page Hit • Read, Burst length=8, Page Hit • Page: Data in the amplifiers of a row • All amplifiers of all blocks in the same bank • Hit: Data from the same row are accessed. Access to DDR-SDRAM, Bank Overlap • Access to another bank can already start when the first burst is trasmitted. Example Configuration Frontside Bus (FSB800) • 200 MHz • Quadpumped • 4*64 Bit 6,4 GB/s DDR400 • 200 MHz • 400 MB/s DIMM (DDR400 chips) DIMM (PC3200) 3,2GB/s DIMM DIMM (PC3200) Prozessor i875P Zwei Kanäle mit je 3,2 GB/s RAMBUS • Rambus DRAM (RDRAM) is internally very similar to DDR SDRAM. • A point-to-point channel with higher clock rate and less pins in the memory controller is used. • Since Intel switched in 2003 to DDR RAM, RAMBUS was almost eliminated. • XDR-DRAM is used in the Sony PlayStation 3 • XDR2-DRAM is used in high-end graphics cards and 3D TVs. 12,8 GBytes/s bandwidth Static Memory • One bit is implemented by 6 MOSFET transistors • No refresh • Very fast access times. • Expensive compared to DRAM • Used for caches FLASH Memories • Write • A high voltage (10-13V) between gate and source lets electrons tunnel into the floating gate. • Read • The charge of the floating gate partially cancels the electric field from the control gate. • Thus, a higher voltage is required to make the channel conduct. • With a certain threshold voltage, the state of the transistor can be sensed. • High negative voltage removes the charge • Reset is done for 16 KB blocks. • Isolation is damaged by reset. NOR vs NAND Bit Line GroundSelectTransistor Bit LineSelectTransistor WordLine 0 WordLine 1WordLine 2 WordLine 3 WordLine 4 WordLine 5WordLine 6 WordLine 7 NAND • more compact since less wires, although more transistors N N N N N N N N N N N • read: offset power for other FETs P Bit Line WordLine 0 WordLine 1 WordLine 2 WordLine 3 WordLine 4 WordLine 5 NOR N N, GND N N, GND P N N, GND N Single and Multi Level Cells (SLC / MLC) • SLCs store one bit • MLCs store up to four bits • Instead of only checking the presence of the current, the strenght is sensed. Thus, more presice measurement is required. • The states are determined by the amount of charge in the floating gate. Thus, precise control of the charge deposit is required. • Higher density, lower cost • Larger bit error ratio • Lower write speeds, lower number of program-erase cycles and higher power consumption NAND Flash Performance • Organized in pages (512 or 2048 bytes) • Writes are performed to entire pages. • 200-300µs • Reset done in larger blocks • 1-2 ms • Reads are fast • 25 µs for 4KB NAND Flash Durability • 10.000 – 1.000.000 writes for each cell • Solution • Wear leveling: distribution of writes to same address over multiple cells. • Spare cells FLASH Usage • Solid State Disc (SSD) • Up to 512 GB (300 €), 1TB (800 €) • Up to 520 MB/s Lesen und 400 MB/s Schreiben • Lower energy consumtion in idle and active mode as normal discs • Comparison with HDD see resources in Mindmap • Hybrid Disc • Nonvolatile buffer for write accesses • Or used as permanent cache controlled by the OS • Turbo Speicher • PCIe-MiniCard from Intel to speedup boot process.