A State Element “Zoo”

Edge-Triggered D Flip-Flop

Master-slave design is expensive in transistor count

Same result can be had using a different design that
uses only 6 NANDs  6 * 4 = 24 transistors

Want to design a circuit that responds on the positive
edge of the clock pulse only

Positive Edge-Triggered D Flip-Flop
1
P3
P1
2
5
Q
6
Q
Clock
P2
3
D
4
P4

Analysis of Previous Flip-Flop

When Clock = 0



P1 = P2 = 1  Q and Q' remain unchanged
P4 = D' and P3 = D
When Clock transitions 0  1


P4 transmits thru gate 3  P2 = D
P3 transmits thru gate 2  P1 = D'


Q = D and Q' = D'
After the 0  1 transition of Clock


If D = 0 at edge of Clock  P4 = 1
regardless of any further D changes
If D = 1 at edge of Clock  P2 = P3 = 1
regardless of any further D changes
Clock = 1  P1 = D', P2 = D, P3 = D, P4 = D' (memory)
Clock transitions 1  0, back to P1 = P2 = 1 case (memory)
Clear and Preset Controls on MS FF


Active low clear and preset – asynchronous
operation on a Master-Slave D Flip-Flop


Preset = 0  Q = 1
Clear = 0  Q = 0
Preset
D
Q
Clock
Preset
Q
D
Q
Q
Clear
Clear

Clear and Preset Again

Same operation, but using an edge-triggered D FF
Preset
Preset
Q
D
Q
Clock
Q
Q
Clear
D
Clear

Synchronous Clear Control

Clear can also be done synchronously with the clock
Clear
D
D
Clock
Q
Q
Q
Q

Terms Reviewed

Latch


Gated latch



Latch with an control enable, called Clk
Two basic types: SR and D, both level sensitive
Master-slave flip-flop


Two NANDs (or NORs) used to store one bit
State changes only on clock edge; made from two gated D
latches
Edge-triggered flip-flop

Same as MS FF with fewer transistors

T Flip-Flop

Toggle flip-flop

Output toggles on clock edge

D = T'Q + TQ'
D
T
Clock
Q
Q
Q
Q
T
Q(t+1)
0
Q(t)
1
Q(t)'
T
Q
Q
JK Flip-Flop


JK behaves just like SR but
removes the S=R=1 problem


J
K
Q(t+1)
Output toggles on clock edge
when J = K = 1
0
0
Q(t)
0
1
0
D = JQ' + K'Q
1
0
1
1
1
Q(t)'
J
D
K
Clock
Q
Q
Q
Q
J
Q
K
Q

State Diagrams: D

The D flip-flop has the following state table


Note that changes on clock edge are always assumed
D
Q(t+1)
0
0
1
1
D
0
1
0
0
1
1
0
1
Q
The corresponding state diagram is

Q(t+1) = D
Again, transitions occurs only on a clock edge
1
0
0
1
0
1
characteristic equation

State Diagrams: T

The T flip-flop state table
T
T
Q(t+1)
0
Q(t)
1
0
1
0
0
1
1
1
0
Q
Q(t)'
Q(t+1) = TQ(t)' + T'Q(t) = T  Q(t)

The state diagram is
1
characteristic equation
0
0
1
1
0

State Diagrams: SR

The SR flip-flop state table
S
R
Q(t+1)
0
0
0
00
01
11
10
Q(t)
SR
Q
1
0
0
0
0
x
1
1
0
1
1
1
0
x
1
1
1
x
Q(t+1) = S + R'Q(t)

The state diagram is
10
0x
0
1
01
x0
characteristic equation

State Diagrams: JK


The JK flip-flop state table
J
K
Q(t+1)
0
0
0
static hazard!!
00
01
11
10
Q(t)
JK
Q
1
0
0
0
0
1
1
1
0
1
1
1
0
0
1
1
1
Q(t)'
Q(t+1) = J Q(t)' + K' Q(t), or
Q(t+1) = J Q(t)' + K' Q(t) + J K'
The state diagram is
1x
0x
0
1
x0
characteristic equation
x1

Characteristic Equations

Summary of the characteristic equations

How is the next state determined from the inputs and
current state?
Flip-flop
Characteristic Equation
D
Q(t+1) = D
T
Q(t+1) = T  Q(t)
SR
Q(t+1) = S + R' Q(t)
JK
Q(t+1) = J Q(t)' + K' Q(t)

Excitation Tables

Summary of the excitation tables

For each state transition Q(t)  Q(t+1), what input
combination(s) will produce that transition?
Q(t)
Q(t+1)
D
T
SR
JK
0
0
0
0
0x
0x
0
1
1
1
10
1x
1
0
0
1
01
x1
1
1
1
0
x0
x0

Common TTL Flip-Flops

7474 is a positive edge triggered D flip-flop


Active low Preset (PRN) and Clear (CLRN)
7473a is a negative edge triggered JK flop-flop

7473 is the master-slave version

positive edge triggered

Registers

A flip-flop stores one bit of information

When you want to store n bits  register



n flip-flops used
Clock is shared by all so action is synchronous with clock
edge
Some common register types




Simple register
Shift register
Parallel access shift register
Lots of counters: up counter, down counter, BCD counter,
ring counter, Johnson counter

Simple 4 Bit Register

A standard 4 bit register using D flip flops
Parallel output
Q3
D
Q
Q
Q2
D
Q
Q
Q1
D
Q
Q
Q0
D
Q
Q
Parallel input
Clock

4 Bit Register with Load Control

Controlling the load capability
Parallel output
Q3
D
Q
Q
Q2
D
Q
Q
Q1
D
Q
Q0
D
Q
Q
Q
Parallel input
Clock
Load

Simple Shift Register

Provide only serial in/out access
In
Clock
D
Q
Q
Q1
D
Q
Q
Q2
D
Q
Q
Q3
D
Q
Q
Q4
Out

Action of Shift Register

In
Q1
Q2
Q3
Q4 = Out
t0
1
0
0
0
0
t1
0
1
0
0
0
t2
1
0
1
0
0
t3
1
1
0
1
0
t4
1
1
1
0
1
t5
0
1
1
1
0
t6
0
0
1
1
1
t7
0
0
0
1
1
Can you use a level sensitive gated latch instead of
a flip-flop?

No!  The values would propagate during Clock = 1

Parallel Access Shift Register



Provide parallel data load
Provide parallel data read
Provide serial shift
D


Shift/Load = 0
 Shift right
Shift/Load = 1
 Load
Parallel output
Q3
Q
Q
Serial Shift/Load
input
Q2
D
Q
Q1
D
Q
Parallel input
Q
Q
Q0
D
Q
Q
Clock

Example Problem: General Shifter

Design a parallel access (parallel data in / out) shift
register that can load or shift either left or right –
choice dictated by a control signal


Then add the ability to "stay in memory"
Don't forget to connect serial in to both MSB and LSB
S1
S0
Function
0
0
memory
0
1
SHR
1
0
SHL
1
1
load

Solution: General Shifter
Parallel output
Q3
D
Q3
Q
D
Q
s1
s0
0 1 2 3
Q3
Q
D
Q
s1
s0
0 1 2 3
Q3
Q
D
Q
s1
s0
0 1 2 3
SRSI
Q
Q
s1
s0
0 1 2 3
SLSI
Parallel input
Clock

74164 Shifter

8 bit serial in / parallel out shifter (used in modems)



Active low clear (CLRN)
Data-in provided by AND(A,B)
Positive edge triggered shift right register

74165 Shifter

8 bit parallel in / serial out shifter (also used in
modems)



Active low asynchronous parallel load – output is H
CLKIH is an active high clock inhibit – memory state
Positive edge-triggered shift right register: SER is serial in

74194 Bi-Directional Shifter

4 bit bi-directional shifter with parallel load




Active low asynchronous clear
Shift Left Serial In (SLSI)
Shift Right Serial In (SRSI)
Positive edge-triggered

Asynchronous Counters

Up counter using T flip-flops

Count clock pulses
1
Clock
T
Q
T
Q


T
Q
Q0

Q
Q
MSB of count
Q
Q1
Q2
Q0 toggles on every 0  1 clock edge
Q1 toggles on every 1  0 transition of Q0
Q2 toggles on every 1  0 transition of Q1

Delays in Asynchronous Counters

Propagation delays slow this counting process!
1
T
Clock
Q
T
Q
Q
T
Q
Q0
Q
Q
Q1
Q2
Clock
Q0
Q1
Q2
Count
0
1
2
3
4
5
6
7
0

Asynch Modulo 8 Up Counter

This counter counts 000  001  …  111  000



Assumes output is in order Q2 Q1 Q0
Modulo 8 up counter
The lower order flip-flop is synchronized to the Clock


All other flip-flops are not – asynchronous
Also called ripple counter
1
Clock
T
Q
T
Q
Q
T
Q
Q0
Q
Q
Q1
Q2

Asynch Modulo 8 Down Counter

To count 111  110  …  001  000  111
1
T
Clock
Q
T
Q
Q
T
Q
Q0
Q
Q
Q1
Q2
Clock
Q0
Q1
Q2
Count
0
7
6
5
4
3
2
1
0

Synchronous Counters

Asynchronous counters are slow due to propagation
delays

Synchronous counters share the clock among all flip-flops
clock cycle
Q2
Q1
Q0
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
0
0
0
T0 = 1
T1 = Q0
T2 = Q1Q0
T3 = Q2Q1Q0
…
always toggle
toggle when Q0 = 1
toggle when Q1Q0 = 1
toggle when Q2Q1Q0 = 1

Mod 16 Synchronous Up Counter
1
Clock
T
Q
Q0
Q
T
Q
Q1
Q
T
Q
Q2
Q
T
Q
Q3
Q

Waveform for Mod 16 Up Counter
1
T
Q
Q
T
T
Q0
Clock
Q
Q1
Q
Q
T
Q2
Q
Q3
Q
Q
Clock
Q0
Q1
Q2
Q3
Count 0
1
2
3
4
5
6
7
8
9
10 11
12 13
14 15
0
1

Adding Clear and Enable Signals


Just use T flip-flop with asynchronous clear
Cascade the Enable via AND gates to the T inputs

Enable
Clock
Clear
Recall: T toggle only when T input = 1
T
Q
Q
T
Q
Q
T
Q
Q
T
Q
Q

4 Bit Up Counter Using D Flip-Flops

How can you make an up counter using D flip-flops?
clock cycle
Q2
Q1
Q0
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
0
0
0
D0 = 1  Q0
D1 = Q1  Q0
D2 = Q2  Q1Q0
D3 = Q3  Q2Q1Q0
…
always toggle
toggle when Q0 = 1
toggle when Q1Q0 = 1
toggle when Q2Q1Q0 = 1

4 Bit Up Counter
Enable
D Q
Q0
Q

Enable input permits
control of counter
D Q
Q1
Q

Output carry permits
chaining of counters
to make larger ones
D Q
Q2
Q
D Q
Q3
Q
Clock
Output
carry

Counter With Parallel Load

Want a counter that
can load any initial
value that you desire
in order to start the
count



Enable
D0
0
1
D1
0
1
DQ
Q0
Q
DQ
Q1
Q
Load = 1  load
D2
Enable = 1  increment
Load = Enable = 0  memory
D3
Load
Clock
0
1
DQ
Q2
Q
0
1
DQ
Q3
Q
Output
carry

Mod n Counting for n  2k

Most counters reset (cycle) to 0 when all k flip-flops
are 1  value of count = 2k-1

Mod 8 counter: k = 3


000  001  010  …  111  000
How to synchronously reset when value < 2k-1?

Want to allow something like:


000  001  …  101  000
This is a mod 6 counter

Mod 6 Synchronous Up Counter

When output = Q2Q1Q0 = 101, load 000 to force
reset on next clock edge

This provides a synchronous reset
1
Enable
0
D0
Q0
0
D1
Q1
0
D2
Q2
Load
Clock
Clock

Other Counter Types

BCD Counter


Count from 0 to 9 and back to 0
Cascade the counters to mimic decimal counting



Ring Counter



00  01  … 09  10  11  …  19  20  …
Each position is a BCD digit
4 bit ring count: 1000  0100  0010  0001  1000 …
One-hot output that cycles in a ring
Johnson Counter

4 bit count: 0000  1000  1100  1110  1111  0111
 0011  0001  0000 …

2 Digit BCD Counter
1
0
0
0
0
Enable
D0
D1
D2
D3
Q0
Q1
Q2
Q3
BCD 0
Load
Clock
Clock
Clear
0
0
0
0
Enable
D0
D1
D2
D3
Load
Clock
Is 1 when 1xx1 is detected
-- first time is for 1001 = 9
Q0
Q1
Q2
Q3
BCD 1

4 Bit Ring Counter Using a Decoder

Counts 1000  0100  0010  0001  1000 …

Ring Counter Using D Flip-Flops

A design that uses a minimum of combinational
logic, but uses more flip-flops
asynchronous preset
Q0
Q1
Qn – 1
Start
D
Q
Q
D
Q
Q
D
Q
Q
Clock
asynchronous clear

Johnson Counter

n-bit counter that generates a sequence of length 2n

0000  1000  1100  1110  1111  0111  0011 
0001  0000 ….
Q0
D
Q
Q
Reset
Clock
Q1
D
Q
Q
Qn – 1
D
Q
Q
pushes the initial 1
into the count
CAD for Sequential Circuits

Verilog for Sequential Circuits

Sequential circuits are modeled in an always block

Example of an implied memory element

The gated D latch
Verilog assumes the value of Q
must be maintained if Clk is 0 and
therefore synthesizes a latch

Verilog for D Flip-Flop

Sensitivity list needs to specify clock edge, not just
change in level

Can specify: posedge or negedge
Verilog will use flip-flops to synthesize
circuits that are edge-triggered

Verilog for T and JK Flip-Flops

Negative edge triggered versions

Also provides complemented outputs

Verilog Example
treated as g = (x1 & x2) | x3
x3
x1
D
Q
g
x2
Q
D
Clock
Q
Q
f

Verilog Example: Reversed Order
Order matters inside an always block!
x3
D
Q
g
Q
x1
x2
Clock
D
Q
Q
f

Blocking Assignments

The order of statements inside an always block can
affect the synthesized design

All previous examples use blocking assignments


Verilog evaluates the assignments in an always block in the
order in which they are written
This can cause unexpected designs
D
D
Clock
Q1
Q
D
treated as Q2 = D since Q1 = D
Q
Q
Q
Q2

Non-Blocking Assignments

What if you wanted a “cascaded” design for the
previous example?


The assignment to Q2 should be from the “previous” Q1
Need both assignments to occur in parallel on the same
clock edge

The LHS of a non-blocking assignment is updated after all
RHS values for all assignments have been evaluated
D
Clock
non-blocking assignment
D
Q
Q
Q1
D
Q
Q
Q2

Non-Blocking Example
Compare this to the earlier example
using blocking assignments
x3
D
Q
g
Q
x1
x2
Clock
D
Q
Q
f

Verilog Coding Tips

Use blocking assignments when designing
combinational logic

Non-blocking is OK when doing finite state machine (FSM)
design (to be covered later)

Use non-blocking assignments when designing
sequential logic (including for latches)

Do not mix blocking and non-blocking assignments
in the same always block

Use separate always blocks for this, if needed

Adding Asynchronous Clear

The sensitivity list cannot mix edge triggered and
level sensitive events

Must make reset edge-triggered, but on a different edge

Synchronous Clear

The only change is in the sensitivity list

ResetN overrides the input

Verilog for N-Bit Register

Verilog for N-Bit Register With Load

Add a load enable input

Verilog for 4-Bit Shift Register
Parallel output

One technique: build a
simple 2X1 MUX
controlled D flip-flop
Q3
Q2
Q1
Q0
D Q
D Q
D Q
D Q
Q
Q
Q
Q
Serial Shift/Load
input
Parallel input
Provide parallel access (including
load) and shift right
Clock

4-Bit Shift Register: Continued
A hierarchical design mixing
behavioral and structural styles

N-Bit Shift Register: Behavioral Style

N-Bit Up Counter

Provide an n-bit up counter with asynchronous clear
and an enable control

N-Bit Up Counter With Load

Provide an n-bit up counter with asynchronous clear,
an enable control, and parallel load

N-Bit Up/Down Counter With Load

Alternate Version of U/D Counter
blocking assignments are executed
before non-blocking ones

Good Coding Style

As a matter of good coding style …

Do not mix blocking and non-blocking assignments in the
same always block

It may work, but you may confuse yourself!

Use separate always blocks when you need both types

Repeating earlier rules …

Use blocking assignments for combinational logic

Use non-blocking assignments for sequential logic, and
latches

Best Version of U/D Counter
This style separates
blocking and non-blocking
assignments into separate
always blocks