Array Structured Memories STMicro/Intel UCSD CAD LAB Weste Text EE141 STMicro/Intel/UCSD/THNU 1 Memory Memory Arrays Memory Arrays Random Access Memory Read/Write Memory (RAM) (Volatile) Static RAM (SRAM) Dynamic RAM (DRAM) Mask ROM Programmable ROM (PROM) Read Only Memory (ROM) (Nonvolatile) Shift Registers Serial In Parallel Out (SIPO) Erasable Programmable ROM (EPROM) EE141 STMicro/Intel/UCSD/THNU Content Addressable Memory (CAM) Serial Access Memory Queues Parallel In Serial Out (PISO) Electrically Erasable Programmable ROM (EEPROM) First In First Out (FIFO) Last In First Out (LIFO) Flash ROM 2 Memory Feature Comparison Between Memory Types EE141 STMicro/Intel/UCSD/THNU 3 Memory Array Architecture 2n words of 2m bits each If n >> m, fold by 2k into fewer rows of more columns wordlines bitline conditioning bitlines row decoder memory cells: 2n-k rows x 2m+k columns n-k column circuitry k n column decoder 2m bits Good regularity – easy to design Very high density if good cells are used EE141 STMicro/Intel/UCSD/THNU 4 Memory Memory - Real Organization Array of N x K words S0 C of M bit words row 0 C of M bit words row 1 C of M bit words row 2 C of M bit words row N-2 C of M bit words row N-1 Row Decoder SR-1 Log2C Address Lines ------------- rows R------------ Log2R Address Lines ------------- columns ------------ KxM - - - - KxM bits - - - - Column Select M bit data word EE141 STMicro/Intel/UCSD/THNU 5 Memory Hierarchical Memory Architecture Ro w A d d r ess Co lu m n A d d r ess Blo ck A d d r ess G lo b al D ata Bu s C o n tro l B lo ck S electo r Circu itry G lo b al A m p lifier /D riv er I/O A dv a n t a g es: 1 . S h o rter w ire s w ith in b lo ck s 2 . B lo ck a d d ress a ctiv a t es o n ly 1 b lo ck = > p o w er sa v in g s EE141 STMicro/Intel/UCSD/THNU 6 Memory Array Organization Design Issues aspect ratio should be relative square Row / Column organisation (matrix) R = log2(N_rows); C = log2(N_columns) R + C = N (N_address_bits) number of rows should be power of 2 number of bits in a row need not be… sense amplifiers to speed voltage swing 1 -> 2R row decoder 1 -> 2C column decoder M column decoders (M bits, one per bit) – M = output word width EE141 STMicro/Intel/UCSD/THNU 7 Memory Simple 4x4 SRAM Memory read precharge enable bit line precharge BL !BL A1 2 bit width: M=2 R = 2 => N_rows = 2R = 4 C=1 A2 c N_columns = 2 x M = 4 N=R+C=3 Array size = N_rows x N_columns = 16 WL[0] WL[1] WL[2] WL[3] A0 A0! clocking and control -> Column Decoder sense amplifiers WE! , OE! EE141 STMicro/Intel/UCSD/THNU write circuitry 8 Memory SRAM Read Timing (typical) tAA (access time for address): time for stable output after a change in address. tACS (access time for chip select): time for stable output after CS is asserted. tOE (output enable time): time for low impedance when OE and CS are both asserted. tOZ (output-disable time): time to high-impedance state when OE or CS are negated. tOH (output-hold time): time data remains valid after a change to the address inputs. EE141 STMicro/Intel/UCSD/THNU 9 Memory SRAM Read Timing (typical) stable ADDR stable stable tAA Max(tAA, tACS) CS_L tOH tACS OE_L tAA DOUT tOZ valid tOE tOZ valid tOE valid WE_L = HIGH EE141 STMicro/Intel/UCSD/THNU 10 Memory SRAM Architecture and Read Timings tOH tAA tACS tOZ tOE EE141 STMicro/Intel/UCSD/THNU 11 Memory SRAM write cycle timing ~WE controlled ~CS controlled EE141 STMicro/Intel/UCSD/THNU 12 Memory SRAM Architecture and Write Timings Setup time = tDW tDH Write driver tWP-tDW EE141 STMicro/Intel/UCSD/THNU 13 Memory SRAM Cell Design Memory arrays are large Need to optimize cell design for area and performance Peripheral circuits can be complex – 60-80% area in array, 20-40% in periphery Classical Memory cell design 6T cell full CMOS 4T cell with high resistance poly load TFT load cell EE141 STMicro/Intel/UCSD/THNU 14 Memory Anatomy of the SRAM Cell Write: •set bit lines to new data value •b’ = ~b •raise word line to “high” •sets cell to new state •Low impedance bit-lines EE141 STMicro/Intel/UCSD/THNU Read: •set bit lines high •set word line high •see which bit line goes low •High impedance bit lines 15 Memory SRAM Cell Operating Principle •Inverter Amplifies •Negative gain •Slope < –1 in middle •Saturates at ends • Inverter Pair Amplifies •Positive gain •Slope > 1 in middle •Saturates at ends EE141 STMicro/Intel/UCSD/THNU 16 Memory Bistable Element Stability § Require Vin = V2 § Stable at endpoints recover from pertubation § Metastable in middle Fall out when perturbed Ball on Ramp Analogy EE141 STMicro/Intel/UCSD/THNU 17 Memory Cell Static Noise Margin Cell state may be disturbed by •DC •Layout pattern offset •Process mismatches •non-uniformity of implantation •gate pattern size errors •AC •Alpha particles •Crosstalk •Voltage supply ripple •Thermal noise EE141 STMicro/Intel/UCSD/THNU SNM (static noise margin) = Maximum Value of Vn not flipping cell state 18 Memory SNM: Butterfly Curves 1 SNM 2 2 SNM 1 2 1 EE141 STMicro/Intel/UCSD/THNU 1 2 19 Memory SNM for Poly Load Cell EE141 STMicro/Intel/UCSD/THNU 20 Memory 12T SRAM Cell Basic building block: SRAM Cell 1-bit/cell (noise margin again) bit write write_b read read_b 12-transistor (12T) SRAM cell Latch with TM-gate write Separately buffered read EE141 STMicro/Intel/UCSD/THNU 21 Memory 6T SRAM Cell Cell size accounts for most of array size Reduce cell size at cost of complexity/margins 6T SRAM Cell Read: Precharge bit, bit_b Raise wordline bit bit_b word Write: Drive data onto bit, bit_b Raise wordline EE141 STMicro/Intel/UCSD/THNU 22 Memory SRAM Design TI 65nm: 0.46x1.06um2 IBM 65nm: 0.41x1.25um2 Intel 65nm: 0.46x1.24um2 * Figures courtesy A. Chatterjee et al., P. Bai et al., and Z. Luo et al., Int. Electron Device Meeting Tech. Digest, 2004 EE141 STMicro/Intel/UCSD/THNU 23 Memory Vertical 6T Cell Layout B- B+ N Well Connection VDD PMOS Pull Up Q/ Q NMOS Pull Down GND SEL SEL MOSFET Substrate Connection EE141 STMicro/Intel/UCSD/THNU 24 Memory SRAM Bitcell Design WL VSS VDD PU1 NL BL PU2 PG1 PU2 NR PG2 PD2 PG1 PD1 VDD WL NL NL NR NR PD2 WL PD1 PU1 PG2 VSS BLB BL BLB Schematic Requirements VDD VSS Layout Micrograph of SRAM bitcell design Stable read operation: Do not disturb data when reading Stable write operation: Must write data within a specified time Stable data retention: Data should not be lost Typical transistor sizing Cell ratio (= I(PD) / I(PG)) = 1.5 ~ 2.5 Pull-up ratio (= I(PU) / I(PG)) = 0.5 EE141 STMicro/Intel/UCSD/THNU 25 Memory Detailed SRAM Bitcell Layout – Vertical: 2 poly pitch – Horizontal: 5 contact pitch – Poly-to-contact space > overlay + spacer + strain_layer + CD_control (6.4nm*) ( 8nm**) (10nm**) ( 2.6nm*) = 27nm – 1 poly pitch = 2 poly_to_contact + poly_width + contact_width 54 + 32 + 45** = 131 nm A pitch is a multiple of a drawing grid for fine-grain pattern placement Ex.: 5 grid per pitch drawing grid = (131/5) = 26 nm poly CNT * From ITRS 32nm tech. Ex.: 6 grid per pitch drawing grid = (131/6) =Verhaegen 22 nm ** From S. et al., spacer SPIE Adv. Litho., 2008 Strain layer EE141 STMicro/Intel/UCSD/THNU 26 Memory SRAM Read bit_b bit word Precharge both bitlines high Then turn on wordline One of the two bitlines will P1 P2 N2 N4 A A_b N1 N3 be pulled down by the cell bit discharges, bit_b stays high But A bumps up slightly A_b Ex: A = 0, A_b = 1 Read stability A must not flip N1 >> N2 EE141 STMicro/Intel/UCSD/THNU bit_b 1.5 1.0 bit word 0.5 A 0.0 0 100 200 300 400 500 time (ps) 27 Memory 600 bit_b bit word P1 P2 N2 A N4 A_b N1 N3 SRAM Read, 0 is stored in the cell EE141 STMicro/Intel/UCSD/THNU 28 Memory SRAM Write bit_b bit word P1 P2 N2 Drive one bitline high, other low A N1 Then turn on wordline Bitlines overpower cell Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high Writability A_b Must overpower feedback bit_b P2 << N4 to force A_b low, N1 turns off, P1 turns on, word raise A high as desired 1.5 N4 A_b N3 A 1.0 0.5 0.0 0 100 200 300 400 500 600 700 time (ps) EE141 STMicro/Intel/UCSD/THNU 29 Memory SRAM Sizing High bitlines must not overpower inverters during reads But low bitlines must write new value into cell bit bit_b word weak med med A A_b strong EE141 STMicro/Intel/UCSD/THNU 30 Memory SRAM Column Example read write Bitline Conditioning 2 More Cells word_q1 bit_b_v1f bit_v1f SRAM Cell write_q1 data_s1 EE141 STMicro/Intel/UCSD/THNU 31 Memory Decoders n:2n decoder consists of 2n n-input AND gates One needed for each row of memory Build AND from NAND or NOR gate choose minimum size to reduce load on the address lines A1 A0 A1 1 1 8 A1 1 4 A0 1 word A0 A0 1/2 4 16 A1 1 1 2 8 word0 word0 word1 word1 word2 static word3 EE141 STMicro/Intel/UCSD/THNU word Pseudo-nMOS word2 word3 32 Memory Single Pass-Gate Mux A1 A0 B0 B1 B2 B3 bitlines propagate through 1 transistor Y EE141 STMicro/Intel/UCSD/THNU 33 Memory Decoder Layout Decoders must be pitch-matched to SRAM cell Requires very skinny gates A3 A3 A2 A2 A1 A1 A0 A0 VDD word GND NAND gate EE141 STMicro/Intel/UCSD/THNU buffer inverter 34 Memory Large Decoders For n > 4, NAND gates become slow Break large gates into multiple smaller gates A3 A2 A1 A0 word0 word1 word2 word3 word15 EE141 STMicro/Intel/UCSD/THNU 35 Memory Predecoding Many of these gates are redundant Factor out common gates into predecoder Saves area Same path effort A3 A2 A1 A0 predecoders 1 of 4 hot predecoded lines word0 word1 word2 word3 word15 EE141 STMicro/Intel/UCSD/THNU 36 Memory EE141 STMicro/Intel/UCSD/THNU 37 Memory Column Circuitry Some circuitry is required for each column Bitline conditioning Sense amplifiers Column multiplexing Each column must have write drivers and read sensing circuits EE141 STMicro/Intel/UCSD/THNU 38 Memory Column Multiplexing Recall that array may be folded for good aspect ratio Ex: 2k word x 16 folded into 256 rows x 128 columns Must select 16 output bits from the 128 columns Requires 16 8:1 column multiplexers EE141 STMicro/Intel/UCSD/THNU 39 Memory Typical Column Access EE141 STMicro/Intel/UCSD/THNU 40 Memory Pass Transistor Based Column Decoder A1 A0 2 input NOR decoder BL3 !BL3 BL2 !BL2 S3 S2 S1 S0 Data BL1 !BL1 BL0 !BL0 !Data Advantage: speed since there is only one extra transistor in the signal path Disadvantage: large transistor count EE141 STMicro/Intel/UCSD/THNU 41 Memory Tree Decoder Mux Column MUX can use pass transistors Use nMOS only, precharge outputs One design is to use k series transistors for 2k:1 mux No external decoder logic needed B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A0 A1 A1 A2 A2 Y to sense amps and write circuits EE141 STMicro/Intel/UCSD/THNU Y 42 Memory Ex: 2-way Muxed SRAM 2 More Cells More Cells word_q1 2-to-1 mux A0 A0 write0_q1 2 write1_q1 data_v1 EE141 STMicro/Intel/UCSD/THNU two bits from two cells and selected by A0 43 Memory Bitline Conditioning Precharge bitlines high before reads bit bit_b bit bit_b Equalize bitlines to minimize voltage difference when using sense amplifiers EE141 STMicro/Intel/UCSD/THNU 44 Memory Sense Amplifier: Why? Bit line cap significant for large array If each cell contributes 2fF, – for 256 cells, 512fF plus wire cap Pull-down resistance is about 15K RC = 7.5ns! (assuming DV = Vdd) Cell pull down Xtor resistance RC D V V dd Cannot easily change R, C, or Vdd, but can change Cell current DV i.e. smallest sensed voltage Can reliably sense DV as small as <50mV EE141 STMicro/Intel/UCSD/THNU 45 Memory Sense Amplifiers Bitlines have many cells attached Ex: 32-kbit SRAM has 256 rows x 128 cols 128 cells on each bitline tpd (C/I) DV Even with shared diffusion contacts, 64C of diffusion capacitance (big C) Discharged slowly through small transistors (small I) Sense amplifiers are triggered on small voltage swing (reduce DV) EE141 STMicro/Intel/UCSD/THNU 46 Memory Differential Pair Amp Differential pair requires no clock But always dissipates static power sense_b bit P1 N1 P2 N2 sense bit_b N3 EE141 STMicro/Intel/UCSD/THNU 47 Memory Clocked Sense Amp Clocked sense amp saves power Requires sense_clk after enough bitline swing Isolation transistors cut off large bitline capacitance bit bit_b isolation transistors sense_clk regenerative feedback sense EE141 STMicro/Intel/UCSD/THNU sense_b 48 Memory Sense Amp Waveforms 1ns / div bit 200mV wordline bit’ wordline begin precharging bit lines 2.5V BIT BIT’ sense clk sense clk EE141 STMicro/Intel/UCSD/THNU 49 Memory Write Driver Circuits EE141 STMicro/Intel/UCSD/THNU 50 Memory Dual-Ported SRAM Simple dual-ported SRAM Two independent single-ended reads bit Or one differential write bit_b wordA wordB wordA reads bit_b (complementary) wordB reads bit (true) Do two reads and one write by time multiplexing EE141 STMicro/Intel/UCSD/THNU Read during ph1, write during ph2 51 Memory Multiple Ports We have considered single-ported SRAM One read or one write on each cycle Multiported SRAM are needed for register files Examples: Multicycle MIPS must read two sources or write a result on some cycles Pipelined MIPS must read two sources and write a third result each cycle Superscalar MIPS must read and write many sources and results each cycle EE141 STMicro/Intel/UCSD/THNU 52 Memory Multi-Ported SRAM Adding more access transistors hurts read stability Multiported SRAM isolates reads from state node Single-ended design minimizes number of bitlines bA bB bC bD bE bF bG wordA wordB wordC wordD wordE wordF wordG write circuits read circuits EE141 STMicro/Intel/UCSD/THNU 53 Memory Logical effort of RAMs EE141 STMicro/Intel/UCSD/THNU 54 Memory EE141 STMicro/Intel/UCSD/THNU 55 Memory Twisted Bitlines Sense amplifiers also amplify noise Coupling noise is severe in modern processes Try to couple equally onto bit and bit_b Done by twisting bitlines b0 b0_b b1 b1_b b2 b2_b b3 b3_b EE141 STMicro/Intel/UCSD/THNU 56 Memory Alternative SRAM Cells Low Voltage/High Leakage/Process Variations crowd the operating margins of conventional SRAM Alternative Sense Amplifiers, column and row arrangements, adaptive timing, smaller hierarchy, redundant and spare rows/columns have all been addressed in the literature with some success. Some problems come from the cell design itself– modifying the cell can break conflicting demands for optimization EE141 STMicro/Intel/UCSD/THNU 57 Memory 10T Features BL Leakage reduction Approaches Separated Read port Stacked effect by M10 Performance 400mV@475kHz, 3.28uW 320mV W/O Read error@27℃ 380mV W/O Write error@27℃ Vmin=300mV@1% bit errors 256 bits/BL A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation B. Calhoun & A. Chandrakasan, JSSC, 2007 EE141 STMicro/Intel/UCSD/THNU 58 Memory 10T Features BL leakage reduction of data Approaches Virtual GND Replica Reverse Short Channel Effect BL Writeback Performance 0.2V@100kHz, 2uW 1024 bits/BL 130nm process technology A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme Chris Kim, ISSCC, 2007 59 EE141 STMicro/Intel/UCSD/THNU Memory 10T Features ST cell array can work @160mV 2.1x larger than 6T cell Approaches Schmitt Trigger based cell Good stability @ LowVDD Good scalability Performance Read SNM↑1.56x @VDD=0.4V More power saving Leakage power↓18% Dynamic power↓50% Hold SNM @150mV is 2.3x of 6T 130nm process A 160mV Robust Schmitt Trigger Based Subthreshold SRAM K. Roy, JSSC, 2007 60 EE141 STMicro/Intel/UCSD/THNU Memory 9T Features Modifying from 10Tcell 17% more area than 6T cell 16.5% less area than 10T cell Approaches More leakage saving than 8T cell Separated read port Performance 128 bits/BL @350mV ,100MHz Hold SNM=117mV @300mV Stand-by power: 6uW 65nm process A 100MHz to 1GHz, 0.35V to 1.5V Supply 256x64 SRAM Block using Symmetrized 9T SRAM cell with controlled Read S. A. Verkila,et al, Conference on VLSI Design, 2008 EE141 STMicro/Intel/UCSD/THNU 61 Memory 9T Features Read stability enhancement Leakage power reduction Approaches Separated read port Min. sizing of N3, N4 and negative Vg7, and larger Node3 during stand-by mode for leakage reduction Performance 2x R-SNM cf. 6T 22.9% leakage power reduction 65 nm PTM High Read Stability and Low Leakage Cache Memory Cell Z. Liu and V. Kursun, IEEE Conference, 2007 EE141 STMicro/Intel/UCSD/THNU 62 Memory 8T Features No read disturb About 30% area penalty Approaches Separate Read & Write WL Separated read port Performance Larger SNM than 6T Better scalability than 6T Stable SRM Cell Design for the 32nm Node and Beyond Leland Chang et. al, 63 Symp. on VLSI,2005 Memory EE141 STMicro/Intel/UCSD/THNU 8T Features No read disturb Low VDD(350mV) Low subthreshold(Sub. Vt) leakage Approaches Separate Read &Write WL Separated read port Foot-drivers reduce the sub.Vt leakage Performance 65nm process ,128 cells/row Operating @ 25KHz 2.2uW leakage power A 256kb 65nm 8T Subhreshold SRAM Employing Sense-Amplifier Redundancy N. Verma ,and A. P. Chandrakasan, JSSC,2008 64 EE141 STMicro/Intel/UCSD/THNU Memory 7T Features 23% smaller than Conv. 6T bitcell Low VDD(440mV) Not suit for low speed demand Approaches Separate Read &Write WL Seperate Read &Write BL Data protection nMOS:N5 Performance 20ns access time@0.5V 90nm process A Read-Static-Noise-Margin-Free SRAM Cell forLow-VDD and High-Speed Applications NEC, JSSC, 2006 EE141 STMicro/Intel/UCSD/THNU 65 Memory 7T Features 90% power saving Approaches BL swing: VDD/6 Performance 0.35um proces Leakage not controlled well 90% Write Power-Saving SRAM Using Sense-Amplifying Memory Cell T. Sakurai et. al., JSSC, 2004 EE141 STMicro/Intel/UCSD/THNU 66 Memory 7T Features Low write power SNM is effected by “Read pattern” (Read 0-N2,P2,N4 & Read 1N1,P1,N3,N5) 17.5% larger than 6T Approaches Reducing write power by cut off the (feedback) connection to BL Performance 0.18um proces 49% write power saving Novel 7T SRAM Cell For Low Power Cache Design R. Aly, M. Faisal and A. Bayoumi IEEE SoC Conf., 2005 EE141 STMicro/Intel/UCSD/THNU 67 Memory 6T • Features – Single-ended – Low VDD • Approaches – Adjustable header/footer (virVDD, virGND) • Performance – VDD range: 1.2V~193mV – Vmin=170mV with 2% redundancy BL WL WL A Sub-200mV 6T SRAM in 0.13μm CMOS 68 ISSCC, 2007 Memory EE141 STMicro/Intel/UCSD/THNU 5T • Features – Single-ended – Single BL, Single WL – Area 23% smaller than 6T • Approaches – BL precharge to Vpc=600mV – Asymmetric cell sizing – Differential SA is used for Read • Performance – 75% BL leakage reduction cf. 6T – SNM is 50% lower than the 6T’s – 0.18um process High-skewed Inverter Low-skewed Inverter A High Density, Low Leakage, 5T SRAM for Embeded Caches I. Carlson et.al., ESSCIRC, 2004 69 Memory EE141 STMicro/Intel/UCSD/THNU Example Electrical Design: UCSD 32nm prototype • Butterfly (read stability) • SPICE Model: • N-curves (read and write stability) – 32nm HKMG (high• Iread (read stability and access K/metal-gate) from time) PTM • VDDHOLD (data retention) • Reference Design • Ileakage (power and data retention) – Scaled bitcell from TSMC 90nm bitcell TSMC 90nm 32nm scaled from TSMC 90nm (REFERENCE) 32nm proposed (for 30x12, 25x12) L (nm) W (nm) L (nm) W (nm) L (nm) W (nm) Pull-up 100 100 32 32 32 44 Pull-down 100 175 32 56 32 88 Pass-Gate 115 120 37 38 32 44 EE141 STMicro/Intel/UCSD/THNU 70 Memory Butterfly and N-Curves • Measure method – Increase VR and measure VL – Increase VL and measure VR – Make voltage transfer curve in VR and VL axes Butterfly – Measure Iin N-curve EE141 STMicro/Intel/UCSD/THNU 71 Memory Iread, Ileakage and VDDHOLD Iread Measure bitline current when WL switches to high ILEAKAGE Measure VDD (or VSS) current when WL=0 VDDHOLD Decreasing VDD voltage, while WL=0 Measure minimum VDD voltage when | V(nl) - V(nr) | = ‘sensing margin’ WL VDD A1 C1 ‘1’ nl B1 A2 nr C2 ‘0’ B2 BL ‘1’ BLb ‘1’ (100mV is assumed) REFERENCE 32nm proposed (for 30x12 and 25x12) Iread 41.2 uA 66.7 uA Ileakage 85.4 nA 142.7 nA VDDHOLD 110 mV 118 mV EE141 STMicro/Intel/UCSD/THNU 72 Memory Corner Simulation: Butterfly and NCurve 1.20E+00 1.20E+00 1.20E+00 • Three candidate layouts across operating corners show little difference 1.00E+00 8.00E-01 25x10, NN, 25degC 25x12, NN, 25degC 30x12, NN, 25degC 1.00E+00 8.00E-01 8.00E-01 6.00E-01 6.00E-01 6.00E-01 4.00E-01 4.00E-01 4.00E-01 2.00E-01 2.00E-01 2.00E-01 0.00E+00 0 0.2 0.4 0.6 0.8 1 1.2 1.0E-04 0.0E+00 -5.0E-05 -1.0E-04 1 6 11 16 21 26 31 36 41 46 51 56 61 66 71 76 81 86 91 96 101 5.0E-05 25x10 25x12 30x12 (SS, 125degC, 1.0V) 0.00E+00 0 0.2 0.4 0.6 0.8 1 1.2 0 1.0E-04 1.0E-04 5.0E-05 5.0E-05 0.0E+00 0.0E+00 1 6 11 16 21 26 31 36 41 46 51 56 61 66 71 76 81 86 91 96 101 0.00E+00 25x10, FF, -40degC 25x12, FF, -40degC 30x12, FF, -40degC 1.00E+00 -5.0E-05 -1.0E-04 -1.5E-04 0.4 0.6 0.8 1 1.2 -5.0E-05 25x10 25x12 30x12 (NN, 25degC, 1.0V) EE141 STMicro/Intel/UCSD/THNU 0.2 1 6 11 16 21 26 31 36 41 46 51 56 61 66 71 76 81 86 91 96 101 25x10, SS, 125degC 25x12, SS, 125degC 30x12, SS, 125degC -1.0E-04 -1.5E-04 25x10 25x12 30x12 (FF, -40degC, 1.0V) 73 Memory Corner Simulation: Iread , Ileakage and VDDHOLD Ileakage (A) Iread (A) 1.00E-04 1.80E-04 1.60E-04 FF, -40 25x10 1.40E-04 FF, -40 25x12 1.20E-04 FF, -40 30x12 1.00E-04 NN, 25 25x10 8.00E-05 NN, 25 25x12 NN, 25 30x12 6.00E-05 SS, 125 25x10 4.00E-05 SS, 125 25x12 2.00E-05 FF, -40 25x10 1.00E-05 FF, -40 25x12 1.00E-06 FF, -40 30x12 NN, 25 25x10 1.00E-07 NN, 25 25x12 NN, 25 30x12 1.00E-08 SS, 125 25x10 SS, 125 25x12 1.00E-09 SS, 125 30x12 SS, 125 30x12 0.00E+00 1.00E-10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 VDDHOLD (V) VDD (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 0.13 0.128 0.126 0.124 0.122 0.12 0.118 0.116 0.114 0.112 25x10 25x12 30x12 25x10 25x12 30x12 25x10 25x12 30x12 FF, -40 EE141 STMicro/Intel/UCSD/THNU NN, 25 SS, 125 74 Memory