Instructor: Yuzhuang Hu
yhu1@cs.sfu.ca
State-Machine Diagrams contd.
(Chapter 5, Section 5-7)
 Use boolean expressions to simplify the diagram.
Inputs: A, B
Outputs: Y, Z
Defaults: Y=0,Z=0
B/Y
Reset
S0
A
AB
A
S3
Z
(A+B)/Y
AB
Y,Z
AB
S1
(A+B)/Z
A
S2
B/Y
Input Conditions in State-Machine
Diagrams
 Input condition: boolean expression or equation in
terms of input variables.
 Transition condition (TC): an input condition on a
transition arc, and causes a state transition to occur.
 Unconditional transition: always occurs on the next
clock. It can be thought of as having an implicit
transition condition equal to 1.
Output Conditions in StateMachine Diagrams

Output condition (OC): an input condition that, if equal to 1,
causes an output action to occur.




Moore output actions: unconditional for each state.
Transition-condition independent (TCI) Mealy output
actions: depend on only states.
Transition-condition dependent (TCD) Mealy output actions:
depend on both the state and a transition condition.
Transition and output condition dependent (TOCD) output
actions: depend on the state, a transition condition, and an
output condition. There is a slash between such an output action
with its associated output condition.
Constraints on Input Conditions
 The transition conditions from a given state Si must be
mutually exclusive. An invalid example:
Inputs: A, B
Outputs: Y, Z
Defaults: Y=0,Z=0
A
AB
S
Y,Z
B
 The transition conditions from a given state must cover
all possible combinations of input values.
Constraints on Output Conditions
 For every output action in state Si or on its transitions having
coincident output variables with differing values, the corresponding
pair of output conditions must be mutually exclusive. An invalid
example:
Z
Inputs: A, B
Outputs: Y, Z
Defaults: Y=0,Z=0
A
AB
S
Y,Z
AB
 For every output variable, the output conditions for state Si or its
transitions must cover all possible combinations of input values that
can occur.
State-Machine Design of a
Sliding Door Control
Input
Symbol
Name
Meaning for Value 1
Meaning for Value 0
LK
Lock with Key
Locked
Unlocked
DR
Door Resistance Sensor
Door resistance >= 15 lb
Door resistance < 15 lb
PA
Approach Sensor
Person/object approach
No person/object
approach
PP
Presence Sensor
Person/object in door
No person/object in
door
MO
Manual Open PB
Manual open
No manual open
CL
Close Limit Switch
Door fully closed
Door not fully closed
OL
Open Limit Switch
Door fully open
Door not fully open
Sliding Door Control contd.
Output Symbol
Name
Meaning for
Value 1
Meaning for
Value 0
BT
Bolt
Bolt closed
Bolt open
CD
Close Door
Close door
Null action
OD
Open Door
Open door
Null action
 What states should we consider?
State-Machine Diagram for the
Automatic Sliding Door
BT
Defaults: BT=0, CD=0, OD=0
LK,
PA·PP·MO
Closed
LK·CL/CD
Reset
OL
LK· (PA+PP+MO)
Open
OD
OL
PA+PP+MO
OL/OD
Opened
PA·PP·MO
CL·PA·PP·MO·DR
Close
CD
CL·PA·PP·MO·DR
PA+PP+MO+DR
Modified State Table for the
Automatic Sliding Door
State
State
Code
Input Condition
Next
State
State
Code
Non-zero
Outputs
Closed
00
LK
Closed
00
BT*
00
PA·PP·MO
Closed
00
LK·CL/CD*
00
LK·(PA+PP+MO)
Open
01
Open
Opened
Close
01
OD
01
OL
Open
01
01
OL
Opened
11
11
PA+PP+MO
Opened
11
11
PA·PP·MO
Close
10
10
OL/OD*
CD
10
CL·PA·PP·MO·DR
Close
10
10
CL·PA·PP·MO·DR
Closed
00
10
PA+PP+MO+DR
Open
01
State Equations for the
Automatic Sliding Door
 PA + PP + MO appears frequently as factors in other
transition conditions.
 X = PA+PP+MO
 Y1(t+1)=Y1·Y2·OL+Y1· Y2 +Y1·Y2·CL ·X·DR
 Y2(t+1)=Y1·Y2·LK·X+Y1· Y2 +Y1·Y2·X+Y1·Y2·(X+DR)
Registers and Register Transfers
(Chapter 7)
 A register consists of a set of flip-flops, together with
gates that implement their state transitions.
 A counter
is a register that goes through a
predetermined sequence of states upon the
application of clock pulses.
The Simplest Register
 Consists of only flip-flops without external gates.
D0
Clock
Clear
D1
D
Q0
>C
R
D
>C
R
Q1
Register with Parallel Load
 Connect Load to C-input or D-input? Be careful of the
clock skew.
D0
Clock
Clear
Load
Clock
D
Q0
>C
R
C inputs
D1
D
>C
R
Q1
Register with Parallel Load
contd.
 Direct Load through gates into the D inputs.
D0
Load
Clock
EN
D
Clock
D
>C
D
Q0
EN
>C
Q
D1
D
EN
>C
Q1
Digital System Design
 In most digital system designs, we partition the system
into two types of modules: a datapath, and a control
unit.
Control Signals
Control
inputs
Control
Unit
Status Signals
Data Path
Data
outputs
Control
outputs
Data
inputs
Register Transfer Operations
 The registers are assumed to be basic components of the
digital system. The movement of the data stored in
registers and the processing performed on the data are
referred to as register transfer operations. They are
specified by the following three basic components.
 The set of registers in the system.
 The operations that are performed on the data stored
in the registers, and
 The control that supervises the sequence of
operations in the system.
Register Transfer Operations
contd.
 Representations of Registers:
R
76543210
(a) Register R
(b) Bits of a register
15
0
R2
(c) A 16-bit Register
15
87
PC(H)
0
PC(L)
(b) Bits of a register
Basic Symbols for Register
Transfers
Symbol
Description
Examples
Letters (and numerals)
Denotes a register
AR, R2, DR, IR
Parentheses
Denotes a part of a
register
R2(1), R2(7:0), AR(L)
Arrow
Denotes transfer of data
R1 <- R2
Comma
Separates simultaneous
transfers
R1 <- R2, R2 <- R1
Square brackets
Specifies an address for
memory
DR <- M[AR]
An Register Transfer Example
 Transfer from R1 to R2 when K1 = 1.
K1
Load
R1
Clock
n
R2
Microoperations
 Transfer microoperations, which transfer binary data from
one register to another.
 Arithmetic microoperations, which perform arithmetic on
data in registers.
 Logic microoperations, which perform bit manipulation
on data in registers.
 Shift microoperations, which shift data in registers.
Shift Registers
 A register capable of shifting its stored bits laterally in
one or both directions is called a shift register.
Serial
input SI
Clock
D
D
D
D
>C
>C
>C
>C
Serial
output SO
Ripple Counter
 The flip-flop is positive edge triggered.
Clock
D
D
D
D
>C
>C
>C
>C
R
Reset
R
R
R
Multiplexer and Bus-based
Transfers for Multiple Registers
Enable
R0
select
2
3-to-1
MUX
R0
EN
bus
R1
R1
EN
R2
R2
EN
Multiplexer Bus
Three-state Bus
Control of Register Transfers
 Programmable system: a portion of the input to the
processor consists of a sequence of instructions. Each
instruction specifies the operation that the system is to
perform, which operands to use, where to place the results
of the operation, and in some cases, which instruction to
execute next.
 Non-programmable system: the control unit determines
the operations to be performed and the sequence of those
operations, based on its inputs and the status bits from the
datapath.
Register-Transfer System Design
Procedure
 Write a detailed system specification.
 Define all external data and control input signals, all
external data, control and status output signals, and
the registers of the datapath and control unit.
 Find a state machine diagram for the system including
the register transfers in the datapath and in the control
unit.
Register-Transfer System Design
Procedure contd.
 Define internal control and status signals.
 Draw a block diagram of the datapath, and a block diagram of the
control unit if it includes register transfer hardware.
 Design any specialized register transfer logic in both the control and
datapath.
 Design the control unit logic.
 Verify the design.
An Example: DashWatch
 The DashWatch is a very inexpensive stopwatch. It has a 4-
digit BCD counter called TM, and a 16-bit parallel load
register SD.
START
Display Time
STOP
CSS
RESET
Inputs, Outputs, and Registers
of the DashWatch
Symbol
Function
Type
START
Initialize timer to 0 and start timer
Control input
STOP
Stop timer and display timer
Control input
CSS
Compare, store and display shortest dash time Control input
RESET
Set shortest value to 10011001
Control input
B1
Digit 1 data vector a,b,c,d,e,f,g to display
Data output vector
B0
Digit 0 data vector a,b,c,d,e,f,g to display
Data output vector
DP
Decimal point to display (=1)
Data output
B-1
Digit -1 data vector a,b,c,d,e,f,g to display
Data output vector
B-2
Digit -2 data vector a,b,c,d,e,f,g to display
Data output vector
B
The 29-bit display input vector(B1,B0,DP,B-1,B-2) Data output vector
TM
4-Digit BCD counter
16-Bit register
SP
Parallel load register
16-Bit register
State-Machine Diagram for the
DashWatch
RESET
START
CSS·START
STOP
S1
SD<-(9999)BCD
S2
TM<-(0000)BCD
START
TM<-(TM+1)BCD, DIS=TM
S3
STOP
CSS·START
S4
DIS=TM
CSS
S5
START
TM<SD
TM>=SD
S7
START
S6
DIS=SD
SD<-TM
Datapath Output Actions and
Status Generation
Action or Status
Control or
Status Signals
Meaning for Values 1 and 0
TM <- (0000)BCD
RSTM
1: reset TM to 0
0: no reset of TM
TM <- (TM+1)BCD
ENTM
1: BCD count up TM by 1,
0: hold TM value
SD <- (9999)BCD
UPDATE
LSR
0: select 1001100110011001 for SD
1: Enable load SD, 0:disable load SD
SD <- TM
UPDATE
LSR
1: Select TM for DIS
Same as above
DIS = TM
DIS = SD
DS
0: Select TM for DIS
1: Select SD for DIS
TM < SD
TM >= SD
ALTB
1: TM less than SD
0: TM greater than or equal to SD
Datapath Block Diagram
TM
C0
ENTM
4-Digit BCD Counter
RSTM
SRST
ALTB
A<B Comparator
DS
SD
LSR
RESET
UPDATE
S
D1
D0
16-Bit 2-to-1 MUX
DIS
LOAD
Storage Register
RESET
D
4-Digit BCD-to-7
Segment Converter
16-Bit 2-to-1 MUX
D1
D0
4-Digit LCD Display
DP
1001100110011001
1
Control State-Machine Diagram
Defaults:
All outputs = 0
RESET
START
CSS·START
STOP
S1
LSR
S2
RSTM
START
ENTM
S3
STOP
CSS·START
S4
CSS
S5
ALTB
START
S7
START
S6
DS
UPDATE, LSR
Thanks!