ANALOG FRONT-END CHIP FOR GEM
DETECTORS
E. Atkin, E. Malankin, V. Shumikhin
NRNU MEPhI, Moscow
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OUTLINE
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GEM
Chip structure
Channels structure
Test benches
Experimental data
Summary
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GEM DETECTORS
~50 µm
Cross-section of a triple GEM detector
P. Abbon et al. / NIM (2007) 455–518
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CBM
Muon system of the international CBM experiment, being
designed on the new accelerator facilities at FAIR GSI (Darmstadt,
Germany), built on the base of the gaseous detector of high
resolution. Muon System consists of about 1 million channels. For
the Muon System signals read-out ASIC application is neccesary.
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CBM
Muon system of the international CBM experiment, being
designed on the new accelerator facilities at FAIR GSI (Darmstadt,
Germany), built on the base of the gaseous detector of high
resolution. Muon System consists of about 1 million channels. For
the Muon System signals read-out ASIC application is neccesary.
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CBM
~1 million channels
↓
~15 000 ASICs x 64 ch.
Muon system of the international CBM experiment, being
designed on the new accelerator facilities at FAIR GSI (Darmstadt,
Germany), built on the base of the gaseous detector of high
resolution. Muon System consists of about 1 million channels. For
the Muon System signals read-out ASIC application is neccesary.
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CBM
~1 million channels
↓
~15 000 ASICs x 64 ch.
Front-end for
MUCH
Muon system of the international CBM experiment, being
designed on the new accelerator facilities at FAIR GSI (Darmstadt,
Germany), built on the base of the gaseous detector of high
resolution. Muon System consists of about 1 million channels. For
the Muon System signals read-out ASIC application is neccesary.
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SPECIFICATIONS
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Input signal range of 1.5-100 fC
Charge polarity – negative
ENC – less than 0.3 fC
Detector capacitance up to 100 pF
Maximum hit rate/channel – 2 MHz
Power consumption – 2 mW/ch
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CHIP STRUCTURE
1. 5 CSA + stand alone
Shaper channels
(Preamp ver. 1)
2. 5 CSA channel with
built-in shaping
(Preamp ver. 2)
3. OpAmp block
4. Digital test structures
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CHANNEL STRUCTURE
PREAMP VER.1
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CSA CORE
• Input transistor –
nMOS (7mm * 360 nm)
• Common source stage
• Folded boost current
amplifier
• Output source follower
Feedback: gain setting cap + discharge transistor to set the maximum hit
rate of channel not less than 2 MHz
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SHAPER
Noninverting 2nd
order
Sallen-Key filter
The shaper has two additional adjustments:
- TAIL – tail cancellation
- SH_BL – baseline tuning
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PREAMP
VER.2
• Input transistor –
nMOS (4mm * 360 nm)
• Common source stage
• Folded boost current
amplifier
• Output source follower
Feedback: gain setting cap + discharge resistor to set the maximum hit
rate of channel not less than 2 MHz
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CHIP LAYOUT
• CLCC68 Package
• Die–1525 x 1525 μm2
• UMC 180 nm CMOS MMRF
process
• 2012 run of Europractice
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TESTBOARD
LDO
regulator
1 pF
capacitance
Detector
capacitance
emulation
CLCC
Socket
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TESTBOARD
LDO
regulator
Reference
potentiometers
1 pF
capacitance
Detector
capacitance
emulation
CLCC
Socket
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OUTPUT RESPONSES (VER.1)
Input charge swept
from 25 to 70 fC
Shaper
CSA
Voltage pulser
CSA
CSA & Shaper
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TRANSFER FUNCTION (VER.1)
• Dynamic range – 1.5 – 100 fC
• Integral nolinearity ~ 4%
Shaper
Channel gain ~ 6 mV/fC
CSA
CSA gain ~ 2.5 mV/fC
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RMS NOISE MEASURMENTS (VER.1)
Aim: Cin >> Cdet
Estimation: CSA open-loop gain ≥ 1400
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CSA OUTPUT RESPONSE & TRANSFER FUNCTION
VER.2
CSA output
transfer function
CSA gain ~ 5 mV/fC
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NOISE ESTIMATION
PreAmp (ver. 1)
ENC – 875е Cdet = 1p
2427e Cdet = 100p
PreAmp (ver. 2)
ENC – 1070е Cdet = 1p
2500e Cdet = 100p
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TESTBOARD WITH GEM*
GEM Anode
Pad area 5x5 mm2
Pad capacitance 12 pF
Socket with
Chip
Gas chamber
with Ar/CO2
*Testboard designed by PNPI team
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TESTS WITH 55FE SOURCE*
Fe amplitude spectrum,
obtained by the preamplifier
& GEM.
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Preamplifier output
*tests provided by PNPI team
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SUMMARY
Designed and prototyped 2 versions of read-out with preliminary CBM
MUCH specifications:
Preamplifier (ver.1)
Preamplifier (ver. 2)
Gain
6 mV/fC;
5 mV/fC
Input signal range
1.5-100 fC;
1.5-100 fC;
Maximum channel
rate
2 MHz
2 MHz
Power consumption
1.2 mW/channel
2 mW/channel
ENC Cdet = 1p
Cdet = 100p
875е
2427e
1070е
2500e
Area on chip
1050 x 100 µm
200 x 100 µm
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THANKS FOR YOUR ATTENTION...
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