-Kavyashree Pilar
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Implementation of parity bit generator and
checker circuit.
Project deliverables:
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Schematic
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Worst case timing analysis
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Power and thermal analysis
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Hardware implementation and functionality verification.
• Random data generator: Pseudo-Random noise generator circuit
• Parity bit generator : Generates a logic high parity bit when odd number of data
bits are on logic high state.
• Channel : Represents noisy environment which can alter one or more data bits and
the parity bit.
• Parity checker: Generates a new parity bit using the data bits and compares it with
the parity bit received with data.
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ICs used:
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74AC164 : 8 bit shift register
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74AC86 : Quad 2-input ExOR gate
PCB Board Specification:
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Standard board : 10mils thick with copper routing
layers on top and bottom.
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Trise_min= 3ns
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F_knee = 166.66MHz
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AC coupling capacitor value = 100pF
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Length of rising edge(L) = 21.347”
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L/4 = 5.3368”
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Longest trace length ~ 5”
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No termination required
• PNR data generator
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tPLH of U1
= 12.5ns
tPLH of U2
= 10.8ns
Q5-Ex-or input = 0.7025
Ex-or output – B = 0.7025
Setup time for U1= 2.5ns
Minimum clock period = 27.205ns
Maximum operating frequency =36.76MHz
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U1: 74AC164
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Each output drives 2 ExOR gate inputs
Q5 and Q6 drive one more ExOR gate
CPD= 150pF, Ci = 10pF, assume f = 36MHz
Vcc=5.5V,Ic=3mA
Pd = 234.3mW
θJA = 700C/W
Junction temperature = 51.4010 C
MTBF is very good – No cooling required.
• All ExOR gates except U5 drive 4 ExOR inputs
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Cpd = 57pF
Icc= 80uA
Ci = 10pF
Pd= 53.256mW
θJA = 700C/W
Junction temperature = 38.7280C
• U5 drives 3 Ex-OR inputs:
• Pd = 47.8115mW
• Junction temperature = 38.34680C
• Hardware implementation
• Functionality testing:
• Verification of parity bit generation circuit
• Verification of parity checker circuit
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PCB design using OrCAD capture/CIS and
PCB editor.
Issues faced and solutions:
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ORCAD capture – schematic done V6.6 demo version can
not be modified with V6.3.
Demo version can handle only upto 60 components.
The following command can be used on command prompt
can be used when netlist generation via GUI fails:
C:\Cadence\SPB_16.3\tools\capture\pstswp -pst -d "<filename>.DSN"
-n "allegro" -c "C:\Cadence\SPB_16.3\tools\capture\allegro.cfg"
• CMOS design – analyze termination requirements before
starting with the schematics.
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Datasheets:
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CD74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE - Texas
Instruments
CD54/74AC164, CD54/74ACT164 8-Bit Serial-In/Parallel-Out Shift Register -
Texas Instruments
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Thermal conductivity information
http://www.ti.com/lit/an/spra953b/spra953b.pdf
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PCB Design :
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“Capture CIS Tutorial” - Ekarat Laohavaleeson
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“Layout Editor Tutorial” - Jordan Bisasky
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http://www.cis.gvsu.edu/~kurmasz/Teaching/OldCourses/CS451/General/Web
Page/ReferenceDocuments/Switches/switches.html