Power and Slew-aware Clock
Network Design for ThroughSilicon-Via (TSV) based 3D
ICs
Xin Zhao and Sung Kyu Lim
School of Electrical and Computer
Engineering
Georgia Institute of Technology
Atlanta, Georgia, U.S.A.
Reference the slides of this paper in ASPDAC 2010
Outline
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Motivation and contribution
Modeling and synthesis of 3D clock tree
Experimental result and discussions
Conclusion
Outline
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Motivation and contribution
Modeling and synthesis of 3D clock tree
Experimental result and discussions
Conclusion
Motivation
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Clock skew is required to be less than
3%-4% of the clock period in an aggressive clock network design according to
ITRS projection.
Driving large capacitive load and switches at a high frequency leads to an
increasingly large proportion of the total
power of a system dissipated in the clock
distribution network
Motivation
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TSV provides the vertical interconnection
to deliver the clock signal to all dies in
the 3D stack
In general, the total wirelength of the 3D
clock network decreases significantly if
more TSVs are used
Too many TSVs often cause routing congestion and yield reduction problem
Contribution
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Three major goals
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Using SPICE to simulate the result
• Clock skew minimization
• Clock slew control
• Clock power reduction
Contribution
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Investigate the impact of design techniques on 3D clock network
Outline
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Motivation and contribution
Modeling and synthesis of 3D clock tree
Experimental result and discussions
Conclusion
Electrical model
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Electrical model
• Wire
• TSVs
• Clock buffer
TSV usage
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TSV upper bound
• Maximum number of TSVs allowed between
•
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adjacent dies
According to yielding and routing reason
TSV count
• The number of TSV be used actually
• Using stacked-TSV
Simple sample clock tree
Problem formulation
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Input
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Output
• Sink set (N dies), clock source location
• Upper bound of TSV usage
• Slew constraint
• Zero-Elmore-skew 3D clock tree
Problem formulation
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Object
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Constraint
• Zero-Elmore-skew
• Minimize wirelength, clock power
• Maximum slew
• Upper bound of TSV usage
3D clock routing algorithm-flow
What is MMM?
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Method of Means and Medians
•
Jackson, Srinivasan, Kuh, “Clock routing for high-performance ICs,”
DAC, 1990.
Each clock pin is represented as a point in the region, S.
The region is partitioned into two subregions, SL and SR.
The center of mass is computed for each subregion.
The center of mass of the region S is connected to each of the
centers of mass of subregion SL and SR.
The subregions SL and SR are then recursively split in Ydirection.
The above steps are repeated with alternate splitting in X- and
Y-direction.
Time complexity: O(n log n).
An MMM example
3D abstract tree
3D abstract tree (cont.)
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A N-colored binary tree
3D-MMM
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Suppose TSV upper bound is 3 and the
clock source is on die-0
3D-MMM
Slew-aware buffering, merging
and embedding
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Merging and slew-aware buffering, embedding
• 3D clock tree with multiple TSVs
• Using deferred-merge embedding, DME
Slew-aware buffering, merging
and embedding (cont.)
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For the purpose of
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That is
• Skew controlling
• Shorter wire length
• Zero skew in Elmore delay model
• Minimize the clock power consumption
3D clock tree
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Unique property of 3D clock tree
• A complete tree + many sub-trees
About clock source location
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In general, locating on middle die can
make #TSVs and wirelength less
About clock source location –
Theoretical max TSV usage
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Suppose M clock sinks evenly distribute
on N dies and clock source location is
die-s
Outline
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Motivation and contribution
Modeling and synthesis of 3D clock tree
Experimental result and discussions
Conclusion
Experimental result
Sample clock tree of IBM r5
benchmark in 6-die
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With TSV upper bound : 20
Impact of TSV bound
Point A: 20% power
saving, TSV bound
≥70% of #sinks
die
TSV bound and slew distribution
r5, six-die CMAX=300fF
[11.4ps, 86.2ps]
Avg. 53.9ps
#Bufs: 2933
[10.9ps, 79.6ps]
Avg. 42.6ps
#Bufs: 2638
Multi-TSV vs. Single-TSV: 4-die stack
Multi-TSV vs. Single-TSV: 6-die
stack
Skew comparison
CMAX and slew
Using single TSV
Using multiple TSVs
Impact of clock source location
on power and wirelength
A uses 33% fewer
TSVs than B
Statistics of TSVs number and
the clock source location
#TSVs = 3720
#TSVs = 2791
Outline
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Motivation and contribution
Modeling and synthesis of 3D clock tree
Experimental result and discussions
Conclusion
Conclusions
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Provided SPICE simulation information
Using multiple TSVs helps to reduce
wirelength and power. Multi-TSV also has
better control on slew variations
Smaller CMAX efficiently lowers the clock slew
Clock source location also affects the 3D clock
network in a significant way: placing the clock
source on the middle die helps reducing slew
and TSV usage under the same power
budgets