Centre for Development of Advanced Computing Software Defined Radio & Cognitive Radio: Implementation Initiatives KRISHNA KUMAR S. Centre for Development of Advanced Computing krishku@cdac.in Centre for Development of Advanced Computing C-DAC A National Centre of Excellence and premier R & D institution under DIT, MCIT, Govt. of India involved in the design, development and deployment of Electronics & IT- based solutions for human advancement 25 Feb 2012 sdr & cr: implementaion initiatives 2 of 60 Centre for Development of Advanced Computing 10 Locations 14 Centres 3000 members 25 Feb 2012 sdr & cr: implementaion initiatives 3 of 60 Centre for Development of Advanced Computing Broadcast & Communications @ C-DAC AM/FM Radios & Television Alpha Numeric Information Displays CCTV Cameras Monitors TETRA VoIP Direct Reception System Digital Audio Multifunction mono/stereo Audio Consoles Software Defined Radio MANET CR CNM CD Players Equalizers NG WF SDR Networking Monitoring Amplifiers Digital Audio Work Stations 1990 25 Feb 2012 TETRA-WiMax 2000 2010 sdr & cr: implementaion initiatives 2015 4 of 60 Centre for Development of Advanced Computing C-DAC SDR programme road map Handheld SDR Demos- 2 SCA WFS Study Report C-DAC SDR proposal CR SDR Manpack 1st SDR SDR Project PoC 2004 2006 2007 2008 DIT DIT DIT C-DAC 25 Feb 2012 SDR-NC 2009 SDR-Demo 2010/11 2012 2012 2013 DIT DIT NAVY C-DAC sdr & cr: implementaion initiatives 5 of 60 Centre for Development of Advanced Computing recent/current projects in SDR/CR SDR for Naval Communication (DRDO) SDR Manpack (DIT) SDR Handheld (Core funding) Cognitive Radio Networks (DIT) jointly with IISc. Next Generation Waveforms for SDR Related projects Mobile Adhoc NETworks (MANET) Autonomic Network Management Systems (ANMS) 25 Feb 2012 sdr & cr: implementaion initiatives 6 of 60 Centre for Development of Advanced Computing the PoC SDR lab model Demonstrated re-configurablity with two SCA compliant waveforms o TETRA UHF band & Military o Legacy FM Radio (VHF band) Clear Mode 25 Feb 2012 sdr & cr: implementaion initiatives 7 of 60 Centre for Development of Advanced Computing SDR manpack: product perspective 25 Feb 2012 sdr & cr: implementaion initiatives 8 of 60 Centre for Development of Advanced Computing agenda introduction SDR architecture SDR waveforms from SDR to CR Spectrum Sensing Engine application scenarios conclusions 25 Feb 2012 sdr & cr: implementaion initiatives 9 of 60 Centre for Development of Advanced Computing Software Defined Radio a radio in which some or all of the radio’s operating functions are implemented through modifiable software or firmware 25 Feb 2012 sdr & cr: implementaion initiatives 10 of 60 Centre for Development of Advanced Computing SDR Platform Consists of Hardware, Firmware, Operating system Middleware Takes different personalities, defined by the waveform that is loaded 25 Feb 2012 sdr & cr: implementaion initiatives 11 of 60 Centre for Development of Advanced Computing SDR platform architecture IF to 250MHz LO LNA AMP 12-16 BITS 60-125MSPS ADC IMG FILTER MXR MEM MEM FPGA DSP + GPP IF FILTER CLK DUPLEXER OR T/R SW CLK MXR AMP CLK DAC CLK MMI RF FILTER IF FILTER LO 12-16 BITS 200-1000MSPS 12 BIT / 250MSPS LO DDS SYNTH ADC MXR LO IF FILTER CLK 25 Feb 2012 CLK sdr & cr: implementaion initiatives CLK CLK CLK FREQ STD 12 of 60 Centre for Development of Advanced Computing RF transceiver 25 Feb 2012 sdr & cr: implementaion initiatives 13 of 60 Centre for Development of Advanced Computing Hopping Synthesizer 25 Feb 2012 sdr & cr: implementaion initiatives 14 of 60 Centre for Development of Advanced Computing Harmonic Filter Bank 25 Feb 2012 sdr & cr: implementaion initiatives 15 of 60 Centre for Development of Advanced Computing Baseband Boards 25 Feb 2012 sdr & cr: implementaion initiatives 16 of 60 Centre for Development of Advanced Computing agenda introduction SDR architecture SDR waveforms from SDR to CR Spectrum Sensing Engine application scenarios conclusions 25 Feb 2012 sdr & cr: implementaion initiatives 17 of 60 Centre for Development of Advanced Computing Waveform: Definition From http://www.wirelessinnovation.org/Introduction_to_SDR The set of transformations applied to information to be transmitted and the corresponding set of transformations to convert received signals back to their information content. Representation of a signal in space The representation of transmitted RF signal plus optional additional radio functions up to and including all network layers. 25 Feb 2012 sdr & cr: implementaion initiatives 18 of 60 Centre for Development of Advanced Computing Waveform Can be visualized at different levels Architecture Conceptual entity Defines and abstracts the waveform functions Almost independent of the platform specifics Implementation Physical realization of architecture Closely related to platform 25 Feb 2012 sdr & cr: implementaion initiatives 19 of 60 Centre for Development of Advanced Computing Waveform Architecture design What it is? What it is not? 25 Feb 2012 sdr & cr: implementaion initiatives 20 of 60 Centre for Development of Advanced Computing Architecture design process User behavioural patterns operational needs Candidate Architecture Radio Standards Technical Specifications SIMULATION Final Architecture 25 Feb 2012 sdr & cr: implementaion initiatives 21 of 60 Centre for Development of Advanced Computing Waveform Implementation Physical realization of architecture Closely related to platform Implementer should know Overall platform architecture Availability of Computing elements • GPP, DSP, FPGA Other configurable resources • clocks, vca, vco, tunable filters etc. 25 Feb 2012 sdr & cr: implementaion initiatives 22 of 60 Centre for Development of Advanced Computing Task Partitioning among CEs GPP DSP Signaling and control Higher layer and MAC functions RULES OF THUMB 25 Feb 2012 PHY Bit level processing Symbol rate processing Soft real-time numerically intensive tasks – e.g. channel estimation FPGA Ideally all hard real time PHY functions Tasks best implemented using parallel architecture Symbol rate processing for wideband systems sdr & cr: implementaion initiatives 23 of 60 Centre for Development of Advanced Computing What devices in a given SDR? Device architectures are being upgraded constantly New FPGAs realize DSP functions using specific architectures New DSPs use hardware accelerators to implement hard real time tasks GPP performance too scales up Blurred boundaries! Vanishing boundaries? Platform designer priorities do matter 25 Feb 2012 sdr & cr: implementaion initiatives 24 of 60 Centre for Development of Advanced Computing Portability & Re-configurability Probably the most important features of SDR Waveform should be portable across platforms [a statement to be qualified] Waveform should be able to configure and control platform resources Ensured by proper design and implementation of Waveform and Platform May result in sub-optimal implementation but that’s okay! in most cases 25 Feb 2012 sdr & cr: implementaion initiatives 25 of 60 Centre for Development of Advanced Computing Application Program Interfaces Key enabler in ensuring portability & reconfigurability Abstracts low level functions Platform provider to facilitate platform abstraction through APIs Waveform implementer to use APIs to access platform features 25 Feb 2012 sdr & cr: implementaion initiatives 26 of 60 Centre for Development of Advanced Computing GPP & DSP APIs GPP API calls are typically POSIX calls DSP API calls are C-function calls API implemented as a library API to be used while building DSP image 25 Feb 2012 sdr & cr: implementaion initiatives 27 of 60 Centre for Development of Advanced Computing RF APIs To abstract Radio functions Tuning LO Configure Tx. DAC Configure AGC Etc. API calls are pre-defined messages Processed and executed by a dedicated controller 25 Feb 2012 sdr & cr: implementaion initiatives 28 of 60 Centre for Development of Advanced Computing FPGA: Wrapper Equivalent of API for FPGA Wrapper defines the platform logic Waveform logic defines the (part of) PHY signal processing Waveform logic to be integrated with wrapper 25 Feb 2012 sdr & cr: implementaion initiatives 29 of 60 Centre for Development of Advanced Computing FPGA: Architecture FPGA IO Ring RF Control TOP module SPI Glue ADC DAC ADC FIFO DAC FIFO SPI Signals 14 bit 16 bit EMIF EMIF Glue Waveform Logic DSP GPIO (Push Buttons, LEDs, DIP Switches, GPIO Headers) UART Port 25 Feb 2012 McBSP McBSP Glue Interrupt 1 Interrupt 2 UART Glue uPP Glue uPP sdr & cr: implementaion initiatives 30 of 60 Centre for Development of Advanced Computing FPGA: model based design To design waveform signal processing Can be done in a graphical way Designer need not no low-level architecture of the device Can be used jointly with Matlab/Simulink or similar simulation environments 25 Feb 2012 sdr & cr: implementaion initiatives 31 of 60 Centre for Development of Advanced Computing FPGA: model based design tools Xilinx - System Generator Altera - DSP Builder Actel - Synplify Lattice - ispLever DSP Agilent system view – VHDL code generation 25 Feb 2012 sdr & cr: implementaion initiatives 32 of 60 Centre for Development of Advanced Computing FPGA: integration with wrapper Combine the HDL source level Combine the wrapper source with waveform netlist Similar to adding a library Combine at bitmap level Wrapper logic implemented in advance Waveform logic added using partial reconfiguration 25 Feb 2012 sdr & cr: implementaion initiatives 33 of 60 Centre for Development of Advanced Computing agenda introduction SDR architecture SDR waveforms from SDR to CR Spectrum Sensing Engine application scenarios conclusions 25 Feb 2012 sdr & cr: implementaion initiatives 34 of 60 Centre for Development of Advanced Computing from SDR to CR A natural evolution CR, by nature, has to be an SDR but, an SDR with certain specific fetures. 25 Feb 2012 sdr & cr: implementaion initiatives 35 of 60 Centre for Development of Advanced Computing CR additional requirements A truly wideband radio front end Support for White/Gray space detection Spectrum sensing - hardware & software Geo-location and Database • IEEE 802.22 Dynamic Spectrum Management Channel & Bandwidth allocation Rate adaptation & Tx power control 25 Feb 2012 sdr & cr: implementaion initiatives 36 of 60 Centre for Development of Advanced Computing from SDR to CR: concerns Algorithm complexities – of course A truly wideband radio front end Tx side RF Power amps Rx side – wide band sensing AD/DA conversion bottle-necks Noise, sensitivity, interference protection, SFDR 25 Feb 2012 sdr & cr: implementaion initiatives 37 of 60 Centre for Development of Advanced Computing agenda introduction SDR architecture SDR waveforms From SDR to CR Spectrum Sensing Engine – design & implementation application scenarios conclusions 25 Feb 2012 sdr & cr: implementaion initiatives 38 of 60 Centre for Development of Advanced Computing Primary Signal Details Primary: Terrestrial analog TV txn in India System: CCIR system B,G PAL Bands: • Band II VHF: 174 to 225 MHz • Band IV UHF: 470 to 582 MHz Channel BW: 8 MHz 25 Feb 2012 sdr & cr: implementaion initiatives 39 of 60 Centre for Development of Advanced Computing Requirements Incumbent Detection Threshold: -94 dBm (measured at peak of sync) Channel Detection Time: <=2 sec per channel Detection Performance: Probability of Detection >=90% at False Alarm rate of <= 10% Guided by IEEE 802.22 WRAN WG interim recommendations 25 Feb 2012 sdr & cr: implementaion initiatives 40 of 60 Centre for Development of Advanced Computing Platform - Lyrtech SFF SDR 25 Feb 2012 sdr & cr: implementaion initiatives 41 of 60 Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 42 of 60 Centre for Development of Advanced Computing From SS Algorithm to SS Engine (from “recipe” to “dish”) Study of algorithm Study of hardware architecture Designing software architecture Optimal partitioning of algorithm Model based design / C-program development Fixed point considerations dynamic range, bit growth, over/under-run, truncation error Defining and realizing interfaces Debugging, testing and optimization 25 Feb 2012 sdr & cr: implementaion initiatives 43 of 60 Centre for Development of Advanced Computing Detection Scheme Pre-processing/Feature extraction stage Extracts the spectrum around the picture carrier Energy Detection stage Computes the energy around the pictures carrier 25 Feb 2012 sdr & cr: implementaion initiatives 44 of 60 Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 45 of 60 Centre for Development of Advanced Computing Pre-Processing Decimating filter stages Digital IF BW: 8MHz 125 Msps 14 bits 5 5 5 2 to sensing algorithm BW: 100kHz 500 Ksps 32 bits DDS @ 30MHz 25 Feb 2012 sdr & cr: implementaion initiatives 46 of 60 Centre for Development of Advanced Computing Implementation Implemented in the FPGA part (Virtex 4) Design using Simulink / System generator Model based design approach Fixed point implementation Word-length selection 25 Feb 2012 bit growth truncation error resource utilization sdr & cr: implementaion initiatives 47 of 60 Centre for Development of Advanced Computing Energy Detection N samples x B buffers Gives the adavntage of averaging Reduces the FFT implementation complexity 25 Feb 2012 sdr & cr: implementaion initiatives 48 of 60 Centre for Development of Advanced Computing Implementation Implemented in the DSP (TMS320C64X) Code developed in C language Debugged using Code Composer Studio & XDS560 ICE A fixed point implementation Word-lengths selection 25 Feb 2012 sdr & cr: implementaion initiatives 49 of 60 Centre for Development of Advanced Computing User Interface 25 Feb 2012 sdr & cr: implementaion initiatives 50 of 60 Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 51 of 60 Centre for Development of Advanced Computing Lab Setup Centre for Development of Advanced Computing Test Settings Picture carrier: 67.25MHz Channel Bandwidth: 8MHz Video pattern: White Sensing duration: 20.4 ms Sampling rate: 125Msps Ensemble size: 1e5 SNR values: -30dB, -27dB, -24dB 25 Feb 2012 sdr & cr: implementaion initiatives 53 of 60 Centre for Development of Advanced Computing PAPR for ATV Courtesy: Martyn J. Horspool, Analog-to-digital Upgradeable Transmitters For the Worldwide Market, Harris Corporation 25 Feb 2012 sdr & cr: implementaion initiatives 54 of 60 Centre for Development of Advanced Computing Results 25 Feb 2012 sdr & cr: implementaion initiatives 55 of 60 Centre for Development of Advanced Computing Results System meets the false alarm/miss detection performance at -27 dB SNR Highly encouraging result Enough margin to accommodate large scale fading Caveat: This is only a lab measurement 25 Feb 2012 sdr & cr: implementaion initiatives 56 of 60 Centre for Development of Advanced Computing agenda introduction SDR architecture SDR waveforms from SDR to CR Spectrum Sensing Engine application scenarios conclusions 25 Feb 2012 sdr & cr: implementaion initiatives 57 of 60 Centre for Development of Advanced Computing application areas Military PMR (public safety, police, paramilitary) Disaster management Commercial Cellular (Base Stations) Rural broadband access IEEE 802.22 system adaptaion Tele-Medicine 25 Feb 2012 sdr & cr: implementaion initiatives 58 of 60 Centre for Development of Advanced Computing acknowledgements Simon Zachariah Beena K. T. S. Sagar Chandra R. Murthy Shine K. P. Satheesh Kumar S. 25 Feb 2012 sdr & cr: implementaion initiatives 59 of 60 Centre for Development of Advanced Computing Questions ?? …thank you