VIIT-GRAPES Collaboration
C S Garde
Vishwakarma Institute of Information Technology (VIIT),
Pune
VIIT-TIFR collaboration
Year
No. of projects
No. of BE
students
No. of faculty
(VIIT)
2
No. of
scientists/
engineers
(TIFR)
1
2009-2010
1
2
2010-2011
8
2011-2012
Departments (VIIT)
E&TC
19
7
8
E&TC
11
33
9
15
2012-2013
13
38
12
10
2013-2014
17
47
12
10
E& TC,
Engg.
E& TC,
Engg., IT
E& TC,
Engg., IT
Computer
Computer
Computer
VIIT students in TIFR
Sr. No.
Name of student (Batch)
Project at TIFR
1
Sanket Kamathe (2010)
Post
2
Ameya Deshpande (2010)
Silicon
Photo
Multiplier Jr. Research Fellow
(SiPM)
Tera Hertz Spectroscopy
Jr. Research Fellow
3
Raj Patil (2011)
Plasmonics NRIM
4
Aniket Patil (2011)
Plasmonic Interconnects
5
Harshad Surdi (2012)
Tera Hertz Spectroscopy
6
Raghunandan Shukla (2011)
SiPM, VLSI, Embedded
7
Sarrah Lokahandwala (2013)
FPGA based systems, SiPM
Jr. Research Fellow
8
Suraj Kolhe (2012)
VLSI, Embedded
Jr. Research Fellow
9
Serin V. John (2013)
High voltage DAS, Embedded
Jr. Research Fellow
Lab at TIFR
Solid State Electronics,
Mumbai
National
Photonics
Fellowship
National
Photonics
Fellowship
Jr. Research Fellow
High Energy Physics,
Mumbai
Cosmic
Rays
Laboratory, Ooty
Software Projects
Sr. No.
1
Data management for Muon Detector Station
2
Data Management for Scintillator Detector system
3
Parallelization of Corsika
4
Parallelization of G3SIM (C++ programme)
5
Dynamic ROOT plotting
Hardware Projects
Sr.
No.
Project
1
32-channel FPGA based counter with USB interface
2
64-channel FPGA based counter with ethernet interface
3
FPGA based I2C communication
4
High voltage Data acquisition system
5
Solar PV
6
High Precision Temperature Compensated Power Supply For
Silicon Photo-Multiplier
32 Channel FPGA Based Counter
• Last year:
• 32 channel 24 bit high-speed counter
implemented on a Actel FPGA (counter and
digital logic part)
• FPGA and PIC micro-controller interfacing done
• Data logging to PC by a PIC micro-controller via
USB protocol (Linux compatible)
32 Channel FPGA Based Counter
• This year:
• FPGA programming – VHDL to Verilog conversion is in
progress (small Verilog programs (counter, etc.)
implemented and tested on hardware)
• Pulse width measurement logic under development
• New counter logic development in Verilog is in
progress
64 Channel FPGA Based Counter (Scalar)
• Last year:
• Simulations of 32 bit 64 channel counter
• 4 channel 16 bit Counter (Scalar) implementation on SPARTAN3E
FPGA using VHDL
• Data transfer to PC through ARM7 controller, via Ethernet protocol
(UDP/IP) demonstrated
• Multi-board configuration (IP Address based) with 2 ARM boards
• Multi-threading approach demonstrated for data reception on PC
64 Channel FPGA Based Counter (Scalar)
•
•
•
•
•
This year:
FPGA programming – VHDL to Verilog conversion is in progress
4 channel 4 bit counter demonstrated SPARTAN3E FPGA in Verilog
Automated approach to toggle between 64 channels is demonstrated
Multi-board configuration: synchronization of boards with I2C protocol
demonstrated for 2 ARM Boards
• Time stamping with milliseconds accuracy is demonstrated
• Pulse width measurement logic under development
• Ethernet part : Data transfer with TCP/IP protocol is under development
High Voltage Data Acquisition System
• Last year:
• 48 channels system for PMT voltage monitoring
developed
• 1 V resolution in 2500 V
• This system tested on actual PMT setup at CRL, Ooty
• Data logging via USB every 5 sec
Block diagram
High voltage monitoring
High Voltage Data Acquisition System
• This year:
• Different protection Circuits for already developed
high voltage data acquisition board being developed
and tested
• Temperature, Humidity etc. sensors being tested for
inclusion in high voltage data acquisition board
Design and Implementation of Multiple
Panels Solar Power System
• Last year:
• Maximum Power Point Tracking (MPPT) based charger
developed for 25W solar panel
• Data logging system (Voltage, Current, Power) for a
single solar panel developed (via USB protocol)
Design and Implementation of Multiple
Panels Solar Power System
• This year:
• Improvement on MPPT charger circuit
• Inclusion of Buck-Boost converter for high efficiency
• Multiple Solar Panel Configuration with Data logging
• Different Protection Circuits inclusion
• Temperature Sensing
Design and Implementation of Multiple
Panels Solar Power System
•
•
•
•
•
This year:Design of solar power system for 1kW of power with 4 solar panels and 8 batteries.
Design of a Buck Boost Converter.
Design of a Isolated Boost Converter.
To design a Load Sharing System.
•
•
•
•
•
Specifications of PV Panels :Voc for each panel = 42V
Isc for each panel = 7.6A
Vmpp for each panel= 35.25V
Impp for each panel=7.4A
I2C based multiple FPGA Configuration
• Started from this year
• Counter based projects uses FPGA, so in future a
multiple FPGA configuration will be needed
• Multiple FPGA’s (slaves) will communicate to PIC
based microcontroller (master) via I2C protocol
• PIC micro-controller to PC communication via USB is
developed previously and used for various projects
High Precision Temperature
Compensated Power Supply For
Silicon Photo-Multiplier
Silicon Photo-Multiplier (SiPM)
• Multi-pixel semiconductor Avalanchephotodiode.
• A Solid State Device
• Operating voltage (30-120V)
• Resolution - Single photon detection
• Response time – ~1 ns
• High gain - 106
• High Quantum Efficiency – 90%
• High Photon Detection Efficiency – 60%
FIIG, University of Pisa, Italy
SiPM Biasing
Specifications of Power Supply
Parameters
Value
Maximum Output Voltage
100 V
Output Voltage Resolution
25 mV
Output Channels
16
Maximum Current Limit (Per Channel)
100 uA
Typical SiPM Temperature Compensation Coeff.
50 mV/˚C
Temperature Detection Resolution
0.1 ˚C
* Also, total power supply unit should be as small as possible.
Temperature Compensation Test
• First Passive Compensation is done for
proof of principle
• SiPM typical temperature coeff. = 50
mV/˚C
• LM 35 temp. Coeff. = 10 mV/˚C
• A Circuit is connected to SiPM supply
directly, that will change the supply
voltage ground according to temperature
SiPM
Test Setup for Compensation test
SiPM Power
Supply
Data logger for
Temperature
measurement
Compensation
Circuit
SiPM VME
Test Setup
Blower
(Heat)
PC
Results of Compensation
Required Compensation is
a non-linear Function
Temperature Compensation Test
30
25
Gain
20
15
without compensation
10
with compensation
5
0
27
28
29
30
Temperature (˚C)
31
32
33
Block Diagram for Proposed Power Supply
High Voltage
Generation
(Voltage Multiplier
Chain)
PC
USB
Temperature
Sensors
Control Unit
(Micro-controller)
Current Sense
DAC
Voltage Regulation
Scheme
SiPM
Test Board
Tests Performed
• DAC Stability
• Line Regulation
• Load Regulation
• Linearity
• Time Drift
• Capacitor for Noise elimination at output and stability
DAC Stability
5.102 uV variation in 5 V
Line Regulation
0.04113% for 10% change in line voltage
0.03% for 20% change in line voltage
Load Regulation
No load to Full load (100uA)
Best 0.6025% Channel 2
Worst 1.55% Channel 8
Linearity
Linearity of 8 channels
120
Regulator Output (V)
100
Channel 1
80
Channel 2
Channel 3
60
Channel 4
Channel 5
40
Channel 6
Channel 7
20
Channel 8
0
0
10
20
30
40
50
Set Voltage (V)
60
70
80
90
100
Time Drift (Channel 1)
Supply
Voltage
Regulator
Output
Time Drift Error Plots
Supply Voltage Error Plot
600 mVp-p change
Regulator Output Error Plot
100 mV change
Ceramic Capacitor for reducing ripple
𝐼𝑜𝑢𝑡 ×𝑑𝑐 × 1−𝑑𝑐 ×1000
𝑓𝑆𝑊 ×𝑉𝑃𝑚𝑎𝑥
𝑉𝑜𝑢𝑡
𝑑𝑐 =
𝑉𝑖𝑛 ×𝑒𝑓𝑓𝑖𝑐𝑖𝑒𝑛𝑐𝑦
• 𝐶𝑚𝑖𝑛 =
• Where
• Iout = 100 uA, dc = 0.98
• fsw = 19.52 (in KHz), Vp = 1 mV
• Cmin = 0.0995 uf
• C1 = 0.1 uf , C2 = 0.01 uf
Time Drift (Improved) with 0.1 f Capacitor
Channel 1
Without Capacitor
With 0.1 uf Cap
15 mV Change
Histograms
Comparison Between 0.1f and 0.01f
Histograms
Voltage Generation (Voltage Multiplier)
• A simple 10-stage Voltage multiplier chain is build
with diodes (1N4148) and capacitors (0.22 F)
• The chain is tested for input frequencies 50 Hz to 5
MHz and for sine and square inputs.
Chain testing
Multiplier Chain Test
100
90
Output Voltage (V)
80
70
60
With Square wave
input
50
40
30
with Sine wave input
20
10
0
1
10
100
1000
10000
Frequency (Hz)
100000
1000000
10000000
Specifications achieved on test board
Parameters
Required Value
Achieved Value
Maximum Output Voltage
100 V
88.5 V with chain
Output Voltage Resolution
25 mV
50 mV
Output Channels
16
8
Maximum Current Limit (Per Channel)
100 uA
100 uA
Typical SiPM Temperature Compensation
Coeff.
50 mV/˚C
Temperature Resolution
0.1 ˚C
A stability of 10 mV in 50 mV resolution is achieved
Conclusions
• Software project:
Except Parallelization of CORSIKA all other software projects have been
partially implemented and are being fine tuned
• Hardware projects:
1. Standard PIC micro-controller based USB has been standardized
2. ARM7 based Ethernet - UDP implemented, TCP in advanced stage
3. FPGA – VHDL to Verilog transition made, 32 channel counter in advanced
stage, 64 channel also in good shape, I2C in initial stage
4. High Voltage Monitoring – Advanced stage
5. Solar PV – R&D on Multiple panel, high power system optimization
6. SiPM power supply – In advanced stage
Guides from VIIT
• C S Garde - Coordinator
• V M Aranake
• M S Karyakarte
• S J Thaware
• K J Raut
• Mrs S Y Desai
Guides from TIFR
•
•
•
•
•
•
•
•
•
•
S K Gupta - Coordinator
S R Dugad
Atul Jain
Jagdeesan
Mohanty
Hariharan
Raghunandan
Sarah
Serin
Suraj
Students (Computer)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Mustafa Adib
Modak Ameya
Marathe Amogh
Rachit Kulshrestha
Shushupti Ajmire
Tejasvi Belsare
Dhawal Priyadarshi
Ms Devanshi Shah
Shubham Gupta
Irom Ajay Singh
Kishan Rao
Tejas Rao
Students (IT)
1.
2.
3.
4.
5.
6.
7.
8.
9.
Qaidjohar Jawadwala
Harsh Kundnani
Dyaneshwar Kothule
Ms Shivangi Hiray
Ms Rekha Sangwan
Runa Ganeshan
Ayushi Tripathi
Ankit Bhavsar
Nikhil Mantri
Students (Electronics)
1.
2.
3.
4.
5.
6.
7.
Aditya Godbole, Veronica D’Souza, Saumitra Kale
Akshay Manjare, Digvijay Tambhale, Shefali Rai
Afshan Shaikh, Akhil Kurup, Syed Shadab
Kamlesh Shinde, Bhagyashree Kalaskar, S Venkatesh
Ravi Prakash, Vinit Shah, Sanket Dahiwal
Jaydeep Kshirsagar, Kushal Kshirsagar
Pankaj Rakshe (ME)
Thank you
Work Plan
Tasks
Duration
Sophisticated Voltage Multiplier Chain Building
November 2013
Temperature Compensation Algorithm implementation in microcontroller
November 2013
Current Sensing Implementation
November 2013
Testing with Actual SiPM Setup
December 2013
All modules-on-one-board PCB design
December 2013
New Board testing and data analysis
January 2014
References
[1] K.C. Ravindran, “Silicon Photo-multiplier development at GRAPESOoty.
3”, WAPP workshop, CRL,
[2] Bajarang Sutar, “A talk on study of characteristics of SiPM”, TIFR, Mumbai.
[3] R. Bencardino, J.E. Eberhardt, “Development of a Fast-Neutron Detector With Silicon
Photomultiplier Readout”, IEEE Trans. On Nuclear Science, 2009
ERP system for Muon Detector
Stations
Problem Statement
• Manufacturing of muon detector stations.
• Lack of integrated solutions
•
•
•
•
Collaboration between departments
Analysis and performance checking
Inventory Management
Ease of retrieval in data
• Management of manufacturing process and employees
Objectives




To maintain and manage the data from production to
construction stage of muon detector station
To generate various reports
To perform the analysis based on failure rate of component
,user performance etc.
Enhancing the operational efficiency of business resources.
What we have done until now ?
• Requirement Gathering
• Literature Survey
• Study about ERP system
• ER diagram
• Schema Diagram
• Proposed System
• Features
• Users and their roles
Literature Survey

Software package that integrates all necessary business functions into a
single system

Features of ERP system-Componentized, Integrated, Flexible

ERP follows three-tier architecture
• Application Layer
• Presentation Layer
• Database Layer
Literature Survey(Continued…)
• Functionalities Of ERP system
•
•
•
•
•
•
Financial Management
Human Resource Management
Manufacturing Management
Product Lifecycle Management
Inventory Management
Security
Literature Survey(Continued…)