Introducing Zynq-7000 EPP
The First Extensible Processing Platform Family
March 2011
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Embedded Designers are Asking For More
More than a processor delivers…
More than an ASIC or ASSP delivers…
More than an FPGA delivers…
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Next-Generation Embedded Processing
The Need
The Limitations
Higher Performance
Microprocessors have insufficient signal processing
Lower Cost
Multiple chip implementations are too expensive
Lower Power
Multiple chip implementations use too much power
Smaller Form Factor
Multiple chip implementations take up too much room
Greater Flexibility
ASICs/ASSPs cannot adapt to rapid changes in
requirements and provide competitive differentiation
What’s Needed is a New Class of Product
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Current Selections Equal Compromise
Performance
Power
Unit Cost
ASIC
ASSP
+
+
+
+
+
+
+
+
+
-
TCO

Risk
-
TTM
Flexibility
Scalability
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
+
+
+
+

+
+ positive, - negative,  neutral
Conflicting Demands Not Served
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2 Chip
Solution
Introducing the Zynq™-7000 EPP
 Breakthrough Processing Platform
– High performance, low power
– Flexible and scalable solution
 Industry Standard Design Environments
– Well defined SW programming model
– Familiar SW & HW design flows
 Flexible Accelerators and IP
– Standard AMBA® AXI-4 interfaces
 Broad Ecosystem Support
– Tools, OS’s & IPs
– Middleware, codecs
Familiar Processing System + Scalable Programmable Logic
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Zynq-7000 Family Highlights
 Complete ARM®-based Processing System
– Dual ARM Cortex™-A9 MPCore™, processor centric
– Integrated memory controllers & peripherals
– Fully autonomous to the Programmable Logic
 Tightly Integrated Programmable Logic
Processing
System
Memory
Interfaces
– Used to extend Processing System
– Scalable density and performance
Common
Peripherals
– Over 3000 internal interconnects
 Flexible Array of I/O
ARM®
Dual Cortex-A9
MPCore™ System
Common Accelerators
– Wide range of external multi-standard I/O
Custom Accelerators
– High performance integrated serial transceivers
– Analog-to-Digital Converter inputs
Software & Hardware Programmable
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7 Series
Programmable
Logic
Common
Peripherals
Custom
Peripherals
Zynq-7000 Architecture
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Complete ARM®-based Processing System
Processor Core Complex
High BW Memory
 Dual
Cortex™-A9
MPCore™ with NEON™
extensions
 Single / Double Precision
Floating Point support
 Up to 800 MHz operation
ARM®
 Internal
– L1 Cache – 32KB/32KB (per Core)
– L2 Cache – 512KB Unified
 On-Chip Memory of 256KB
 Integrated Memory Controllers
(DDR3, DDR2, LPDDR2, 2xQSPI,
NOR, NAND Flash)
AMBA Open Standard
Interconnect
Integrated Memory Mapped Peripherals




2x USB 2.0 (OTG) w/DMA
2x Tri-mode Gigabit Ethernet w/DMA
2x SD/SDIO w/DMA
2x UART, 2x CAN , 2.0B, 2x I2C, 2x SPI, 32b GPIO
 High bandwidth interconnect
between Processing System and
Programmable Logic
 ACP port for enhanced hardware
acceleration and cache coherency
for additional soft processors
Processing System Ready to Program
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Tightly Integrated Programmable Logic
Built with State-of-the-art
7 Series Programmable Logic
Over 3000 Internal
Interconnects
 28K-235K logic cells
 430K-3.5M equivalent ASIC gates
Note: ASIC equivalent gates based
on analysis over broad range of
designs
 Up to 100Gb of BW
 Memory-mapped
interfaces
Enables Massive
Parallel Processing
Integrated Analog Capability
 Dual multi channel 12-bit A/D
converter
 Up to 1Msps
 Up to 760 DSP blocks
delivering over 900 GMACs
Scalable Density and Performance
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Flexible External I/O
54 Dedicated Peripheral I/Os
76 Dedicated Memory I/Os
 Supports integrated peripherals
 Static memory (NAND, NOR,
QSPI)
 More I/Os available though
the Programmable Logic
 DDR3 / DDR2 / LPDDR2 Memory
Interfaces
 Configurable as 16bit or 32bit
High Performance Integrated
Serial Tranceivers
350 Multi-standard and
High Performance I/O
(Two largest devices only)
 Up to 12 transceivers
 Operates up to 10.3Gbs
 Supports popular protocols
 Integrated PCIe Gen2 block
 Up to 200 3.3V capable
multi-standard I/O
 Up to 150 high performance I/O
 Up to differential 17 ADC inputs
Flexibility Beyond Any Standard Processing Offering
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Zynq-7000 EPP Value Proposition
ASIC
ASSP
+
+
+
TCO

Risk
-
+
+
+
+
+
+
-
-

Performance
Power
Unit Cost
TTM
Flexibility
Scalability
+ positive, -
2 Chip
Solution
Zynq-7000

+
+
+

+
+
+
+
+
+
+
+
+
negative,  neutral
Conflicting Demands Now Served by the Zynq-7000 Family
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Zynq-7000 Device Portfolio Summary
Zynq-7000 EPP Devices
Z-7010
Z-7020
Processing System
Programmable
Logic
NEON™ & Single / Double Precision Floating Point
Processor Extensions
Max Frequency
800MHz
Memory
L1 Cache 32KB I / D, L2 Cache 512KB, on-chip Memory 256KB
External Memory Support
Approximate ASIC Gates
Extensible Block RAM
Peak DSP Performance (Symmetric FIR)
DDR3, DDR2, LPDDR2, 2x QSPI, NAND, NOR
2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet,
2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
~430K (30k LC)
~1.3M (85k LC)
~1.9M (125k LC)
~3.5M (235k LC)
240KB
560KB
1,060KB
1,860KB
58 GMACS
158 GMACS
480 GMACS
912 GMACS
Gen2 x4
Gen2 x8
PCI Express® (Root Complex or Endpoint)
-
Agile Mixed Signal (XADC)
2x 12bit 1Msps A/D Converter
I/O
Processor System IO
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Multi Standards 3.3V IO
Z-7040
Dual ARM® Cortex™-A9 MPCore™
Processor Core
Peripherals
Z-7030
130
100
200
100
200
Multi Standards High Performance 1.8V IO
-
-
150
150
Multi Gigabit Transceivers
-
-
4
12
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Zynq-7000 EPP Applications Mapping
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Zynq-7000 Devices at Work in
Automotive Driver Assistance
 Performance
– Complex system inputs drives signal
processing performance demands
ASIC
– Video cameras (>720p30 Multi-stream)
– Fusion with infrared sensors,
+
+
Unit Cost
+
+
+
TCO

Risk
-
+
+
+
+
+
Performance
radar sensors
– DSP & memory performance to meet
even the most demanding DA application
requirements
 Flexibility
– Emerging and evolving camera interface
standards & DA application algorithms
 Scalability at right price point
– Enables unique sets of bundled features
in a cost effective manner
Z-7010
Z-7020
Power
TTM
Flexibility
Scalability
Optimized for Performance, Flexibility and Scalability
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
Zynq-7000 EPP Driver Assistance Application
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Zynq-7000 at Work in Industrial Applications
 Flexibility
– Need time to market, while enabling
in-system programmability accommodating
“future proofing” products
2 Chip
Solution
Z-7010
Z-7020
Z-7030
Performance

+
Power
-
+
Unit Cost
-

TCO
+
+
Risk
+
+
TTM
+
+
Flexibility
+
+
Scalability
+
+
 Scalability
– Z-7010 – Z-7030 devices allow customers
to offer support for various standards
from a single platform
 Power, Size & Cost
– Power, Size and cost are critical
requirements
– Addressed by integration and
reconfigurability of the Programmable Logic
 Performance
– Integration and tight coupling of the
processing System and Programmable
Logic allows high bandwidth, low latency
for real-time industrial networking and
motor control hardware accelerators
Scalable, Flexible, Power and Cost Efficient with the Right Level of Performance
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Zynq-7000 Industrial Motor Control Application
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Zynq-7000 Devices at Work in
Broadcast Camera
 Performance
– Processing System to Programmable Logic
interconnect enables high bandwidth for high
accuracy video processing and analytics
– Required for high picture quality, high quality color
grading system, high accuracy video/audio
statistics system in broadcast camera
 Power
– Strict power dissipation budget requirements
 Flexibility
– Accommodates changing broadcast standards
and future algorithms evolution
 Scalability
– Ability to target range of cameras:
“Prosumer” to high-end professional
2 Chip
Solution
Z-7020
Z-7030
Z-7040
Performance

+
Power
-
+
Unit Cost
-

TCO
+
+
Risk
+
+
TTM
+
+
Flexibility
+
+
Scalability
+
+
High Performance, Power Efficient solution that is – Scalable and Flexible
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Zynq-7000 EPP Broadcast Camera Application
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Zynq-7000 EPP Platform Offering
Libraries & APIs
Custom
Processing System
Simulators
SW Development
Tools
Partners
OS Kernel
High Level and Low Level Drivers
Xilinx
OS BSP’s
Silicon
Reference Design & Board
Applications
Programmable Logic
SW & HW IP
HW Development
Tools
More than just Silicon: A Comprehensive Platform Offering
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Embedded Design Flow Using Zynq-7000 EPP
System
Architect
Software
Developer
Hardware
Designer
Programming
Design
 Industry-Leading Tools
– Xilinx SDK (Eclipse IDE, GNU)
– ARM Ecosystem
 Many Sources of SW IP
Custom IP
Integrate IP
– Xilinx, ARM libraries
– 3rd Parties
Xilinx IP
Integrate IP
Partner IP
Test
Test
Debug
Debug
 Industry-Leading
Tools
– C-Gates / AutoESL
– System Generator
– VHDL/Verilog
 Many Sources of
HW IP
– Standardized around AXI
– 3rd Parties
Accelerates Application Development and TTM
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Zynq-7000 EPP SW Development Environment
 Widely Used ARM
Development Environment
– Easily migrate code already
developed for ARM-based systems
Applications
– ARM
– Xilinx Software Development Kit
– Other 3rd Parties
OS BSP’s
 Widely Available SW and Libraries
– Open source
Silicon
 ARM Ecosystem Support
Libraries & APIs
OS Kernel
High Level and Low Level Drivers
Processing System
Programmable Logic
– Commercially available
 Drivers and APIs
– Provided for a common set of peripherals and system functions
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Custom
Zynq-7000 EPP HW Design Environment
 Xilinx ISE Development Suite
– Embedded Edition
– AutoESL HLS support
– HDL & HLS simulation &
synthesis
Silicon
 Plug & Play IP Portfolio
– AMBA® AXI enabled
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Applications
OS BSP’s
 Standard “FPGA” EDA Design
tools
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Libraries & APIs
OS Kernel
High Level and Low Level Drivers
Processing System
Custom
Programmable Logic
Jump-Start Zynq-7000 EPP Developments Now
 Zynq-7000 EPP Emulation Platform
– First systems delivered: Summer 2010
– Customers & partners developing SW, HW and IP
 Customer and Partner Activities
– Linux applications
– Android applications
– Video processing functions
– System interoperability testing
• CAN, USB, Ethernet, …
– Custom AMBA® AXI IP blocks
– 3rd party GNU & debugging tools ports
– And more…
A Fast Track to Full System Design
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Zynq-7000 Extensible Processing Platform Summary
 New Scalable Family of Devices
– Zynq-7000 EPP device portfolio
– Four devices for a broad range of applications
 Industry Standard Design Environments
– Well defined SW programming model
– Familiar HW design flow
– Flexible accelerators and IP
– Standard AMBA® AXI interfaces
 Broad and Expanding Ecosystem
– Tools, OS’s, IP
– Middleware, codecs …
 Availability
– Initial devices 2H CY2011
– Production 2H CY2012
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For Further Details
 Learn more about the Zynq-7000 family
– Download the latest collateral from Xilinx.com
– Register for “be the first know”
– Contact your local sales rep
 View the online Zynq-7000 Videos
– Introduction to Zynq-7000 EPP: ARM & Xilinx joint video
– Emulation Platform demonstrations from Embedded World
– Partner and customer testimonials
 Learn more about our 28nm Programmable Logic
– Worlds first 28nm FPGA device already shipping since March 2011
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Device Tables
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Zynq-7000 EPP Device Table
SW Developer’s View
Zynq™-7000 Extensible Processing Platform
Device Name
Z-7010
Z-7020
Z-7030
Z-7040
Part Number
XC7Z010
XC7Z020
XC7Z030
XC7Z040
Dual ARM® Cortex™-A9 MPCore™ w ith CoreSight™
Processor Core
NEON™ & Single / Double Precision Floating Point
Processor Extensions
Maxim um Frequency
800 MHz
L1 Cache
32 KB Instruction, 32 KB Data per processor
L2 Cache
512 KB
On-Chip Mem ory
Processing System
256 KB
External Mem ory Support
DDR3, DDR2, LPDDR2
External Static Mem ory Support
2x Quad-SPI, NAND, NOR
DMA Channels
8 (4 dedicated to Programmable Logic)
2x USB 2.0 (OTG) w /DMA, 2x Tri-mode Gigabit Ethernet w /DMA,
2x SD/SDIO w /DMA, 2x UART,
2x CAN 2.0B, 2x I2C,
2x SPI, 4x 32b GPIO
Peripherals
AES and SHA 256b for secure boot
Security
Peripherals and Static Mem ory Multiplexed I/O(1)
54
2x AXI 32b Master, 2x AXI 32b Slave,
4x AXI 64b/32b Memory
AXI 64b ACP
16 Interrupts
Processing System to Program m able Logic Interface Ports
(Prim ary Interfaces & Interrupts Only)
Xilinx 7 Series Program m able Logic Equivalent
Program m able Logic Cells (Approxim ate ASIC Gates (3))
Extensible Block RAM (# 36 Kb Blocks)
Program m able DSP Slices (18x25 MACCs)
Program m able Logic
Peak DSP Perform ance (Sym m etric FIR)
PCI Express® (Root Com plex or Endpoint)
Artix™-7 FPGA
Artix™-7 FPGA
Kintex™-7 FPGA
Kintex™-7 FPGA
28K Logic Cells (~430K)
85K Logic Cells (~1.3M)
125K Logic Cells (~1.9M)
235K Logic Cells (~3.5M)
240KB (60)
560KB (140)
1,060KB (265)
1,860KB (465)
80
220
400
760
58 GMACS
158 GMACS
480 GMACS
912 GMACS
—
Gen2 x4
Gen2 x8
—
2x 12 bit, 1 MSPS ADCs w ith up to 17 Differential Inputs
Agile Mixed Signal (AMS) / XADC
AES and SHA 256b for secure configuration
Security
Multi-Standards I/O(2)
100
200
250
350
Serial Transceivers (2)
—
—
4
12
Notes: 1. Static memory interface combined w ith the usage of many peripherals could require more than 54 I/Os. A designer can use the Programmable Logic I/Os.
2. Total Number of I/O and Transceivers depends on package used.
3. Eqivalent ASIC gate count is dependent of the function implemented. The assumption is 1 Logic Cell = ~15 ASIC Gates.
4. Preliminary product information. Subject to change. Please contact your Xilinx representative for the latest information
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Zynq-7000 EPP Device Table
HW Designer’s View
Zynq™-7000 Extensible Processing Platform
Device Name
Z-7010
Z-7020
Z-7030
Z-7040
Part Number
XC7Z010
XC7Z020
XC7Z030
XC7Z040
Processing System
(Dual ARM® Cortex™-A9 MPCore™ w ith NEON™ & Double
Precision FPU Cache, Mem ory Controllers, DMA, Security
and Peripherals)
Xilinx 7 Series Program m able Logic Equivalent
Program m able Logic Cells (Approxim ate ASIC Gates (2))
Program m able Logic
Same Processing System for All Devices.
Artix™-7 FPGA
Artix™-7 FPGA
Kintex™-7 FPGA
Kintex™-7 FPGA
28K Logic Cells (~430K)
85K Logic Cells (~1.3M)
125K Logic Cells (~1.9M)
235K Logic Cells (~3.5M)
Logic Cells
28,160
85,120
125,760
235,840
Look-Up Tables LUTs
17,600
53,200
78,600
147,400
Flip Flops
35,200
106,400
157,200
294,800
240 KB (60)
560 KB (140)
1,060 KB (265)
1,860 KB (465)
Extensible Block RAM (# 36 Kb Blocks)
80
220
400
760
58 GMACS
158 GMACS
480 GMACS
912 GMACS
—
Gen2 x4
Gen2 x8
Program m able DSP Slices (18x25 MACCs)
Peak DSP Perform ance (Sym m etric FIR)
—
PCI Express® (Root Com plex or Endpoint)
2x 12 bit, 1 MSPS ADCs w ith up to 17 Differential Inputs
Agile Mixed Signal (AMS) / XADC
Security(1)
Package Type
Packages
AES and SHA 256b for secure configuration
CSG400
CSG484
CSG400
CSG484
FBG484
FBG676
FFG676
FBG676
FFG676
FFG900
Size (m m )
17x17
19x19
17x17
19x19
23x23
27x27
27x27
27x27
27x27
31x31
Pitch (m m )
0.8
0.8
0.8
0.8
1.0
1.0
1.0
1.0
1.0
1.0
Processing System Total I/Os (includes Multiplexed I/Os)
130
130
130
130
130
130
130
130
130
130
Multi-Standards and Multi-Voltage SelectIOTM Interfaces
(1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V)
100
100
120
200
100
100
100
100
100
200
Multi-Standards and Multi-Voltage High Perform ance SelectIO
Interfaces
(1.2V, 1.35V, 1.5V, 1.8V)
—
—
—
—
63
150
150
150
150
150
8
12
—
—
—
—
4
4
4
8
N/A
N/A
N/A
N/A
6.6 Gb/s
6.6 Gb/s
10.3 Gb/s
6.6 Gb/s
Serial Transceivers
Maxim um Transceiver Speed (Fastest Speedgrade)
Notes: 1. Security is shared by the Processing System and the Programmable Logic.
2. Eqivalent ASIC gate count is dependent of the function implemented. The assumption is 1 Logic Cell = ~15 ASIC Gates.
3. Preliminary product information. Subject to change. Please contact your Xilinx representative for the latest information
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10.3 Gb/s 10.3 Gb/s