XC5200 Family
A Low-cost Gate Array Alternative
®
XC5200 FPGA Family
 Up to 23,000 gates
 50-MHz system
performance
 Robust feature set
 Unlimited
reprogrammability
 Pin-locking flexibility:
VersaRingTM routing
 5V devices
®
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XC5200 Family Features
 Gate array replacement success since 1995
— World’s fastest 5V FPGA volume ramp
 A low cost FPGA/gate array alternative
— Low cost, process-optimized architecture
— 5V, 0.5 micron process
 High performance with robust feature set
—
—
—
Carry logic
Cascade chain
JTAG logic
3-state buffers
4 global nets
Slew rate control
®
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XC5200 Architecture Overview
 Architecture highlights
— VersaBlockTM logic
module
— VersaRing I/O interface
— General Routing Matrix
(GRM)
®
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Abundant VersaBlock Routing
 VersaBlock equals:
— Configurable Logic Block
(CLB)
– 4 identical Logic Cells
– 4 3-state buffers
— Local Interconnect Matrix
(LIM)
– 100% local connectivity
– Up to 23 in, 8 out
— Direct connects
 Result: abundant local
routing
— Minimizes routing
congestion
— Granular and
symmetrical
®
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XC5200 Configurable
Logic Block
 Configurable Logic Block
(CLB)
— 4 identical Logic Cells
— 20 inputs, 12 outputs
— 2 5-input functions
 Logic Cell (LC0 - LC3)
— Function generator,
register, & control logic
— Independently usable F &
FD
— Programmable flip-flop or
latch
— Fast carry logic or
cascade chain
— Independent feedthrough
®
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XC5200 Carry Logic: 4-bit Adder
carry out
®
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XC5200 Cascade Chain:
16-bit Decoder
 Fast implementation of
wide input functions
 Adjacent CY_MUX
connects to provide
cascadable decode
logic
 Flexible LUT allows
general decode, AND
and OR cascade
chains
®
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XC5200 Family
Efficient 5-Input Functions
 Allows any combination of
2 separate 5-input
functions in one CLB
 LC0 and LC1 and/or LC2
and LC3 combined with
F5_MUX
 Unified library support:
— F5MAP or F5_MUX
 Efficient 4:1 muxes
®
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Optimizing 5-Input Functions
- or Five input AND using F5_MUX
Five input AND using F5MAP
Both schematics will result in identical implementations
®
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Implementing 4:1 MUX
Using F5_MUX
 Allows 4:1 muxes in 1/2
CLB
®
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Abundant Routing Resources
 Six Levels of Hierarchy
Local
Interconnect
Matrix
Single
Length
Lines
 General Routing Matrix
— 10 single-length lines
— 4 double-length lines
— 8 long lines per channel
 VersaBlock
— Local Interconnect Matrix
— Direct connects to all
neighbors
— Logic cell feedthrough
Longlines
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Double
Length
Lines
Direct
Connects
®
XC5200 Global Line Network
 4 global clock buffers
 Direct access to all CLB
clock pins (CK)
 Access to non-clock pins
via GRM
 Buffers can be sourced by
IOB or internal routing
®
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XC5200 TBUF Connectivity
 Four TBUFs/CLB
 Any CLB output can drive
any TBUF
 “Weak-keeper” circuit
maintains previous state
 No pull-ups; use cascade
chain for wired functions
®
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VersaRingTM: High Utilization
AND Pin Assignment Flexibility
 Versatile interface
between internal logic and
I/O
— I/O decoupled from core
logic
— Incremental edge routing
 VersaRing resources
— 8 horizontal/vertical
longlines
— 4 direct-connects in/out
— 4 double-length lines to
GRM
— 10 single-length lines to
GRM
— 8 single-length lines to
adjacent VersaRing tile
®
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XC5200 Input/Output Block
 Selectable input, output or 3state
 Optional pull-up/pull-down
 Dedicated boundary scan
logic
 8-mA output sink & source
current
 4 global nets
 Programmable slew rate
control
 Programmable input delay line
®
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XC5200 Family
XC5202 XC5204 XC5206
XC5210 XC5215
Max Logic Gates
3,000
6,000
10,000
16,000
23,000
Typical Gate Range 2-3K
4-6K
6-10K
10-16K
15-23K
Logic Cells
256
480
784
1,296
1,936
Flip-Flops
256
480
784
1,296
1,936
Max I/O
81
124
148
196
197
Performance
-6/-5/-4/-3 -6/-5/-4/-3 -6/-5/-4/-3 -6/-5/-4/-3 -6/-5/-4/-3
Packages:
VQ64
PC84
PC84
PC84
PC84
PQ/VQ100 PQ/VQ100PQ/VQ100
TQ144 TQ144
TQ144
PQ160 PQ160
PQ160
PQ160
PQ208
PQ208
HQ208
PQ240
HQ240
100% Footprint Compatibility in Common Packages
®
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XC5200 Success Since 1994
Revenue
Units
High Volume Design Wins
• Digital camera add-in card
• Cable modem
• Set-up box
• Video game
• CD player
• Graphics add-in card
• 10/100 Mbit Ethernet add-in cards
XC5200 support to year 2005 and beyond
®
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XC5200 Series Success
Market
Consumer-Video
Consumer-Audio
Consumer-Video
Data Processing
Data Processing
Communication
Communication
Communication
Automotive
Application
Set Top Box
High-end CD Player
Video Game
PC Add-in Card
Display Monitor
PCS Base Station
Modem Card
Voice Mail
Shock Absorber Control
Volume
150,000 units
25,000 units
50,000 units
250,000 units
100,000 units
25,000 units
100,000 units
50,000 units
>100,000 units
®
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Xilinx XC5200 vs. Altera Flex 6K
 XC5200 Advantages
—
—
—
—
Segmented interconnect
Lower power
Five XC5200 devices vs. three 6K devices
More features (flip-flop clock enables, cell feedthrough, VersaRing, VersaBlock, etceteras.)
 Altera Flex 6K is a poor copy of the innovative
XC5200 architecture
®
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Logic Cell Comparison
Feature
XC5200
Flex 6K
Clock enable
Yes
No
Direct feed-through
Yes
No
Independent logic &
flip-flop outputs
Yes
No
Clocks per flip-flop
1:4
2:10
Logic Cells per block
4
10
®
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XC5200 Benefit Summary
 Process optimized architecture
— Small die size
— Unlimited reprogrammability
— Up to 50-MHz performance
 VersaRing I/O interface
— Pin assignment flexibility
— Logic change flexibility without requiring PCB relayout
 100% footprint compatibility
— Easy density migration within family
®
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XC5200 Robust System Level
Features
 Fast carry logic
— High-speed arithmetic functions
 Dedicated JTAG logic
— Eases system-level testability
 3-state buffers
— Efficient on-chip bussing
 Cascade chain
— Efficient wide-input functions
®
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