80386DX
Task Switching
• The multitasking/multiuser OS needs the
ability to rapidly switch between tasks or
processes.
• 80386DX supports this operation by providing
a task switch instruction hardware.
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Task Switching
• The task switch operation
– saves the entire state of the machine(all of
reg.s,address space and a link to previous task),
– loads a new execution state,
– performs protection checks and
– commences execution in the new task
• in about 17 microseconds
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Task Switching
• Each task must have a Task State Segment
(TSS) associated with it.
• The current TSS is identified by the Task State
Segment Register(TR)
• TR contains the selector referring to TSS
Descriptor that defines the current TSS
• Returning from a task through IRET makes the
current task state to be saved and old task
state is restored from TSS
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TSS of 80386
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• A task switching operation involves the
following steps:
1. Checking that the current task is allowed to
switch to the designated task
2. Checking that the TSS descriptor of the new
task is marked present and has a valid limit
3. Saving the state of the current task
4. Loading the task register with the selector of
the incoming task’s TSS descriptor
5. Loading the incoming task’s state from its TSS
and resuming execution
Virtual 8086
• UQ: Write short note on V-86 mode of
operation(05Marks)
Virtual 8086
• It allows the execution of 8086 applications
while still allowing to take full advantage of
protection mechanism
• It allows simultaneous execution of 8086 OS
and its applications and an 80386DX OS and
both 80286 and 80386DX applications
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Virtual Mode Addressing Mechanism
• The segment registers are used as in REAL
mode
• The contents of segment register is shifted by
4 bits and added to offset to form linear
address
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Paging in Virtual Mode
• It allows concurrent running of multiple VM
tasks.
• It is not necessary that paging should be
enabled in V86 mode but for multiple tasks it
is required
• Paging allows 20-bit linear address to form
256 pages and can be allocated anywhere in
4GB physical memory
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Paging in Virtual Mode
• Since CR3 is loaded by a task switch, each VM
task can use a different mapping scheme to
map pages to different physical location
• The paging hardware allows the sharing of
8086 application.
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Virtual Mode Memory Management
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Protection in Virtual Mode
• All VM Tasks execute at a privilege level 3.
• Virtual 8086 mode are subject to all
protection checks defined in protection mode
• An attempt to execute privileged instruction
will cause an exemption
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Structure of a V86 Task
• A V-86 task consists
– Partly of 8086 program
– Partly of 80386 code that serves as the VM
(Virtual Machine)monitor
• To run V86 mode 8086 program needs:
– A V-86 monitor
– Operating System Services
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V86 Monitor
• It is an 80386 code that executes at level 0
• It consists primarily of initialization and
exception handling procedures.
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Entering and Leaving V86 Mode
• The processor can enter V86 by two means:
• Case 1:
– A task switch to an 80386 task loads the image of
EFLAGS from the new TSS.
– The TSS of the new task contains the VM flag
– VM = 1 of the new EFLAGS indicates that the new
task is executing 8086 instructions and therefore
the segment registers from the TSS forms base
addresses as 8086 would.
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Entering and Leaving V86 Mode
• Case 2:
– An IRET from a procedure of an 80386 task loads
the image of EFLAGS from the stack
– VM = 1 indicates that the procedure to which
control is being returned is an 8086 procedure
– The CPL at the time the IRET is executed must be
zero, else the processor does not change VM.
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Entering and Leaving V86 Mode
• Case 2:
– An IRET from a procedure of an 80386 task loads
the image of EFLAGS from the stack
– VM = 1 indicates that the procedure to which
control is being returned is an 8086 procedure
– The CPL at the time the IRET is executed must be
zero, else the processor does not change VM.
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Entering and Leaving V86 Mode
• The processor leaves V86 mode when an
interrupt or exception occurs.
• Case 1:
– The interrupt or exception causes a task switch
which loads EFLAGS from the TSS of the new task.
– If the new TSS is an 80386 TSS and VM bit is 0 in
the EFLAGS, then the processor
• clears the VM bit of EFLAGS
• loads the segment registers from the new TSS and
• begins executing the instructions of the new task
according to 80386 protected-mode semantics.
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Entering and Leaving V86 Mode
• Case 2:
– The interrupt or exception vectors to a privilegelevel zero procedure.
– The processor stores the current setting of EFLAGS
on the stack, then clears the VM bit.
– The interrupt or exception handler, therefore,
executes as 80386 protected-mode code
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