Linux on an FPGA
Team:
Anthony Bentley
Dylan Ismari
Bryan Myers
Tyler Jordan
Mario Espinoza
Sponsor: Dr. Alonzo Vera
Presentation Overview
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Project Description
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Why it's necessary
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Milestones
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Challenges and Concerns
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Design process
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Milestones
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Current Status
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Deliverables
Project Description
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Get a working Linux kernel running on an FPGA
implementing the OpenRISC processor
architecture
Document the process for reproducibility
Create low-level hardware and software
modules using the base platform
Why it's necessary
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The process of loading a Linux kernel onto an
FPGA is complicated, time consuming, and not
well documented
This project will streamline the process and be
used as a starting place for further development
Contribute to the Open Source community
Team Breakdown
Hardware Team: Dylan Ismari, Tyler Jordan, Mario
Espinoza
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In charge of implementing the hardware cores
Software Team: Anthony Bentley, Bryan Myers, Mario
Espinoza
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In charge of configuring and loading the kernel, and
writing software drivers
Team Leader: Anthony Bentley
Sponsor: Dr. Alonzo Vera
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Provides insight, mentorship and previous experience
Hardware:
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Technologies
OpenRISC – opensource processor architecture made
available from opencores.org
ML505 board – FPGA made by Diligent
Xilinx ISE development environment – Environment
we will use to develop the hardware specifications
Software:
OpenRISC development toolchain – GCC configured
for OpenRISC, Binutils, uClibc, Busybox, OpenRISC
simulator
Linux kernel – Pared down and configured for
OpenRISC
Challenges and Concerns
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Inconsistent environments – drivers, software
and toolchains
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Bad documentation
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Closed-source software
Design Process: Methodology
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Iterative development – promotes flexibility,
easier to debug
Divide the design steps into a set of Tiers where
Tier 0 is the minimum functionality of the
system and Tier 3 has all the desired
functionality
Design phase for each Tier will include a
hardware core, software drivers, and
testing/debugging
Design Process: Tier 0
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Tier 0 is the absolute minimum needed for a
working system
Includes OpenRISC CPU configured for the
ML505 FPGA
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RAM
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UART and wishbone
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SD-Flash Memory to boot the kernel
Design Process: Tier 0
Design Process: Tier 1
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Tier 1 will build VGA and USB cores on top of
Tier 0 through the wishbone bus
VGA and USB cores are required for our
system to interact with devices such as a
display and webcam
Minimum tier necessary for a demonstration of
the project
Design Process: Tier 1
Design Process: Tier 2
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Tier 2 of the design implements an ethernet
core
Ethernet capabilities will allow our system to
network with other systems
Design Process: Tier 2
Design Process: Tier 3
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Tier 3 will implement SATA hard disk and audio
cores
Will be implemented as time allows
The “icing on the cake” for our system, allows
access to mass storage and audio capabilities
Design Process: Tier 3
Milestones
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Setting up repository and toolchain
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Running software on OpenRISC simulator
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Linux demo on physical hardware
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External hardware modules
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Software applications and drivers
Current Status
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Git repository – set up and storing our code and
documents
Toolchain – installed and working on
development computers
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Next Month:
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Synthesized CPU core loaded on board
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Compiling and running our own programs in
simulation
Deliverables
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Documentation – Upstream READMEs and
web/wiki pages, full tutorials, requirements
document, project timeline and Gantt chart,
meeting minutes, and weekly reports
Source Code – VHDL and Verilog hardware
specifications, C code for drivers and
applications
Git repository: Stores up-to-date versions of all
documentation and source code as well as
revision history