Operating Systems and Computer
Organization
Chapter 4
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Operating System and Computer
Organization
•
•
•
•
•
•
•
Organization of Conventional Computers
The ALU
The Control Unit
The Memory Unit
I/O Devices
Interrupts
Hardware protection
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Conventional Computer Organization
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The ALU
Operands
R1
R2
….
Rn
Functional Unit
Status Registers
Result
MDR
MAR
CMD
To/from main memory
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Memory Data Access
Main Memory
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Program Specification
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Machine Language
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Control Unit
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Control Unit Operation
• Instruction Fetch Phase: instruction is retrieved
from memory
• Instruction Decode Phase: instruction is decoded
and control signals generated
• Instruction Execute Phase: ALU op, memory
data access, or I/O op is executed.
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Control Unit Operation
PC = <Machine-Start-Address> ;
IR = Memory[PC] ;
haltFlag = CLEAR ;
Decode(IR);
while (haltFlag not SET) {
Execute(IR);
PC = PC + InstructionSize;
IR = Memory[PC] ;
Decode(IR);
}
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How does it all start?
• When the computer is started, the control unit branches to
a fixed memory location; e.g. initial PC value hardwired.
• The fixed location is a ROM address that contains a the
BIOS loader.
• The BIOS loader loads a “bootstrap loader” from the disk
“boot sector” into memory and branches to the bootstrap
loader program.
• The bootstrap loader may be comprehensive enough to
load the nucleus of the OS; Otherwise, it loads a loader
program that does so.
• Once bootstrap phase is done, any program can be run by
loading it in memory and loading its initial address in the
PC (fetch-decode-exec algorithm)
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Bootstrapping
Bootstrap loader (“boot sector”)
1
BIOS loader
0x0000100
0x0001000
Fetch Unit
PC
0000100
IR
…
Decode Unit
Execute Unit
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Primary Memory
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Bootstrapping
Bootstrap loader (“boot sector”)
1
2
Fetch Unit
PC
0001000
IR
…
BIOS loader
0x0000100
0x0001000
Loader
0x0008000
Decode Unit
Execute Unit
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Primary Memory
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Bootstrapping
Bootstrap loader (“boot sector”)
1
2
Fetch Unit
BIOS loader 0x0000100
0x0001000
3
PC
0008000
Decode Unit
OS
IR
…
Execute Unit
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Loader
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0x0008000
0x000A000
Primary Memory
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Bootstrapping
Bootstrap loader (“boot sector”)
1
2
Fetch Unit
Loader
000A000
Decode Unit
OS
IR
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0x0001000
3
PC
Execute Unit
BIOS loader 0x0000100
…
0x0008000
0x000A000
Primary Memory
4. Initialize hardware
5. Create user environment
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6. …
Primary Memory Unit
• Main (Primary) Memory holds both program and
data while they are being executed by CPU.
• The main memory interface consists of the
registers: MAR, MDR, CMD.
• Unit of information accessed depends on the
width of memory and width of data bus.
• Max. addressing space depends on width of
address bus.
• One request at a time.
• CPU and I/O devices may contend for memory
access.
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Primary Memory Unit
MAR
1234
MDR
98765
Command
read
Read Op:
1. Load MAR with address
2. Load Command with “read”
3. Data will then appear in the MDR
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1
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1234 98765
n-1
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I/O devices
• Each I/O device consists of a device controller and
the physical device itself.
• Devices:
- storage devices: for permanent storage (e.g.
disk, tape)
- communication devices: to transfer data from
the computer to another machine (e.g.
keyboard, a terminal display, or a serial port to
a modem or a network).
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I/O Devices (cont.)
• Device controller: hardware that connects the
device to the computer.
– continuously monitors and controls the
operation of the device.
– provides an interface to the computer.
• Device Manager: program (part of the OS) that
manages device controllers
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Software in the CPU
The Device-Controller-Software Relationship
Application
Program
•Device manager: Program to manage
device controllers
Abstract I/O
Machine
Device Controller
Device
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Device Controller Interface
...
busy
Command
done
Error code
Status
...
busy done
0
0 idle
0
1 finished
1
0 working
1
1 (undefined)
Data 0
Data 1
Logic
Data n-1
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I/O Devices (cont.)
• How does the computer communicate with an I/O device?
– device controller has a set of registers: Command reg.,
Status reg., Data regs., Address regs, etc.
– Status reg.: tells the computer the status of device: idle,
busy, non functional, etc.
– A process can request an operation from device by
placing a command in device’s Command reg.
– Data regs. Are used to exchange data
– Address regs: used to indicate address of
source/destination
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Performing a Write Operation
while(deviceNo.busy || deviceNo.done) <waiting>;
deviceNo.data[0] = <value to write>
deviceNo.command = WRITE;
while(deviceNo.busy) <waiting>;
deviceNo.done = TRUE;
• Devices much slower than CPU
• CPU waits while device operates
• Would like to multiplex CPU to a different process
while I/O is in process
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…
CPU
Ready Processes
Ready Processes
Ready Processes
CPU-I/O Overlap
…
CPU
Device
CPU
Device
I/O Operation
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Device
Uses CPU
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I/O Devices (cont.)
• How does the computer operate on device
controller registers? How does it identify each
device?
1. Instruction set of the CPU may have special
instructions to operate on I/O devices. E.g.
Input
DeviceN, DeviceRegisterN, Rn
Output
Rn, DeviceN, DeviceRegisterN
etc.
2. Memory Mapped I/O
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Memory Mapped I/O
• A set of memory addresses are reserved for I/O
devices. E.g: 0000 to 3FF in Intel 8086
– each device is assigned a sub-set of memory
addresses.
– A memory address is assigned to each register
of each device controller
• regular CPU instructions are used to interact with
device controller.
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I/O Devices (cont.)
How does the CPU know when a device controller
has completed the requested operation?
• 1. Polling: CPU continually check status register
of device controller
• 2. Interrupt driven I/O: device controller sends a
signal to CPU through the bus.
– bus must support interrupts
– CPU must include an interrupt flag
– CPU instruction set must include instructions to
test and set/clear interrupt flag.
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Determining When I/O is Complete
CPU
Interrupt Pending
Device
Device
Device
• CPU incorporates an “interrupt pending” flag
• When device.busy  FALSE, interrupt pending flag is set
• Hardware “tells” OS that the interrupt occurred
• Interrupt handler part of the OS makes process ready to run
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Fetch-Execute Cycle with Interrupt
PC = <Machine-Start-Address> ;
IR = Memory[PC] ;
haltFlag = CLEAR ;
Decode(IR);
while (haltFlag not SET) {
Execute(IR);
PC = PC + InstructionSize;
if (InterruptFlag) {
save current PC; // (e.g. in system stack)
PC = AddressOfInterruptHandler;
reset InterruptFlag;
}
IR = Memory[PC] ;
Decode(IR);
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Hardware Protection
• Dual-Mode Operation
• I/O Protection
• Memory Protection
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Dual-Mode Operation
• Sharing system resources requires that the
operating system ensures a level of protection to
the users:
– an incorrect program can not cause other
programs to execute incorrectly
– that a user program cannot have access
resource for it does not have permission
– some operations should not be performed by
user programs
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Dual-Mode Operation (Cont.)
• Provide hardware support to differentiate between
at least two modes of operations:
1. User mode - execution done on behalf of the
user
2. Supervisor mode (also called monitor mode or
privileged mode or protected mode or system
mode etc.) - execution done on behalf of the
operating system
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Dual-Mode Operation (Cont.)
• Mode bit is added to computer hardware (to
CPU) to indicate the current mode.
Supervisor mode (0)
user mode (1)
• Instruction set: privileged instructions and nonprivileged instructions - privileged instructions
can be executed only in supervisor mode.
• Operating system can execute any instruction.
• Must insure that a user program can not execute
privileged instructions directly.
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Going from User Mode to
Supervisor Mode
• When a user program need service from the OS (e.g.
open a file, read, write, allocate memory etc.), it makes
a system call: i.e. a call to one of the OS functions.
• OS functions must run in supervisor mode.
• User processes run in user mode.
• computer designers had to come up with some kind of
approach that would allow a user process to
miraculously change the CPU mode to supervisor and
branch to one of these OS functions simultaneously.
The trap instruction is just the ticket.
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Trap Instruction
• A trap instruction is a machine-level instruction
that:
– Switches the CPU mode to supervisor
– Looks up the address of the target function in a kernelspace trap table
– Branches to the entry point of the kernel-space function
using the address from the trap table
• The trick is that the instruction does all three of
these steps rather than just one or two. And trap is
the only instruction that sets the CPU mode bit to
supervisor.
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• The system call is translated into a trap
instruction
– the trap instruction is a machine level
instruction that is part of the instruction set of
the processor
• The trap instruction will do the following:
– change mode-bit to supervisor mode
– jump to a trap handler which will determine
which OS function is being requested etc.
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Dual-Mode Operation (Cont.)
Processor must provide the following:
• A Mode-bit flag
• Instruction set: privileged instructions and nonprivileged instructions
• A trap instruction
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I/O protection
•
•
•
•
•
Instruction to change the mode must be privileged
I/O operation are privileged instructions
How can user program perform I/O?
It makes a system call to OS.
When a system call is made a trap instruction is
executed:
– sets the mode to supervisor mode
– OS function verifies that parameters are correct and
legal, executes the request, sets mode to user mode,
and returns control to user program
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Memory Protection
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Example of Memory Protection
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Protection Hardware
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