SPRING 2026
ECE-124: DIGITAL CIRCUITS AND SYSTEMS
LAB 1 ADDENDA
LAB SAFETY POINTERS
• Take note of the Exit Door
• Take note of the preferred building exit for this Lab
• First Aid Kit is available in the Lab
• Emergency information near the Lab door
• If the alarm activates, exit the Lab promptly and orderly.
LAB RULES
• NO FOOD OR DRINK IN THE LAB AT ANY TIME
• The Lab experiments are done in teams of two people per team. No changes in team members
permitted after first lab session.
• Each Team member is to develop the Lab Project files on the workstation C: Drive. After the lab time,
zip the Lab Project folder and copy it to the N:Drive.
• Each student in the Team should get a copy of the project after each Lab.
• Each student is responsible for their own Lab Project design file information.
• Logoff and Clean up your workstation before leaving.
• Learn the Lab entry code please or keep a handy reference note on your phone.
• BLOCKING THE LAB DOORS OPEN (with chairs etc.) OR LEAVING THE LAB WORKSTATIONS IN
AN UNTIDY STATE ARE GROUNDS FOR CLOSING THE LAB OUTSIDE OF LAB SESSION HOURS.
LAB 1 TOPIC: LOGICALSTEP DEVELOPMENT PLATFORM
LAB TOOL FOR THE S2026 TERM
LAB 1 TOPIC: WORKSTATION SETUP
• You will create your PROJECT Folders on the C:Drive for each unique LAB Project
• Zipped LAB folders to be downloaded from LEARN into your C: Drive
• Further setup details are explained in the Lab Manual
• At the end of the Lab Session, EXIT ALL QUARTUS TOOLS FIRST
• Then zip your Project folder (on the C:Drive) and copy it to the N:Drive. This will be your backup
project location.
LAB 1 TOPIC: LAB OUTLINE & GOALS
• Digital Signals Versus Analog Signals
• What is an FPGA? How do we use them in a digital design?
• Intended Learning Outcomes:
• Construct a digital circuit in Schematic and Verilog descriptions
• Verify digital circuit representations using functional simulations
• FPGA hardware verification:
• Download your FPGA design(s) into the LogicalStep FPGA
• Activate inputs (Push Button Keys) to confirm simulations
LAB 1 TOPIC: DIGITAL VS ANALOG (SIGNALS)
LAB 1 TOPIC: WHAT IS FPGA TECHNOLOGY?
- FOR DIGITAL SIGNALS
LAB 1 TOPIC: DIGITAL CONFIGURATIONS
LAB 1 DESIGN ENTRY: THE BIG PICTURE
Push Buttons
Verilog_gates
Switches
Library
components
Schem_gates
Top Level Starting Schematic is provided on Learn
Leds[7..4]
Leds[3..0]
LAB 1: INITIAL SCHEMATIC (TOP-LEVEL)
The Inputs and Outputs for the Lab1 FPGA design are already defined for you. You will
be adding logic functions to this schematic
LAB 1 DESIGN ENTRY: BASIC LOGIC GATES
IN 1 input
0
0
1
1
IN 0 input
0
1
0
1
XOR output
0
1
1
0
OR output
0
1
1
1
NAND output
1
1
1
0
AND output
0
0
0
1
GATE SYMBOL →
These functions will be added to your LogicalStep_Lab1_top
schematic in two sub-blocks. One will be in schematic form and the
other in Hardware Description Language form (Verilog)
LAB 1 DESIGN ENTRY: SCHEMATIC SUB-BLOCK
LAB 1 : ADDING SCHEMATIC SUB-BLOCK CONNECTIONS
Your design will now be processed (synthesized into a gate-level model) for simulation.
LAB 1 : BASIC LOGIC GATES SIMULATION
IN 1 input
IN 0 input
0
0
1
1
0
1
0
1
GATE SYMBOL →
XOR
output
0
1
1
0
OR output
0
1
1
1
NAND
output
1
1
1
0
AND output
0
0
0
1
These functions will be
simulated to observe their
functionality with typical
stimulus at the inputs.
Simulations is also very
useful for design
debugging.
The Lab Manual has
further details.
Below the stimulus inputs
are the outputs. They
default to UNDEFINED
STATES until the simulation
is run.
The leds7 to leds4 will
stay undefined in the
simulation because they
are not yet used.
LAB 1 DESIGN ENTRY: VERILOG SUB-BLOCK IS IDENTICAL
LAB 1 : ADDING THE VERILOG GATES SUB-BLOCK
LAB 1: SCHEMATIC AND VERILOG GATES SIMULATION
IN 1 input
0
0
1
1
IN 0 input
0
1
0
1
AND output
0
0
0
1
NAND output OR output
1
0
1
1
1
1
0
1
XOR output
0
1
1
0
GATE SYMBOL →
This time, the outputs of
leds7 to leds4 should
match the states for the
outputs of leds3 to leds0
respectively.
LAB 1 : ADDING OUTPUT SIGNAL POLARITY CONTROL
(ACTIVE-HIGH OR ACTIVE-LOW OUTPUTS)
A SINGLE TWO-INPUTS GATE TYPE IS CHOSEN
SO THAT WHEN:
POLARITY_CNTRL IS HIGH, OUTPUTS ARE ACTIVE HIGH
POLARITY_CNTRL IS LOW, OUTPUTS ARE ACTIVE LOW
SCHEMATIC
REPRESENTATION
Verilog
REPRESENTATION
LAB 1 : ADDING OUTPUT SIGNAL POLARITY CONTROL
LAB 1 : SIMULATING OUTPUT SIGNAL POLARITY CONTROL
SET THE SIMULATION END TIME BEFORE CREATING THE STIMULUS FOR THE INPUTS.
Simulation time is extended to 2 usec.
SW(1) is LOW FOR THE FIRST HALF, HIGH FOR THE SECOND HALF
PB1, PB0 inputs have their stimulus extended for repetition
Observe the outputs for Active-High, Active Low operation
LAB 1: DOWNLOADING THE DESIGN TO LOGICALSTEP
MOVING TO THE LOGICALSTEP we have added inverters to the input PB
signals since those inputs on the LogicalStep board are ACTIVE-LOW.
LAB 1: NOTING THE LEDS ON THE LOGICALSTEP BOARD
This final design will be FITTING
compiled and downloaded into
the LogicalStep FPGA. THIS
WILL BE USED FOR YOUR LAB1
DEMO AT THE NEXT LAB
SESSION.