Memory Controller and
DDR PHY
Memory Controller
• Memory Controller and DDR PHY in a SoC/ASIC, they are two
different blocks that work together to communicate with DDR
SDRAM.
• The Memory Controller (MC) is the digital logic that manages access
to external DDR memory.
• It sits between the CPU/SoC and the DDR PHY:
The controller handles things such as:
• Read and write requests
• Address translation
• Row/column/bank addressing
• DDR commands
• Scheduling memory requests
• Refresh operations
• Timing requirements
• Initialization/training coordination
• Arbitration between multiple masters
• Error handling such as ECC, if implemented
For example, when the CPU says:
• "Read data from address 0x80001000"
• the memory controller determines which DDR bank, row and column
correspond to that address and generates the appropriate DDR transaction.
DDR PHY
• PHY = Physical Layer
• The DDR PHY is much closer to the actual DRAM pins.
• It converts the controller's internal digital signals into the
electrical/timing signals required by DDR.
• The PHY deals heavily with high-speed timing.
• Typical PHY responsibilities include:
• DQ data transmit/receive
• DQS generation and capture
• Clock generation
• DLL/PLL
• Read/write leveling
• Write leveling
• DQS training
• Delay-line control
• Voltage/reference handling
• Timing calibration
• Serialization/deserialization
• I/O electrical interface
+----------------------+
CPU / AXI Master |
|
---------------->
| Memory Controller |
|
|
| Address Decoder |
| Request Queue
|
|Command Scheduler |
| Refresh Controller |
| Read/Write FSM |
| ECC (optional)
|
+----------+-----------+
|
| DFI-like interface
v
+----------------------+
|
DDR PHY
|
|
|
| TX Data Path
|
| RX Data Path
|
|DQS Generation
|
| Read Capture
|
| Training
|
| Calibration
|
+----------+-----------+
|
DDR signals
|
+-------------+-------------+
|
|
DDR4/DDR5 DRAM chips
System level, sub system level and IP level
• In VLSI/SoC design, the terms IP level, subsystem level, and system
level describe different levels of design hierarchy.
System Level
|
+-----------------------------+
|
|
Subsystem A
Subsystem B
|
|
IPs
IPs
|
+---+---+---+
| | | |
IP IP IP IP
IP Level
• IP = Intellectual Property
• An IP is a relatively self-contained block designed to perform a particular
function.
• Examples:
• UART IP , SPI IP , I2C IP , GPIO IP , DMA IP , SRAM controller IP
• DDR Memory Controller IP
• DDR PHY IP
• USB controller IP
• PCIe controller IP
• AXI interconnect IP
• At IP level, you concentrate mainly on:
• RTL design
• Functional behavior
• FSMs
• Registers
• Interfaces
• Timing
• Assertions
• Functional coverage
• Unit-level verification
• If you're designing a UART:
UART
|
+-- TX logic
+-- RX logic
+-- Baud-rate generator
+-- Control registers
+-- Status registers
UART IP
+-------------+
TX <----|
|
RX ---->| UART
|
| Controller |
|
|
+-------------+
|
AXI
Subsystem Level
• Several IPs are integrated together to create a subsystem.
• For example, consider a Memory Subsystem:
Memory Subsystem
|
+------------+------------+
|
|
|
AXI
Memory Ctrl DDR PHY
|
|
|
+------------+------------+
|
DDR4/DDR5
• The individual blocks are IPs:
Connectivity Subsystem
• AXI Interconnect → IP
|
+----------+----------+
• Memory Controller → IP
|
|
|
USB
PCIe
Ethernet
• DDR PHY → IP
|
|
|
• Together they form a Memory Subsystem. +----------+----------+
|
AXI/NoC