I²C Protocol
Complete Technical Reference
Frame Format · Clock Sync · Arbitration · Clock Stretching
This reference covers the Inter-Integrated Circuit (I²C) protocol: bus structure, frame format, clock synchronisation,
multi-master arbitration, clock stretching, addressing modes, and practical design notes.
1. Overview
I²C (pronounced I-squared-C) is a synchronous, half-duplex, multi-master / multi-slave serial protocol developed by
Philips (now NXP) in 1982. It uses only two wires: Serial Data Line (SDA) and Serial Clock Line (SCL). Both lines are
open-drain with pull-up resistors, giving the bus a wired-AND property.
Parameter
Standard Mode
Fast Mode
Fast-Mode Plus
High-Speed
Max bit rate
100 kbit/s
400 kbit/s
1 Mbit/s
3.4 Mbit/s
Logic '1' drive
Pull-up only
Pull-up only
Pull-up only
Current source
Typical R_pull
10 kΩ
2.2 kΩ
1 kΩ
< 500 Ω
Introduced
1982
1992
2007
1998
2. Bus Structure & Electrical Characteristics
2.1 Open-Drain / Wired-AND
Every device on the bus can only pull a line LOW (by turning on an N-FET to GND). No device drives HIGH — the pull-up
resistor does that passively. This means: if any device pulls a line LOW, the bus is LOW. The bus is HIGH only when all
devices release it.
• Prevents bus contention — no short-circuit between a driver pulling HIGH and another pulling LOW.
• Enables clock stretching — a slave can hold SCL LOW to pause the master.
• Enables multi-master arbitration — masters can detect if they lost control of SDA.
• Pull-up value R_p must be chosen based on bus capacitance and desired speed.
2.2 Pull-up Resistor Sizing
The RC time constant formed by R_p and bus capacitance C_b limits the rise time. The I²C spec mandates maximum
rise times (t_r): 1000 ns (Sm), 300 ns (Fm), 120 ns (Fm+).
R_p_max = t_r / (0.8473 × C_b) [from spec: V_IL/V_DD ratio]
R_p_min = (V_DD - V_OL_max) / I_OL [e.g. (3.3V - 0.4V) / 3mA ≈ 967 Ω]
NOTE: For a 400 kHz bus with 100 pF capacitance, R_p ≈ 2.2 kΩ is typical. Larger capacitance → smaller R_p, which
means higher current draw.
3. Frame Format
An I²C transaction consists of a START condition, one or more frames, and a STOP condition. Each frame is 9 bits: 8
data/address bits + 1 ACK/NACK bit.
SCL
SDA
IDLE
S
ADDR[6:0]
R/W
ACK
DATA[7:0]
ACK
P
IDLE
Figure 1 — Complete I²C write transaction: S · ADDR[6:0] · W · ACK · DATA[7:0] · ACK · P
3.1 START and STOP Conditions
START and STOP are uniquely identified by SDA transitions while SCL is HIGH — the only time SDA is allowed to
change.
SCL
START Condition (S)
STOP Condition (P)
SCL
SDA
SDA
SDA falls while SCL HIGH
SDA rises while SCL HIGH
Figure 2 — START: SDA falls while SCL is HIGH. STOP: SDA rises while SCL is HIGH.
• START (S): Master pulls SDA LOW while SCL is HIGH. Marks start of transaction.
• Repeated START (Sr): A new START without a preceding STOP. Used to change direction or address without
releasing the bus.
• STOP (P): Master releases SDA HIGH while SCL is HIGH. Releases the bus.
3.2 Address Frame (7-bit)
The first frame after START contains the 7-bit slave address and a R/W■ bit. The master sends MSB first. Every slave on
the bus compares this address with its own.
Bit position
7
6
5
4
3
2
1
0 (bit 8)
Content
A6
A5
A4
A3
A2
A1
A0
R/W■
Direction
←MSB
-
-
-
-
-
LSB→ 0=Write, 1=Read
NOTE: Reserved addresses: 0x00 (general call), 0x01 (CBUS), 0x02 (different bus format), 0x03, 0x78–0x7B (10-bit
address prefix), 0x7C–0x7F (reserved). Usable 7-bit range: 0x08 – 0x77 (112 addresses).
3.3 10-Bit Addressing
10-bit addressing expands the address space to 1024 devices. The first byte sent is a reserved prefix 11110XX (where
XX are the two MSBs of the address), followed by a second byte with the remaining 8 address bits.
Frame 1: 1 1 1 1 0 A9 A8 W■ (master → slave, slave ACKs if 2 MSBs match)
Frame 2: A7 A6 A5 A4 A3 A2 A1 A0 (slave ACKs if full address matches)
3.4 ACK / NACK
After each 8-bit frame, the transmitter releases SDA. The receiver then drives SDA during the 9th clock pulse to signal
acknowledgement.
Signal
SDA during bit 9
Meaning
ACK
LOW (receiver pulls)
Data accepted. Continue sending.
NACK
HIGH (nobody pulls)
Not accepted. Master should stop or repeat.
• Slave sends NACK: address not recognised, or data byte not accepted (e.g. register overflow).
• Master sends NACK after the last data byte during a read, then sends STOP — tells slave it's done.
• If slave is busy (not yet ready), it may not ACK — master must retry.
3.5 Data Phase — Bit Timing
Data bits on SDA must be stable while SCL is HIGH. SDA may only change while SCL is LOW. This rule is violated only
for START and STOP conditions.
Timing Parameter
Symbol
Standard (100k)
Fast (400k)
Fm+ (1M)
SCL high period
t_HIGH
≥ 4000 ns
≥ 600 ns
≥ 260 ns
SCL low period
t_LOW
≥ 4700 ns
≥ 1300 ns
≥ 500 ns
SDA setup to SCL↑
t_SU;DAT
≥ 250 ns
≥ 100 ns
≥ 50 ns
SDA hold from SCL↑
t_HD;DAT
0 – 3450 ns
0 – 900 ns
0 – 450 ns
Rise time (SDA/SCL)
t_r
≤ 1000 ns
≤ 300 ns
≤ 120 ns
Fall time
t_f
≤ 300 ns
≤ 300 ns
≤ 120 ns
4. Clock Synchronisation
In a multi-master environment, two masters may start transmitting simultaneously and both generate SCL. The I²C spec
defines a hardware clock synchronisation mechanism that lets both masters use a single, compatible clock — no
software arbitration of the clock is needed.
4.1 Wired-AND Clock Synchronisation Mechanism
• Each master starts its SCL LOW period when it drives SCL LOW.
• Because SCL is open-drain, if any master holds SCL LOW, the bus is LOW — even if other masters have already
released it.
• A master waiting for SCL to go HIGH must wait until ALL masters have released SCL.
• The resulting clock has a LOW period = longest LOW of any master, and a HIGH period = shortest HIGH of any
master.
• This ensures all masters sample and transmit data at the same bit boundaries.
NOTE: Clock synchronisation is automatic — it's a property of the open-drain bus, not a protocol step. No master needs to
'know about' other masters for this to work.
5. Clock Stretching
Clock stretching allows a slave (or sometimes a slow master) to pause the bus by holding SCL LOW after the master has
released it. The master must check that SCL actually went HIGH before sampling or driving the next bit.
SLAVE holds SCL LOW
(clock stretching)
SCL
SDA
Slave processing / not ready
Figure 3 — Slave holds SCL LOW to pause master while it processes data.
5.1 How It Works
• After a clock HIGH period, master pulls SCL LOW to start the next bit.
• At the end of the LOW period, master releases SCL (stops driving it LOW).
• Slave detects its own internal data isn't ready, so it pulls SCL LOW itself.
• Master sees SCL still LOW (bus remains LOW). It waits.
• When slave is ready, it releases SCL. The pull-up drives SCL HIGH.
• Master detects SCL HIGH and resumes transmission.
5.2 Master Implementation Requirement
A master MUST check the actual SCL line state after releasing it, not just assume SCL went high based on its timer.
Microcontrollers with I²C hardware handle this automatically. Bit-banged implementations must read the SCL GPIO pin
after releasing it:
scl_release(); // stop driving SCL low
while (scl_read() == LOW) {} // wait for slave to release
delay_half_period(); // SCL HIGH period
// ... sample SDA ...
■ CAUTION: If your bit-bang I²C driver does not implement clock-stretch detection, it will mis-sample bits from slow slaves
(e.g. sensors doing ADC conversion). This is a common bug in bare-metal drivers.
6. Multi-Master Arbitration
When two masters both see the bus idle and begin a START simultaneously, arbitration determines which one gets to
proceed. It is a fully distributed, hardware-level mechanism — no central arbiter exists.
Master 1 drives
M1 loses arbitration
(drives HIGH, sees LOW)
Master 2 drives
SDA (bus)
SCL (bus)
Figure 4 — Master 1 drives HIGH at bit 1; Master 2 drives LOW. Bus = LOW (wired-AND). Master 1 detects mismatch and loses.
6.1 Arbitration Algorithm
• Both masters simultaneously send a START condition.
• Each master drives its first SDA bit and then reads back the SDA bus.
• If a master drove HIGH but reads back LOW, another master pulled it LOW → the reading master has LOST
arbitration.
• The losing master immediately stops transmitting and becomes a passive observer.
• The winning master continues — it never even knows arbitration occurred.
• If both drive the same bit, arbitration continues to the next bit.
• The master whose address is numerically LOWER wins (more leading zeros → more time driving LOW).
6.2 Key Properties
Property
Detail
Non-destructive
The winning message is transmitted completely without corruption.
Automatic
No software protocol; hardware compares drive vs. read on SDA.
Priority
Lower address byte value wins (wired-AND favours zeros).
Timing
Arbitration is decided bit by bit during normal data transmission.
Clock
Clock is already synchronised (§4), so bit boundaries align.
6.3 Arbitration vs. Clock Stretching: Key Difference
Clock stretching is driven by a slave holding SCL LOW. Arbitration is decided on SDA between masters. They are
independent mechanisms that can coexist on the same bus.
7. Special Bus Conditions
Condition
Description
Who initiates
General Call (0x00 W)
Broadcast to all slaves. Slaves that support it ACK.
Master
START byte (0x01)
Slow polling: master sends 0x01 before real address so hardware-polling
Master
slaves can detect bus activity witho
Repeated START (Sr)
New START without STOP. Retains bus ownership. Used for combined
Master
read/write or address-change.
CBUS (0x02)
Reserved for different bus formats (e.g. old CBUS protocol). I²C slaves
— must not ACK.
Device ID (0x7C)
Read 3-byte manufacturer + device ID from a slave. Slave must support
Master
it.
8. Practical Design Notes
8.1 Bus Capacitance
• Spec limit: 400 pF (Standard & Fast Mode). Fm+ raises this to 550 pF.
• PCB trace, connector, and device input capacitance all add up. Keep traces short.
• Use a buffer (e.g. PCA9600) to extend reach beyond 400 pF.
8.2 Stuck Bus Recovery
If power is lost mid-transaction, a slave may hold SDA LOW permanently (waiting to finish a byte). The master must
recover the bus:
• Send up to 9 SCL pulses — slave will complete its byte and release SDA.
• Then send a STOP condition to reset the slave's state machine.
• If that fails, toggle SCL manually or assert a hardware reset.
// Bit-bang bus recovery
for (int i = 0; i < 9; i++) {
scl_high(); delay(); scl_low(); delay();
}
i2c_send_stop();
8.3 Address Conflicts
• Only 112 usable 7-bit addresses. Multiple same-device ICs on one bus = problem.
• Many devices have 1–3 hardware address pins (A0, A1, A2) to differentiate them.
• If more devices needed, use an I²C multiplexer (e.g. TCA9548A — 8 channels).
8.4 Bit-Banging Checklist
• Implement clock stretching (read SCL after release — see §5.2).
• Respect t_SU;DAT: change SDA at least 250 ns before SCL rises.
• Respect t_HD;DAT: hold SDA after SCL falls (min 0 ns, but add margin).
• Check for arbitration loss if using multi-master (compare SDA driven vs. read).
• Always terminate transactions with STOP on error to reset slave state machines.
• Use open-drain GPIO config — never push-pull on SDA/SCL.
9. Quick Reference
Symbol
Meaning
Symbol
Meaning
S
START condition
P
STOP condition
Sr
Repeated START
A
ACK (SDA LOW on bit 9)
NA
NACK (SDA HIGH)
R/W■
Read=1, Write=0
SCL
Serial Clock Line
SDA
Serial Data Line
t_r
Rise time
t_f
Fall time
t_HIGH
SCL high period
t_LOW
SCL low period
C_b
Bus capacitance
R_p
Pull-up resistance
I²C Protocol Reference · Generated for Arul · All timings from NXP UM10204 Rev 7