SD Specifications
Part 1
UHS-II Addendum
Version 2.00 Draft 0.87
October 7, 2016
Addendum to:
SD Specifications
Part 1 Physical Layer Specification
Version 4.00 May 30, 2011, or later
Technical Committee
SD Card Association
©Copyright 2010-2016 SD Card Association
UHS-II Addendum Version 2.00 Draft
Draft Only Page
This Page is used to describe draft version and information limited to the draft. This page will be
removed when releasing the Supplementary Notes.
Draft Revision History
Date
Sep 11, 2014
Mar 17, 2015
Mar 19, 2015
April 10, 2015
Sep. 16, 2016
Sep. 23, 2016
Oct. 7, 2016
Revision
0.80
Candidate
0.85
0.85
0.85
0.86
0.86
0.87
Changes compared to previous issue
The first draft for Version 2.00, modified protocol part from Version
1.02.
Draft for Verification.
Draft for Verification.
Draft for Verification.
Updating protocol specification description
Updating PHY specification description
Updating specification with reference to the UHS TG on Sep. 29.
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Revision History
Date
May 30, 2011
Version
1.00
June 28, 2013
1.01
May 28, 2014
1.02
Changes compared to previous issue
The first release of UHS-II Addendum.
(Typos fixed from the IP Review Draft are indicated in red.)
The Revised Version which includes:
(1) Modifications in UHS-II 1.00 Supplementary Note Version 1.00
(2) Modifications found after the Supplementary Notes.
Fixed Section number from 3.2 to 3.5
Fixed Section number from 6.2.15.to 6.3
To the extent this proposed specification, which is being submitted for review under the IP
Policy, implements, incorporates by reference or refers to any portion of versions 1.0 or 1.01
of the SD Specifications (including Parts 1 through 4), adoption of the proposed specification
shall require Members utilizing the adopted specification to obtain the appropriate licenses
from the SD-3C, LLC, as required for the utilization of those portion(s) of versions 1.0 or 1.01
of the SD Specifications.
For example, implementation of the SD Specifications in a host device under versions 1.0 or
1.01 and under the adopted specification requires the execution of a SD Host Ancillary
License Agreement with the SD-3C, LLC; and implementation of the SD Specifications under
versions 1.0 or 1.01 and under the proposed specification in a SD Card containing any
memory storage capability (other than for storage of executable code for a controller or
microprocessor within the SD Card) requires the execution of a SD Memory Card License
Agreement with the SD-3C, LLC.
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Conditions for publication
Publisher and Copyright Holder:
SD Card Association
2400 Camino Ramon, Suite 375
San Ramon, CA 94583 USA
Telephone: +1 (925) 275-6615,
Fax: +1 (925) 886-4870
E-mail: office@sdcard.org
Confidentiality:
The contents of this document are deemed confidential information of the SD-3C LLC and/or the SD
Card Association (the "Disclosers"). As such, the contents and your right to use the contents are
subject to the confidentiality obligations stated in the written agreement you entered into with the
Disclosers which entitled you to receive this document, such as a Non-Disclosure Agreement, the
License Agreement for SDA Memory Card Specifications (also known as "LAMS"), the SD
Host/Ancillary Product License Agreement (also known as "HALA") or the IP Policy.
Disclaimers:
The information contained herein is presented only as a standard specification for SD Card and SD
Host/Ancillary products. No responsibility is assumed by SD Card Association for any damages, any
infringements of patents or other right of the third parties, which may result from its use. No license is
granted by implication or otherwise under any patent or rights of SD Card Association or others.
Conventions Used in This Document
Naming Conventions
• Some terms are capitalized to distinguish their definition from their common English meaning. Words
not capitalized have their common English meaning.
Numbers and Number Bases
• Hexadecimal numbers are written with a lower case "h" suffix, e.g., FFFFh and 80h.
• Binary numbers are written with a lower case "b" suffix (e.g., 10b).
• Binary numbers larger than four digits are written with a space dividing each group of four digits, as
in 1000 0101 0010b.
• All other numbers are decimal.
Key Words
• May:
• Shall:
Indicates flexibility of choice with no implied recommendation or requirement.
Indicates a mandatory requirement. Designers shall implement such mandatory
requirements to ensure interchangeability and to claim conformance with the specification.
• Should: Indicates a strong recommendation but not a mandatory requirement. Designers should
give strong consideration to such recommendations, but there is still a choice in
implementation.
Application Notes
Some sections of this document provide guidance to the host implementers as follows:
Application Note:
This is an example of an application note.
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Table of Contents
1. General ................................................................................................................................ 1
2. System Features ................................................................................................................. 2
3. UHS-II System Concept ...................................................................................................... 3
3.1 Interface Speed .......................................................................................................................... 3
3.2 Connection Topologies ............................................................................................................... 3
3.2.1 Point to Point Connection ..................................................................................................... 3
3.2.2 Multi-device Connection ....................................................................................................... 5
3.2.2.1 Ring Connection....................................................................................................................6
3.2.2.2 Hub Connection ....................................................................................................................6
3.3 Layering...................................................................................................................................... 7
3.4 UHS-II Transaction ..................................................................................................................... 8
3.4.1 UHS-II Packet ...................................................................................................................... 8
3.4.2 Data Transaction .................................................................................................................. 9
3.4.3 CM-TRAN............................................................................................................................. 9
3.4.4 SD-TRAN ........................................................................................................................... 10
3.4.5 Aborting Transaction ........................................................................................................... 10
3.5 UHS-II Initialization Outline ........................................................................................................11
3.5.1 UHS-II Initialization Flow without Boot Code Loading .......................................................... 11
3.5.2 UHS-II Initialization Flow with Boot Code Loading .............................................................. 12
4. Physical Layer Specification ........................................................................................... 14
4.1 Physical Layer Overview .......................................................................................................... 14
4.2 Physical Layer Interface Architecture ........................................................................................ 14
4.2.1 Lane Definition ................................................................................................................... 16
4.2.2 Range Definition for Data Rate ........................................................................................... 16
4.2.3 Power Supply Connections ................................................................................................ 17
4.2.4 Operating Condition ........................................................................................................... 17
4.2.5 Over-voltage Tolerance ...................................................................................................... 18
4.2.6 Impedance and Termination Scheme ................................................................................. 19
4.2.6.1 Impedance Definition........................................................................................................... 19
4.2.6.2 Input Termination Scheme ................................................................................................... 20
4.2.7 Definition of Test Points for Host and Device ...................................................................... 21
4.3 Electrical Specification .............................................................................................................. 22
4.3.1 Definition of Single-ended and Differential Signals ............................................................. 22
4.3.2 Specification of Transmitter and Receiver........................................................................... 24
4.3.2.1 Host Transmitter Specification ............................................................................................. 24
4.3.2.2 Device Receiver Specification ............................................................................................. 25
4.3.2.3 Device Transmitter Specification ......................................................................................... 27
4.3.2.4 Host Receiver Specification................................................................................................. 28
4.3.3 Eye-mask Template ............................................................................................................ 29
4.3.4 Jitter ................................................................................................................................... 33
4.3.5 Return Loss ........................................................................................................................ 35
4.3.5.1 Differential Mode Return Loss ............................................................................................. 36
4.3.5.2 Common-mode Return Loss ............................................................................................... 39
4.3.5.3 Common-to-Differential Return Loss (Impedance Balance) ................................................. 40
4.3.6 Line States ......................................................................................................................... 41
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4.3.7 Host Power Delivery Network Model .................................................................................. 41
4.4 EIDL State ................................................................................................................................ 42
4.5 Symbol Coding ......................................................................................................................... 45
4.6 Loopback Mode ........................................................................................................................ 50
4.7 PHY Test Mode ......................................................................................................................... 52
4.7.1 The Sequences used in PHY Test Mode ............................................................................ 53
4.7.2 Definition of TMD1 and TMD2 ............................................................................................ 55
4.7.2.1 TMD1 .................................................................................................................................. 55
4.7.2.2 TMD2 .................................................................................................................................. 55
4.7.3 Test Modes ......................................................................................................................... 57
4.7.4 An Example Procedure ....................................................................................................... 60
4.7.5 Test Mode for Host ............................................................................................................. 60
4.8 2L-HD Mode (Optional) ............................................................................................................. 62
4.9 Additional Lanes Support (Optional) ......................................................................................... 62
4.10 Interface between PHY and LINK ........................................................................................... 62
4.11 EMI ......................................................................................................................................... 63
5. Link Layer Specification................................................................................................... 64
5.1 Link Layer Overview ................................................................................................................. 64
5.2 Link Layer Protocol ................................................................................................................... 64
5.2.1 Protocol Overview .............................................................................................................. 64
5.2.2 Link Symbol Set (LSS) ....................................................................................................... 64
5.2.2.1 Special Symbols.................................................................................................................. 64
5.2.2.2 Link Symbol Set .................................................................................................................. 65
5.2.3 Header for UHS-II Packet ................................................................................................... 67
5.2.4 Message Packet (MSG) ..................................................................................................... 68
5.2.4.1 Overview ............................................................................................................................. 68
5.2.4.2 CODE Definition for Each IDX ............................................................................................. 69
5.2.4.3 MSG Duplication ................................................................................................................. 70
5.2.5 Error Identifier .................................................................................................................... 70
5.2.6 Framing Rules .................................................................................................................... 70
5.2.6.1 Packet Framing ................................................................................................................... 70
5.2.6.2 DATA Burst Framing ............................................................................................................ 71
5.2.6.2.1 DATA Burst Framing Rule in Block Mode ...................................................................... 71
5.2.6.2.2 DATA Burst Framing Rule in Byte Mode ........................................................................ 72
5.2.7 Symbol Encoding and Byte Ordering in 8b/10b .................................................................. 73
5.2.8 Physical Lane State Machine (PLSM) ................................................................................ 73
5.2.8.1 Overview ............................................................................................................................. 73
5.2.8.2 Details of VLD State ............................................................................................................ 75
5.2.8.3 In Case of 8b/10b Error ....................................................................................................... 77
5.2.9 Data Link State Machine (DLSM) ....................................................................................... 77
5.2.9.1 Overview ............................................................................................................................. 77
5.2.9.2 Dormant State ..................................................................................................................... 78
5.2.9.3 Wakeup State...................................................................................................................... 78
5.2.9.4 Config State ........................................................................................................................ 78
5.2.9.5 Active State ......................................................................................................................... 79
5.3 PHY Initialization....................................................................................................................... 82
5.3.1 PHY Initialization Sequence ............................................................................................... 82
5.3.2 LINK State Transition during PHY Initialization (Point to Point) ........................................... 83
5.3.3 LINK State Transition during PHY Initialization (Ring Connection) ...................................... 84
5.4 Power Management.................................................................................................................. 85
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5.4.1 Overview ............................................................................................................................ 85
5.4.2 Lane-level LPS Management ............................................................................................. 86
5.4.3 Link-level LPS Management ............................................................................................... 86
5.4.4 Detailed Specifications for Low Power Mode ...................................................................... 89
5.5 Flow Control ............................................................................................................................. 93
5.5.1 Flow Control Overview ....................................................................................................... 93
5.5.2 Flow Control Handshake and Terminating Data Transmission ............................................ 94
5.5.3 Details of Flow Control Sequence ...................................................................................... 97
5.5.3.1 Read Transaction (FD) in Fast Mode ................................................................................... 97
5.5.3.2 Read Transaction (FD) in Low Power Mode ........................................................................ 99
5.5.3.3 Write Transaction (FD) in Fast Mode ................................................................................. 101
5.5.3.4 Write Transaction (FD) in Low Power Mode....................................................................... 103
5.5.4 DATA Burst Retry.............................................................................................................. 104
5.6 Packet Bypassing ................................................................................................................... 106
5.6.1 Overview .......................................................................................................................... 106
5.6.2 Control Packet Bypassing ................................................................................................ 106
5.6.3 DATA Burst Streaming ...................................................................................................... 107
5.7 Data Integrity .......................................................................................................................... 108
5.7.1 Overview .......................................................................................................................... 108
5.7.2 Detection and Notification of CRC Error ........................................................................... 108
5.7.3 CRC16 Generation Polynomial ......................................................................................... 108
5.7.3.1 Overview ........................................................................................................................... 108
5.7.3.2 Example of CRC16 Calculation ......................................................................................... 109
5.7.4 Scrambling ....................................................................................................................... 109
5.7.4.1 Overview ........................................................................................................................... 109
5.7.4.2 The Operation Order of CRC, Scrambling and 8b/10b ....................................................... 110
5.7.4.3 LSS Scrambling ................................................................................................................ 110
5.7.4.4 Example of Scrambling Calculation ................................................................................... 111
5.8 Packet Receiving Flow Chart ................................................................................................... 112
5.8.1 Overview ...........................................................................................................................112
5.8.2 Top Level Flow Chart ......................................................................................................... 112
5.8.3 Control Packet Reception Flow Chart ................................................................................ 114
5.8.4 DATA Burst Reception Flow Chart ..................................................................................... 115
5.9 Details of Boot Code Loading .................................................................................................. 117
5.9.1 LINK State Transition during Wakeup including Boot Device (Ring Connection) ................ 117
5.9.2 Protocol for Boot Code Transmission ................................................................................ 119
6. Transaction Layer Specification .................................................................................... 120
6.1 Transaction Layer Overview ................................................................................................... 120
6.1.1 Packet Types and Format Overview ................................................................................. 121
6.2 Transaction Layer Protocol ..................................................................................................... 123
6.2.1 UHS-II I/O Space and Memory Address Space ................................................................ 123
6.2.2 Packet Format Details ...................................................................................................... 124
6.2.2.1 Header .............................................................................................................................. 124
6.2.2.2 CCMD ............................................................................................................................... 124
6.2.2.3 Broadcast CCMD .............................................................................................................. 128
6.2.2.4 DCMD ............................................................................................................................... 129
6.2.2.5 RES (NACK = 0) ............................................................................................................... 131
6.2.2.6 RES (NACK = 1) ............................................................................................................... 134
6.2.2.7 DATA................................................................................................................................. 134
6.2.2.8 Operation of Reserved Bits in the Packet .......................................................................... 135
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6.2.3 Supplements of UHS-II Initialization ................................................................................. 136
6.2.4 Transition to Dormant State .............................................................................................. 137
6.2.4.1 General ............................................................................................................................. 137
6.2.4.2 Hibernate Mode................................................................................................................. 138
6.2.4.2.1 Overview .................................................................................................................... 138
6.2.4.2.2 Entry to Hibernate Mode ............................................................................................. 139
6.2.4.2.3 Exit from Hibernate Mode ........................................................................................... 140
6.2.5 Reset................................................................................................................................ 141
6.2.6 Device Initialization Mechanism ........................................................................................ 142
6.2.6.1 General ............................................................................................................................. 142
6.2.6.2 Operation of Device .......................................................................................................... 143
6.2.6.3 Operation of Host .............................................................................................................. 146
6.2.7 Enumeration Mechanism .................................................................................................. 148
6.2.7.1 General ............................................................................................................................. 148
6.2.7.2 Enumeration Examples in Point to Point Connection ......................................................... 149
6.2.7.3 Enumeration Examples in Multi-device Connection (Ring) ................................................. 150
6.2.8 Configuration Mechanism ................................................................................................. 151
6.2.8.1 Basic Specification ............................................................................................................ 151
6.2.8.2 Determination of Block Length........................................................................................... 153
6.2.8.3 Quick Configuration ........................................................................................................... 153
6.2.9 Configuration Register (CFG_REG) ................................................................................. 156
6.2.9.1 Register Map..................................................................................................................... 156
6.2.9.2 CFG_REG Description ...................................................................................................... 156
6.2.9.2.1 Generic Capabilities Register ...................................................................................... 158
6.2.9.2.2 PHY Capabilities Register ........................................................................................... 159
6.2.9.2.3 LINK/TRAN Capabilities Register................................................................................ 161
6.2.9.2.4 Generic Settings Register ........................................................................................... 163
6.2.9.2.5 PHY Settings Register ................................................................................................ 164
6.2.9.2.6 LINK/TRAN Settings Register ..................................................................................... 166
6.2.9.2.7 Preset Register ........................................................................................................... 167
6.2.10 Status Register (ST_REG) ............................................................................................. 168
6.2.10.1 Register Map................................................................................................................... 168
6.2.10.2 ST_REG Description ....................................................................................................... 168
6.2.10.2.1 Status in TRANS_ABORT Register ........................................................................... 168
6.2.11 Interrupt Register (INT_REG) ......................................................................................... 170
6.2.11.1 Register Map ................................................................................................................... 170
6.2.11.2 INT_REG Description ...................................................................................................... 170
6.2.11.2.1 INT Enable ................................................................................................................ 170
6.2.11.2.2 INT Status ................................................................................................................. 170
6.2.12 Command Register (CMD_REG).................................................................................... 171
6.2.13 Transaction Control and Management State Machine .................................................... 172
6.2.13.1 Transaction Scheduling State Machine (TSSM) ............................................................... 172
6.2.13.2 Transaction Processing State Machine (TPSM) ............................................................... 173
6.2.13.3 Transaction Buffer-management State Machine (TBSM) ................................................. 176
6.2.13.4 Detail Definition of Command Time Slot .......................................................................... 179
6.2.13.5 State Machines during Boot Code Loading ...................................................................... 180
6.2.14 Transaction Rules........................................................................................................... 182
6.2.14.1 Control Transaction Sequence ........................................................................................ 182
6.2.14.2 Data Transaction Sequence (Outline) .............................................................................. 184
6.2.14.3 Data Transaction Sequence (Detail) ................................................................................ 191
6.2.15 Error Handling ................................................................................................................ 193
6.2.15.1 NACK Notification for Command Error............................................................................. 193
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6.2.15.2 Error Notification during Data Transaction ....................................................................... 195
6.2.15.3 Error Detection from Broadcast CCMD ............................................................................ 197
6.2.15.4 Fractional DATA Burst in LM = 0 ...................................................................................... 198
6.3 Timing Rules ........................................................................................................................... 199
6.3.1 Overview .......................................................................................................................... 199
6.3.2 Example Sequence of Timeout Occurrence...................................................................... 202
7. SD-TRAN Specification .................................................................................................. 204
7.1 SD-TRAN Overview ................................................................................................................ 204
7.1.1 Packet Types and Format Overview ................................................................................. 204
7.1.2 Registers for Legacy SD................................................................................................... 205
7.2 SD-TRAN Protocol.................................................................................................................. 205
7.2.1 Packet Format Details ...................................................................................................... 205
7.2.1.1 CCMD ............................................................................................................................... 205
7.2.1.2 DCMD ............................................................................................................................... 207
7.2.1.3 RES .................................................................................................................................. 208
7.2.1.4 RES (NACK = 1) ............................................................................................................... 210
7.2.1.5 DATA................................................................................................................................. 211
7.2.1.6 Application Commands...................................................................................................... 211
7.2.1.7 Note for Legacy SD Commands ........................................................................................ 211
7.2.2 DATA Burst Framing Rules in SD-TRAN........................................................................... 212
7.2.2.1 Multi-block Read / Write Command ................................................................................... 212
7.2.2.2 CMD42.............................................................................................................................. 212
7.2.2.3 Other DCMD on SD-TRAN ................................................................................................ 212
7.2.3 Interface Selection for UHS-II Card and Initialization ........................................................ 212
7.2.3.1 Overview ........................................................................................................................... 212
7.2.3.2 Interface Selection after Power Up .................................................................................... 212
7.2.3.3 Interface Selection after FULL_RESET or GO_DORMANT_STATE................................... 214
7.2.4 Transaction Control and Management State Machine ...................................................... 215
7.2.4.1 Card Identification Mode ................................................................................................... 215
7.2.4.2 Data Transfer Mode .......................................................................................................... 217
7.2.4.3 Relation to State Machines in CM-TRAN and LINK ........................................................... 219
7.2.4.4 Card State Transition by UHS-II Native Command ............................................................ 219
7.2.4.5 Capability Indication for Receiving Arbitrary CCMD during CTS......................................... 219
7.2.5 Basic Transaction Rules ................................................................................................... 220
7.2.5.1 CCMD ............................................................................................................................... 220
7.2.5.2 Read DCMD (Fixed Transfer Length) ................................................................................ 221
7.2.5.3 Read DCMD (Infinite Transfer Length) .............................................................................. 223
7.2.5.4 Write DCMD (Fixed Transfer Length)................................................................................. 224
7.2.5.5 Write DCMD (Infinite Transfer Length) ............................................................................... 226
7.2.5.6 Other DCMD ..................................................................................................................... 227
7.2.6 SD-TRAN Specific Transaction Rules............................................................................... 228
7.2.6.1 Definition of Application Specific MSG ............................................................................... 228
7.2.6.2 CMD0................................................................................................................................ 229
7.2.6.3 Representing Busy Period and 'prg' State ......................................................................... 230
7.2.6.4 Other Transaction Rules .................................................................................................... 238
7.2.7 Packet Handling ............................................................................................................... 238
7.2.8 Error Handling .................................................................................................................. 238
7.2.8.1 Concept ............................................................................................................................ 238
7.2.8.2 Detecting Illegal CMD........................................................................................................ 239
7.2.8.3 Reaching Read Address to the End of User Data Area ...................................................... 240
7.2.8.4 Reaching Write Address to the End of User Data Area ...................................................... 241
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7.3 Timing Rules ........................................................................................................................... 243
7.3.1 Overview .......................................................................................................................... 243
7.3.2 Example Sequence of Timeout Occurrence in SD-TRAN ................................................. 244
8. 2L-HD Mode (optional in Range A and B) ..................................................................... 247
8.1 Overview ................................................................................................................................ 247
8.2 PHY Layer Specification ......................................................................................................... 247
8.2.1 Direction Switching ........................................................................................................... 247
8.3 Link Layer Specification .......................................................................................................... 247
8.3.1 Framing Rules for 2L-HD Mode ........................................................................................ 247
8.3.1.1 Block Mode ....................................................................................................................... 247
8.3.1.2 Byte Mode ......................................................................................................................... 250
8.3.2 Sequence for Duplex Mode Switching .............................................................................. 250
8.3.3 PLSM for 2L-HD Mode ..................................................................................................... 252
8.3.4 Details of Duplex Mode Switching Sequence ................................................................... 252
8.3.4.1 2L-HD Read Transaction ................................................................................................... 253
8.3.4.2 2L-HD Write Transaction ................................................................................................... 255
8.4 Transaction Layer Specification .............................................................................................. 257
8.4.1 Transaction Control and Management State Machine ...................................................... 257
8.4.2 Error Handling .................................................................................................................. 257
8.4.2.1 Handling CRC Error .......................................................................................................... 257
8.5 SD-TRAN Specification .......................................................................................................... 257
8.5.1 Basic Transaction Rules in SD-TRAN............................................................................... 257
8.5.2 Error Handling .................................................................................................................. 260
8.5.2.1 Handling CRC Error .......................................................................................................... 260
8.5.2.2 Reaching Address to the End of User Data Area ............................................................... 260
8.6 Timing Rules ........................................................................................................................... 260
9. Additional Lanes Support (optional) ............................................................................. 261
9.1 Overview ................................................................................................................................ 261
9.1.1 Capabilities and Settings .................................................................................................. 263
9.1.2 Additional Lanes and Multi-device Topologies .................................................................. 263
9.2 PHY Layer Specification ......................................................................................................... 263
9.2.1 PHY Specification and Direction Switching ....................................................................... 263
9.2.2 Default Behavior ............................................................................................................... 263
9.3 Link Layer Specification .......................................................................................................... 264
9.3.1 Framing Rules .................................................................................................................. 264
9.3.2 Lane Direction for 2D2U-FD Mode ................................................................................... 265
9.3.3 LINK State Transition for 2D2U-FD Mode during Data Read – Fast Mode........................ 266
9.3.4 LINK State Transition for 2D2U-FD Mode during Data Read – Low Power Mode ............. 266
9.3.5 LINK State Transition for 2D2U-FD Mode during Data Write – Fast Mode ........................ 267
9.3.6 LINK State Transition for 2D2U-FD Mode during Data Write – Low Power Mode ............. 269
9.4 Transaction Layer Specification .............................................................................................. 270
9.4.1 Initialization ...................................................................................................................... 270
9.4.2 Transaction Control and Management State Machine ...................................................... 271
9.4.3 Error Handling .................................................................................................................. 272
9.4.3.1 Handling CRC Error .......................................................................................................... 272
9.5 SD-TRAN Specification .......................................................................................................... 272
9.5.1 Error Handling .................................................................................................................. 272
9.5.1.1 Handling CRC Error .......................................................................................................... 272
9.5.1.2 Reaching Address to the End of User Data Area ............................................................... 272
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Appendix A (Normative) : Reference ................................................................................. 273
A.1 Related Documentation .......................................................................................................... 273
Appendix B (Normative) : Special Terms .......................................................................... 274
B.1 Terminology ............................................................................................................................ 274
B.2 Abbreviations.......................................................................................................................... 275
Appendix C (Normative) : Test Condition of Measuring Output Signals ....................... 278
C.1 Test Condition for Host Output Signal at TP2 ......................................................................... 278
C.2 Test Condition for Card Output Signal at TP2 ......................................................................... 278
Appendix D (Normative) : Register ................................................................................... 280
D.1 Register Summary ................................................................................................................. 280
D.1.1 Register Types ................................................................................................................. 280
D.1.2 Register Initial Values ...................................................................................................... 280
Appendix E (Informative) : Design Guide ......................................................................... 281
E.1 Host Design............................................................................................................................ 281
E.1.1 Informative Specification of Host Transmitter at TP1 ........................................................ 281
E.1.2 Informative Specification of Host Receiver at TP1 ............................................................ 282
E.1.3 Host PCB Design ............................................................................................................. 283
E.1.4 Multi-Reflection of the Signal............................................................................................ 283
E.1.5 Care for the Floating Input ............................................................................................... 283
E.1.6 Spread Spectrum Clocking (SSC) .................................................................................... 284
E.2 Device Design ........................................................................................................................ 286
E.2.1 Device Transmitter Design ............................................................................................... 286
E.2.2 Device Receiver Design ................................................................................................... 286
E.2.3 Device System Level CM Noise ....................................................................................... 287
Appendix F (Informative) : PHY-LINK I/F .......................................................................... 289
F.1 Overview................................................................................................................................. 289
F.2 I/F Detail ................................................................................................................................. 289
F.2.1 Block Diagram .................................................................................................................. 289
F.2.2 Definition of Interface Signal ............................................................................................. 289
F.2.3 Details of PCMD and PACK .............................................................................................. 291
F.3 Clock Generation .................................................................................................................... 292
F.3.1 Clock Generation in Host .................................................................................................. 292
F.3.2 Clock Generation in Device .............................................................................................. 293
F.4 I/F Timing Sequence ............................................................................................................... 293
F.4.1 Reset and Activation (Exiting from Dormant state) ............................................................ 293
F.4.2 Packet Transfer in Fast Mode ........................................................................................... 296
F.4.3 Packet Transfer in Low Power Mode ................................................................................ 297
F.4.4 Error Occurrence during Packet Transfer.......................................................................... 299
F.4.5 Loopback Control for DATA Burst Streaming .................................................................... 300
F.4.6 Switching of Duplex Mode ................................................................................................ 305
F.4.7 Entering to Dormant State ................................................................................................ 309
Appendix G (Informative) : Host's Operation in Detecting Timeout ............................... 311
G.1 P2P CMD of UHS-II Native Protocol ....................................................................................... 311
G.2 Broadcast CCMD ................................................................................................................... 312
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G.3 CMD of SD-TRAN .................................................................................................................. 313
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Table of Figures
Figure 3-1 : Interface Speed Comparison ....................................................................................................3
Figure 3-2 : Point to Point Topology (FD mode) ...........................................................................................4
Figure 3-3 : Point to Point Topology (Supporting 2L-HD Mode) ....................................................................5
Figure 3-4 : Direction Changing in 2L-HD Mode ..........................................................................................5
Figure 3-5 : Example of Ring Connection ....................................................................................................6
Figure 3-6 : Examples of RCLK distribution method for Ring .......................................................................6
Figure 3-7 : Example of Hub Connection .....................................................................................................7
Figure 3-8 : Layering Overview ....................................................................................................................7
Figure 3-9 : Basic UHS-II Transaction ..........................................................................................................9
Figure 3-10 : UHS-II Transaction by SD-TRAN .......................................................................................... 10
Figure 3-11 : UHS-II Initialization Flow ....................................................................................................... 11
Figure 3-12 : UHS-II Initialization Flow When Boot Code Loading Is Executed .......................................... 13
Figure 4-1: Physical Layer Overview ......................................................................................................... 14
Figure 4-2: Physical Layer Interface Architecture ....................................................................................... 15
Figure 4-3: Signal Test Points .................................................................................................................... 21
Figure 4-4: Single-ended Signal Names on Differential Line ...................................................................... 22
Figure 4-5: Definition of Single-ended and Differential Signals ................................................................... 23
Figure 4-6: Eye-mask Templates (Range A,B) ........................................................................................... 30
Figure 4-7: Eye-mask Templates (Range C) .............................................................................................. 31
Figure 4-8: Eye-mask Templates (Range D) .............................................................................................. 32
Figure 4-9: Jitter Tolerance Specification ................................................................................................... 35
Figure 4-10: Differential Mode Return Loss (RLDD) Template for Device..................................................... 36
Figure 4-11: Differential Mode Return Loss (RLDD) Template for Host supporting up to Range B................ 37
Figure 4-12: Differential Mode Return Loss (RLDD) Template for Host supporting up to Range C or D........38
Figure 4-13: Common-mode Return Loss (RLCC) Template for Host/Device ............................................... 39
Figure 4-14: Common-to-Differential Return Loss (RLDC) Template for Host/Device ................................... 40
Figure 4-15: Power Delivery Network for VDD1 and VDD2 Domains ......................................................... 41
Figure 4-16: Line States and Timing in the Recovery from EIDL State and in EIDL Entry ........................... 44
Figure 4-17: Diagram of Symbol Coding .................................................................................................... 45
Figure 4-18: Location of Forward Loopback in PHY of the Host ................................................................. 50
Figure 4-19: Location of Backward Loopback in PHY of the Host .............................................................. 51
Figure 4-20: Location of Forward Loopback in PHY of the Device ............................................................. 51
Figure 4-21: Location of Backward Loopback in PHY of the Device ........................................................... 51
Figure 4-22: Sequences used in PHY Test Mode ....................................................................................... 54
Figure 4-23: Structure of TMD1 and TMD2 ................................................................................................ 56
Figure 4-24: Normal Modes Sequence ...................................................................................................... 58
Figure 4-25: Disconnect Mode Sequence .................................................................................................. 59
Figure 4-26: An Example Procedure (Backward Loop Back Test with PLL Multiplier is x30) ....................... 60
Figure 4-27: States Regarding Host PHY Test ........................................................................................... 61
Figure 5-1 : Link Layer Overview ............................................................................................................... 64
Figure 5-2 : Header Format ....................................................................................................................... 67
Figure 5-3 : MSG Format ........................................................................................................................... 68
Figure 5-4 : Packet Framing Rule of TLP ................................................................................................... 71
Figure 5-5 : Packet Framing Rule of MSG ................................................................................................. 71
Figure 5-6 : DATA Burst Framing Rule in Block Mode (N_FCU = 2) ........................................................... 71
Figure 5-7 : Framing Rules for Fractional DATA Burst ................................................................................ 72
Figure 5-8 : Framed DATA Packet Format in Case of Block Length Is Odd ................................................ 72
Figure 5-9 : DATA Burst Framing Rule in Byte Mode.................................................................................. 72
Figure 5-10 : DATA Burst Framing Rule in Byte Mode When TLEN Is Odd ................................................ 73
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Figure 5-11 : Symbol Encoding .................................................................................................................. 73
Figure 5-12 : Byte Ordering in Symbol Transfer ......................................................................................... 73
Figure 5-13 : Physical Lane State Machine (PLSM) ................................................................................... 74
Figure 5-14 : VLD State ............................................................................................................................. 76
Figure 5-15 : Data Link State Machine (DLSM) .......................................................................................... 77
Figure 5-16 : Wakeup State ....................................................................................................................... 78
Figure 5-17 : Active State .......................................................................................................................... 80
Figure 5-18 : PHY Initialization Sequence .................................................................................................. 82
Figure 5-19 : LINK State Transition during PHY Initialization (Point to Point).............................................. 83
Figure 5-20 : Ring Connection Including Two Devices ............................................................................... 84
Figure 5-21 : LINK State Transition during Wakeup (Ring) ......................................................................... 84
Figure 5-22 : State Transition of Lane-level LPS Management (Tx Side) ................................................... 86
Figure 5-23 : LINK State Transition during Entry to Dormant State (Fast Mode)......................................... 87
Figure 5-24 : LINK State Transition during Entry to Dormant State (Low Power Mode) .............................. 88
Figure 5-25 : Sample Block Diagram of a Lane .......................................................................................... 89
Figure 5-26 : Transition from/to EIDL ......................................................................................................... 92
Figure 5-27 : Flow Control Sequence Overview ......................................................................................... 94
Figure 5-28 : CTS during FC and Terminating Data Transmission .............................................................. 95
Figure 5-29 : Flow Control Sequence during Data Read (FD, Fast Mode).................................................. 97
Figure 5-30 : LINK State Transition during Data Read (FD, Fast Mode) ..................................................... 98
Figure 5-31 : Flow Control Sequence during Data Read (FD, Low Power Mode) ....................................... 99
Figure 5-32 : LINK State Transition during Data Read (FD, Low Power Mode) ........................................ 100
Figure 5-33 : Flow Control Sequence during Data Write (FD, Fast Mode) ................................................ 101
Figure 5-34 : LINK State Transition during Data Write (FD, Fast Mode) ................................................... 102
Figure 5-35 : Flow Control Sequence during Data Write (FD, Low Power Mode) ..................................... 103
Figure 5-36 : LINK State Transition during Data Write (FD, Low Power Mode)......................................... 104
Figure 5-37 : DATA Burst Retry Sequence ............................................................................................... 105
Figure 5-38 : Example of LINK Architecture for Packet Bypassing ........................................................... 106
Figure 5-39 : Packet Handling for DATA Bypassing.................................................................................. 108
Figure 5-40 : CRC16 Calculation ............................................................................................................. 109
Figure 5-41 : LFSR with Scrambling Polynomial ...................................................................................... 110
Figure 5-42 : LSS Scrambling .................................................................................................................. 111
Figure 5-43 : Top Level Flow Chart for Starting Packet Reception............................................................ 113
Figure 5-44 : Control Packet Reception Flow Chart ................................................................................. 114
Figure 5-45 : DATA Burst Reception Flow Chart ...................................................................................... 116
Figure 5-46 : Ring Connection Including a Boot Device ........................................................................... 118
Figure 5-47 : LINK State Transition during Wakeup when Including a Boot Device .................................. 118
Figure 6-1 : Transaction Layer Overview ................................................................................................. 120
Figure 6-2 : TLP Format Overview ........................................................................................................... 121
Figure 6-3 : Control Transaction and Data Transaction Sequence ........................................................... 122
Figure 6-4 : UHS-II I/O Space Layout for Device...................................................................................... 123
Figure 6-5 : CCMD Format ...................................................................................................................... 125
Figure 6-6 : Transmission Order of Payload in CCMD (PLEN = 01b) ....................................................... 126
Figure 6-7 : Transmission Order of Payload in CCMD (PLEN = 11b) ....................................................... 127
Figure 6-8 : DCMD Format ...................................................................................................................... 129
Figure 6-9 : TMODE Parameters ............................................................................................................. 129
Figure 6-10 : RES (NACK = 0) Format..................................................................................................... 131
Figure 6-11 : Transmission Order of Payload in RES (NACK = 0, PLEN = 01b) ....................................... 132
Figure 6-12 : Transmission Order of Payload in RES (NACK = 0, PLEN = 11b) ....................................... 133
Figure 6-13 : RES (NACK = 1) Format..................................................................................................... 134
Figure 6-14 : Basic DATA Format............................................................................................................. 135
Figure 6-15 : UHS-II Initialization Flow When Recovery from Dormant State ........................................... 136
Figure 6-16 : An Example of UHS-II Initialization Flow (in Case of Using Higher Speed Range) .............. 137
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Figure 6-17 : GO_DORMANT_STATE CCMD Format ............................................................................. 138
Figure 6-18 : Transition from / to Hibernate Mode .................................................................................... 139
Figure 6-19 : Entry to Hibernate Mode ..................................................................................................... 140
Figure 6-20 : Exit from Hibernate Mode ................................................................................................... 141
Figure 6-21 : DEVICE_INIT CCMD Format .............................................................................................. 142
Figure 6-22 : Power Consumption during Initialization ............................................................................. 143
Figure 6-23 : Device's Operation Flow of Receiving DEVICE_INIT .......................................................... 145
Figure 6-24 : DEVICE_INIT Broadcast CCMD Issued by Host ................................................................. 146
Figure 6-25 : Host's Operation Flow of Receiving DEVICE_INIT .............................................................. 146
Figure 6-26 : Device Initialization Process (Example 1) ........................................................................... 147
Figure 6-27 : Device Initialization Process (Example 2) ........................................................................... 147
Figure 6-28 : ENUMERATE CCMD Format.............................................................................................. 148
Figure 6-29 : Device's Algorithm for Enumeration Process....................................................................... 148
Figure 6-30 : Enumeration Process in Point to Point Connection (Example 1) ......................................... 149
Figure 6-31 : Enumeration Process in Point to Point Connection (Example 2) ......................................... 150
Figure 6-32 : Enumeration Process in Ring Connection (Example 1) ....................................................... 150
Figure 6-33 : Enumeration Process in Ring Connection (Example 2) ....................................................... 151
Figure 6-34 : Device Configuration Flow .................................................................................................. 152
Figure 6-35 : INQUIRY_CONFIG Format ................................................................................................. 154
Figure 6-36 : Operation of INQUIRY_CONFIG......................................................................................... 155
Figure 6-37 : SET_COMMON_CONFIG CCMD Format........................................................................... 155
Figure 6-38 : State Diagram of TSSM ...................................................................................................... 172
Figure 6-39 : State Diagram of TPSM ...................................................................................................... 173
Figure 6-40 : State Transition of TPSM during Data Transaction .............................................................. 176
Figure 6-41 : State Diagram of TBSM ...................................................................................................... 177
Figure 6-42 : State Transition of TBSM and TPSM during Data Transaction ............................................ 179
Figure 6-43 : Relation between CTS and TP_C_WAIT............................................................................. 180
Figure 6-44 : Example Sequence of Control Read Transaction ................................................................ 182
Figure 6-45 : Example Sequence of Control Write Transaction ................................................................ 183
Figure 6-46 : Example Sequence of Data Read Transaction (LM = 1, TLUM = 0) .................................... 184
Figure 6-47 : Example Sequence of Data Write Transaction (LM = 1, TLUM = 0)..................................... 186
Figure 6-48 : Example Sequence of Data Write Transaction (LM = 1, TLUM = 1)..................................... 188
Figure 6-49 : Example Sequence of Data Read Transaction (LM = 0) ...................................................... 190
Figure 6-50 : Example Sequence of Data Read Transaction with LMSG .................................................. 192
Figure 6-51 : Example Sequence of Data Write Transaction with LMSG .................................................. 193
Figure 6-52 : CCMD Error Sequence ....................................................................................................... 194
Figure 6-53 : DCMD Error Sequence ....................................................................................................... 195
Figure 6-54 : Example Sequence Including UNRECOVERABLE_ERROR with Read Data Packet .......... 196
Figure 6-55 : Example Sequence Including UNRECOVERABLE_ERROR with Write Data Packet .......... 197
Figure 6-56 : Sequence in Case of Error Detection from Broadcast CCMD .............................................. 198
Figure 6-57 : Example Sequence of Write Transaction with Fractional DATA Burst in LM = 0 ................... 199
Figure 6-58 : Device Timing Parameters Related to Wakeup Group ........................................................ 201
Figure 6-59 : Device Timing Parameters Related to Basic or Flow Control Group .................................... 201
Figure 6-60 : Example Sequence When Missing RES ............................................................................. 202
Figure 6-61 : Example Sequence When Missing FCRDY during Write Transaction .................................. 203
Figure 7-1 : SD-TRAN Overview.............................................................................................................. 204
Figure 7-2 : Conceptual Diagram of SD-encapsulation ............................................................................ 204
Figure 7-3 : Encapsulation of Legacy SD Format ..................................................................................... 205
Figure 7-4 : CCMD Format on SD-TRAN ................................................................................................. 206
Figure 7-5 : DCMD Format on SD-TRAN ................................................................................................. 207
Figure 7-6 : RES Format on SD-TRAN (Generic)..................................................................................... 208
Figure 7-7 : RES Format on SD-TRAN (R2) ............................................................................................ 209
Figure 7-8 : RES Format on SD-TRAN (Other than R2) ........................................................................... 210
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Figure 7-9 : RES (NACK = 1) Format on SD-TRAN ................................................................................. 210
Figure 7-10 : DATA Format on SD-TRAN ................................................................................................. 211
Figure 7-11 : Initialization Flow after Power Up ........................................................................................ 213
Figure 7-12 : Initialization Flow after FULL_RESET or GO_DORMANT_STATE ...................................... 214
Figure 7-13 : Power Consumption after Exiting from Dormant State ........................................................ 215
Figure 7-14 : State Diagram on SD-TRAN (Card Identification Mode) ...................................................... 216
Figure 7-15 : State Diagram on SD-TRAN (Data Transfer Mode) ............................................................. 218
Figure 7-16 : Sequence of CCMD on SD-TRAN (CMD9) ......................................................................... 220
Figure 7-17 : Sequence of Read DCMD on SD-TRAN (CMD18, LM = 1) ................................................. 221
Figure 7-18 : Sequence of Read DCMD on SD-TRAN (CMD18, LM = 0) ................................................. 223
Figure 7-19 : Sequence of Write DCMD on SD-TRAN (CMD25, LM = 1) ................................................. 224
Figure 7-20 : Sequence of Write DCMD on SD-TRAN (CMD25, LM = 0) ................................................. 226
Figure 7-21 : Sequence of ACMD51 on SD-TRAN ................................................................................... 227
Figure 7-22 : Sequence of CMD0 on SD-TRAN ....................................................................................... 229
Figure 7-23 : Sequence of CMD38 on SD-TRAN ..................................................................................... 231
Figure 7-24 : Sequence of Write DCMD on SD-TRAN with Busy Period (Fixed Transfer Length) ............. 232
Figure 7-25 : Sequence of Write DCMD on SD-TRAN with Busy Period (Infinite Transfer Length) ........... 234
Figure 7-26 : Sequence of Read DCMD on SD-TRAN with Busy Period (Fixed Transfer Length)............. 235
Figure 7-27 : Sequence of Read DCMD on SD-TRAN with Busy Period (Infinite Transfer Length) ........... 237
Figure 7-28 : Detecting Illegal CMD (Example 1) ..................................................................................... 239
Figure 7-29 : Detecting Illegal CMD (Example 2) ..................................................................................... 240
Figure 7-30 : Sequence of Read DCMD (at the End of User Data Area) .................................................. 240
Figure 7-31 : Sequence of Write DCMD (at the End of User Data Area 1) ................................................ 241
Figure 7-32 : Sequence of Write DCMD (at the End of User Data Area 2) ................................................ 242
Figure 7-33 : Example Sequence When Missing RES of CMD38............................................................. 244
Figure 7-34 : Example Sequence When Missing FCREQ during Data Transaction by CMD18................. 245
Figure 7-35 : Example Sequence When Missing FCRDY during Data Transaction by CMD25 ................. 246
Figure 8-1 : Overview of FD Mode and 2L-HD Mode ............................................................................... 247
Figure 8-2 : DATA Packet Framing Rule for 2L-HD Mode (Block Mode) ................................................... 248
Figure 8-3 : DATA Packet Framing Rule in 2L-HD Mode (Block Length Is Aliquant of 4)........................... 249
Figure 8-4 : DATA Burst Framing Rule in 2L-HD Mode ............................................................................ 250
Figure 8-5 : Duplex Mode Switching Sequence in Data Read .................................................................. 250
Figure 8-6 : Duplex Mode Switching Sequence in Data Write .................................................................. 251
Figure 8-7 : PLSM for Non-default Tx or Rx in 2L-HD Mode .................................................................... 252
Figure 8-8 : Example LINK State Transition during Duplex Mode Switching (FD to 2L-HD Read)............ 253
Figure 8-9 : Example LINK State Transition during Duplex Mode Switching (2L-HD Read to FD)............ 254
Figure 8-10 : Example LINK State Transition during Duplex Mode Switching (FD to 2L-HD Write) .......... 255
Figure 8-11 : Example LINK State Transition during Duplex Mode Switching (2L-HD Write to FD) .......... 256
Figure 8-12 : Sequence of Read DCMD on SD-TRAN (CMD18, TMODE = 1100) .................................... 257
Figure 8-13 : Sequence of Write DCMD on SD-TRAN (CMD25, TMODE = 1000) .................................... 259
Figure 9-1 : Possible Lanes Configurations in FD / 2L-HD Mode ............................................................. 261
Figure 9-2 : Overview of 2D1U-FD Mode – Write Boost ........................................................................... 261
Figure 9-3 : Overview of 1D2U-FD Mode – Read Boost........................................................................... 262
Figure 9-4 : Overview of 2D2U-FD Mode ................................................................................................. 262
Figure 9-5 : Usage of 4 Lanes in Ring Topology....................................................................................... 263
Figure 9-6 : Read Operation in 2D2U-FD Mode ....................................................................................... 264
Figure 9-7 : Write Operation in 2D2U-FD Mode ....................................................................................... 265
Figure 9-8 : Lane Direction for 2D2U-FD Mode ........................................................................................ 265
Figure 9-9 : LINK State Transition for 2D2U-FD mode during Data Read – Fast Mode ............................ 266
Figure 9-10 : LINK State Transition for 2D2U-FD Mode during Data Read – Low Power Mode ................ 267
Figure 9-11 : LINK State Transition for 2D2U-FD Mode during Data Write – Fast Mode ........................... 268
Figure 9-12 : LINK State Transition for 2D2U-FD Mode during Data Write – Low Power Mode ................ 269
Figure 9-13 : Flow Chart of Activating Additional Lanes ........................................................................... 270
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Figure 9-14 : Activating Additional Lanes through GO_DORMANT_STATE Command ............................ 271
Figure C- 1: Host Test Fixture Illustration (Concept) ................................................................................. 278
Figure C- 2: Card Test Fixture Illustration (Concept) ................................................................................ 279
Figure E- 1: Example Period Modulation for Triangular SSC .................................................................... 285
Figure E- 2: Calibration of Signal Source ................................................................................................. 286
Figure E- 3: SI Simulation for Checking the Eye Opening at Receiver Termination .................................. 287
Figure F- 1 : Block Diagram of PHY-LINK I/F for Device .......................................................................... 289
Figure F- 2 : An Example Sequence of PCMD and PACK ........................................................................ 292
Figure F- 3 : Clock Generation in Host ..................................................................................................... 292
Figure F- 4 : Clock Generation in Device ................................................................................................. 293
Figure F- 5 : I/F Timing Sequence (Reset and Activation for Host) ........................................................... 294
Figure F- 6 : I/F Timing Sequence (Reset and Activation for Device)........................................................ 295
Figure F- 7 : I/F Timing Sequence (Packet Transfer in Fast Mode) .......................................................... 296
Figure F- 8 : I/F Timing Sequence (Packet Transfer in Low Power Mode) ................................................ 297
Figure F- 9 : I/F Timing Sequence (Error Occurrence during Packet Transfer) ......................................... 299
Figure F- 10 : Ensuring Disparity Continuity ............................................................................................. 301
Figure F- 11 : Example of Loopback Selector Operation (Rule A.) ........................................................... 302
Figure F- 12 : Example of Loopback Selector Operation (Rule C.) ........................................................... 303
Figure F- 13 : I/F Timing Sequence (Loopback Control for DATA Burst Streaming) .................................. 304
Figure F- 14 : I/F Timing Sequence (Switching from FD to HDIN or HDOUT) ........................................... 305
Figure F- 15 : I/F Timing Sequence (Switching from HDIN or HDUT to FD).............................................. 307
Figure F- 16 : I/F Timing Sequence (Entering to Dormant State) .............................................................. 309
Figure G- 1 : Host's Operation for Timeout in Case of P2P CMD for UHS-II Native Protocol .................... 311
Figure G- 2 : Host's Operation for Timeout in Case of Broadcast CCMD.................................................. 312
Figure G- 3 : Host's Operation for Timeout in Case of SD-TRAN ............................................................. 313
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Table of Tables
Table 3-1 : Definition of Initiator ...................................................................................................................8
Table 4-1: Range Definition for Data Rate.................................................................................................. 17
Table 4-2: Operating Voltage ..................................................................................................................... 17
Table 4-3: Leakage Current ....................................................................................................................... 18
Table 4-4: Device Impedance Characteristics ............................................................................................ 19
Table 4-5: Host Impedance Characteristics ................................................................................................ 19
Table 4-6: D0, D1 Output Requirements for Host Transmitter at TP2 ......................................................... 24
Table 4-7: RCLK Output Requirements for Host Transmitter at TP2 ........................................................... 25
Table 4-8: D0, D1 Input Requirement for Device Receiver at TP2 .............................................................. 26
Table 4-9: RCLK Input Requirement for Device Receiver at TP2 ............................................................... 26
Table 4-10: D0, D1 Output Requirement at TP2 for Device Transmitter...................................................... 28
Table 4-11: Input Requirement at TP2 for Host Receiver............................................................................ 28
Table 4-12: Line States .............................................................................................................................. 41
Table 4-13: Data Symbol 8b/10b Coding Table .......................................................................................... 46
Table 4-14: Data Symbol 8b/10b Coding Table (cont.) ............................................................................... 47
Table 4-15: Data Symbol 8b/10b Coding Table (cont.) ............................................................................... 48
Table 4-16: Control Symbol 8b/10b Coding Table ...................................................................................... 49
Table 5-1 : Special Symbols for Link Layer ................................................................................................ 65
Table 5-2 : Link Symbol Set ....................................................................................................................... 66
Table 5-3 : Packet Type Encodings and Descriptions ................................................................................. 68
Table 5-4 : Detailed Definition of MSG ....................................................................................................... 69
Table 5-5 : Code Definition of FCREQ and FCRDY ................................................................................... 69
Table 5-6 : Code Definition of STAT ........................................................................................................... 69
Table 5-7 : PLSM State Definition for Tx and Rx ........................................................................................ 75
Table 5-8 : Condition of State Transition (Wakeup) .................................................................................... 78
Table 5-9 : Condition of State Transition (Config) ....................................................................................... 79
Table 5-10 : Condition of State Transition from Active State ....................................................................... 81
Table 5-11 : Condition of State Transition within Active.Trans State............................................................ 81
Table 5-12 : Condition of State Transition within Active.Recv State ............................................................ 82
Table 5-13 : Example of Scrambling ........................................................................................................ 112
Table 5-14 : Header Check (TYPE-1) ...................................................................................................... 115
Table 5-15 : Header Check (TYPE-2) ...................................................................................................... 117
Table 5-16 : Parameters for Boot Code Transmission .............................................................................. 119
Table 6-1 : I/O Address Space Map ......................................................................................................... 124
Table 6-2 : Definition of PLEN .................................................................................................................. 126
Table 6-3 : Availability of TMODE............................................................................................................. 131
Table 6-4 : Error Categories and Descriptions.......................................................................................... 134
Table 6-5 : Operation for the Reserved Bits in the Packet ........................................................................ 135
Table 6-6 : CFG_REG Map...................................................................................................................... 156
Table 6-7 : Generic Capabilities Register ................................................................................................. 159
Table 6-8 : PHY Capabilities Register ...................................................................................................... 161
Table 6-9 : LINK/TRAN Capabilities Register ........................................................................................... 162
Table 6-10 : Generic Settings Register..................................................................................................... 164
Table 6-11 : PHY Settings Register .......................................................................................................... 165
Table 6-12 : Detailed Definitions of Transmission Speed Range .............................................................. 166
Table 6-13 : LINK/TRAN Settings Register .............................................................................................. 167
Table 6-14 : Preset Register .................................................................................................................... 168
Table 6-15 : Status Register .................................................................................................................... 168
Table 6-16 : Status in TRANS_ABORT Register ...................................................................................... 169
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Table 6-17 : Interrupt Register ................................................................................................................. 170
Table 6-18 : INT Enable Register ............................................................................................................. 170
Table 6-19 : INT Status Register .............................................................................................................. 171
Table 6-20 : Command Register .............................................................................................................. 171
Table 6-21 : Transaction Conditions of TSSM .......................................................................................... 173
Table 6-22 : Transaction Conditions of TPSM .......................................................................................... 175
Table 6-23 : Transaction Conditions of TBSM .......................................................................................... 178
Table 6-24 : Transaction Conditions of TPSM while Boot Code Loading .................................................. 181
Table 6-25 : Device Timing Parameters in CM-TRAN............................................................................... 201
Table 7-1 : Additional Rules of Legacy SD Commands in UHS-II ............................................................. 212
Table 7-2 : Card State Transition by UHS-II Native Command ................................................................. 219
Table 7-3 : Detailed Definition of SD-TRAN Specific MSG ....................................................................... 228
Table 7-4 : Code Definition of EBSY ........................................................................................................ 229
Table 7-5 : Device Timing Parameters in SD-TRAN ................................................................................. 243
Table 8-1 : Timing Parameters Related to Direction Switch ...................................................................... 260
Table D- 1 : Register Attribute Table ......................................................................................................... 280
Table E- 1: D0, D1 Output Requirement for Host Transmitter at TP1 (Informative) ................................... 282
Table E- 2: RCLK Output Specification for Host Transmitter at TP1 (Informative) ..................................... 282
Table E- 3: D0, D1 Input Specification for Host Receiver at TP1 (Informative) .......................................... 283
Table E- 4: SSC Parameters.................................................................................................................... 284
Table F- 1 : Interface Signals (Transmit / Control Data) ............................................................................ 290
Table F- 2 : Interface Signals (Receive / Status Data) .............................................................................. 291
Table F- 3 : Interface Signals (Miscellaneous Data) ................................................................................. 291
Table F- 4 : External Signals .................................................................................................................... 291
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1. General
This Addendum Specification defines an additional category to the Part 1 Physical Layer Specification
Version 4.00 or later. The following sections describe additional and modified parts of the base
specification for this new category.
Key background factors behind Ultra High Speed Type II (UHS-II) Specification are shown below:
 High speed interface is required to handle large volumes of HD (High Definition) contents
In recent years, the number of SD-applications which handle large amount of data is increasing
steadily with an increase in HD (High Definition) contents (HD, Super-HD, 3D-TV, etc.). At the
same time, the data size of HD contents is also increasing year by year.
UHS-II is necessary to meet the ultrahigh-speed requirement to handle HD contents and farther
large-capacity contents in the future.
 Interface should be widely available for many kinds of hosts
It is difficult to keep signal integrity at high-speed data transfer especially for mobile devices.
Generally, board design of hosts becomes more difficult with high speed interface. UHS-II should
be considered both high-speed and availability for many kinds of hosts.
 Reusability of legacy resource (IPs, software, etc.) is important for host development
Hosts require the compatibility with legacy protocol for their efficient development.
For example, in SD protocol, preserving the SD legacy infrastructures (CMD, RES, States, Status,
Errors, etc.) provides efficient development with SD hosts, and this leads to a speedy expansion of
UHS-II applications.
 Interoperability and compatibility to Legacy SD I/F is important to avoid market confusion
Hosts and Devices require also the interoperability and compatibility with Legacy SD cards
installed based to enable UHS-II specifications to be smoothly adopted by the market.
 Low voltage, low power consumption and low EMI are needed for mobile devices
To apply new high-speed interface to many kinds of mobile devices, it is important to realize low
power consumption and low EMI.
Some low power and low EMI techniques need to be considered for UHS-II.
 Multiple device connectivity for minimizing the number of ports and circuit size is required
Multi device connectivity is required to reduce the number of ports and circuit size for lower
developing cost.
In UHS-II Addendum Version 1.02, Range A (up to 780Mbps) and Range B (up to 1560Mbps) were
introduced as a range of data rate per lane. Now, to realize further enhancement of the data
transmission performance, Range C (up to 3120Mbps) and Range D (up to 6240Mbps) are newly
added at the Addendum Version 2.00 (refer to Table 6-12 for transmission speed range definition).
Based on the marketing regulation, products which support Range C and Range D will be indicated as
“UHS-III” instead of UHS-II. However, the word “UHS-II” is used as a technical terminology in this
specification for simplicity, even the descriptions are related to Range C or Range D.
System features of UHS-II Specification based on the background are described in the next chapter.
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2. System Features
From background factors mentioned in Chapter 1, the features of UHS-II are defined as follows:
(1) High speed interface up to 312MB/s for Version 1.02, and up to 624MB/s for Version 2.00.
(2) Easy implementation for whole system
(3) Compatibility with Legacy SD interface
(4) Ensuring effective performance of data transfer
(5) Low voltage, low power consumption, low EMI
(6) Multiple device connectivity
The followings are additional explanations for system features.
• Interface speed
(1) Full Duplex mode (abbreviated to "FD mode"): data rate from 39MB/sec to 156MB/sec in Version
1.02. The maximum speed of this mode is enhanced to 624MB/s in Version 2.00.
(2) Half Duplex with 2 Lanes mode (abbreviated to "2L-HD mode"): data rate from 78MB/sec to
312MB/sec in Range A and Range B (refer to Table 6-12).
(3) Interface speed is continuously variable up to 312MB/s. For over 312MB/s, it is partially variable
for some speed ranges (refer to Table 6-12).
(4) Infrastructure for additional Lanes is defined as follows, allowing future bit rate expansion. (Refer
to Section 3.1 for the definition of downstream or upstream.)
• Full Duplex with 2 Downstream and 1 Upstream Lanes mode (abbreviated to "2D1U-FD mode")
• Full Duplex with 1 Downstream and 2 Upstream Lanes mode (abbreviated to "1D2U-FD mode")
• Full Duplex with 2 Downstream and 2 Upstream Lanes mode (abbreviated to "2D2U-FD mode")
• Layering architecture
(1) The system is divided into at least 4 layers, Mechanical, Physical, Link and Transaction.
(2) Application specific layer can be introduced as a bridge between UHS-II common Transaction
layer and the application.
• Legacy SD compatibility (for Card form factor)
(1) Host and Device shall support Legacy SD I/F for ensuring fully backward compatibility.
(2) Encapsulation of Legacy SD Format for Software Compatibility.
• Easy expansion for advanced features in the future
(1) CMD Queuing: Another arbitrary command can be issued during some transaction.
(2) Relaxed Ordering: Transaction order can be rearranged with reference to priority or processing
speed.
(3) Inter-device Communication: Some Device (called "CMD issuable Device") allows issuing
commands and directly communicating to other Device.
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3. UHS-II System Concept
In this chapter, the overall of UHS-II interface and system are described. UHS-II Card (or simply Card)
denotes an SD memory card which supports UHS-II interface..
3.1 Interface Speed
UHS-II interface consists of at least two Lanes based on two differential signaling lines. Each Lane
provides 624MB/sec as a maximum interface speed.
Basically, direction of both Lanes is opposite each other, that is, one is from Host to Device
(downstream) and the other is from Device to Host (upstream). This mode is defined as Full Duplex
mode (abbreviated to "FD mode").
At Range A or Range B, it is possible that both Lanes are set to transfer data in the same directions. In
that case, maximum interface speed is doubled to 312MB/sec (twice as high as FD mode). This status
is defined as Half Duplex with 2 Lanes mode (abbreviated to "2L-HD mode") and is optional for Range A
and Range B in this specification. Note that 2L-HD mode is not available for Range C and Range D. It is
also possible to have more than two Lanes, 3 or 4 Lanes for increasing system speed. This behavior is
optional in this specification.
Figure 3-1 illustrates interface speed comparison among bus modes in Legacy SD, UHS-I and UHS-II
(for UHS-II interface of 2 Lanes is assumed).
Bus mode
Default Speed DS
High Speed
HS
UHS50
SDR50/
DDR50
UHS104
FD: Full Duplex
HD: Half Duplex
SDR104
UHS-II FD156
UHS156
UHS-II HD312
←UHS-II FD624→
UHS624
0 12 25 39 50 78 104
103
104
105
106
107
108
156
288 312
576 624
Throughput (MB/s)
Figure 3-1 : Interface Speed Comparison
The interface speed shall be variable continuously except some specified speed range of UHS624. Host
and Device supporting UHS624 also shall support UHS156.
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3.2 Connection Topologies
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3.2.1 Point to Point Connection
Minimum topology is consisting one Host and one Device is called "Point to Point" connection. Figure
3-2 shows the connection of a Host and a Device.
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CPU S/W
D0 Lane (Downstream)
Host
including
D0.Tx, D0.Rx Port and D0 Line
UHS-II I/F
Controller
Legacy
SD I/F
Tx
Tx
Host PHY
Rx
RCLK Line
D0 Line
D1 Line
RCLK Lane
including
RCLK.Tx, RCLK.Rx
Port and RCLK Line
Legacy
SD I/F
Link
including
RCLK, D0 and D1 Lane
Rx
Rx
Tx
Controller
UHS-II I/F
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including
RCLK.Tx, D0.Tx and D1.Rx Port
Device
Device PHY
including
RCLK.Rx, D0.Rx and D1.Tx Port
D1 Lane (Upstream)
including
D1.Tx, D1.Rx Port and D1 Line
Figure 3-2 : Point to Point Topology (FD mode)
In UHS-II interface, both Host and Device have a PHY and a Controller which are responsible for
performing Physical and Link / Transaction layer functions respectively. And UHS-II interface are
connected by the following three Lanes.
• RCLK: transmits reference clock to Device from Host.
• D0: is a data Lane. It transmits commands, data, or other packets from Host to Device
(downstream).
• D1: is another data Lane. It transmits responses, data, or other packets from Device to Host
(upstream).
In general, each Lane consists of a Tx (Transmitter) Port and an Rx (Receiver) Port and a transmission
Line between them. The notations used in this specification are used to specify each Tx or Rx Port
clearly. For instance, Tx Port of RCLK Lane is described as RCLK.Tx and Rx Port of RCLK Lane is
described as RCLK.Rx. The same rule is applied for other Lanes. And all Lanes are collectively called
Link. Host PHY (PHY of Host) includes RCLK.Tx, D0.Tx and D1.Rx. Similarly, Device PHY (PHY of
Device) includes RCLK.Rx, D0.Rx and D1.Tx.
All following descriptions relate to interface with two data Lanes. The optional case of 3 or 4 Lanes is
described in Chapter 9.
Figure 3-3 shows the connection of Host and Device supporting 2L-HD mode.
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CPU S/W
D0 Lane (default Downstream)
Host
including
D0.Tx, D0.Rx Port and D0 Line
(D0.Tx / D0.Rx Port also have Rx / Tx respectively)
UHS-II I/F
Controller
Host PHY
Legacy
SD I/F
Tx
Tx/Rx
Rx/Tx
RCLK Line
D0 Line
D1 Line
RCLK Lane
including
RCLK.Tx, RCLK.Rx
Port and RCLK Line
Link
including
RCLK, D0 and D1 Lane
Rx
Legacy
SD I/F
Rx/Tx
Tx/Rx
Device PHY
including
RCLK.Rx, D0.Rx and D1.Tx Port
Controller
UHS-II I/F
D1 Lane (default Upstream)
Device
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including
RCLK.Tx, D0.Tx and D1.Rx Port
including
D1.Tx, D1.Rx Port and D1 Line
(D1.Tx / D1.Rx Port also have Rx / Tx respectively)
Figure 3-3 : Point to Point Topology (Supporting 2L-HD Mode)
The default direction of D0 Lane is downstream, and D1 is upstream. If Host decides to send data to
Device in 2L-HD mode, D1 Lane changes downstream temporarily (Figure 3-4 (a)). Similarly if Host
decides to get data from Device in 2L-HD mode, D0 changes upstream (Figure 3-4 (b)). As a result, all
Ports for data Lanes are necessary to have both functions of Tx and Rx.
(b)
(a)
CPU S/W
CPU S/W
D0 Lane
(Downstream)
Host
UHS-II I/F
Controller
Legacy
SD I/F
Legacy
SD I/F
Tx/Rx
Rx/Tx
Rx
Rx/Tx
Tx/Rx
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Device PHY
(D1.Tx Port is temporarily switched to Rx)
Controller
UHS-II I/F
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UHS-II I/F
Controller
Host PHY
(D1.Rx Port is temporarily switched to Tx)
Tx
Device
D0 Lane
(temporary Upstream)
Host
Legacy
SD I/F
Legacy
SD I/F
Tx/Rx
Rx/Tx
Rx
Rx/Tx
Tx/Rx
Device PHY
(D0.Rx Port is temporarily switched to Tx)
Controller
UHS-II I/F
D1 Lane
(temporarily Downstream)
Host PHY
(D0.Tx Port is temporarily switched to Rx)
Tx
Device
D1 Lane
(Upstream)
Figure 3-4 : Direction Changing in 2L-HD Mode
3.2.2 Multi-device Connection
In order that Host can control or communicate with multiple Devices, UHS-II provides Multi-device
connection. There are two types of topologies to realize Multi-device connection, one is Ring connection
and the other is Hub connection. Ring connection is introduced to realize a cost effective topology that
minimizes the total number of PHY in the embedded system. And Hub connection is introduced to
realize more flexible topology compared to Ring, in terms of capability of hot insertion and removal.
Note that RCLK shall be distributed individually to removable Devices, and not only UHS-II interface but
also Legacy SD interface shall be connected to removable Devices.
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3.2.2.1 Ring Connection
Figure 3-5 illustrates an example of Ring connection. Connection rule of data Lanes is as follows.
(Note that 2L-HD mode is not available in Ring connection in UHS-II Addendum Version 1.00 or later.)
Host
Tx Rx
Rx Tx
Rx Tx
Rx Tx
Device#1
Device#2
Device#3
Device#N
Figure 3-5 : Example of Ring Connection
(1) D0.Tx of Host is connected to D0.Rx of Device#1
(2) D1.Tx of Device#1 is connected to D0.Rx of Device#2, and this operation is repeated.
(3) D1.Tx of Device#N (final Device) is connected to D1.Rx of Host, and Ring connection completes.
Examples of RCLK distribution method are illustrated in Figure 3-6.
(a)
(b)
Terninated externally or
at the final receiver
RCLK Tx
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Tx
D0
Rx
D1
Rx
D0
Tx
D1
Rx
D0
Tx
D1
Rx
Rx
D0
Tx
D1
Rx
Device#3
Rx
D0
Tx
D1
Rx
Device#2
Rx
D0
Tx
D1
RT
Rx
Host
Rx
D0
Tx
D1
Rx
Device#4
Rx
D0
Tx
D1
Rx
Device#3
Tx
D0
Rx
D1
Rx
Device#1
Host
Rx
Rx
D0
Tx
D1
Device#4
Tx
Tx
Tx
Tx
Device#2
RCLK#4
RCLK#3
RCLK#2
RCLK#1
Device#1
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Rx Tx
Figure 3-6 : Examples of RCLK distribution method for Ring
Figure 3-6 (a) shows a multiple point to point method which uses a separate RCLK driver (RCLK.Tx) for
each Device. With this method, Host needs to have at least the same number of RCLK.Tx Ports as the
number of connecting Devices. If Host has only one RCLK.Tx Port, multi-drop method can be applied to
connect multiple Devices (Figure 3-6 (b)). With this method, RCLK bus is terminated externally or at the
final receiver. In addition this method requires careful signal integrity design.
Note that Device has only one RCLK.Rx Port even in the case of Figure 3-6 (b).
3.2.2.2 Hub Connection
Figure 3-7 illustrates an example of Hub connection.
Hub shall have one Device PHY for Host connection and plural number of Host PHYs for Device
connection. Hub also has functions such as transmitting signals to all connected Devices
simultaneously, or selecting a packet destination according to its content.
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Host
Device PHY for
Host Connection
Tx Rx
Rx Tx
Hub
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Tx Rx
Tx Rx
Tx Rx
Tx Rx
Rx Tx
Rx Tx
Rx Tx
Rx Tx
Device#1
Device#2
Device#3
Device#N
Host PHYs for
Device Connection
Figure 3-7 : Example of Hub Connection
Note that from Device point of view behavior does not depend on UHS-II topology. Hub specification is
not described in this document.
3.3 Layering
Figure 3-8 shows the overview of UHS-II interface layer structure.
SD CMD/ RES/ DAT
SD-TRAN
( SD specific)
Applicat ion
specific layer
CM-TRAN
( Common layer)
Transact ion
Pow er Mgmt
SD Card Reg ist er
* * -TRAN
( extensible TRAN for future use)
SD St ate Mach in e
Pro to co l Brid ge (SD< -> CM)
Tran Man agemen t
Transactio ns ( D at a, Cont rol)
Ext en ded Part
TPSM
En umerat ion
CMD Queu ing
TBSM
Con figu rat io n
Relaxed Orderin g
TSSM
Common Packet s ( D CMD, CCM D, RES, D ATA)
I D ba sed Mu x/ De mu x
Device-level
power saving
state
Link Man agemen t
Link
Flow Cont rol
DLSM
Physical
PLSM(D0/ D1)
I n-ba nd Link Messag e (MSG)
Da ta I nt eg rit y (Framing & CRC)
Direct ion Cont rol (Opt iona l)
LSS (SYN, LI DL, SOP, EOP, .. .)
PHY I nit ializat ion
8b10b En c / De c, SERDES
Loo pb ack mode
CLK Ph ase Ad just & Da ta Recovery
Syn t hesizer fo r Ref. CLK
Transmit t er (Tx) / Receiver (Rx)
Tx-Rx Switch
(in 2L-HD mod e)
Amplitu de Det ect or
Link-level
po wer saving
stat e
(Do rma nt /
Po wer Down)
Lan elevel
po wer
saving
stat e
(EI DL)
Emp hasis Fun ction (Tx)
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Mechanical
Figure 3-8 : Layering Overview
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Basically, UHS-II interface consists of four layers described below.
• Mechanical layer defines mechanical specification such as card form factor, connector pins and
so on.
• Physical layer (denoted by PHY) defines electrical specification such as signaling architecture,
and handle bit or symbol encoding and decoding.
• Link layer (denoted by LINK) is responsible for Link management including PHY initialization,
and data integrity (packet framing / de-framing and CRC generation / checking). It is also in charge
of power management and flow control.
• Transaction layer (denoted by TRAN) is responsible for protocol-base management including
packet generation and analysis, command-response handshake, and so on.
TRAN is split into sub layers, one is a common layer called CM-TRAN and the other is an application
specific layer. CM-TRAN is responsible for Basic IO or Memory transaction and control. The application
specific layer bridges CM-TRAN and upper application layer in order to keep compatibility. SD-TRAN is
one of the application specific layers and bridges CM-TRAN and Legacy SD applications or drivers.
In this specification, SD-TRAN is also described. Other application specific layers can be defined in the
future.
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3.4 UHS-II Transaction
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3.4.1 UHS-II Packet
The following five packet types are defined for UHS-II TRAN. UHS-II Packet other than MSG is also
called Transaction Layer Packet (TLP).
• Control command packet (denoted by CCMD) is a command without Data packet transaction.
There are two categories of CCMD, one is P2P CCMD and the other is broadcast CCMD. Refer to
Section 6.2.2.3 for the details of them.
• Data command packet (denoted by DCMD) is a command accompanied with Data packet.
• Response packet (denoted by RES) is a response that Device returns to Host after receiving
CCMD or DCMD.
• Data packet (denoted by DATA) is for transmitting data payload between Host and Device.
• Message packet (denoted by MSG) is for transmitting short information. Only MSG is generated
or analyzed in LINK.
Basically, UHS-II packet consists the following three parts, Header, Argument, and Payload. The Header
part is common for all types of packet.
TLP is basically packetized based on information provided by TRAN and depacketized in LINK. Refer to
packet format described in Section 6.2.2 or Section 7.2.1 for the details of the information.
Let initiator denote a Node (Host or Device) that newly creates a packet and transmits it. The following
table indicates the initiator for each packet type.
Packet Type
CCMD/DCMD
RES
DATA
MSG
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Initiator
Host (regardless of P2P CMD or broadcast CMD)
Device
Node creating DATA packet
(Host for write transaction, Device for read transaction)
Node creating MSG packet
Table 3-1 : Definition of Initiator
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3.4.2 Data Transaction
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3.4.3 CM-TRAN
Length Unit Mode is defined to specify the unit of total data transfer length (TLEN) transmitted by Data
packet (DATA). Length Unit Mode has the following two modes, one is a Block Mode and the other is a
Byte Mode. Note that these modes can be set as a parameter of DCMD.
• Block Mode: TLEN is specified by a unit of Block Length, which is a payload length for one block.
Block Length is finally determined through Configuration (refer to Section 6.2.8 and 6.2.9) or
settings in the application specific layers.
• Byte Mode; TLEN is specified by a unit of byte. TLEN shall be less than or equal to Block Length.
Also refer to Section 5.2.6 about a data framing rule of above two modes.
In addition, at most one data transaction can be executed in UHS-II Addendum Version 1.00 or later.
As described in Figure 3-8, UHS-II transaction layer is split into common layer (CM-TRAN) and
application specific layer (SD-TRAN in case of UHS-II Card).
CM-TRAN specifies the common protocol suitable for UHS-II PHY and LINK (UHS-II native protocol).
CM-TRAN generates UHS-II packets and sends them in the transmitter side according to the UHS-II I/O
Register, or analyzes received packets in the receiver side. UHS-II I/O register is accessed by the
Application Driver (Host) or Backend (Device).
Application Driver
UHS-II I/O Register
Host
CM-TRAN
PHY/LINK
UHS-II packets
(CCMD, DCMD, RES, DATA, MSG)
Device
PHY/LINK
UHS-II I/O Register
CM-TRAN
Backend (Flash memory, MPU etc.)
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Figure 3-9 : Basic UHS-II Transaction
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3.4.4 SD-TRAN
SD-TRAN bridges UHS-II interface (CM-TRAN) and Legacy SD IPs or software. SD-TRAN analyzes SD
Host/Device Register and sets parameters to UHS-II I/O Register. In this case, CM-TRAN generates
UHS-II packets which encapsulate Legacy SD command, response or data. Moreover, when CM-TRAN
receives the encapsulated packets, CM-TRAN analyzes it and notifies to SD-TRAN.
Host
Driver
SD Host Register
SD-TRAN (Host bridge)
UHS-II I/O Register
CM-TRAN
PHY/LINK
Encapsulated UHS-II packets
Device (UHS-II Card)
PHY/LINK
UHS-II I/O Register
CM-TRAN
SD-TRAN (Card bridge)
SD Card Register
Backend
(Flash memory, MPU etc.)
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Figure 3-10 : UHS-II Transaction by SD-TRAN
3.4.5 Aborting Transaction
In UHS-II, TRANS_ABORT CCMD is introduced as following purposes.
• Terminating data transmission in UHS-II native protocol. (Note that the encapsulated CMD12 shall
be used instead of TRANS_ABORT if SD-TRAN is implemented.)
• Aborting the outstanding transaction when timeout is detected.
Example sequences using TRANS_ABORT are described in Section 6.2.14, Section 6.3.2, Section 0,
and Section 7.3.2.
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3.5 UHS-II Initialization Outline
Host shall execute UHS-II Initialization flow as described in Section 3.5.1 (in case of without Boot Code
Loading) or in Section 3.5.2 (in case of with Boot Code Loading). If Host violates those rules, Device
operation is not guaranteed.
3.5.1 UHS-II Initialization Flow without Boot Code Loading
Figure 3-11 shows a UHS-II Initialization flow after I/F power cycle or issuing FULL_RESET command
(refer to Table 6-20 for more details). Details of state transition are defined in Section 5.2.9.
Power On
Process name
FULL_RESET
Outline of process
PHY Initialization starts when
Device detects STB.L
PHY Initialization
• PLL Activation
• Establishing synchronization
Device Initialization
These processes are
mandatory after power cycle
or FULL_RESET.
Wakeup State
Config State
• Starting Device wakeup
Enumeration
• Device ID assignment
Configuration
• Reading and Setting for
CFG_REG
"Config Completion"
is set to 1
Active State
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Figure 3-11 : UHS-II Initialization Flow
After I/F power cycle or FULL_RESET, PHY Initialization process is started by Host's providing RCLK
and STB.L (refer to Section 5.3 for more details).
After finishing PHY Initialization, the state transits to Config State and the following three processes are
taken place.
• Device Initialization: This process is executed by DEVICE_INIT CCMD and makes whole
components in Device activated. Refer to Section 6.2.6 for more details.
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• Enumeration: This process is executed by ENUMERATE CCMD and assigns Node IDs for each
Device uniquely. Refer to Section 6.2.7 for more details.
• Configuration: This process is for determination of parameters for transaction among Host and
Devices. First Host reads capabilities or properties from Configuration Register (CFG_REG) of
Devices, then determines the parameters for transaction, and finally writes the parameters to the
register. Refer to Section 6.2.8 and 6.2.9 for more details.
If "Config Completion" flag defined in CFG_REG is set to 1 successfully during Configuration process,
the state transits to Active State.
Before completing Device Initialization it shall not operate and not transmit RES or broadcast CCMD
when Device receives CMD other than DEVICE_INIT CCMD.
3.5.2 UHS-II Initialization Flow with Boot Code Loading
It is possible for Host to load its Boot Code from one of connected Device, called Boot Device. Boot
Device is optional in embedded system. It is required for Host to read the Boot Code as soon as
possible.
Needless to say, Boot Device and Host are possible to transmit or receive Boot Code. In addition,
considering the Ring connection, all other Devices also have functionality to bypass Boot Code and its
related packets.
In this Section, the specification of loading Boot Code is described when the system includes Boot
Device. This function is called "Boot Code Loading". Figure 3-12 shows UHS-II Initialization flow when
Boot Code Loading is executed.
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Power On
Process name
FULL_RESET
Outline of process
When Device detects BSYN
Boot
SYN at
LSS
at PHY
PHY Initialization.
Initialization.
Device shall set its own
"Config Completion" to 1, and
take place Boot Code Loading.
PHY Initialization
Wakeup State
• PLL Activation
• Establishing synchronization
Config State
Boot Code Loading
Active State
• Transmit Boot Code to Host
(for Boot Code Loading)
"Config Completion" is set to 0
Device Initialization
These processes are
mandatory after power cycle
or FULL_RESET.
Config State
• Starting Device wakeup
Enumeration
• Device ID assignment
Configuration
• Reading and Setting for
CFG_REG
"Config Completion" is set to 1
Active State
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Figure 3-12 : UHS-II Initialization Flow When Boot Code Loading Is Executed
Different from Figure 3-11, Host transmits not SYN LSS but BSYN LSS in order to establish
synchronization (refer to Section 5.2.2.2 and Section 5.9). At that time, all Devices shall set their own
"Config Completion" to 1.
After finishing PHY Initialization, DLSM normally transits to Config state, but as "Config Completion" is
equal to 1, DLSM immediately transits to Active state in order to execute Boot Code Loading.
After finishing Boot Code Loading, Host shall set "Config Completion" to 0 for all Devices before
DEVICE_INIT CCMD. Device shall accept the Broadcast Write CCMD for setting "Config Completion" to
0 even before receiving DEVICE_INIT CCMD. Then DLSM transits to Config state. The rest of flow is
same as Figure 3-11.
Details of Boot Code Loading are defined in Section 5.9.
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The details of UHS-II Physical layer such as signaling architecture electrical specification and handle bit
or symbol encoding and decoding are described in this chapter.
The UHS-II standard is targeted for mobile, portable applications and home applications. It shall be
compatible to legacy SD Cards. It provides enhanced data rate, while maintaining low power and low
EMI. It is recommended for short cable length, typically below 20cm.
This UHS-II specification is defined for Card and also for Embedded Device. In this specification,
"Device" means both Card and Embedded Device. If some specification items or descriptions are only
for Card, "Card" is used. If some specification items or descriptions are only for Embedded Device,
"Embedded Device" is used.
The key features of Physical Layer are defined as follows:







380
381
382
383
384
385
386
387
388
Differential low voltage Signaling with DC coupling
Flexibility of transmission rates
Low Frequency Reference Clock (RCLK)
Two types of duplex mode: FD mode (mandatory), 2L-HD mode (optional)
Additional pins for High-Speed Differential transmission
8b/10b coding
Enhanced power saving modes
4.1 Physical Layer Overview
Physical layer consists of the following functions:







Differential Transmitter(Tx) and Receiver(Rx)
Emphasis Function (Tx)
CLK phase adjustment and Data recovery
Serializer and De-serializer (SERDES)
8b/10b encoding and 10b/8b decoding
Amplitude Detection
Synthesizer for Reference CLK
Physical
369
370
371
372
373
374
375
376
377
378
379
4. Physical Layer Specification
8b10b Enc / Dec, SERDES
Loopback mode
CLK Phase Adjust & Data Recovery
Synt hesizer for Ref. CLK
Tx-Rx Switch
(in 2L-HD mode)
Transmitt er (Tx) / Receiver (Rx)
Amplit ude Det ect or
Emphasis Funct ion (Tx)
Figure 4-1: Physical Layer Overview
4.2 Physical Layer Interface Architecture
Figure 4-2 illustrates an example of the interface architecture of physical layer in case of point to point
connection between Host and Card. The UHS-II interface utilizes transmission Lines (including socket
and pins) and terminations which are meant to keep the impedance matching for high speed
transmission. UHS-II interface introduces the additional pins for high speed data transmission.
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390
391
392
393
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396
397
398
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400
401
402
403
404
405
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410
UHS-II interface has continuous variable data rate as follows (effective data rate);
- Generation 1: 39MB/sec to 156MB/sec
- Generation 2: 39MB/sec to 156MB/sec, 288MB/sec to 312MB/sec, 576MB/sec to 624MB/sec
Device shall cover the whole range corresponding to the Generation which Device suports.
UHS-II has two data Lanes. As default, one Lane (D0) is used for downstream (from Host to Device),
and another Lane (D1) is used for upstream (from Device to Host). Both data Lanes may be used for
downstream Lanes or upstream Lanes at the same time by activating the 2L-HD mode (optional).
The transmitted data is encoded by 8b/10b encoder.
Host Tx selects own emphasis strength and instructs Device to use the same emphasis strength for
getting same signal integrity on Downstream and Upstream. So Host is strongly recommended to
implement emphasis levels according to Table E-1.
The Differential Clock (RCLK) may be tuned in the range of 26MHz to 52MHz for Range A or B, and
48MHz to 52MHz for Range C or D. Regarding Card, RCLK is sent through the legacy SD transmission
lines DAT0, DAT1 and corresponding Card pins.
Amplitude Detectors, which detect the Lane's electrical level, are equipped to Host side of D1 Lane
(optional) and Device side of D0 Lane (mandatory). Amplitude Detectors make the I/O circuits, such as
receiver, to wake up when transmission is resumed at the Lane after Dormant state.
Host Equipment
UHS-I I SD Card
Legacy Pins
Legacy I / F
OSC
Ref.CLK
Legacy I / F
RCLK
DAT0/ RCLK+
RCLK
RCLK
DAT1/ RCLK-
Legacy I / F
Legacy I / F
PLL
Additional Signal Pins
PCLK
D0
PHY Logic
10b/ 8b
8b/ 10b
Tx
Rx
D1
Emphasis
SER/
DES
D1-
Rx
Rx
8b/ 10b
10b/ 8b
Emphasis
SER/
DES
Tx
8/ 16
Amplitude
Detector
8/ 16
CTRL
STATUS
D1+
10b/ 8b
8b/ 10b
8/ 16
SER/
DES
Tx
STATUS
8/ 16
Emphasis
D0-
PHY Logic
CTRL
Emphasis
SER/
DES
Rx
Link Layer
8/ 16
Tx
8/ 16
8b/ 10b
10b/ 8b
D0+
Link Layer
PLL
PCLK
8/ 16
8/ 16
Amplitude
Detector
Physical Layer
411
412
413
Note 1: All function blocks and connection lines used in 2L-HD mode are colored by gray.
Note 2: I / O circuits of Legacy SD I nterface, which are not used in UHS-I I , are shown by dash-line and filled with light gray.
Note 3: RCLK termination of Device shall be switchable.
Figure 4-2: Physical Layer Interface Architecture
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415
416
417
418
419
420
In case that a UHS-II micro SD card performs UHS-II signal transferring to a host which has a Standard
Size SD socket by using a Card adapter, The combination of the micro SD Card and the adapter shall
comply with UHS-II Device spec. But there is a possibility that combination of a UHS-II micro SD card
and another vendor's adapter doesn't comply with UHS-II Device spec. So it's strongly recommended
that micro SD card vendors notify end users to use adapters which complies with UHS-II Device spec
under the combination with their micro SD card.
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425
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427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
4.2.1 Lane Definition
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458
459
460
461
462
463
464
4.2.2 Range Definition for Data Rate
Host and Device are connected by 3 differential Lanes with DC coupling:
 High speed data Lanes (D0, D1):
D0 is used for downstream (from Host to Device), thus WRITE data and command are
transferred from Host to Device on this Lane. However, when enabling the optional 2L-HD mode,
it is possible to use D0 Lane as upstream (from Device to Host).
D1 is used for upstream, thus READ data and response are transferred from Device to Host on
this Lane. However, when enabling the optional 2L-HD mode, it is possible to use D1 Lane as
downstream.
D0 and D1 Lanes are used for differential transmission between Host and Device which are
dedicated to UHS-II interface only, and are separate from signals of legacy SD interface. The D0
and D1 signals are encoded by 8b/10b code before transmission, and decoded by 10b/8b after
receiving, as described in Section 4.5.
 Reference clock Lane (RCLK):
RCLK is transmitted from Host to Device. Whenever Host outputs a RCLK to the UHS-II Device,
the RCLK signal frequency and phase should be stable. The RCLK shall not be stopped and its
frequency shall not be changed during UHS-II transmission, even within the same range. (Refer
to Section 4.2.2 for the Range definition and Section 6.2.3 for frequency change procedure).
The RCLK frequency is lower than lowest data rate. Therefore, the Device shall generate high
frequency clock or multi-phase clocks internally for sampling the high-speed data. The RCLK
frequency is in the range of 26MHz to 52MHz at Range A,B, and 78MHz to 104MHz at Range
C,D; Data rate pre Lane is 390Mbps to 780Mbps at Range A, 780Mbps to 1.56Gbps at Range B,
2.34Gbps to 3.12Gbps at Range C and 4.68Gbps to 6.24Gbps at Range D (Refer detail in
Section 4.2.2).
Regarding Card, RCLK is sent through DAT0 and DAT1 lines of legacy SD interface. Thus, RCLK
does not require additional pins. Card RCLK receiver shall be tolerant to single ended voltage
range of 0V to 3.6V DC.
For power save purposes, when no data is transferred each Lane may enter EIDL state individually, or
all Lanes including RCLK Lane may enter EIDL state concurrently, which is called Dormant state.
During those states and mode, an Amplitude Detector of each D0, D1 Lane is active, monitoring the
Line voltage and flagging wakeup notice. After detecting the wakeup notice, the detector activates PHY
circuits of own port.
In UHS-II, relations between RCLK frequency and Data rate depend on each Range. Four Ranges are
defined for the ease of PLL design as shown in Table 4-1.
Initialization of UHS-II interface after power down shall be done with the Range A.
Device PLL acquisition time shall be at most 2ms. But only the first PLL acquisition time after power up,
PLL of Host and Device shall finish locking less than 100ms. This is Tactivate. (Refer to Section 5.3 for
PHY Initialization.)
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RCLK Frequency
466
467
Ratio
(Data rate / RCLK
Frequency)
Range A
390Mbps to 780Mbps
x 15
26MHz to 52 MHz
Range B
780Mbps to 1.56Gbps
x 30
Range C
2.34Gbps to 3.12Gbps
x 60
48MHz to 52MHz
Range D
4.68Gbps to 6.24Gbps
x 120
Note 1: Considering Crystal Oscillator’s accuracy. Maximum RCLK frequency may be allowed
up to 52MHz+1% and minmun RCLK frequency of Range C and D may be also allowed
down to 48MHz-1%. But even if supporting SSC, the minimum RCLK frequency shall
not be lower than the minimum frequency including the accuracy margine at each
range.
Table 4-1: Range Definition for Data Rate
468
469
470
471
472
473
474
475
476
4.2.3 Power Supply Connections
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479
480
481
4.2.4 Operating Condition
Data Rate/channel
Two power supply connections are needed for UHS-II interface, named VDD1 and VDD2, for powering
the Device by the Host.
VDD1 is dedicated for powering the legacy SD interface, logic and the memory devices in the Device
VDD2 is used for powering UHS-II interface. It should power the PHY and upper layers logic.
GND node is common to all the devices and all the circuits. It is also used as reference for the UHS-II
signaling levels, thus it is recommended that both Host and Device design for minimal DC variation and
AC noise on this node.
UHS-II Device shall operate with the condition shown in Table 4-2 and Table 4-3.
Operating temperature was defined by mechanical addendum.
Value
Min Typ
Max
Unit
VDD1 Supply voltage
2.7
3.3
3.6
V
VDD2 Supply voltage
1.7
1.8
1.95
V
Note 1: VDD1 of 1.8V is under evaluation.
Note 2: VDD2 of 1.2V is optional for embedded Device.
Item
note
Note 1
Note 2
Table 4-2: Operating Voltage
482
483
484
Item
Leakage current of each
UHS-II pin
Min
Value
Typ
Max
Unit
-
-
uA
10
note
Absolute value.
Note 1, 2, 3
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Note 1: Refer to leakage of D0+, D0-, D1+, D1-, RCLK+ and RCLK-.
Note 2: When pin is at input state, with static valid input voltage.
Note 3: Input termination resistor is disconnected.
Table 4-3: Leakage Current
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487
488
489
490
491
492
493
494
495
496
497
498
499
500
4.2.5 Over-voltage Tolerance
When UHS-II Card is inserted to the existing multi-card socket, the differential contact pads of D0 and
D1 might accidentally be in touch with the other contact terminals of the multi-card socket, which are
used for the connection with the other standards removable device.
These contact terminals have a possibility to be pulled up to 3.6V via 10kohm resistor or more.
Device shall tolerate this over voltage condition. However it is not expected to function under this
condition.
In addition, RCLK Rx of Card shall be tolerant to 3.6V (Refer to Section 4.2.1 "Reference Clock Lane").
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4.2.6 Impedance and Termination Scheme
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505
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509
510
511
4.2.6.1 Impedance Definition
The performance of high-speed transmission depends on the impedance matching for all elements of
the differential Lanes, such as transmission Lines on PCB, connectors and terminations.
This section specifies the impedance and termination requirements for the components of the
differential Lanes.
Table 4-4 denotes the requirement of impedance characteristics for Device side. UHS-II Device shall
comply with this requirement.
Item
Symbol
RSE-TX
Tx Output Impedance
Min
value
Typ
Max
Unit
35
50
ohm
65
Note
Each single-ended
output Impedance.
Differential mode.
Rx Termination
RtermDIF
74
100
126
ohm
Measured at DC
Impedance
Input
RCLK+,
Note 1
CRCLK
10
pF
Capacitance RCLKNote 1: CRCLK is equivalent to CDIE + CPKG in Section 6.7.1.3.3 Figure 6-14 of the Physical Layer
Specification Version 4.00 or later.
512
513
514
515
516
517
Table 4-4: Device Impedance Characteristics
Table 4-5 denotes the requirement of impedance characteristics for Host. UHS-II Host shall comply with
the requirement.
Item
Symbol
Min
Value
Typ
Max
Unit
Tx Output Impedance
RSE-TX
35
50
65
Ohm
Characteristic Impedance of
differential Transmission
Line
ZD
85
100
115
Ohm
Note
Each single-ended
output Impedance.
Differential mode
Note 1,2
Differential mode
Measured at DC
Note 1: Socket and cable shall also comply with this spec. But a single exception is permitted for
socket: 100ohm ±30ohm only for 200ps duration.
Note 2: For the differential transmission Line, the difference of characteristic single-ended impedance
between + and - single-ended trace (intra pair single ended impedance match) is
recommended to be within ±5% (as informative).
Rx Termination Impedance
518
519
520
521
522
RtermDIF
74
100
126
Ohm
Table 4-5: Host Impedance Characteristics
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Application Note:
In regard to D0+,D0-,D1+ and D1-, Card and Host die capacitance itself* would make a great
impedanece discontinuity in front of Rx termintaiton impedance and also Tx output impedance.
It results signal reflections which makes eye opening narrow. Thus, these capacitances should be
small as much as possible.
The following values are recommended as a desing target for these die capacitances of D0+,D0,D1+,D1-:
- Generation 1 : up to 2pF
- Generation 2 : 1.2pF to 1.5pF
If possible, much less value is preferable. And also any value may be implemented as long as the
eye mask and return loss requirements are met.
* It is called as "CDIE" in Section 6.7.1.3.3 Figure 6-14 of the Physical Layer Specification Version
4.00 or later.
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525
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530
531
532
533
534
535
536
537
538
539
4.2.6.2 Input Termination Scheme
By default, the interface is set to be FD mode, where Host is Tx and Device is Rx on D0 Lane, Host is
Rx and Device is Tx on D1 Lane. As the default settings, Rx of each Lane shall activate the receiver
termination.
When supporting 2L-HD mode, direction of D0 and D1 Lane may be changed if required. The receiver
side of each Lane shall activate the termination and transmitter side of each Lane should deactivate the
termination.
For the RCLK Lane, Host always functions as transmitter and Device always functions as receiver.
Thus, the Device side shall always activate the termination, and the Host side has no need for parallel
termination. Multi-drop method for RCLK distribution may be applied to Embedded Devices, in that case
the termination of RCLK is used in only at the last Device or the end point of RCLK Line. (Refer to
Figure 3-6(b) in System and Protocol specification draft for more details).
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548
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553
554
555
4.2.7 Definition of Test Points for Host and Device
The signal test points are shown in Figure 4-3.
TP1 is the point where the Host LSI pins are connected to the PCB. The Tx and Rx electrical
specifications at TP1 are described in Appendix E, while eye-mask templates at TP1 are described in
Figure 4-6, Figure 4-7 and Figure 4-8. All signals specifications at TP1 are for recommendation only.
In case of Host and Card connection (Figure 4-3 (a)), TP2 is the connection point between Host and
Card, which are Card socket contacts. In case of Host LSI and Embedded Device connection (Figure
4-3 (b)), TP2 is the point where the Embedded Device pins are connected to the PCB.
Note: Figure 4-3 describes the conceptual location of TP1 and TP2 when Host is connected to Device.
Nevertheless, all requirements that refer to TP1 and TP2 (informative and normative) in this
specification are targeted to be tested for compliance in separate test fixture environments as
described in Appendix C.1 (for Host) and Appendix E.2 (for Device).
Socket
Lead
RCLK
LSI
LSI
D0 / D1
UHS-II SD Card
Socket
Host PCB
Host
TP1
TP2
(a) In case of Host and Card connection
RCLK
Host
LSI
Embedded
Device
D0 / D1
Host PCB
TP1
TP2
(b) In case of Host LSI and Embedded Device connection
556
557
558
559
Figure 4-3: Signal Test Points
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4.3 Electrical Specification
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562
563
564
565
4.3.1 Definition of Single-ended and Differential Signals
Single ended signals, representing either the positive or negative signal of a differential pair Line, are
illustrated in Figure 4-4, Figure 4-5(a) as VDp and VDn respectively. The absolute value of the difference
between VDp and VDn are defined as differential voltage;
Vdiff = VDp − VDn
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567
568
569
570
The differential net swing is from –Vdiff to +Vdiff centered on 0V differential. Thus peak to peak voltage of
differential signal Vdiffp-p is two times of Vdiff;
Vdiff p − p = 2 * Vdiff
= 2 * VDp − VDn
571
572
573
574
575
The common mode swing of differential Line (VCM) is defined as the mean value of both single ended
swings VDp and VDn.
VCM =
576
VDp + VDn
2
577
578
579
VDp
Rx
RTerm
RSE-Tx
Tx
580
581
582
583
584
VDn
Figure 4-4: Single-ended Signal Names on Differential Line
Note: The schematics of Tx side and Rx side in this Figure 4-4 are only example. The actual
implementation may be different.
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VDp
Vdh
Vdiff = | VDp – VDn |
Vcm
VDn
Vdl
0
(a) Single-ended Signals
Time
Differential Signal
Voltage level
+Vdiff
Vdiffp-p = 2*Vdiff
= 2*| VDp – VDn |
+Vdiff
0
Time
-Vdiff
-Vdiff
(b) Differential Signal
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586
587
588
Figure 4-5: Definition of Single-ended and Differential Signals
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590
591
592
4.3.2 Specification of Transmitter and Receiver
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596
597
598
599
600
4.3.2.1 Host Transmitter Specification
When Host transmits differential signal at each differential Lane (D0 or D1), the output waveform shall
meet the electrical specifications listed in Table 4-6 at TP2.
The specifications of transmitter and receiver are detailed in this section. These specifications are
defined at TP2 point.
The eye-mask templates for Host transmitter related to Table 4-6 are shown in Figure 4-6 (2), Figure 4-7
(2) and Figure 4-8 (2).
Item
Symbol
Range
A,B
Differential
voltage
Vdiff
C
D
Min
value
Typ
Max
125
185
280
-
350
-
350
105
(125)
60
(125)
Unit
mV
Absolute value.
Note 1
Absolute value.
125mV min is for STB.L period.
Note 1
Informative.
From 20% to 80% of voltage swing.
Note 2
Rise/Fall time of
Differential signal
Tr,Tf
A,B,
C,D
25
-
-
ps
Common mode
voltage
VCM
A,B
C
D
150
200
160
200
-
250
350
350
mV
Vdiff_PD
A to D
-10
0
10
mV
VCM_PD
A to D
-10
0
10
mV
Skinter
A,B
C,D
-
-
1.0
2.0
UI
EIDL state
differential
voltage
EIDL state
common mode
voltage
Inter skew
Note
Note 1,5
Note 3
Note 3,5
Note 4
Note 1: With a differential termination of 100Ω.
Note 2: Designers should consider improvement of signal integrity and reduction of EMI to determine rise/fall time of Host and
Device output. Use of slower rise/fall time as much as possible at each operation Range is an example implementation.
Note 3: In EIDL state, both positive and negative lines of D0 Line are pulled down by Tx.
Note 4: Inter skew means the skew between D0 and D1 when both transmitters transmit from Host to Device. This is mandatory
for 2L-HD mode and not applied to FD mode.
Note 5: VCM_PD and VCM are measured in reference to its local GND. More details are in UHS-II PHY Test Guidelines document.
601
602
603
604
605
606
Table 4-6: D0, D1 Output Requirements for Host Transmitter at TP2
The output waveform from Host shall meet the electrical specifications listed in Table 4-7 at TP2 for the
RCLK Lane.
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Item
Symbol
Differential voltage
Vdiff
Min
value
Typ
Max
125
185
280
Unit
Note
mV
Absolute value.
Note 1
Rise/Fall time of
Differential signal
Tr,Tf
-
-
0.2
TRCLK
Common mode voltage
VCM
150
200
280
mV
Total Jitter
TJ
-
-
0.3
UI
Duty Cycle
TCKH
42.5
57.5
%
From 20% to 80% of
voltage swing.
Refer to Section 4.11 for
low EMI.
Note 2
Note 1,3,4
Note 5,6,7
Refer to Section 4.3.4
Of TRCLK
Note 1: With a differential termination of 100Ω.
Note 2: TRCLK means the period time of RCLK
Note 3: VCM is measured in reference to its local GND. More details are in UHS-II PHY Test Guidelines document.
Note 4: It is recommended for Host to disconnect legacy DAT0 DAT1 pull up resistors in UHS II mode.(Legacy Tx in Hi-Z )
Note 5: Total jitter is comprised of all jitter components from LSI such as deterministic jitter, random jitter etc.
Note 6: RCLK jitter for Host transmitter is measured related to itself using a 2nd order soft PLL with BW of 2.34MHz/Sf inside
the test equipment. Detailed measurement procedure is described in UHS-II PHY Test Guidelines document.
(Sf is a scaling factor. Refer to Figure 4-7 in Section 4.3.4)
Table 4-7: RCLK Output Requirements for Host Transmitter at TP2
608
609
610
611
612
613
614
615
616
617
618
619
4.3.2.2 Device Receiver Specification
When receiving D0 signal (and D1 signal in 2L-HD mode) from Host, Device receiver shall comply with
specification requirements listed in Table 4-8 at TP2 for every data rate of UHS-II.
The eye-mask templates of the Device receiver related to Table 4-8 are shown in Figure 4-6 (3), Figure
4-7 (3) and Figure 4-8 (3). In addition to Table 4-8, Device receiver shall receive signals that comply
with Figure 4-6 (3), Figure 4-7 (3) and Figure 4-8 (3) correctly.
A,B,
C
D
Min
95
80
45
value
Typ
-
Max
-
Vdiff_STB.L
A to D
95
-
-
mV
Common mode
voltage source
VCM_source
A,B
C
D
150
200
160
200
-
250
350
350
mV
EIDL state common
mode voltage
VCM_PD
A to D
-10
0
10
mV
Item
Symbol
Range
Differential voltage
Vdiff
Differential voltage
of STB.L
Unit
Note
Absolute value.
mV
Absolute value.
Note 6
Note 1, 3,4
Note 1,2, 5
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Note 1:VCM_source and VCM_PD are measured in reference to its local GND.
More details in UHS-II PHY Test Guidelines document.
Note 2: In EIDL state, both positive and negative lines of D0 Lanes are pulled down by Tx.
Note 3: VCM_source is the common-mode voltage which is transmitted by Host Tx together with diff D0/D1 signal.
Note 4: In addition to VCM_source, undefined amount of VCM_noise is expected to appear at device Rx LSI, depending on
device implementation. It is recommended to follow the design guidelines at Appendix E.2.3 .
Note 5: In addition to VCM_PD, undefined amount of VCM_noise is expected to appear at device Rx LSI, depending on device
implementation. It is recommended to follow the design guidelines at Appendix E.2.3 .
Note 6: Amplitude Detector shall detect 95mV STB.L at least (90mV as Detection threshold of Amplitude Detector is
recommended, though it's implementation specific).
Note 7: Jitter tolerance specification is defined in Section 4.3.4.
Note 8: Device Receiver shall tolerate the inter skew spec defined in Table 4-6
620
621
622
623
624
625
Table 4-8: D0, D1 Input Requirement for Device Receiver at TP2
Device receiver shall meet the input requirement listed in Table 4-9 for the RCLK Lane.
Vdiff
Min
95
value
Typ
-
Max
-
VCM_source
150
200
280
mV
Total Jitter
TJ
-
-
0.35
UI
Duty Cycle
TCKH
40
60
%
Item
Symbol
Differential voltage
Common mode voltage
source
Unit
mV
Note
Absolute value.
Note 1, 2,3
Refer to Section 4.3.4
Note 4
Of TRCLK
Note 1: VCM_source is the common-mode voltage which is transmitted by Host Tx together with diff RCLK signal.
Note 2: VCM_source is measured in reference to its local GND. More details in UHS-II PHY Test Guidelines document.
Note 3: In addition to VCM_source, undefined amount of VCM_noise is expected to appear at device Rx LSI, depending on device
implementation. It is recommended to follow the design guidelines at Appendix E.2.3 .
Note 4: Common-mode noise inside device may cause additional jitter on Device Rx LSI, depending on device
implementation. Device designer should take this jitter into account.
626
627
Table 4-9: RCLK Input Requirement for Device Receiver at TP2
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628
629
630
631
632
633
634
635
636
637
638
4.3.2.3 Device Transmitter Specification
When Device transmits differential signal at D1 Lane (and D0 Lane in 2L-HD mode), the output
waveform shall comply with the electrical specifications listed in Table 4-10 at TP2 for every data rate of
UHS-II.
Device transmitter shall have Emphasis functions for Range C and D. The strength of the Emphasis is
selected in initialization by Host.
The eye-mask template for Device transmitter at TP2 related to Table 4-10 is shown in (4) of Figure 4-6,
Figure 4-7 and Figure 4-8..
Item
Symbol
Range
A,B
Differential
voltage
Vdiff
C
D
Rise/Fall time
of Differential
signal
Tr,Tf
Emphasis
TxEmp0
TxEmpL
TxEmpM
TxEmp0
TxEmpL
TxEmpM
TxEmpH
Common mode
voltage source
Common mode
voltage noise
Total Common
mode voltage
EIDL state
differential
voltage
EIDL state
common mode
voltage
EIDL state
common mode
voltage noise
EIDL state total
common mode
voltage
Min
Value
Typ
140
200
135
(140)
80
(140)
-
Max
280
(560)
300
(560)
300
(560)
A,B
100
-
-
C,D
25
-
-
C
1.0
2.5
Unit
mV
ps
A,B
C
D
A,B
C,D
A,B
C
D
1.0
2.5
4.0
150
200
145
-100
-50
50
150
95
0
1.5
3.0
0
1.5
3.0
4.5
200
-
2.0
3.5
5.0
250
300
300
150
100
400
400
400
Vdiff_PD
A to D
-10
0
10
mV
VCM_PD
A to D
-10
0
10
mV
A ,B
-100
0
150
VCM_source
VCM_noise
VCM_total
D
2.0
3.5
dB
Note
Absolute value.
Note.1,2
Absolute value.
140mV min is for STB.L period.
Note.1,2
From 20% to 80% of voltage
swing.Note 3
Informative.
From 20% to 80% of voltage
swing.
Note 3
Disable Emphasis.Note 13
Note 13,14,15
Disable Emphasis. Note 13
Note 13,14,15
Note 4,5,7
mV
mV
Note 4,5,11,12
Note 5,10,11,12
mV
Note 8
Note 4,6,8
VCM_PD_noise
VCM_PD_total
Total Jitter
TJ
Inter skew
Skinter
C,D
-50
-
100
A,B
-110
0
160
C,D
-60
0
110
A,B,C
D
A,B
C,D
-
-
0.35
0.4
0.35
1.4
Note 4,6,8,11,12
mV
Note 6,8,11,12
mV
UI
UI
Refer to Section 4.3.4
Note 9
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Note 1: With a differential termination of 100Ω.
Note 2: The maximum differential voltage is allowed up to 560mV only when first driving STB-L just after power up.
After first STB.L driving, the following SYN symbols shall conform to the regular signaling voltage definitions (280mV at
Range A, B and 300mV at Range C, D, as muximum)
Note 3: Designers should consider improvement of signal integrity and reduction of EMI to determine rise/fall time of Host and
Device output. Use of slower rise/fall time as much as possible at each operation Range is an example implementation.
Note 4: VCM_source is the common-mode voltage which is transmitted by Device Tx together with diff D0/D1 signal
VCM_noise is the common-mode voltage which is added because of Device internal activity. See Appendix E.2.3
VCM_PD is the common-mode voltage which is generated by Device Tx in EIDL state.
VCM_PD_noise is the common-mode voltage which is added because of Device internal activity in EIDL state.
See Appendix E.2.3
Note 5: VCM_total = VCM_source + VCM_noise.
Note 6: VCM_PD_total = VCM_PD + VCM_PD_noise.
Note 7: VCM_source and VCM_PD are measured in reference to its local GND.
More details in UHS-II PHY Test Guidelines document.
Note 8: In EIDL state, both positive and negative lines of D1 Lane are pulled down by Tx.
Note 9: Inter skew means the skew between D0 and D1 when both transmitters transmit from Host to Device. This is mandatory
for 2L-HD mode and not applied to FD mode.
Note 10: This parameter is valid while the Tx drives the following states: Active transfer, STB_L, STB_H.
Note 11: Using Section 4.3.7 – "Host Power Delivery Network Model" as device design condition
Note 12: It is recommended to follow the design guidelines at Appendix E.2.3 .
Note 13: Emphasis Strength is selected by Host in initialization.
Note 14: The duration period is from the beginning to the end of transition bit (1UI).
Note 15: Output wave form shall comply with the Eye mask spec even in the case applying Emphasis.Applying PreEmphasis or
DeEmphasis is implementation
639
640
641
Table 4-10: D0, D1 Output Requirement at TP2 for Device Transmitter
642
643
644
645
646
647
648
649
4.3.2.4 Host Receiver Specification
When Host receives D1 signal (and D0 signal on 2L-HD mode) from Device, Host receiver shall comply
with the requirement listed in Table 4-11 at TP2 at own data rate.
The eye-mask templates for Host receiver at TP2 related to Table 4-11 are shown in Figure 4-6 (5),
Figure 4-7 (5) and Figure 4-8 (5). In addition to Table 4-11, Host receiver shall be capable to receive
signals that comply with Figure 4-6 (5), Figure 4-7 (5) and Figure 4-8 (5).
A,B
C
D
Min
110
100
60
Value
Typ
-
Max
-
A to D
110
-
-
A,B
C
D
A,B
C,D
A,B,C
D
50
150
95
-110
-60
-
200
0
0
-
400
400
400
160
110
0.4
0.45
Item
Symbol
Range
Differential voltage
Vdiff
Differential voltage
of STB.L
Vdiff_STB.L
Common mode
voltage
VCM
EIDL state common
mode voltage
VCM_PD
Total Jitter
TJ
Unit
Note
Absolute value
mV
mV
Absolute value.
Note 1
mV
mV
UI
Note 1,2
Refer to Section 4.3.4
Note 3
Note 1: VCM_PD and VCM are measured in reference to its local GND. More details in UHS-II PHY Test Guidelines document.
Note 2: In EIDL state, both positive and negative lines of D1 Lane are pulled down by Tx.
Note 3: Host Rx data recovery function minimum BW is 2.34MHz/Sf, as described on Table 4-9(2)
Note 4: Host Receiver shall tolerate the inter skew spec defined at Table 4-10 and additional inter skew caused in Host PCB.
650
651
Table 4-11: Input Requirement at TP2 for Host Receiver
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652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
4.3.3 Eye-mask Template
The eye-mask templates are the graphical representation of the limit for the voltage and jitter for the
differential signals. The eye-mask templates of UHS-II are shown in Figure 4-6, Figure 4-7 and Figure
4-8. The horizontal margin of eye-mask template is calculated as 1 UI - T J.
For the transmitters of Host and Device, when transmitting differential signal, these signals including
over/under-shoot and Emphasis shall remain in the white area of each Eye-mask template (Tx) in these
figures anytime except in EIDL state.
For the receivers of Host and Device, when receiving the differential signals that have the eye-opening
shown in eye-templates (Rx) in these figures, receivers shall receive these signals correctly.
As bitrate becomes higher, ISI jitter makes eye closed. Emphasis by the transmitters helps ISI jitter
suppression. Besides, the receivers may have Equalization function for ISI jitter elimination.
Equalization is implementation.
The eye mask templates specified in Figure 4-6, Figure 4-7 and Figure 4-8 refer to measurements at
standard measurement conditions and BER of 1E-12. The standard measurement conditions are
described in UHS-II PHY Test Guidelines document.
Note: The Host and Device are tested separately at "ideal" compliance environment, while in real
system Host and Device are connected together, so there will be some mutual effects because of
this connection. The margin between (2) to (3) Eye-masks and (4) to (5) Eye-masks in Figure
4-6, Figure 4-7 and Figure 4-8 are taken based on the effects. The following elements are
covered by this margin:
A. Power delivery noise,
B. Internal Device Xtalk due to other internal activity
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Host Compliance test environment
Device Compliance test environment
0.75UI
140
Tx
-140
Differential Swing [mV]
280
0
(3) Eye-mask for Device Receiver at TP2
(2) Eye-mask for Host Transmitter at TP2
Differential Swing [mV]
Differential Swing [mV]
(1) Eye-mask for Host Transmitter at TP1
280
0.65UI
125
Tx
0
-125
0.6UI
95
0
Rx
-95
0.375UI
-280
0
-280
0.125
0.3125 0.5 0.6875
Unit Interval [UI]
0.875
0
0.175
0.5
Unit Interval [UI]
0
0.825
0.2
0.5
Unit Interval [UI]
0.8
Eye-mask at TP1 is design guide
Card Test Fixture PCB
Host
RCLK
Host Test Fixture PCB
LSI
RCLK
LSI
Tx
D0
Rx
D0
Tx
Rx
PCB
D1
UHS-II SD Card
Socket
D1
Socket
Host PCB
TP2
TP1
TP2
95
0
Rx
-95
Differential Swing [mV]
0.5UI
(4) Eye-mask for Device Transmitter at TP2
(5) Eye-mask for Host Receiver at TP2
Differential Swing [mV]
Differential Swing [mV]
(6) Eye-mask for Host Receiver at TP1
0.6UI
110
Rx
0
-110
280
0.65UI
140
0
Tx
-140
0.3UI
0.325UI
-280
0
682
683
684
685
686
687
688
689
690
691
692
693
0.25
0.5
0.75
Unit Interval [UI]
0
0.2
0.35
0.5 0.65
Unit Interval [UI]
0.8
0
0.175 0.3375 0.5 0.6625
Unit Interval [UI]
0.825
Eye-mask at TP1 is design guide
Note 1 : In case of Host LSI and embedded device connection, the same Eye-mask templates are applied respectively.
Note 2 : For eye testing De-embedding of the test fixture should be performed. More details in UHS-II Test Guidelines document.
Note 3 : RLCK shall be used as reference when testing downstream (host transmitter) eye diagram.
Details are defined in UHS-II Test Guidelines document.
Note 4 : Eye diagram for upstream (Device transmitter) is measured related to itself using a Clock Recovery Unit (CRU)
inside the test equipment. CRU bandwidth and detailed measurement procedure are described in the UHS-II Test
Guidelines document.
Note 5 : D0/D1 jitter for Host Tx is measured related to RCLK using a 2nd order soft PLL with BW of 2.34MHz/Sf inside
the test equipment. Detailed measurement procedure is described in the UHS-II Test Guidelines document.
Figure 4-6: Eye-mask Templates (Range A,B)
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Host Compliance test environment
Device Compliance test environment
0.75UI
135
Tx
Tx
-135
-350
0
350
Differential Swing [mV]
350
0
(3) Eye-mask for Device Receiver at TP2
(2) Eye-mask for Host Transmitter at TP2
Differential Swing [mV]
Differential Swing [mV]
(1) Eye-mask for Host Transmitter at TP1
0.65UI
105
Tx
0
-105
0.6UI
80
0
-80
Rx
-350
0.125
0.5
Unit Interval [UI]
0.875
0
0.175
0.5
Unit Interval [UI]
0
0.825
0.2
0.5
Unit Interval [UI]
0.8
Eye-mask at TP1 is design guide
Card Test Fixture PCB
Host
RCLK
Host Test Fixture PCB
LSI
RCLK
LSI
Tx
D0
Rx
D0
Tx
Rx
PCB
D1
UHS-II SD Card
Socket
D1
Socket
Host PCB
TP2
TP1
TP2
80
0
Rx
-80
Differential Swing [mV]
0.5UI
(4) Eye-mask for Device Transmitter at TP2
(5) Eye-mask for Host Receiver at TP2
Differential Swing [mV]
Differential Swing [mV]
(6) Eye-mask for Host Receiver at TP1
0.6UI
100
Rx
0
-100
300
0.65UI
135
Tx
0
-135
-300
0
694
695
696
697
698
699
700
701
702
703
704
705
0.25
0.5
0.75
Unit Interval [UI]
0
0.2
0.5
Unit Interval [UI]
0.8
0
0.175
0.5
Unit Interval [UI]
0.825
Eye-mask at TP1 is design guide
Note 1 : In case of Host LSI and embedded device connection, the same Eye-mask templates are applied respectively.
Note 2 : For eye testing De-embedding of the test fixture should be performed. More details in UHS-II Test Guidelines document.
Note 3 : RLCK shall be used as reference when testing downstream (host transmitter) eye diagram.
Details are defined in UHS-II Test Guidelines document.
Note 4 : Eye diagram for upstream (Device transmitter) is measured related to itself using a Clock Recovery Unit (CRU)
inside the test equipment. CRU bandwidth and detailed measurement procedure are described in the UHS-II Test
Guidelines document.
Note 5 : D0/D1 jitter for Host Tx is measured related to RCLK using a 2nd order soft PLL with BW of 2.34MHz/Sf inside
the test equipment. Detailed measurement procedure is described in the UHS-II Test Guidelines document.
Figure 4-7: Eye-mask Templates (Range C)
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Host Compliance test environment
Device Compliance test environment
Tx
350
0.55UI
60
0
-60
Tx
Differential Swing [mV]
0.6UI
90
0
-90
(3) Eye-mask for Device Receiver at TP2
(2) Eye-mask for Host Transmitter at TP2
Differential Swing [mV]
Differential Swing [mV]
(1) Eye-mask for Host Transmitter at TP1
0.5UI
45
0
-45
Rx
-350
0
0.2
0.5
Unit Interval [UI]
0.8
0
0.225
0
0.5
0.775
Unit Interval [UI]
0.25
0.5
0.75
Unit Interval [UI]
Eye-mask at TP1 is design guide
Card Test Fixture PCB
Host
RCLK
Host Test Fixture PCB
LSI
RCLK
LSI
Tx
D0
Rx
D0
Tx
Rx
PCB
D1
UHS-II SD Card
Socket
D1
Socket
Host PCB
TP2
TP1
TP2
40
0
-40
Rx
0.55UI
60
0
-60
Rx
Differential Swing [mV]
0.5UI
(4) Eye-mask for Device Transmitter at TP2
(5) Eye-mask for Host Receiver at TP2
Differential Swing [mV]
Differential Swing [mV]
(6) Eye-mask for Host Receiver at TP1
300
0.6UI
80
0
-80
Tx
-300
0
706
707
708
709
710
711
712
713
714
715
716
717
718
0.25
0.5
0.75
Unit Interval [UI]
0
0.225
0.5
0.775
Unit Interval [UI]
0
0.2
0.5
Unit Interval [UI]
0.8
Eye-mask at TP1 is design guide
Note 1 : In case of Host LSI and embedded device connection, the same Eye-mask templates are applied respectively.
Note 2 : For eye testing De-embedding of the test fixture should be performed. More details in UHS-II Test Guidelines document.
Note 3 : RLCK shall be used as reference when testing downstream (host transmitter) eye diagram.
Details are defined in UHS-II Test Guidelines document.
Note 4 : Eye diagram for upstream (Device transmitter) is measured related to itself using a Clock Recovery Unit (CRU)
inside the test equipment. CRU bandwidth and detailed measurement procedure are described in the UHS-II Test
Guidelines document.
Note 5 : D0/D1 jitter for Host Tx is measured related to RCLK using a 2nd order soft PLL with BW of 2.34MHz/Sf inside
the test equipment. Detailed measurement procedure is described in the UHS-II Test Guidelines document.
Figure 4-8: Eye-mask Templates (Range D)
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719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
4.3.4 Jitter
The relation between eye-opening and total jitter is defined by Eye Opening = 1UI- T J. The more jitter is,
the less eye opens. Thus, for ensuring the interconnection between Host and Device, jitter specification
shall be adhered for each differential Lane: RCLK, D0 and D1.
Total Jitter TJ consists of two jitter components: deterministic peak to peak jitter DJ and random root
mean square jitter RJ-rms.
Total Jitter TJ is calculated by the following equation:
TJ =DJ + Q ⋅ RJ _ rms
Where, Q factor is related to Bit error rate (BER). In UHS-II, BER performance of PHY shall be achieved
by 10-12, when Q is 14.1.
The DJ contains two elements DJ(ISI) which is the deterministic jitter caused by ISI and SJ which is a
sinusoidal jitter component.
Test pattern, jitter element budgeting and jitter injection method is specified in UHS-II PHY Test
Guidelines document.
4.3.4.1 Downstream Jitter
Generally speaking about tendency of PLL, low frequency jitter tends to go through PLL more than high
frequency jitter. RCLK and D0 (also D1 when it is used as downstream) may have a lot of low frequency
jitter.
But in case that Host and Device are connected as point to point topology, RCLK and D0 transmitted by
the Host are coherent transfer system. In such a system both RCLK and D0 may have the same
correlative jitter and no relative jitter between RCLK and D0. This correlative jitter is invisible for Device
Rx data recovery function within Device Rx PLL BW.
On the other hand, in case of Ring topology (especially Device #2 or latter Device), RCLK is provided
from Host directly and D0 is provided from adjacent Device in the Ring. Thus, Device receiver will see
uncorrelated low frequency jitter (non-coherent transfer system).
Taking in account the two cases above, the jitter tolerance specification of a Device receiver is defined
at Figure 4-9(1) as relative to RCLK. To follow the non-coherent transfer system, Device receiver shall
comply with Figure 4-9(1).
This Downstream jitter specification for Device receiver is applied not only for Device D0 but also for
Device D1 when it is used as Device Rx.
For the RCLK jitter specification is defined at Table 4-7, Table 4-9 and Table E-2.
Notes:
• It is recommended that Device data recovery function has wider bandwidth than Device Rx PLL.
• Device Rx PLL should be at least 2nd order.
• Effective minimum BW of Device Rx (PLL and CDR) should be 2.34MHz/Sf.
• Device designer should take in account the influence of SSC on Rx PLL, data recovery function
and Device Tx. For example: Certain amount of additional jitter is expected to appear on Device
Rx PLL output, depending upon PLL design.
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770
771
772
773
774
775
776
777
778
779
780
781
782
4.3.4.2 Upstream Jitter
RCLK is generated by a PLL in the Host, D1 (also D0 when it is used as upstream) is generated by
another PLL in a Device. Thus, a Host receiver will see the uncorrelated low frequency jitter. It is the
same condition as Downstream Jitter of Ring topology above. The jitter tolerance specification of a Host
receiver is defined as Figure 4-9(2). Host receiver shall comply with Figure 4-9(2).
The data recovery circuit in the Host receiver shall be designed to follow this non-coherent transfer
system.
This Upstream jitter specification for Host is applied not only for Host D1 but also for Host D0 when it is
used as Host Rx.
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Host Compliance test environment
Device Compliance test environment
(1)Jitter Tolerance for Device Receiver at TP2
Host
Host Test Fixture PCB
TJ ptp = SJ_ptp + DJ(ISI)_ptp + Q*RJ_rms
RCLK
LSI
Jitter Components (ptp) [UI]
D0
D1
Socket
Host PCB
TP1
TP2
-20dB/decade
DJ(ISI) and Q*RJ_rms
SJ
234K
S
2.34M
S
RLCK
Frequency
Frequency [Hz]
(2)Jitter Tolerance for Host Receiver at TP2
Frequency [Hz]
TJ ptp [UI]
SJ ptp [UI]
Range A~C Range D
Jitter Components (ptp) [UI]
TJ ptp = SJ_ptp + DJ(ISI)_ptp + Q*RJ_rms
234K
Sf
2.34M
Sf
1.3
1.4
1.0
0.4
0.5
0.1
RLCK Frequency
0.4
0.5
0.1
-20dB/decade
D0 to RCLK Relative jitter
DJ(ISI) and Q*RJ_rms
Card Test Fixture PCB
SJ
234K
S
2.34M
S
RCLK
RLCK
Frequency
Frequency [Hz]
D0
Frequency [Hz]
TJ ptp [UI]
LSI
SJ ptp [UI]
PCB
UHS-II SD Card
Range A~C Range D
234K
Sf
2.34M
Sf
1.3
1.35
1.0
0.4
0.45
0.1
RLCK Frequency
0.4
0.45
0.1
Socket
D1
TP2
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
Note 1 : The graphs above shows each Jitter components for indicating the concept of Total Jitter budgeting. Refer to the UHS-II
PHY Test Guidelines document for more details.
1.56
Note 2 : Scaling factor: �� =
actual data rate [Gbps]
Note 3 : RLCK shall be used as reference when testing downstream (host transmitter) jitter. Details are defined in the UHS-II PHY
Test Guidelines document.
Note 4 : In Jitter tolerance curves of (1) and (2) above, SJ slope at low jitter frequencies is equal to -20dB/decade.
Note 5 : Regarding PHY testing, Rx will be tested with less jitter budget and different jitter cocktail than that of Addendum due to
the test equipment's limitation. Refer to the UHS-II PHY Test Guideline document for more details.
Figure 4-9: Jitter Tolerance Specification
4.3.5 Return Loss
The mismatch and unbalance of impedance between the components which form transmission Line
causes the signal reflection. Signal reflection contributes to the degradation of signal integrity and EMI.
The return loss limits (differential return loss, common-mode return loss and common-to-differential
return loss) are defined in UHS-II specification for keeping signal integrity and EMI mitigation.
Both transmitter and receiver shall comply with the return loss specification. When 2L-HD mode is
supported, each port is bi-directional, thus return loss specification are applied for transmitter and
receiver respectively.
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804
805
806
807
808
809
The return loss is defined as the ratio of reflected power to incident power, and measured by using Test
fixtures (Refer to Appendix C). The characteristic impedances of the Test Fixtures (mean differential
impedance and common-mode impedance) are reference values for the return loss measurement. For
Return Loss testing, De-embedding of the test fixture should be performed.
The detailed measurement method is described in UHS-II PHY Test Guidelines document.
810
811
812
813
814
4.3.5.1 Differential Mode Return Loss
The differential return loss RLDD is the ratio of differential mode reflection power to differential mode
incident power. It is defined as following:
815
816
817
818
819
RLDD =20 * log10 S DD11
Figure 4-10 is the RLDD template and the detail limit level for Device. This is applied both for transmitter
and receiver of Device. The return loss of Device shall not exceed the limit.
Frequency [MHz]
RLDD [dB]
39
-14
120
-14
800
-7
2000
-2
5460
-2
Note 1: For Device supporting up to Range B, the maximum frequency of the RLDD is 2.4GHz.
For Device supporting up to Range D, the maximum frequency of the RLDD is 5.46GHz.
820
821
822
823
Figure 4-10: Differential Mode Return Loss (RLDD) Template for Device
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Figure 4-11 and Figure 4-12 are the RLDD templates and the detail limit levels for Host. Figure 4-11 is for
Host supporting up to Range B. Figure 4-12 is for Host supporting up to Range C or D. The frequency
range depends on Host's own maximum bit rate because Host may operate on specific bit rates, means
it is not necessary to operate on the maximum bit rate of UHS-II.
These are applied both for transmitter and receiver of Host. The return loss of Host shall not exceed the
limit.
Applied for 390Mbps operation Host
Applied for 1.56Gbps operation Host
Frequency [MHz]
156
Sf
800
Sf
2400
Sf
RLDD [dB]
-11
-4
-4
1.56
Scaling factor : Sf =
actual data rate [Gbps]
Note 1: Host shall comply with a RLDD mask specified by scaling factor Sf.
Note 2: For designing Device Receiver supporting up to Range B, only the Host RLDD mask with
Sf=1 should be taken in account.
833
834
835
836
837
838
Figure 4-11: Differential Mode Return Loss (RLDD) Template for Host supporting up to Range B
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Frequency [MHz]
156
800
2400
5460
RLDD [dB]
-11
-4
-4
-2
Note 1: A specific frequency range of the RLDD Mask is calculated by the Host’s operating bitrate.
-In case Host operates up to Range C:
The frequency range is from 0.1*Bitrate_min to 1.5*Bitrate_max,
- In case Host operates up to Range D:
The frequency range is from 0.1*Bitrate_min to 0.875*Bitrate_max
where, Bitrate_min and Bitrate_max mean minimum and maximum operating bitrate respectively
at the Range.
Example.1) Host operates on 2.5Gbps and 3.12Gbps Range C and doesn't support
Range D, the RLDD range is from 250MHz (= 0.1*2.5G) to 4.68GHz (= 1.5*3.12G).
Example.2) Host operates on 3.0Gbps Range C and 6.0Gbps Range D, the RLDD range is
from 300MHz (= 0.1*3.0G) to 5.25GHz (= 0.875*6.0G)
839
840
841
842
843
Note 2: For designing Device Receiver Supporting Range D, Host Return Loss up to 5.46GHz
should be taken into account.
Figure 4-12: Differential Mode Return Loss (RLDD) Template for Host supporting up to Range C
or D
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4.3.5.2 Common-mode Return Loss
The common-mode return loss RLCC is the ratio of common-mode reflection power to common-mode
incident power. It is defined as following:
RLCC =20 * log10 S CC11
Figure 4-13 is the RLCC template and the detail limit level. This is applied both for transmitter and
receiver. The return loss of Device and Host shall not exceed the limit.
Note: Some Hosts using common-mode filter to prevent EMI will not comply with the RLCC limit level.
These Hosts shall be the only allowable exception. In this case special compliance conditions are
defined. More details in UHS-II PHY Test Guidelines document.
Frequency [MHz]
RLCC [dB]
320
-7
800
-7
2000
-1
2400
-1
5460
0
Note 1: The maximum frequency of Device RLCC depends on the range supported by Device.
- In case Device supports up to Range B (gen.1 Device), the frequency is 2.4GHz.
- In case Device supports up to Range D (gen.2 Device), the frequency is 5.46GHz.
857
858
859
860
861
862
The maximum frequency of Host RLCC Mask is calculated by the Host maximum bitrate.
- In case Host operates up to Range C, the frequency is 1.5*Bitratemax.
- In case Host operates up to Range D, the frequency is 0.875*Bitratemax.
(Bitratemax means the Host maximum operating bitrate)
Figure 4-13: Common-mode Return Loss (RLCC) Template for Host/Device
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4.3.5.3 Common-to-Differential Return Loss (Impedance Balance)
The common-to-differential return loss (Impedance Balance) RLDC is the ratio of common-mode incident
power to differential-mode reflected power. It is defined as following:
RLDC =20 * log10 S DC11
Figure 4-14 is the RLDC template and the detail limit level. This is applied both for transmitter and
receiver. The return loss of Device and Host shall not exceed the limit.
Frequency [MHz]
RLDC [dB]
39 2400
-28
-20
5460
-15
Note 1: The maximum frequency of Device RLDC depends on the range supported by Device.
- In case Device supports up to Range B (gen.1 Device), the frequency is 2.4GHz.
- In case Device supports up to Range D (gen.2 Device), the frequency is 5.46GHz.
871
872
873
874
875
876
877
The maximum frequency of Host RLDC Mask is calculated by the Host maximum bitrate.
- In case Host operates up to Range C, the frequency is 1.5*Bitratemax.
- In case Host operates up to Range D, the frequency is 0.875*Bitratemax.
(Bitratemax means the Host maximum operating bitrate)
Figure 4-14: Common-to-Differential Return Loss (RLDC) Template for Host/Device
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4.3.6 Line States
UHS-II has the following 4 Line states:
-
DIF-H denotes differential high state. That means the positive terminal of Tx outputs is at high level,
and the negative terminal of Tx outputs is low level.
DIF-L denotes differential low state. That means the positive terminal of Tx outputs is at low level,
and the negative terminal of Tx outputs is at high level.
DIF-PD denotes Pull down state. Both single-ended voltage levels of a differential Line (VDp and
VDn) are pulled down to VCM_PD by TX.
DIF-Z denotes High-Z (high impedance). Tx becomes High-Z.
Transmission
Line Status
Differential High
Symbol
Signal Levels
Condition of application
DIF-H
-Active-state
Differential Low
DIF-L
Pull down
DIF-PD
VDp = VDH
VDn = VDL
VDp = VDL
VDn = VDH
VDp = VDn =VCM_PD
Hi-Z
DIF-Z
Floating
-2L-HD switching
Remarks
-Active-state
-EIDL state
Table 4-12: Line States
4.3.7 Host Power Delivery Network Model
The Host power delivery model for VDD1 and VDD2 domains is defined in Figure 4-15.
UHS-II Host Power Delivery Model
Socket
VDD1
((
))
Rs, Ls
CH1
Rs, Ls
Rs+i∙Ls
Rs+i∙Ls
VSS
CH2
VDD2
((
))
898
899
900
901
902
Rs, Ls
TP2
Figure 4-15: Power Delivery Network for VDD1 and VDD2 Domains
RS, LS - Resistance/Inductance of each contact pin of the UHS-II Socket.
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906
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911
912
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914
915
916
917
918
919
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921
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923
924
925
926
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930
931
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933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
Refer to mechanical addendum for detailed definition.
CH1, CH2 - Decoupling capacitors adjacent to the UHS-II Socket.
Note 1: It is mandatory for Host to place CH1 and CH2 adjacent to the socket pins as shown in Figure
4-15, for each power domain (VDD1, VDD2). Otherwise Host may fail interoperability with
Device. Sum of equivalent series inductance (ESL) of these capacitors and inductance of their
connection to the socket should be negligible value than LS. (Less than Ls/10)
Note 2: The Host Power Delivery Network Model described in Figure4-12 is condition for Device
Receiver and Transmitter functionality. In other conditions Device circuitry may not perform
properly.
Note 3: Properties of the CH1 and CH2 Capacitors:
• Minimum value is 1[uF] (nominal value)
• Capacitor such as MLCC X5R/X7R with low equivalent series resistance (ESR) and low
equivalent series inductance (ESL). Any size of capacitor may be used (0201, 0402, 0603...), as
long as it is not too big to be located very close to socket pins.
• Should be allocated adjacent to UHS-II socket.
Application Note:
The capacitors configuration may be improved to give better noise rejection properties per Host
designer consideration. Additionally Host may chose to add more capacitors to support hot-insertion,
for voltage stabilization or any other reason. Refer to Appendix E of the Physical Layer Version 4.00
or later for more information.
4.4 EIDL State
When recovering from EIDL state, Amplitude Detector is used for detecting the voltage level of
differential transmission Line, making receiver waked up and informs link layer that the differential Lane
gets out of EIDL state.
Device D0 receiver, and Host D1 receiver have Amplitude Detector (mandatory for Device D0 receiver;
optional for Host D1 receiver), as shown in Figure 4-2
During EIDL state, the state of the differential Line is settled to DIF-PD as shown Figure 4-16 as
measured in receiver side.
During Dormant state, Host may settle the RCLK Lane to DIF-PD (Refer to the timing diagram Figure 523 in Protocol specification).
When getting out of EIDL state, the driver of the differential Lane (means D0 driver of Host or D1 driver
of Device) shall settle the differential voltage from DIF-PD to DIF-L within the period (a) of Figure 4-16,
and then transmits DIF-L during the STB.L period; (b) of Figure 4-16 for the detection by the Rx
Amplitude Detector.
The Rx Amplitude Detector shall detect the 95mV STB.L as minimumwithin the period (b) of Figure 4-16
at any Range (ex. 90mV as Detection threshold of Amplitude Detector is recommended, though it's
implementation specific).
When the detection occurs, the high speed receivers are waked up and the link layer is being notified
for EIDL recovery.
To increase the noise immunity, it is recommended to implement the Amplitude Detector with hysteresis.
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967
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969
970
971
972
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975
When entering EIDL state, the driver of the differential Lane shall drive the differential voltage to DIF-H
and then drive to DIF-PD controlled by Link layer. The Rx Amplitude Detector shall be masked before
Rx transit to EIDL state (mean until the end of T_EIDL_GAP) and unmasked afterwards (refer to Figure
5-26 for further details).
Regarding the Power Management including EIDL state, refer to Section 5.4.
Notes:
1. On performing a compliance test, test equipment may have a difficulty to keep the defined timing
where state transition occurs from and to EIDL state. In this case, the test equipment may provide a
lane with Vcm level on Device test or Vcm_source level on Host test, instead of DIF_PD for EIDL.
Vdp and Vdn may vary within defined VCM or VCM_source variation and |VDp-VDn| shall be less than or
equal to Vdiff_PD.
Amplitude Detector shall function properly with defined performance when detecting the transition
from VCM (VCM_source) to STB.L.
This condition is only valid for compliance testing.
2.
In addition to input signals complying with the specification, it should be assumed the existence of
CM noise caused inside of Device depends on implementation. Since the CM noise may affect
Amplitude Detector, it is recommended to follow the design guidelines in Appendix E.2.3
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T1 T2
V
T3 T4
T5
T8
T_EIDL_ENTRY T_EIDL_GAP
T_EIDL_RECOVERY
(a)
T7
T6
(a)
(b)
Vdh
Vcm
STB.L
SYN
PACKET
STB.H
Vdl
0
VPD
time
|VDP-VDN|
90mV
Detector Threshold (Implementation Specific)
976
977
978
979
(a) Driver Enabling / Disabling Period (max)
A,B
2
Range
C
4
D
8
(b) Stable STB.L Duration for detection (min)
14
28
56
T_EIDL_RECOVERY (min)
16
32
64
T_EIDL_ENTRY (min)
4
8
16
T_EIDL_GAP (min)
8
16
32
Unit
SI
Figure 4-16: Line States and Timing in the Recovery from EIDL State and in EIDL Entry
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983
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985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
4.5 Symbol Coding
UHS-II interface uses an 8b/10b transmission code in valid symbol transfer. The 8b/10b coding rule and
the detail calculation method of Running Disparity (RD) refers to ANSI X3, 230-1994, clause 11 (and
also IEEE 802.3z, 36.2.4)
As shown in Figure 4-17, 8-bit data characters ("HGFEDCBA") are treated as 3 bits ("HGF") and 5 bits
("EDCBA"), which are mapped onto a 4-bit code group ("jhgf") and a 6-bit code group ("iedcba"),
respectively. The control bit in conjunction with the 8-bit data characters is used to indicate whether the
transmission symbol is a Data symbol (D) or a Control symbol (K). After the mapping, bit "a" shall be
transmitted first, followed by bits "b", "c", "d", "e", "i", "f", "g", "h" and "j" in that order. (Refer to Section
5.2.7 for related description.)
Table 4-13 to Table 4-16 show the valid translation tables between 8-bit data characters and 10-bit
symbols. These tables shall be used for both 8-bit to 10-bit encoding at transmitter and 10-bit to 8-bit
decoding at receiver.
The symbol K28.5 is treated as the comma (delimiter) symbol, which is used for symbol lock (or re-lock)
of Deserializer for the Receiver side when symbol lock is unlocked. (Refer to Section 5.2.2.2). And also,
the comma symbol is used for initialization (or re-initialization) of RD value when RD becomes incorrect
value by some kind of reason.
Regarding the handling for Symbol coding errors (8b/10b decode error and 8b/10b disparity error), refer
to Section 5.2.8.3.
Note: during the period of not transferring valid symbol (such as exiting EIDL state and so on),
Fixed Low (continuous DIF-L), Fixed High (continuous DIF-H) and Fixed Pull-down (continuous
DIF-PD) are transmitted on UHS-II interface. (Refer to Section 5.2.8.1 for more details including
other Lane states)
Tx side
MSb
Rx side
Control
bit(K/D)
LSb
MSb
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
H
H
G
F
E
D
C
B
A
G
F
E
8b to 10b Enc
10b to 8b Dec
Last
Transmitted bit
1012
1013
1014
1015
i
e
d
A
10bits
c
LSb
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
f
B
MSb
LSb
g
C
8bits
10bits
h
D
8bits
MSb
j
Control
bit(K/D)
LSb
a
j
First
Transmitted bit
Last
Received bit
b
h
g
f
i
e
d
c
b
a
First
Received bit
Figure 4-17: Diagram of Symbol Coding
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8bit data
characters
1016
1017
8bit data
characters
10bit data symbol
Current RDName HGF EDCBA abcdei fghj
D0.0 000 00000 100111 0100
D1.0 000 00001 011101 0100
D2.0 000 00010 101101 0100
D3.0 000 00011 110001 1011
D4.0 000 00100 110101 0100
D5.0 000 00101 101001 1011
D6.0 000 00110 011001 1011
D7.0 000 00111 111000 1011
D8.0 000 01000 111001 0100
D9.0 000 01001 100101 1011
D10.0 000 01010 010101 1011
D11.0 000 01011 110100 1011
D12.0 000 01100 001101 1011
D13.0 000 01101 101100 1011
D14.0 000 01110 011100 1011
D15.0 000 01111 010111 0100
D16.0 000 10000 011011 0100
D17.0 000 10001 100011 1011
D18.0 000 10010 010011 1011
D19.0 000 10011 110010 1011
D20.0 000 10100 001011 1011
D21.0 000 10101 101010 1011
D22.0 000 10110 011010 1011
D23.0 000 10111 111010 0100
D24.0 000 11000 110011 0100
D25.0 000 11001 100110 1011
D26.0 000 11010 010110 1011
D27.0 000 11011 110110 0100
D28.0 000 11100 001110 1011
D29.0 000 11101 101110 0100
D30.0 000 11110 011110 0100
D31.0 000 11111 101011 0100
D0.1 001 00000 100111 1001
D1.1 001 00001 011101 1001
D2.1 001 00010 101101 1001
D3.1 001 00011 110001 1001
D4.1 001 00100 110101 1001
D5.1 001 00101 101001 1001
D6.1 001 00110 011001 1001
D7.1 001 00111 111000 1001
D8.1 001 01000 111001 1001
D9.1 001 01001 100101 1001
D10.1 001 01010 010101 1001
D11.1 001 01011 110100 1001
D12.1 001 01100 001101 1001
D13.1 001 01101 101100 1001
D14.1 001 01110 011100 1001
D15.1 001 01111 010111 1001
Current RD+
abcdei fghj
011000 1011
100010 1011
010010 1011
110001 0100
001010 1011
101001 0100
011001 0100
000111 0100
000110 1011
100101 0100
010101 0100
110100 0100
001101 0100
101100 0100
011100 0100
101000 1011
100100 1011
100011 0100
010011 0100
110010 0100
001011 0100
101010 0100
011010 0100
000101 1011
001100 1011
100110 0100
010110 0100
001001 1011
001110 0100
010001 1011
100001 1011
010100 1011
011000 1001
100010 1001
010010 1001
110001 1001
001010 1001
101001 1001
011001 1001
000111 1001
000110 1001
100101 1001
010101 1001
110100 1001
001101 1001
101100 1001
011100 1001
101000 1001
10bit data symbol
Current RDName HGF EDCBA abcdei fghj
D16.1 001 10000 011011 1001
D17.1 001 10001 100011 1001
D18.1 001 10010 010011 1001
D19.1 001 10011 110010 1001
D20.1 001 10100 001011 1001
D21.1 001 10101 101010 1001
D22.1 001 10110 011010 1001
D23.1 001 10111 111010 1001
D24.1 001 11000 110011 1001
D25.1 001 11001 100110 1001
D26.1 001 11010 010110 1001
D27.1 001 11011 110110 1001
D28.1 001 11100 001110 1001
D29.1 001 11101 101110 1001
D30.1 001 11110 011110 1001
D31.1 001 11111 101011 1001
D0.2 010 00000 100111 0101
D1.2 010 00001 011101 0101
D2.2 010 00010 101101 0101
D3.2 010 00011 110001 0101
D4.2 010 00100 110101 0101
D5.2 010 00101 101001 0101
D6.2 010 00110 011001 0101
D7.2 010 00111 111000 0101
D8.2 010 01000 111001 0101
D9.2 010 01001 100101 0101
D10.2 010 01010 010101 0101
D11.2 010 01011 110100 0101
D12.2 010 01100 001101 0101
D13.2 010 01101 101100 0101
D14.2 010 01110 011100 0101
D15.2 010 01111 010111 0101
D16.2 010 10000 011011 0101
D17.2 010 10001 100011 0101
D18.2 010 10010 010011 0101
D19.2 010 10011 110010 0101
D20.2 010 10100 001011 0101
D21.2 010 10101 101010 0101
D22.2 010 10110 011010 0101
D23.2 010 10111 111010 0101
D24.2 010 11000 110011 0101
D25.2 010 11001 100110 0101
D26.2 010 11010 010110 0101
D27.2 010 11011 110110 0101
D28.2 010 11100 001110 0101
D29.2 010 11101 101110 0101
D30.2 010 11110 011110 0101
D31.2 010 11111 101011 0101
Current RD+
abcdei fghj
100100 1001
100011 1001
010011 1001
110010 1001
001011 1001
101010 1001
011010 1001
000101 1001
001100 1001
100110 1001
010110 1001
001001 1001
001110 1001
010001 1001
100001 1001
010100 1001
011000 0101
100010 0101
010010 0101
110001 0101
001010 0101
101001 0101
011001 0101
000111 0101
000110 0101
100101 0101
010101 0101
110100 0101
001101 0101
101100 0101
011100 0101
101000 0101
100100 0101
100011 0101
010011 0101
110010 0101
001011 0101
101010 0101
011010 0101
000101 0101
001100 0101
100110 0101
010110 0101
001001 0101
001110 0101
010001 0101
100001 0101
010100 0101
Table 4-13: Data Symbol 8b/10b Coding Table
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8bit data
characters
1018
1019
8bit data
characters
10bit data symbol
Current RDName HGF EDCBA abcdei fghj
D0.3 011 00000 100111 0011
D1.3 011 00001 011101 0011
D2.3 011 00010 101101 0011
D3.3 011 00011 110001 1100
D4.3 011 00100 110101 0011
D5.3 011 00101 101001 1100
D6.3 011 00110 011001 1100
D7.3 011 00111 111000 1100
D8.3 011 01000 111001 0011
D9.3 011 01001 100101 1100
D10.3 011 01010 010101 1100
D11.3 011 01011 110100 1100
D12.3 011 01100 001101 1100
D13.3 011 01101 101100 1100
D14.3 011 01110 011100 1100
D15.3 011 01111 010111 0011
D16.3 011 10000 011011 0011
D17.3 011 10001 100011 1100
D18.3 011 10010 010011 1100
D19.3 011 10011 110010 1100
D20.3 011 10100 001011 1100
D21.3 011 10101 101010 1100
D22.3 011 10110 011010 1100
D23.3 011 10111 111010 0011
D24.3 011 11000 110011 0011'
D25.3 011 11001 100110 1100
D26.3 011 11010 010110 1100
D27.3 011 11011 110110 0011
D28.3 011 11100 001110 1100
D29.3 011 11101 101110 0011
D30.3 011 11110 011110 0011
D31.3 011 11111 101011 0011
D0.4 100 00000 100111 0010
D1.4 100 00001 011101 0010
D2.4 100 00010 101101 0010
D3.4 100 00011 110001 1101
D4.4 100 00100 110101 0010
D5.4 100 00101 101001 1101
D6.4 100 00110 011001 1101
D7.4 100 00111 111000 1101
D8.4 100 01000 111001 0010
D9.4 100 01001 100101 1101
D10.4 100 01010 010101 1101
D11.4 100 01011 110100 1101
D12.4 100 01100 001101 1101
D13.4 100 01101 101100 1101
D14.4 100 01110 011100 1101
D15.4 100 01111 010111 0010
Current RD+
abcdei fghj
011000 1100
100010 1100
010010 1100
110001 0011
001010 1100
101001 0011
011001 0011
000111 0011
000110 1100
100101 0011
010101 0011
110100 0011
001101 0011
101100 0011
011100 0011
101000 1100
100100 1100
100011 0011
010011 0011
110010 0011
001011 0011
101010 0011
011010 0011
000101 1100
001100 1100
100110 0011
010110 0011
001001 1100
001110 0011
010001 1100
100001 1100
010100 1100
011000 1101
100010 1101
010010 1101
110001 0010
001010 1101
101001 0010
011001 0010
000111 0010
000110 1101
100101 0010
010101 0010
110100 0010
001101 0010
101100 0010
011100 0010
101000 1101
10bit data symbol
Current RDName HGF EDCBA abcdei fghj
D16.4 100 10000 011011 0010
D17.4 100 10001 100011 1101
D18.4 100 10010 010011 1101
D19.4 100 10011 110010 1101
D20.4 100 10100 001011 1101
D21.4 100 10101 101010 1101
D22.4 100 10110 011010 1101
D23.4 100 10111 111010 0010
D24.4 100 11000 110011 0010
D25.4 100 11001 100110 1101
D26.4 100 11010 010110 1101
D27.4 100 11011 110110 0010
D28.4 100 11100 001110 1101
D29.4 100 11101 101110 0010
D30.4 100 11110 011110 0010
D31.4 100 11111 101011 0010
D0.5 101 00000 100111 1010
D1.5 101 00001 011101 1010
D2.5 101 00010 101101 1010
D3.5 101 00011 110001 1010
D4.5 101 00100 110101 1010
D5.5 101 00101 101001 1010
D6.5 101 00110 011001 1010
D7.5 101 00111 111000 1010
D8.5 101 01000 111001 1010
D9.5 101 01001 100101 1010
D10.5 101 01010 010101 1010
D11.5 101 01011 110100 1010
D12.5 101 01100 001101 1010
D13.5 101 01101 101100 1010
D14.5 101 01110 011100 1010
D15.5 101 01111 010111 1010
D16.5 101 10000 011011 1010
D17.5 101 10001 100011 1010
D18.5 101 10010 010011 1010
D19.5 101 10011 110010 1010
D20.5 101 10100 001011 1010
D21.5 101 10101 101010 1010
D22.5 101 10110 011010 1010
D23.5 101 10111 111010 1010
D24.5 101 11000 110011 1010
D25.5 101 11001 100110 1010
D26.5 101 11010 010110 1010
D27.5 101 11011 110110 1010
D28.5 101 11100 001110 1010
D29.5 101 11101 101110 1010
D30.5 101 11110 011110 1010
D31.5 101 11111 101011 1010
Current RD+
abcdei fghj
100100 1101
100011 0010
010011 0010
110010 0010
001011 0010
101010 0010
011010 0010
000101 1101
001100 1101
100110 0010
010110 0010
001001 1101
001110 0010
010001 1101
100001 1101
010100 1101
011000 1010
100010 1010
010010 1010
110001 1010
001010 1010
101001 1010
011001 1010
000111 1010
000110 1010
100101 1010
010101 1010
110100 1010
001101 1010
101100 1010
011100 1010
101000 1010
100100 1010
100011 1010
010011 1010
110010 1010
001011 1010
101010 1010
011010 1010
000101 1010
001100 1010
100110 1010
010110 1010
001001 1010
001110 1010
010001 1010
100001 1010
010100 1010
Table 4-14: Data Symbol 8b/10b Coding Table (cont.)
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8bit data
characters
1020
1021
1022
1023
1024
8bit data
characters
10bit data symbol
Current RDName HGF EDCBA abcdei fghj
D0.6 110 00000 100111 0110
D1.6 110 00001 011101 0110
D2.6 110 00010 101101 0110
D3.6 110 00011 110001 0110
D4.6 110 00100 110101 0110
D5.6 110 00101 101001 0110
D6.6 110 00110 011001 0110
D7.6 110 00111 111000 0110
D8.6 110 01000 111001 0110
D9.6 110 01001 100101 0110
D10.6 110 01010 010101 0110
D11.6 110 01011 110100 0110
D12.6 110 01100 001101 0110
D13.6 110 01101 101100 0110
D14.6 110 01110 011100 0110
D15.6 110 01111 010111 0110
D16.6 110 10000 011011 0110
D17.6 110 10001 100011 0110
D18.6 110 10010 010011 0110
D19.6 110 10011 110010 0110
D20.6 110 10100 001011 0110
D21.6 110 10101 101010 0110
D22.6 110 10110 011010 0110
D23.6 110 10111 111010 0110
D24.6 110 11000 110011 0110
D25.6 110 11001 100110 0110
D26.6 110 11010 010110 0110
D27.6 110 11011 110110 0110
D28.6 110 11100 001110 0110
D29.6 110 11101 101110 0110
D30.6 110 11110 011110 0110
D31.6 110 11111 101011 0110
Current RD+
abcdei fghj
011000 0110
100010 0110
010010 0110
110001 0110
001010 0110
101001 0110
011001 0110
000111 0110
000110 0110
100101 0110
010101 0110
110100 0110
001101 0110
101100 0110
011100 0110
101000 0110
100100 0110
100011 0110
010011 0110
110010 0110
001011 0110
101010 0110
011010 0110
000101 0110
001100 0110
100110 0110
010110 0110
001001 0110
001110 0110
010001 0110
100001 0110
010100 0110
10bit data symbol
Current RDName HGF EDCBA abcdei fghj
D0.7 111 00000 100111 0001
D1.7 111 00001 011101 0001
D2.7 111 00010 101101 0001
D3.7 111 00011 110001 1110
D4.7 111 00100 110101 0001
D5.7 111 00101 101001 1110
D6.7 111 00110 011001 1110
D7.7 111 00111 111000 1110
D8.7 111 01000 111001 0001
D9.7 111 01001 100101 1110
D10.7 111 01010 010101 1110
D11.7 111 01011 110100 1110
D12.7 111 01100 001101 1110
D13.7 111 01101 101100 1110
D14.7 111 01110 011100 1110
D15.7 111 01111 010111 0001
D16.7 111 10000 011011 0001
D17.7 111 10001 100011 0111
D18.7 111 10010 010011 0111
D19.7 111 10011 110010 1110
D20.7 111 10100 001011 0111
D21.7 111 10101 101010 1110
D22.7 111 10110 011010 1110
D23.7 111 10111 111010 0001
D24.7 111 11000 110011 0001
D25.7 111 11001 100110 1110
D26.7 111 11010 010110 1110
D27.7 111 11011 110110 0001
D28.7 111 11100 001110 1110
D29.7 111 11101 101110 0001
D30.7 111 11110 011110 0001
D31.7 111 11111 101011 0001
Current RD+
abcdei fghj
011000 1110
100010 1110
010010 1110
110001 0001
001010 1110
101001 0001
011001 0001
000111 0001
000110 1110
100101 0001
010101 0001
110100 1000
001101 0001
101100 1000
011100 1000
101000 1110
100100 1110
100011 0001
010011 0001
110010 0001
001011 0001
101010 0001
011010 0001
000101 1110
001100 1110
100110 0001
010110 0001
001001 1110
001110 0001
010001 1110
100001 1110
010100 1110
Table 4-15: Data Symbol 8b/10b Coding Table (cont.)
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8bit control
characters
Comma Symbol
1025
1026
1027
10bit control symbol
Current RDName HGF EDCBA abcdei fghj
K28.0 000 11100 001111 0100
K28.1 001 11100 001111 1001
K28.2 010 11100 001111 0101
K28.3 011 11100 001111 0011
K28.4 100 11100 001111 0010
K28.5 101 11100 001111 1010
K28.6 110 11100 001111 0110
K28.7 111 11100 001111 1000
K23.7 111 10111 111010 1000
K27.7 111 11011 110110 1000
K29.7 111 11101 101110 1000
K30.7 111 11110 011110 1000
Current RD+
abcdei fghj
110000 1011
110000 0110
110000 1010
110000 1100
110000 1101
110000 0101
110000 1001
110000 0111
000101 0111
001001 0111
010001 0111
100001 0111
Table 4-16: Control Symbol 8b/10b Coding Table
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1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
4.6 Loopback Mode
The PHY block in the Device and Host shall have loopback path that is needed for testability purposes,
and the loopback path is also used for Devices in order to perform data bypassing in ring topology
(Regarding data bypassing in Ring topology, refer to Section 5.6.3 for more details). It is expected that
loopback path will have the same clocking scheme as Tx and Rx lanes in FD mode, for both forward
and backward loopback.
The loopback causes the data that is received at the serial input of a Lane to transmit at the serial
output of another Lane after recovery. The loopback is done from the output of the de-serializer in the
receiver path, to the input of the serializer of the transmitter path, by dedicated 10 bit multiplexer in the
transmitter block. This loopback enables testing the PHY with any symbols including patterns which are
illegal for 10b/8b decoding.
In normal condition, the loopback path in the PHY of the Host is done from the D1 receiver to the D0
transmitter, as presented in Figure 4-18. This path is named "forward loopback". For testing the other
direction, which test D0 as receiver and D1 as transmitter, which are used in 2L-HD mode, there is a
need for backward loopback path, as shown in Figure 4-19.
In normal condition, the loopback path in the PHY of the Device is done from the D0 receiver to the D1
transmitter, as presented in Figure 4-20. This path is named "forward loopback". For testing the other
direction, which test D1 as receiver and D0 as transmitter, which are used in 2L-HD mode, there is a
need for backward loopback path, as shown in Figure 4-21.
The loopback modes are controlled by the LINK layer while in normal operation, while in Test mode
loopback may also be controlled internally in the PHY. Each PHY vendor may specify additional
loopback modes, but it is beyond the mandatory requirements of the standard.
D1
Data
recovery
DeSerializer
10b/8b
Decoding
LINK
8b/10b
Encoding
LINK
Forward
loopback
D0
1057
1058
1059
1060
Serializer
Figure 4-18: Location of Forward Loopback in PHY of the Host
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D1
Data
recovery
D1
DeSerializer
10b/8b
Decoding
LINK
Serializer
8b/10b
Encoding
LINK
DeSerializer
10b/8b
Decoding
LINK
Serializer
8b/10b
Encoding
LINK
Backward
loopback
D0
Data
recovery
D0
1061
1062
1063
1064
1065
Figure 4-19: Location of Backward Loopback in PHY of the Host
D0
Data
recovery
DeSerializer
10b/8b
Decoding
LINK
8b/10b
Encoding
LINK
Forward
loopback
D1
1066
1067
1068
1069
1070
Serializer
Figure 4-20: Location of Forward Loopback in PHY of the Device
D0
Data
recovery
D0
DeSerializer
10b/8b
Decoding
LINK
Serializer
8b/10b
Encoding
LINK
DeSerializer
10b/8b
Decoding
LINK
Serializer
8b/10b
Encoding
LINK
Backward
loopback
D1
D1
1071
1072
1073
Data
recovery
Figure 4-21: Location of Backward Loopback in PHY of the Device
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1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
4.7 PHY Test Mode
For the Compliance test of UHS-II PHY, Re-Sync state and following method are defined to UHS-II PHY
in order to configure PHY for the specific test condition.
In PHY Test mode, Dormant state and Re-Sync state are used in case of changing PLL multiplier.
Dormant state used in PHY Test mode is the same state as in UHS-II normal operation, which is applied
to the Rx which has Amplitude Detector (for example, Device D0.Rx), Therefore in the Dormant state
during PHY Test mode, all PHY circuitry are powered off except Amplitude Detector. When exiting
Dormant state, Amplitude Detector is used to detect STB.L.
Re-Sync state is applied to the Rx which has no Amplitude Detector (for example, Device D1.Rx). In the
Re-Sync state PHY circuitry keeps power on (except for PLL while changing its multiplier) because Rx
having no Amplitude Detector shall be able to receive symbols from Test equipment.
The difference between Dormant state and Re-Sync state is whether PHY is powered off or
still powered on. Exiting Dormant state and Re-Sync state take the same sequences (Sequence to exit
Dormant or Re-Sync; refer to Figure 4-22). When exiting these states, re-synchronization of CDR is
performed.
Items to be configured in Test mode are as follows.
• Disconnect and Normal (Non-Disconnect) mode
- Disconnect mode: Device and Host keep current test mode for any input levels.
That means Device and Host do not enter Dormant state even if it happens the
connection change between the Device/Host and test equipment.
It is possible to exit Disconnect mode by using Power cycle, or transfer to Normal
mode by using "Sequence to Set Test Mode".
- Normal (Non-Disconnect) mode: This mode is capable to enter the Dormant state.
This mode is useful to perform multiple test items automatically.
• Loop Back Direction
- Forward Loopback: Default loopback direction for all Devices and Hosts.
- Backward Loopback: Device and Host which support 2L-HD mode support
Backward Loopback.
For Detailed Definition of Loopback modes, refer to Section 4.6 Loop Back mode.
Notes:
1. To enter Backward Loopback test mode, the sequence to set Test Mode (refer to Figure
4-22) shall be provided on Device D0 Rx and Host D1 Rx.
2. To enter Forward Loopback test mode retrieved from Backward Loopback test mode, the
sequence to set Test Mode (refer to Figure 4-22) shall be provided on Device D1 Rx and
Host D0 Rx.
3. Dormant state shall be used on Device D0 Rx (Forward Loopback) for testing an Amplitude
Detector.
4. Which state Dormant or Re-sync should be used is dependent on implementation of
Amplitude Detector especially on Device D1 Rx (Backward Loopback), Host D0 Rx
(Backward Loopback) and Host D1 Rx (Forward Loopback).
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1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
5. Device and Host may transmit a few broken symbols instead of COM+SYN symbols
expected, on switching Loopback direction.
• Emphasis
Emphasis strength of Host and Device driver may be set by the test mode entry method
without setting configuration Register. Change of Emphasis strength is effective immediately.
• Range / PLL Multiplier
Range and PLL Multiplier may be set by the test mode entry method without setting
configuration Register. Change of PLL Multiplier is effective only when exiting Dormant or ReSync state.
• Future Test Mode Expandability
Additional vendor specific Test Modes may be defined.
4.7.1 The Sequences used in PHY Test Mode
Figure 4-22 shows the sequences used in PHY Test Mode. Test mode configuration is done by setting
the TMD1 and TMD2 in the symbol named "TEST-MODE" (which is constructed by COM (K28.5) + Kcode (K30.7) + TMD1 + TMD2 as described in Figure 4-22). To avoid entering a test mode by mistake,
TEST-MODE symbol is sent 4 times continuously.
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Sequence to Enter Dormant or Re-Sync
- When necessary to change PLL multiplier, this sequence is used
Dormant or Re-Sync
DIF-H
(STB.H)
Any Symbol
DIF-PD
DIF-Z
The length of DIF-Z may
be 0 if no direction
change occurs.
Test mode configurations shall be kept
internally even if UHS-II interface goes
through Dormant or Re-Sync.
Sequence to Exit Dormant or Re-Sync
- When direction is switched, started by this sequence.
- When necessary to change PLL multiplier, this sequence is used
Dormant or Re-Sync
DIF-Z
DIF-PD
DIF-L
(STB.L)
SYN
The length of DIF-Z may
be 0 if no direction
change occurs.
Sequence to Set Test Mode
- Before setting Test-Modes, re-synchronization should be performed by through Dormant or Re-Sync state.
(Not necessary for every test mode setting.)
SYN
TEST-MODE
TEST-MODE
TEST-MODE
TEST-MODE
SYN
4 times
It is necessary to enter Test mode
or change Test mode configuration.
1148
1149
1150
1151
1152
COM
(K28.5)
K-code
(K30.7)
TMD1
TMD2
Figure 4-22: Sequences used in PHY Test Mode
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1153
1154
1155
1156
1157
4.7.2 Definition of TMD1 and TMD2
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
4.7.2.1 TMD1
TMD1 is used for configuring Main mode and Sub mode.
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
4.7.2.2 TMD2
TMD2 is specified by each Main Mode.
The structure of TMD1 and TMD2 are defined as follows and in Figure 4-23. Device maintains setting of
TMD1 and TMD2 during PHY test mode until Host changes setting of TMD1 and TMD2, even if going
through Dormant or Re-Sync mode.
Upper 4-bit is used to assign Main Mode:
• 0h : assigned for Loop Back Test Modes
• Fh : assigned for vendor specific test modes (Vendor may define TMD1 and TMD2
to control vendor specific test modes)
Lower 4-bit is used to assign Sub Mode:
• "Timing"(Sub Mode 00): determines the timing when Sub-Mode 03-01 is effective.
• "Disconnect"(Sub Mode 01): determines whether Disconnected mode
or Normal (Non-Disconnect mode).
•
"Loop Back Direction"(07): determines whether Forward Loop back or Backward Loop back.
When this bit is changed, the change of Loop Back Direction is done immediately.
Everytime Loopback direction is changed, both D0 and D1 are set to input at first
in order to re-connect Test tool.
After re-connecting Test tool to Device/Host:
<In case Loop Back Direction bit is changed 0 to 1>
- After Device detects SYN from D1, D0 is enabled as output,
and then the change of Loopback direction is done.
- After Host detects SYN from D0, D1 is enabled as output,
and then the change of Loopback direction is done.
<In case Loop Back Direction bit is changed 1 to 0>
- After Device detects SYN from D0, D1 is enabled as output,
and then the change of Loopback direction is done.
- After Host detects SYN from D1, D0 is enabled as output,
and then the change of Loopback direction is done.
• "SSCE"(06): controls Host SSC On/Off if Host supports SSC function. This bit is not
effective to Device.
•
•
"Emphasis" (04-03): determines Emphasis strength of driver.
"Range / PLL Multiplier"(02-00): determines Range and PLL Multiplier. The actual change of
PLL Multiplier is done after exiting Dormant or Re-Sync state.
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TMD1
07-04
Main Mode
TMD2
03-00
Sub Mode
07-00
Specified by each Main Mode
Main Mode
0h:
Loop Back Test Modes
1h-Eh: Reserved
Fh:
Vendor Specific Test Modes
(a) General Definition
TMD1
TMD2
07-04
03-02
01
00
07
06
05
04-03
02-00
0h
00b
Disconnect
Timing
Loop Back Direction
SSCE
Rsv
Emphasis
Range / PLL Multiplier
Loop Back
Test Mode
Reserved
Disconnect
0b: Normal (Non-Disconnect) Mode
; Capable to go Dormant or
Re-Sync state
1b: Disconnect Mode
; Can’t go Dormant
Test Mode Entry Timing
0b: Effective Immediately
1b: When exiting Dormant
or Re-Sync state
Range / PLL Multiplier
000b: Range A / x15
001b: Range B / x30
010b: Range C / x60
011b: Range D / x120
100b-111b: Reserved
SSC Enable
0b: SSC Disabled
1b: SSC Enabled
Control for Host
This is effective when exiting Dormant
or Re-Sync state.
Emphasis
00b
01b
10b
11b
Range C
Range D
TxEmp0 (0dB)
TxEmpL (1.5dB)
TxEmpM (3.0dB)
TxEmpM (3.0dB) TxEmpH (4.5dB)
This is effective immediately.
Emphasis is not available for Range A/B (set to 00b).
Loop Back Direction
0b: Forward (Device: D0.Rx to D1.Tx, Host: D1.Rx to D0.Tx)
1b: Backward (Device: D1.Rx to D0.Tx, Host: D0.Rx to D1.Tx)
This is effective immediately.
Everytime Loopback direction is changed, both D0 and D1 are set to input at first in
order to re-connect Test tool.
(b) TMD1 and TMD2 Definition in Loop Back Test Mode
1200
1201
1202
1203
1204
Note: Symbols are described in 8-bit domain for the convenience of explanation. Actual symbols to enter and exit
test mode are transferred from test equipment after 8b/10b encoding.
Figure 4-23: Structure of TMD1 and TMD2
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1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
4.7.3 Test Modes
Parameters for entering each Test mode are described as follows. The sequences for entering each test
mode are shown in Figure 4-24 and Figure 4-25.
TMD1 Modes:
• 00h: Normal Mode At Once
Setting in Sub Modes 03-01(Normal Mode) is effective immediately.
After entering a test mode, it is possible to go back to Dormant state.
• 01h: Normal Mode Through Dormant state
Setting in Sub Modes 03-01(Normal Mode) is effective when exiting Dormant state.
After entering a test mode, it is possible to go back to Dormant state.
• 02h: Disconnect Mode At Once
Setting in Sub Modes 03-01 (Disconnect Mode) is effective immediately.
After entering a test mode, the Device cannot go Dormant state.
• 03h: Disconnect Mode Through Dormant state
Setting in Sub Modes 03-01 (Disconnect Mode) is effective when exiting Dormant state.
After entering a test mode, the Device cannot go Dormant state.
TMD2 Modes:
Range / PLL Multiplier (Bit 02-00)
• 000b: Range A / x15
• 001b: Range B / x30
• 010b: Range C / x60
• 011b: Range D / x120
• 100b-1111b: Reserved
Change of this field is effective when exiting Dormant or Re-Sync state. Clock frequency may
be changed only during Dormant or Re-Sync state.
Loop Back Direction (Bit 07)
• 0b: Forward Loop Back (means from D0.Rx to D1.Tx)
• 1b: Backward Loop Back (means from D1.Rx to D0.Tx)
When this bit is changed, both D0 and D1 are set to input mode immediately.
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Time A
Time B
Time C
Time D
Time E
(DIF-Z)
(DIF-Z)
= EIDL Length
= After Power up 100ms (min.) (Manual Start) and after that 200us.
= Teidl_stb
= 200us(min.)
= Tactivate
= After Power up 100ms (min.) and after that 2ms (min.)
= T_EIDL_ENTRY = 4SI (min.) PHY Spec. defines as fixed but test mode defines as min.
= T_DMT_ENTRY = 750RCLK (min.)
EIDL
(DIF-PD)
RCLK
EIDL
(DIF-PD)
STB.L
(DIF-L)
Time A
Time B
SYN
SYN
COM
(K28.5)
Time C
K-code
(K30.7)
TMD1 TMD2
COM
(K28.5)
K-code
(K30.7)
TMD1 TMD2
SYN
Sub Mode 03-01
are effective here
(K28.5+K30.7+TMD1+TMD2) x 4
RCLK
(DIF-Z)
SYN
SYN
Data.0 Data.1 Data.2 Data.3 Data.4 Data.N
Time C
STB.H
(DIF-H)
EIDL
(DIF-PD)
Time D
data xN
(DIF-Z)
Time E
(DMT Ent.)
Test Mode can be changed.
(a) Normal Mode at once
(DIF-Z)
(DIF-Z)
EIDL
(DIF-PD)
RCLK
EIDL
(DIF-PD)
STB.L
(DIF-L)
Time A
Time B
(DIF-Z)
EIDL
(DIF-PD)
RCLK
EIDL
(DIF-PD)
STB.L
(DIF-L)
Time A
Time B
(DIF-Z)
(DIF-Z)
SYN
SYN
COM
(K28.5)
Time C
K-code
(K30.7)
TMD1 TMD2
COM
(K28.5)
K-code
(K30.7)
TMD1 TMD2
(K28.5+K30.7+TMD1+TMD2) x 4
STB.H
(DIF-H)
EIDL
(DIF-PD)
Time D
Time E
(DMT Ent.)
(DIF-Z)
(DIF-Z)
SYN
SYN
Data.0 Data.1 Data.2 Data.3 Data.4 Data.N
Time C
data xN
STB.H
(DIF-H)
EIDL
(DIF-PD)
Time D
(DIF-Z)
Time E
(DMT Ent.)
Test Mode can be changed.
1246
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(b) Normal Mode through Dormant or Re-Sync state
Figure 4-24: Normal Modes Sequence
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Time A
Time B
Time C
Time D
Time E
(DIF-Z)
(DIF-Z)
= EIDL Length
= After Power up 100ms (min.) (Manual Start) and after that 200us.
= Teidl_stb
= 200us(min.)
= Tactivate
= After Power up 100ms (min.) and after that 2ms (min.)
= T_EIDL_ENTRY = 4SI (min.) PHY Spec. defines as fixed but test mode defines as min.
= T_DMT_ENTRY = 750RCLK (min.)
EIDL
(DIF-PD)
RCLK
EIDL
(DIF-PD)
STB.L
(DIF-L)
Time A
Time B
SYN
SYN
COM
(K28.5)
K-code
(K30.7)
Time C
TMD1 TMD2
COM
(K28.5)
K-code
(K30.7)
TMD1 TMD2
SYN
Sub Mode 03-01
are effective here
(K28.5+K30.7+TMD1+TMD2) x 4
RCLK
(DIF-Z)
SYN
SYN
Data.0 Data.1 Data.2 Data.3 Data.4 Data.N
Cannot go Dormant by STB.H
(If necessary to go Dormant,
transfer to Normal mode by
using "Sequence to Set Test
Mode".)
data xN
Time C
(a) Disconnect Mode at once
(DIF-Z)
(DIF-Z)
EIDL
(DIF-PD)
RCLK
EIDL
(DIF-PD)
STB.L
(DIF-L)
Time A
Time B
(DIF-Z)
(DIF-Z)
(DIF-Z)
SYN
SYN
COM
(K28.5)
K-code
(K30.7)
Time C
EIDL
(DIF-PD)
RCLK
EIDL
(DIF-PD)
STB.L
(DIF-L)
Time A
Time B
TMD1 TMD2
COM
(K28.5)
K-code
(K30.7)
TMD1 TMD2
STB.H
(DIF-H)
Time D
(K28.5+K30.7+TMD1+TMD2) x 4
EIDL
(DIF-PD)
(DIF-Z)
Time E
(DMT Ent.)
(DIF-Z)
SYN
SYN
Data.0 Data.1 Data.2 Data.3 Data.4
Time C
Data.n
Cannot go Dormant by STB.H
(If necessary to go Dormant,
transfer to Normal mode by
using "Sequence to Set Test
Mode".)
data xN
Sub Mode 03-01
are effective here
1248
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(b) Disconnect Mode through Dormant or Re-Sync
Figure 4-25: Disconnect Mode Sequence
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4.7.4 An Example Procedure
An example procedure for entering test mode is shown in Figure 4-26. This procedure is about
Backward Loop Back test under the condition that PLL Multiplier is x30.
Test Equipment
Device under PHY test
Supply power
Disconnect mode at once
D0 is input as default
Exiting Dormant state
D0
Test mode setting
TMD1 = Disconnect Mode At Once
TMD2 = Backward Loop Back
D0
Backward Loopback Mode is
effective.
Both D0 and D1 are set to
input mode.
- Disconnect all lanes and re-connect the Test Equipment
in Backward Loopback
- Start sending SYN from Test Equipment to D1 of device
After device detects SYN from D1,
enable D0 as output.
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D1
TMD1 = Normal Mode Through Re-Sync
TMD2 = Backward Loop Back, PLL Multiplier x30
Go Re-Sync
D1
Exit Re-Sync
D1
PLL Multiplier is set to x30
Input Test data
Loop Back Test data
D1
D0
...
Normal Mode through Re-Sync
Test mode setting
Figure 4-26: An Example Procedure (Backward Loop Back Test with PLL Multiplier is x30)
4.7.5 Test Mode for Host
Host shall have "Slave Mode" and enter this mode for Host PHY test. The Slave Mode is correspondent
to Dormant state of a Device. The method to enter the Slave Mode depends on Host implementation.
Figure 4-27 shows the states regarding Host PHY Test.
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Host equipment
specific method
Power ON
Host Off
Normal
Mode
The sequence for
Test Mode Entry
Slave
Mode
(Normal Host
Operation)
Power Off
Entry
Exit
PHY Test
Mode
D1: Input
D0: DIF-Z
Power Off
D1: Test In
D0: Test Out
Power Off
1263
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1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
Figure 4-27: States Regarding Host PHY Test
In Slave Mode,
• Host watches D1 Line to detect the sequence for Test Mode entry.
• Host continuously provides RCLK at any frequency selected by itself.
• Disable SSC when entering Slave Mode as a default.
When entering PHY test mode from Slave mode,
• PLL Multiplier may be changed by TMD2
• Backward Loop Back mode may be selected by TMD2
• SSC Enable may be changed by TMD2
When the Slave Mode and PHY Test Mode, test equipment may be connected to Host.
The following is recommended for Host:
• Disable all timeout detectors when the sequence for Test Mode entry is detected
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4.8 2L-HD Mode (Optional)
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4.9 Additional Lanes Support (Optional)
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4.10 Interface between PHY and LINK
Duplex mode switching (means from FD mode to 2L-HD mode, and vise versa) is controlled by LINK
Layer. When a direction switching is instructed by LINK Layer, PHY shall complete the direction switch
and notify the completion to LINK Layer within a defined time (T_DIR_SWITCH = 8 SI). Refer to Section
8.3.3 and Section 8.3.4 for more details.
UHS-II may have additional Lanes in addition to D0 and D1 Lane. Refer to Chapter 9 for the details.
For the purpose of distributing PHY and Protocol IP separately, PHY-LINK I/F is defined as informative,
so as to abstract the vendor-specific implementation of UHS-II PHY. Refer to Appendix F.
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1300
1301
1302
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1305
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1307
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1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
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1321
1322
1323
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4.11 EMI
Many devices such as cellular phones, suffer from EMI problem.Designing Host and Device considering
low EMI is important. The EMI characteristic of UHS-II itself is improved compared to Legacy SD
interface because of following features:
 Differential signaling
 Low voltage swing
 Sending lower RCLK frequency compared to D0,D1 bit rate
In addition to the above, the followings are recommended for further preventing EMI:
 Minimizing intra skew
Intra skew is the time difference between the single-ended mid-points of the VDp and VDn signal
falling/rising edge.
The more intra skew becomes, the more common mode voltage fluctuates. Intra skew has a direct
impact on EMI. Wire length of two traces for each differential lane should be equivalent as much as
possible.
 Common-mode Impedance matching
In differential signaling, it is important not only to keep differential impedance but also to keep
common-mode impedance between transmission Line and termination for prevention of EMI.
 Slow down the rise/fall time
The rise/fall time also has a direct impact on EMI.
The frequency of RCLK is one tenth of bit rate of D0, D1, therefore it is recommended to slow down
the rise/fall time of RCLK than that of D0, D1. Slowing down the rise/fall time is effective for
realizing low EMI.
 Tunable RCLK frequency range
UHS-II provides a benefit to select the operating frequency. This feature allows keeping the EMI
frequency outside the operating frequency of other sensitive system elements, like RF receivers.
 Spread Spectrum Clocking (SSC)
RCLK has a narrow frequency spectrum at the base frequency and its harmonics frequencies.
Spread-spectrum clocking (SSC) is an effective method to reduce the spectral density of the EMI
that the UHS II system is generating.
Using SSC is optional for the Host, but if used, it has to comply with the definitions at
Appendix E.1.6
Device shall support receiving RCLK with SSC, but usually no special design for Device is needed.
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5. Link Layer Specification
5.1 Link Layer Overview
Figure 5-1 shows the overview of Link Layer.
Link Management
Link
Flow Control
DLSM
PLSM(D0/ D1)
1345
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1354
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1359
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1361
I n-band Link Message (MSG)
Data I ntegrity (Framing & CRC)
Direction Control (Optional)
LSS (SYN, LI DL, SOP, EOP, ...)
PHY I nitialization
Figure 5-1 : Link Layer Overview
Link Layer is in charge of controlling data flow and making management for LINK and PHY. The key
features of Link Layer are defined as follows.
•
•
•
•
PHY Initialization Control
Data Integrity: Packet framing with SOP and EOP, CRC generation and checking.
Flow Control: Fixed window flow control only for Data packet transfer.
Direction Control: Duplex mode switching between FD mode and 2L-HD mode (Optional for
Range A and Range B, not available for Range C and Range D).
• Power Management (PM):
Lane level power saving state (EIDL: Electrical Idle)
Link level power saving state (Dormant)
• PHY and LINK error handling
• Packet Bypassing
1362
5.2 Link Layer Protocol
1363
1364
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1367
1368
1369
1370
5.2.1 Protocol Overview
1371
5.2.2 Link Symbol Set (LSS)
1372
1373
1374
1375
5.2.2.1 Special Symbols
In 8b/10b encoding scheme, special symbols of 8b/10b K-symbol are defined and these are used for
transmission control. Table 5-1 describes special symbols for Link Layer.
Link Layer generates Link Symbol Set (LSS) to control PHY (synchronization, direction control, etc.),
frames UHS-II packet (refer to Section 3.4.1 for more details) in terms of packet separation and data
integrity. When Link accepts outgoing packets from upper layer (CM-TRAN), it generates CRC for each
packet and the packet accompanied by its CRC is framed with SOP and EOP LSS. The framed UHS-II
packets are transmitted through UHS-II bus via PHY. Each byte of original packet and CRC is encoded
to 8b/10b Data symbol (D) in PHY. Refer to Chapter 4 for the 8b/10b encoding scheme.
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K-Symbol
Symbol
name
K28.0
K28.1
K28.2
K28.3
K28.4
K28.5
SDB
SOP
LIDL
COM
K28.6
DIDL
K28.7
K23.7
K27.7
K29.7
K30.7
PAD
EDB
EOP
-
Function
Start of DATA Burst
Start of Packet
Reserved
Logical Idle
Reserved
Comma
Logical Idle during
data transmission
Reserved
Padding
End of DATA Burst
End of Packet
Reserved (See Note (1))
Original Byte
Hex
HGF EDCBA
1Ch
000 11100b
3Ch
001 11100b
5Ch
010 11100b
7Ch
011 11100b
9Ch
100 11100b
BCh
101 11100b
CurrentRDabcdei fghj
001111 0100
001111 1001
001111 0101
001111 0011
001111 0010
001111 1010
CurrentRD+
abcdei fghj
110000 1011
110000 0110
110000 1010
110000 1100
110000 1101
110000 0101
DCh
110 11100b
001111 0110 110000 1001
FCh
F7h
FBh
FDh
FEh
111 11100b
111 10111b
111 11011b
111 11101b
111 11110b
001111 1000
111010 1000
110110 1000
101110 1000
011110 1000
110000 0111
000101 0111
001001 0111
010001 0111
100001 0111
Note:
(1) K30.7 is used for PHY Test. Refer to Section4.7.1 and 4.7.3 for more details.
Table 5-1 : Special Symbols for Link Layer
5.2.2.2 Link Symbol Set
Table 5-2 describes a definition of LSS. The unit of Duration is the number of LSS. Valid reception
denotes the minimum number of LSS to be regarded that LSS can receive properly. "DIR" is used for
Direction Switch and refer to Chapter 8 for more details.
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LSS Name
LSS
Symbol0
SYN
Function
Symbol1
SYN0
(D31.5)
SYN1
(D26.2)
BSYN0
(D4.5)
BSYN
BSYN1
(D21.2)
DIR
(D31.2)
DIR
LIDL
DIDL
SDB
SOP
EOP
EDB
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
Synchronization
for exiting from
STB.
See Note (1)
Synchronization
for exiting from
STB and direction
for Boot Code
Loading.
See Note (2)
Direction Switch
COM
(K28.5)
LIDL0
(K28.3)
LIDL1
(D16.7)
DIDL0
(K28.6)
DIDL1
(D12.2)
SDB
(K28.0)
SOP
(K28.1)
EOP
(K29.7)
EDB
(K27.7)
Logical Idle
See Note (3)
Logical Idle during
data transmission
See Note (4)
Duration
• Variable in Wakeup.Sync
state
• N_LSS_SYN * 4 in
Active.Control state
• Variable in Wakeup.Sync
state
• N_LSS_DIR * 8 when FD
mode to 2L-HD mode
• Variable when 2L-HD mode
to FD mode
N/A
N/A
Valid
reception
1
1
1
1
(NOP if
received)
1
(NOP if
received)
Start of DATA 2
Burst
Start of Packet
1
1
End of Packet
1
1
End of DATA Burst
2
1
1
Note:
(1) It is required to select either SYN0 or SYN1 randomly when transmitting SYN LSS. Refer to Section 5.7.4 for more details
(2) It is required to select either BSYN0 or BSYN1 randomly when transmitting BSYN LSS. Refer to Section 5.7.4 and Section
5.9 for more details.
(3) It is required to select either LIDL0 or LIDL1 randomly when transmitting LIDL LSS on Config state or Active.Control state.
Refer to Section 5.7.4 for more details.
(4) It is required to select either DIDL0 or DIDL1 randomly on Active.Trans or Active.Stream state. Refer to Section 5.7.4 for
more details.
Table 5-2 : Link Symbol Set
For recovering from Lane standby (STB state), at least the predetermined number (N_LSS_SYN * 4) of
SYN LSS shall be issued as follows (+/- denotes the running disparity). In Tx side of PHY, the initial
disparity of the first transmitting "COM" is allowed to select either disparity.
• "COM-" g "SYN0 (D31.5)+" g "COM-" g "SYN1 (D26.2)+" g "COM+" g ...
In Rx side of PHY, symbol lock is established by "COM" reception at a Deserializer regardless of the
next symbol of LSS. It is recommended that plural number of "COM" within a certain period of time in
order to establish symbol lock because a single "COM" may be falsely generated by transmission error.
In this way, repeatedly transmitted other LSSes, such as a series of LIDL, DIDL or DIR LSS, can also be
used for symbol (re-)lock. Even if symbol lock is lost during transmission, it can be recovered by a
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1418
1419
1420
1421
1422
1423
1424
1425
series of LSSes. Also, the running disparity of 8b/10b decoder is (re-)initialized to the disparity of "COM"
used for symbol (re-)lock.
Note that "SYN0", "BSYN0", "LIDL0" and "DIDL0" keep the disparity of the following "COM" during a
series of LSS transfer because these symbols are not DC balanced. On the other hand, "SYN1",
"BSYN1", "LIDL1" and "DIDL1" always invert the disparity of "COM" because these symbols are DC
balanced. To avoid a periodic pattern that causes EMI problem, these two types of symbols shall be
randomly selected and transferred as a second symbol of LSS.
5.2.3 Header for UHS-II Packet
Figure 5-2 illustrates header structure for UHS-II packet, that is compliant to UHS-II Addendum Version
1.00 or later. First, Node ID whose range is from 0 to 15 denotes a value to identify the individual Hosts
and Devices. Node ID = 0 is set aside for Host. For Devices, number 15 is set as the initial value for
Node ID after I/F power cycle or FULL_RESET, and one of numbers from 1 to 15 is assigned to each
Device by Enumeration process described in Section 6.2.7. Note that Node ID of Boot Device is
temporarily assigned for Boot Code Loading at first, then one of numbers from 1 to 15 is assigned by
Enumeration (refer to Section 5.9).
Considering future extension, header format is allowed to be changed linked to LINK/TRAN Major
Revision in CFG_REG (refer to Table 6-9).
Bit
Byte
7
6
0
NP
TYP (Packet Type)
1
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
5
4
SID (Source ID)
3
2
1
0
DID (Destination ID)
Rsvd
TID (Transaction ID)
Figure 5-2 : Header Format
UHS-II Packet Header shall be composed of the following fields;
• NP (Native Packet): Indicator whether the packet follows native protocol or not
• 0: not native protocol (application specific protocol)
• 1: native protocol
• NP field in MSG shall be set to '1'. (MSG packet transaction is defined on native protocol.)
• TYP[2:0] (Packet Type): Packet type described in Table 5-3.
• DID[3:0] (Destination ID): Node ID of destination Device or Host.
• SID[3:0] (Source ID): Node ID of source Device or Host.
• TID[2:0] (Transaction ID): Identification number of outstanding transactions
• The TID field is defined in order to manage outstanding transactions for multiple
command execution. (Details of multiple command execution will be defined in the future
specification.)
• Also refer to Section 6.2.14 for the setting of TID.
• Rsvd (Reserved): Reserved bits. Initiator shall set them to '0', and receiver shall ignore them.
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TYP [2:0]
000b
001b
010b
011b
111b
Others
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1445
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1447
1448
1449
1450
1451
1452
1453
1454
Packet Type
CCMD
DCMD
RES
DATA
MSG
Reserved
Description
Control Command packet
Data Command packet
Response packet
Data payload packet
Message packet
Reserved
Note
TLP
TLP
TLP
TLP
Handled in LINK
--
Table 5-3 : Packet Type Encodings and Descriptions
DID and SID are used as routing information. If SID = DID, the packet is handled as broadcast. For
UHS-II Addendum Version 1.00 or later, broadcast packet is applicable only for CCMD. Details of
broadcast CCMD are described in Section 6.2.2.3.
Basically, Host or Device processes a packet with the same DID as its own Node ID. In case of
receiving a packet with different DID from own Node ID, Host or Device does not process it except
broadcast packet and bypasses it to the next Host or Device on the bus. If Host or Device receives
broadcast packet (SID = DID), it shall process even when DID is not equal to its own Node ID, and
transmit to the next Host or Device.
1455
5.2.4 Message Packet (MSG)
1456
1457
1458
1459
1460
5.2.4.1 Overview
Message Packet (MSG) is introduced to realize flow control, error or interrupt handling instead of hardwired signals.
Figure 5-3 illustrates a structure of MSG packet. Note that NP in Header shall be set to 1.
Bit
Byte
7
6
5
0
3
2
1
0
Header
(NP=1, Packet Type = MSG)
1
CTG
2
Rsvd
IDX
CODE
3
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
4
Header
Argument
Figure 5-3 : MSG Format
• CTG[2:0] (Message Category): indicates category of MSG.
• Refer to Table 5-4 for more details.
• IDX[3:0] (Message Index): indicates message Index related to CTG. Refer to Table 5-4 for more
details.
• CODE[7:0] (Message Code): indicates code to define message detail.
• Rsvd (Reserved): Reserved bits. Initiator shall set them to '0', and receiver shall ignore them.
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Bits
000b
011b
100b
Others
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1473
1474
1475
1476
1477
1478
1479
1480
CTG
Name
LMSG
(See Note
(1))
Bits
0000b
IDX
Name
FCREQ
0001b
FCRDY
0010b
STAT
INT
AMSG
others Reserved
all
Reserved
See Note (2)
Reserved
all
Reserved
Refer to Table
5-5
Refer to Table
5-5
Refer to Table
5-6
Reserved
Reserved
Flow Control Request from initiator of
DATA
Flow Control Ready from receiver of DATA
Reserved
Status of DATA Burst transfer notified from
receiver of DATA
Reserved
Reserved for interrupt
Application specific message. It depends
on application defined in CFG_REG.
Reserved
Table 5-4 : Detailed Definition of MSG
Also refer to Section 6.2.2.8 for operating reserved bits in the packet.
5.2.4.2 CODE Definition for Each IDX
Table 5-5 describes the CODE definition of FCREQ and FCRDY.
6:0
Reserved
Value
'0' = no error
'1' = error
Reserved
Description
Error occurs that it cannot be recovered
by DATA Burst Retry.
Reserved
Table 5-5 : Code Definition of FCREQ and FCRDY
If Host receives an FCREQ, FCRDY or STAT MSG with UNRECOVERABLE_ERROR = 1, it needs to
abort the data transaction by issuing TRANS_ABORT CCMD or encapsulated CMD12 (in case of
SD-TRAN). This bit is not cleared until the transaction is aborted or completed. And once this bit is
set, the transaction cannot be completed successfully.
Table 5-6 describes the CODE definition of STAT. Refer to Section 5.2.6 for framing rules or CRC.
Bits
Identifier
7
UNRECOVERABLE_ERROR
6:1
0
1490
1491
1492
1493
1494
1495
1496
1497
Description
Note:
(1) LMSG is handled within LINK.
(2) In case of SD application, refer to Section 7.2.6.1.
Bits
Identifier
7
UNRECOVERABLE_ERROR
1481
1482
1483
1484
1485
1486
1487
1488
1489
CODE
Reserved
RECOVERABLE_ERROR
Value
'0' = no error
'1' = error
Reserved
'0' = no error
'1' = error
Description
Error occurs that it cannot be recovered
by DATA Burst Retry.
Reserved
Error occurs that it can be recovered by
DATA Burst Retry. This bit is set as a
request for DATA Burst Retry.
Table 5-6 : Code Definition of STAT
UHS-II has two types of error identifiers, one is UNRECOVERABLE_ERROR and the other is
RECOVERABLE_ERROR. Refer to Section 5.2.5 for more details.
If LINK of DATA initiator side receives a STAT MSG with RECOVERABLE_ERROR = 1 and
UNRECOVERABLE_ERROR = 0 just after a DATA Burst transmission, it needs to start performing
DATA Burst Retry. Note that RECOVERABLE_ERROR in STAT MSG represents status of preceding
DATA Burst. Details of DATA Burst Retry are described in Section 5.5.4.
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1500
1501
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5.2.4.3 MSG Duplication
For the purpose of getting transaction robustness, the MSG initiator shall send the same MSG packets
twice for one message transmission. There are no gaps between the duplicated MSG packets.
Receiver shall recognize the MSG reception successful if at least one of MSG packets is recognized as
a valid MSG. In other word, if the receiver detects the first MSG packet as a valid MSG, it can ignore the
second one. Else if it fails the first MSG but succeeds to get the second one, it shall be considered as a
valid MSG reception. Otherwise, it is recognized as MSG reception error.
From now on, "MSG" means the duplicated MSG packets if not otherwise specified.
1508
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1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
5.2.5 Error Identifier
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1537
5.2.6 Framing Rules
1538
1539
1540
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1543
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5.2.6.1 Packet Framing
Figure 5-4 illustrates a packet framing rule of TLPs (TLP is described in 6.1.1). First, the TLP provided
by CM-TRAN is supplied to CRC calculator and added the 16 bits CRC to its end. Second, the TLP with
CRC is prefixed by SOP (Start of Packet) and postfixed by EOP (End of Packet) as its delimiters. Note
that the target of CRC calculation is the original packet data only and it does not include SOP and EOP.
Note that CRC is transmitted MSB (Most Significant Byte) first and LSB (Least Significant Byte) last.
Detailed CRC specification is described in Section 5.7.
Details of error identifiers in UHS-II are as follows.
• UNRECOVERABLE_ERROR: includes ILLEGAL_HEADER_ERROR,
DEVICE_SPECIFIC_ERROR and RETRY_EXPIRE_ERROR as follows.
•
ILLEGAL_HEADER_ERROR: indicates error detection in UHS-II Header on the condition of
no CRC errors. Details of ILLEGAL_HEADER_ERROR conditions are described in Section
5.8.
•
DEVICE_SPECIFIC_ERROR: is defined as a general error occurred in outside of UHS-II
interface. For example, memory write error is treated as a DEVICE_SPECIFIC_ERROR. That
kind of error is indicated from outside of UHS-II (backend, for example) in receiver side
internally.
•
RETRY_EXPIRE_ERROR: indicates the retry counter reaches to its own
"MAX_RETRY_NUM". Details of RETRY_EXPIRE_ERROR conditions are described in
Section 5.5.4.
• RECOVERABLE_ERROR: includes FRAME_ERROR and CRC_ERROR as follows.
•
FRAME_ERROR: indicates detection of framing error. In other words, a control packet or
DATA Burst violates the framing rules described in Section 5.2.6. Details of FRAME_ERROR
conditions are described in Section 5.8.
•
CRC_ERROR: indicates that CRC error is detected from a control packet or at least one of
Framed DATA packet in the previous DATA Burst. Details of CRC_ERROR conditions are
described in Section 5.8.
Basically these error identifiers are indicated in Status Register (ST_REG) described in Section 6.2.10.
Moreover, when Device detects these errors during DATA Burst transmission, it should notify them to
Host by STAT, FCREQ, or FCRDY MSG. Host can detect such errors by those MSGs or timeout.
In this section, framing rules are described.
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LSB
(transmitted first)
Packet (Dxx.x)
SOP LSS
Header
2
[Argument]
[Payload]
CRC
(Dxx.x)
EOP LSS
2
2
2
MSB
Transaction layer
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1549
1550
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Link layer
Figure 5-4 : Packet Framing Rule of TLP
Figure 5-5 illustrates a packet framing rule of MSG. The framing rule is same as that of TLP, but note
that MSG is generated by LINK, and the MSG initiator shall duplicate MSG packets as illustrated in
Figure 5-5.
LSB
(transmitted first)
Packet (Dxx.x)
SOP LSS
Header
Argument
CRC
(Dxx.x)
EOP LSS
SOP LSS
2
2
2
2
2
2
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Packet (Dxx.x)
Header
Argument
CRC
(Dxx.x)
EOP LSS
2
2
2
2
MSB
Link layer
Figure 5-5 : Packet Framing Rule of MSG
Packet deframing is basically the inverse operation of framing. Also refer to Section 5.8 for packet
deframing.
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5.2.6.2 DATA Burst Framing
Each data transfer performed by DCMD is split into some DATA Bursts, and the DATA Burst is a basis of
performing flow control. The number of DATA to be bundled in DATA Burst is less than or equal to flow
control unit window size (N_FCU) defined in Configuration Register (CFG_REG). DATA Burst deframing
is basically the inverse operation of framing.
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5.2.6.2.1 DATA Burst Framing Rule in Block Mode
Figure 5-6 illustrates a DATA Burst framing rules in Block Mode (in case of N_FCU = 2). A Framed DATA
packet is generated by the Packet Framing rules described in Section 5.2.6.1. The DATA Burst shall
have N_FCU Framed DATA packets. The gaps between one Framed DATA packet and another are
filled with at least N_DATA_GAP (more than or equal to zero) of Data Idle symbol set (DIDL), and DATA
Burst is generated as a result. The DATA Burst is framed again with symbol set named SDB (Start of
DATA Burst) and EDB (End of DATA Burst). In other words, two SDB LSSes appear at the top of the
DATA Burst, and two EDB LSSes do at the bottom.
<In case of N_FCU = 2>
Framed DATA packet
LSB
(transmitted first)
DATA Packet (Dxx.x)
SDB
LSS
SDB
LSS
SOP
LSS
Header
2
2
2
2
Payload
DIDL * N_DATA_GAP (≥0)
CRC
(Dxx.x)
EOP
LSS
DIDL
LSS
2
2
2
...
Transaction layer
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Framed DATA packet
DATA Packet (Dxx.x)
DIDL
LSS
SOP
LSS
Header
2
2
2
Payload
CRC
(Dxx.x)
EOP
LSS
EDB
LSS
EDB
LSS
2
2
2
2
MSB
Transaction layer
Link layer
Figure 5-6 : DATA Burst Framing Rule in Block Mode (N_FCU = 2)
If TLEN is not divisible by N_FCU, fractional DATA Burst, which consists of Framed DATA packet less
than N_FCU, can be transmitted only as a final part of data transaction, as illustrated in Figure 5-7. Note
that the fractional DATA Burst is not allowed if TLEN is not specified in DCMD, except when the data
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transfer length is determined by another means for the DCMD (for example, secure multi-block read /
write command such as ACMD18 or ACMD25). In this exception, CMD12 is not required even in case of
LM=0.
<In case of TLEN = 14, N_FCU = 4>
Transmitted first
Allowed to have less than 4 Framed DATA packets
(2 packets in this example)
Mandatory to have 4 Framed DATA packets
Data in a transaction
DATA Burst
DATA Burst
DATA Burst
Fractional
DATA Burst
Payload size of Framed
DATA packet shall be
equal to Block Length
Fractional DATA Burst
(The number of Framed DATA
packet < N_FCU)
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SDB SDB
LSS LSS
Framed
DATA packet
DIDL
LSS
DIDL
LSS
Framed
DATA packet
EDBEDB
LSS LSS
Figure 5-7 : Framing Rules for Fractional DATA Burst
The payload length for all DATA Packets shall be equal to Block Length in Block Mode. If Block Length
is odd, the DATA initiator shall insert one PAD (K23.7) at the end of each DATA Packet in order to make
the length of Framed DATA Packet even bytes.
LSB
(transmitted first)
DATA Packet (Dxx.x)
PAD
CRC
(K23.7) (Dxx.x)
SOP
LSS
Header
Payload
2
2
Block Length (odd)
1
2
EOP
LSS
MSB
2
(PAD symbol exists only when Block Length is odd.)
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Figure 5-8 : Framed DATA Packet Format in Case of Block Length Is Odd
5.2.6.2.2 DATA Burst Framing Rule in Byte Mode
Figure 5-9 illustrates a DATA Burst Framing rule in Byte Mode.
LSB
(transmitted first)
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1601
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DATA Packet (Dxx.x)
SDB
LSS
SDB
LSS
SOP
LSS
Header
Payload
CRC
(Dxx.x)
EOP
LSS
EDB
LSS
EDB
LSS
2
2
2
2
TLEN
2
2
2
2
MSB
Figure 5-9 : DATA Burst Framing Rule in Byte Mode
Note that the following rules shall be kept in of Byte Mode.
•
•
•
TLEN shall be specified in DCMD.
TLEN shall be smaller than or equal to Block Length.
A DATA Burst shall have only one Framed DATA Packet.
Moreover, if TLEN is odd, the DATA initiator shall insert one PAD (K23.7) at the end of DATA Packet in
order to make the length of Framed DATA Packet even bytes.
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LSB
(transmitted first)
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DATA Packet (Dxx.x)
SDB
LSS
SDB
LSS
SOP
LSS
Header
Payload
2
2
2
2
TLEN (odd)
PAD
(K23.7)
CRC
(Dxx.x)
EOP
LSS
EDB
LSS
EDB
LSS
1
2
2
2
2
MSB
(PAD symbol exists only when TLEN is odd.)
Figure 5-10 : DATA Burst Framing Rule in Byte Mode When TLEN Is Odd
5.2.7 Symbol Encoding and Byte Ordering in 8b/10b
Each byte of framed packet (TLP or MSG) and LSS is encoded to corresponding symbol with 8b/10b as
Figure 5-11. These symbols are transferred over each Lane from LSB (Least Significant Byte) to MSB
(Most Significant Byte) as Figure 5-12.
b7
LSB
a
b0
Byte 0
Byte 1
MSB
1617
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1619
j
Symbol 0
8b/10b
Symbol 1
Byte 2
Symbol 2
…
…
Byte (n-1)
Symbol (n-1)
Figure 5-11 : Symbol Encoding
Symbol 0
Symbol 1
a b c d e i
f g h j
Symbol 2
Symbol (n-1)
time
0
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1622
1 x Symbol
Time
n x Symbol
Time
Figure 5-12 : Byte Ordering in Symbol Transfer
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5.2.8 Physical Lane State Machine (PLSM)
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5.2.8.1 Overview
Physical Lane State Machine (PLSM) denotes transmitting / receiving status for each data Lane. Figure
5-13 shows a top level state diagram of PLSM. PLSM is defined for both Tx and Rx of each data Lane
and those are synchronously managed between Host and Device. For example, when D0.Tx of Host
transits to EIDL, D0.Rx of Device shall also transit to EIDL soon afterward.
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I/F Power Off
Power Off (from any state)
Direction Switch
LSS
PKT
VLD
Direction Switch
OFF
EIDL
STB
Power On
Direction Switch
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Note 1: It is allowed to go through EIDL before transiting to OFF.
Note 2: PLSM shall go through STB.H when transiting from VLD to EIDL, and STB.L when
transiting from EIDL to VLD. Also refer to Figure 5-22 for the detailed PLSM transitions.
Figure 5-13 : Physical Lane State Machine (PLSM)
•
•
•
•
•
I/F Power Off state: State indicating that I/F power supply (e.g. VDD2 in SD Memory) is off.
Both Tx and Rx transit to this state from any state only when I/F power supply is off.
OFF state: State indicating Tx or Rx is disabled. Both Tx and Rx transit to this state when
direction switch occurs. In this state, both Tx driver and Rx termination resistor of a Lane are
turned off. So, the Line between them becomes high impedance and floating state (DIF-Z).
EIDL state: Electrical-Idle state with DIF-PD (pull-down) as a Lane level power saving state.
In this state, the Lane state is kept to DIF-PD.
STB state: Lane standby state with DIF-L (STB.L) or DIF-H (STB.H) required for transition
from or to EIDL state. STB.L and STB.H are used as a prefix and postfix of a group of valid
symbols respectively (refer to Section 5.4.2 for more details). Physically, Tx side keeps
sending DIF-L during STB.L and DIF-H during STB.H, respectively. Rx side can receive
(sample) serial data as a series of bit clocked data symbol at Deserializer after its PLL is
locked. During wakeup from Dormant state, Rx side can transit from EIDL to STB.L when
Amplitude Detector on Rx detects the amplitude difference between DIF-PD and DIF-L.
VLD state: State for valid 8b/10b symbols including LSS sub-state and PKT sub-state (refer
to Section 5.2.8.2 for more details).
• LSS sub-state: State for Link layer symbol set including multiple symbol states.
• PKT sub-state: State for packet including multiple symbol states.
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Table 5-7 shows a PLSM state definition and the corresponding Tx and Rx status of PHY.
Tx Status
Diff.
8b/10b
Driver
Encode
PLSM
in Link
Line
state
in PHY
OFF
DIF-Z
Off
EIDL
DIF-PD
(See
Note (1))
Not used
--
DIF-L or
DIF-H
On
VLD
DIF-L or
(LSS or
DIF-H
PKT)
On
STB
Not used
Rx Status
Amp.
Term.
Diff.
Symbol
Detector Resistor Receiver
Lock
Not used
Not
Off
Off
(Masked)
locked
Used
Not
On
Off
(Unmasked)
locked
8b/10b
Decode
Not used
Not used
(See Note (2))
Not used
Not used
(Masked)
On
On
Valid
Symbol
Not used
(Masked)
On
On
Not
locked
(See
Note (3))
Locked
Invalid
Symbol
Valid
Symbol
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Note:
(1) Both the plus and minus Lines of the Differential Lane shall be pulled down (low impedance drive to ground). It is
implementation issue whether this feature is implemented utilizing the Differential driver itself or by additional circuitry.
(2) When Amplitude Detector detects amplitude difference, PLSM transits to STB.
(3) STB may be received even after symbol is locked. Symbol lock is lost when receiving STB continuously.
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5.2.8.2 Details of VLD State
Figure 5-14 shows a symbol state diagram for VLD state including LSS and PKT sub-state. The
underlined characters in PLSM denote symbol states. Also refer to Table 5-1 and Table 5-2 for the
corresponding K-symbols and D-symbols for each LSS and PAD symbol.
Table 5-7 : PLSM State Definition for Tx and Rx
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VLD (Valid 8b/10b Symbols)
LSS
Exit to
STB
EDB
SDB
DIDL0
DIDL1
LIDL0
LIDL1
DIR
SYN0
SYN1
BSYN0
BSYN1
Enter from
STB
COM
PKT
EOP
SOP
DAT
PAD
Note: Transition represented by dashed arrow is valid
only when 2L-HD mode.
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Exit to
LSS
(EOP)
CRC
CRC
K-Symbol
D-Symbol
PAD
Figure 5-14 : VLD State
When entering to VLD state from STB state, PLSM shall transit to LSS sub-state and start to acquire
symbol lock by transferring SYN (or DIR) LSS.
PKT sub-state requires SOP LSS at its entry and EOP LSS at its exit. DAT symbol state stands for a
data symbols, and repeats predetermined number of times to construct a UHS-II packet. PAD symbol
state stands for a PAD symbol. Rules of inserting PAD are described in Section 5.2.6.2 for FD mode, in
Section 8.3.1 for 2L-HD mode. CRC symbol state stands for its CRC symbol. CRC is calculated for the
padded packet including a series of DAT, and PAD before 8b/10b encoding, and placed just after the
padded packet as described in Section 5.2.6. When exiting from VLD state, PLSM shall transit from
LSS to STB again.
In addition to the transition above, Transmitter shall keep the following rules.
•
•
•
State transitions related to SDB, EDB and DIDL comply with DATA Burst framing rule
described in Figure 5-6.
State transitions related to SOP and EOP comply with packet and DATA Burst framing rules
described in Figure 5-4 through Figure 5-6.
The number of repetition for SYN is regulated by "N_LSS_SYN" in CFG_REG after
Configuration completes.
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5.2.8.3 In Case of 8b/10b Error
8b/10b error includes decoded error and disparity error. 8b/10b decoded error indicates that received
symbol does not comply with 8b/10b decode valid 10-bit code word. And 8b/10b disparity error indicates
that received symbol has unexpected disparity compared with to the current disparity. Note that all
8b/10b error symbols except for all-zero symbol (STB.L) and all-one symbol (STB.H) are notified to
LINK as PHY Receive Error.
If Rx side of PHY continuously detects an implementation specific period of 8b/10b error, symbol lock
shall be regained as soon as possible. And also, once Rx side of PHY transits to EIDL, its symbol lock
is lost and supposed to be regained by receiving plural "COM" during a series of SYN LSS. Note that
the actual timing to lose symbol lock is implementation specific and beyond the scope of this
specification.
When LINK detects PHY Receive Error during PKT state, it may be CRC_ERROR. And if LINK detects
PHY Receive Error related to Framing Rule violation, it may be FRAME_ERROR. Otherwise, during
LIDL period of packet gap for instance, LINK may handle PHY Receive Error as PHY internal error.
Here is an example of LINK implementation related to handling PHY Receive Error.
1711
5.2.9 Data Link State Machine (DLSM)
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5.2.9.1 Overview
Data Link State Machine (DLSM) is responsible for LINK Management such as LINK synchronization,
direction control, PM and so on. Figure 5-15 shows a state diagram of DLSM.
• When PHY Receive Error = 0, LINK treats data from PHY is correct and checks Framing rule and
CRC.
• When PHY Receive Error = 1 and LINK detects LIDL, LINK ignores PHY Receive Error.
• When PHY Receive Error = 1 and LINK detects Framing rule violation, LINK indicates it as
FRAME_ERROR.
• When PHY Receive Error = 1 between SOP and EOP, LINK indicates it as CRC_ERROR without
CRC check.
Reset (Initial State)
I n act iv e
1716
1717
1718
1719
Wakeup
Dormant
Config
Active
I n it ialize
Act iv e
Figure 5-15 : Data Link State Machine (DLSM)
•
Dormant: Link level power saving state. All Lanes are EIDL and PLL can be powered off.
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•
•
•
Wakeup: PHY initialization state with two sub-states (refer to Section 5.2.9.3).
Config: Device configuration state in which Device is initialized, enumerated and functions
are configured to be available at Active state.
Active: Normal operation state with four sub-states (refer to Section 5.2.9.5).
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5.2.9.2 Dormant State
Dormant state realizes power saving. Refer to Section 5.4 for more details.
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5.2.9.3 Wakeup State
Wakeup state includes the following two sub-states described in Figure 5-16.
Wakeup
Dormant
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Activate
Sync
Config
Figure 5-16 : Wakeup State
•
•
Wakeup.Activate: UHS-II Interface wakeup request and PLL activation
Wakeup.Sync: LINK synchronization. All of the data Lanes are in the process of symbol
locking.
Table 5-8 shows a condition of state transition related to Wakeup state.
State Transition
Current State
Next State
Dormant
Wakeup.Activate
Host
Device
Wakeup.Activate
Wakeup.Sync
Host
Device
Wakeup.Sync
Config
Host
Device
Transition Condition;
Action
Start initializing UHS-II interface;
Sending STB.L for a wakeup request.
Detecting STB.L from Host;
Sending STB.L for a wakeup
acknowledgement.
Detecting STB.L;
Starting to send SYN or BSYN LSS.
(See Note (1).)
Detecting SYN or BSYN LSS from Host;
Starting to send SYN or BSYN LSS.
(See Note (2).)
Detecting SYN or BSYN LSS from Device;
Starting to send LIDL LSS.
Detecting LIDL LSS from Host;
Starting to send LIDL LSS.
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Note:
(1) Host transmits BSYN LSS if it requires loading Boot Code from Boot Device, and SYN LSS otherwise. The selection of
SYN or BSYN is alternative during wakeup. Refer to Section 5.2.2.2 and 5.9 for more details.
(2) When Device receives SYN LSS, it also sends SYN LSS from its Tx. Likewise, when Device receives BSYN LSS, it also
sends BSYN LSS.
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5.2.9.4 Config State
Config state is a state for preparation of transiting to Active state. At least Device Initialization,
Enumeration and Configuration are taken place in Config state by CCMD. Note that Host shall issue
Table 5-8 : Condition of State Transition (Wakeup)
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commands after receiving LIDL from Device when transiting from Wakeup.Sync.
Basically, state transits to Active.Control state when "Config Completion" flag in CFG_REG is successful
to set to 1.
If the flag is already set to 1 at the entry of Config state, the transition is taken place after receiving EIDL
or LIDL. This situation occurs when receiving BSYN LSS at PHY Initialization (refer to Section 5.9) or
recovering from Dormant state.
Table 5-9 shows a condition of state transition from Config state.
State Transition
Current State
Next State
Config
Active.Control
Config
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Dormant
Transition Condition
If "Config Completion" flag is equal to 0, the value of the flag
becomes to 1, and EIDL or LIDL is received. In this case, Device
shall transit to Active.Control before transmitting the broadcast
CCMD or RES of P2P CCMD for setting the flag to 1.
Otherwise, EIDL or LIDL is received.
Host
Directing PHY to transit to Dormant state after
the conditions are satisfied described in
Section 5.4.3. As a result, RCLK may be
stopped.
Device
Directing PHY to transit to Dormant state after
the conditions are satisfied described in
Section 5.4.3.
Table 5-9 : Condition of State Transition (Config)
Application Note:
In case of Ring Connection, Host shall use broadcast write CCMD to set "Config Completion" flag to
1.
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5.2.9.5 Active State
Active state includes the following four sub-states described in Figure 5-17 (a). This state is basically
used for regulating the packet transmission. Packet reception in FD mode is done on Active.Control
state and that in 2L-HD mode on Active.Recv state, So, transition to Active.Recv state is taken place in
case of DATA Burst reception in 2L-HD mode.
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(b)
(a)
Dormant
Trans
Control
Active
Control
Config
Trans
WaitRDY
TransFD
WaitSTAT
SwtHD
TransHD
SwtFD
Recv
(c)
Stream
Recv
Control
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
SwtHD
RecvHD
SwtFD
Note:
(1) Dashed line denotes transition or state relevant to the optional 2L-HD mode.
(2) When LINK transmits or receives MSG with UNRECOVERABLE_ERROR, it shall transit its DLSM to Active.Control state.
Figure 5-17 : Active State
•
•
•
•
Active.Control: State for transmitting control packets or control LSSes and receiving any
packets in FD mode.
Active.Trans: State for transmitting DATA Burst in both FD mode and 2L-HD mode (refer to
Figure 5-17 (b) for more details). Note that LINK shall not transmit control packets during
Active.Trans.TranFD and Active.Trans.TranHD.
Active.Recv: State for receiving DATA Burst in 2L-HD mode and associated direction switch
(refer to Figure 5-17 (c) for more details). This state is optional because it is only for DATA
Burst reception in 2L-HD mode. Note that any packets cannot be transmitted in this state
because all data Lanes are occupied for DATA Burst reception or direction switch.
Active.Stream: State for DATA Burst Streaming described in Section 5.6.
Any MSG can be transmitted in Active.Control state, but the transmitting rule of each MSG depends on
other LINK specification such as Flow Control (refer to Section 5.5) or application. Moreover, any
packets with NP = 0 can be transmitted only in Active state.
Conditions of state transition related to Active state are described from Table 5-10 to Table 5-12.
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State Transition in Active state
Current State
Next State
Active.Control
Active.Trans
(Trans.WaitRDY)
Active.Recv
(Recv.SwtHD)
Active.Stream
Active.Control
FCRDY corresponding to DCMD whose DM = 1 is
transmitted.
FCREQ is bypassed;
LINK instructs the PHY to enable Loopback path.
Host
Directing PHY to transit to Dormant state after
the conditions are satisfied described in
Section 5.4.3. As a result, RCLK may be
stopped.
Device Directing PHY to transit to Dormant state after
the conditions are satisfied described in
Section 5.4.3.
The first operation of setting "Config Completion" to 0
after Wakeup synchronized by BSYN. (See Note (1))
STAT MSG or TRANS_ABORT is received.
Active.Control
TRANS_ABORT is accepted. (See Note (2))
Active.Control
DIDL LSS is received via unswitched Lane after DIR LSS
exchange.
LIDL or EIDL is received after disabling Loopback path.
Dormant
Config
Active.Trans
(Trans.WaitSTAT)
Active.Trans
(Trans.WaitRDY)
Active.Recv
(Recv.SwtFD)
Active.Stream
1790
1791
1792
1793
1794
Active.Control
Note:
(1) This transition is only taken place after finishing Boot Code Loading. Refer to Section 5.9.
(2) If SD-TRAN is implemented, this transition also takes place in case that CMD12 is accepted.
Table 5-10 : Condition of State Transition from Active State
State Transition in Trans sub state
Current State
Next State
Trans.WaitRDY
Trans.TransFD
Trans.SwtHD
1795
1796
Transition Condition;
Action
FCREQ is transmitted.
Trans.TransFD
Trans.WaitSTAT
Trans.SwtHD
Trans.TransHD
Trans.TransHD
Trans.SwtFD
Trans.SwtFD
Trans.WaitSTAT
Transition Condition;
Action
FCRDY corresponding to DCMD whose DM = 0 is
received.
FCRDY corresponding to DCMD whose DM = 1 is
received.
EDB LSS of a DATA Burst is transmitted;
starting to send DIDL LSS.
After sending STB.L for T_EIDL_RECOVERY via
switched Lane;
Starting to send at least N_LSS_DIR * 8 of DIR LSS for
each Lane.
EDB LSS of a DATA Burst is transmitted through all data
Lanes;
Starting to send DIR LSS via unswitched Lane.
DIR LSS is received via switched Lane;
Starting to send DIDL LSS same as in FD mode.
Table 5-11 : Condition of State Transition within Active.Trans State
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State Transition in Recv sub state
Current State
Next State
Recv.SwtHD
Recv.RecvHD
Recv.RecvHD
Recv.SwtFD
1797
1798
Transition Condition
DIR LSS is received via all data Lanes.
EDB LSS of a DATA Burst is received.
Table 5-12 : Condition of State Transition within Active.Recv State
1799
1800
1801
1802
5.3 PHY Initialization
1803
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5.3.1 PHY Initialization Sequence
In this section, PHY Initialization with no Boot Code Loading is described. Refer to Section 5.9 for that
with Boot Code Loading.
Figure 5-18 illustrates a PHY initialization sequence. Initial state of DLSM is Dormant in which almost all
of PHY circuits are powered off.
Host side
Device side
Dormant state (Initial state)
T L P
T1
T2
T3
T5
P L T
Tx
EIDL
Rx
Rx
EIDL
Tx
Tx
STB.L
Rx
Rx
STB.L
Tx
Tx
SYN
Rx
Rx
STB.L
Tx
Tx
SYN
Rx
Rx
SYN
Tx
Tx
LIDL
Rx
Rx
SYN
Tx
Tx
LIDL
Rx
Rx
LIDL
Tx
T2'
T3'
T4
T6
time
Enter to Config state
1807
1808
1809
1810
1811
1812
1813
1814
LINK layer Symbol Set (LSS)
Figure 5-18 : PHY Initialization Sequence
T1: In Dormant state, both Lanes are EIDL state (Electrical Idle state with DIF-PD: pull-down).
T2: For initializing PHY, LINK of Host starts to provide RCLK, drives Tx to STB.L (Lane Standby with
DIF-L) to poll the existence of UHS-II Device. After that, DLSM of Host transits to Wakeup.Activate
state.
T2': After receiving RCLK and STB.L, LINK of Device also enters to Wakeup.Activate and responds by
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driving Tx to STB.L and PHY of Device starts to acquire PLL lock.
T3: After Host receives STB.L, LINK of Host starts to send SYN LSS immediately for LINK
synchronization, and its state transits to Wakeup.Sync.
T3': Device completes its PLL lock.
T4: If Device successfully receives SYN LSS after PLL lock, LINK of Device also starts to send SYN
LSS and its state transits to Wakeup.Sync.
T5: After receiving SYN LSS from Device, LINK of Host starts to send LIDL and its state transits to
Config.
T6: After receiving LIDL LSS from Host, LINK of Device starts to send LIDL and its state transits to
Config.
Note that PHY speed range setting performed by "Selected Transmission Speed Range" in CFG_REG
shall be reflected to PHY before starting PLL. Both sides of LINK can set the PHY speed range during a
short period just after starting RCLK in Dormant state.
5.3.2 LINK State Transition during PHY Initialization (Point to Point)
Figure 5-19 illustrates a LINK state transition during PHY Initialization for Point to Point Connection.
Descriptions of timing such as T1 in Figure 5-19 are same as described in Section 5.3.1. Also refer to
Section 6.3.1 for the detailed definition of timing parameters such as Teidl_stb, Tactivate or Tlidl_lidl.
time T1 T2
T3
T2'
T4
T3'
T5
T6
Host
Device
RCLK
EIDL
D0
EIDL
D1
RCLK Active
Start RCLK
Send STB.L
Activate
D1
Config
Sync
LIDL
LIDL
COM
LIDL
COM
LIDL
COM
LIDL
COM
LIDL
COM
COM
COM
LIDL
LIDL
COM
SYN
COM
SYN
COM
SYN
COM
SYN
COM
SYN
COM
SYN
COM
SYN
COM
SYN
COM
SYN
COM
SYN
COM
COM
SYN
SYN
COM
SYN
COM
SYN
STB.L
COM
EIDL
SYN
LSS
(2)
Receive
STB.L
Dormant
(3)
Send
STB.L
PLL
Lock
COM
LIDL
SYN
SYN
COM
(6)
Receive
LIDL
Send
SYN
Wakeup
Activate
COM
(5)
(4)
Receive
SYN
SYN
SYN
COM
STB.L
COM
LSS
EIDL
(1)
Send LIDL
Enter to Config
Config
Sync
LIDL
COM
COM
LIDL
COM
LIDL
COM
LIDL
COM
LIDL
LIDL
COM
LIDL
COM
LIDL
COM
COM
SYN
SYN
Before Activation
COM
PLL
(MUL)
COM
STB.L
SYN
EIDL
SYN
PLSM
(D1.Tx)
COM
STB.L
COM
EIDL
SYN
PLSM
(D0.Rx)
COM
LSS
Device
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1841
D0
Send LIDL
Enter to Config
Receive
SYN
Wakeup
Dormant
PLSM
(D1.Rx)
During Lock acquisition
LIDL
COM
SYN
SYN
COM
COM
SYN
SYN
COM
COM
COM
LSS
SYN
DLSM
SYN SYN SYN SYN SYN SYN LIDL LIDL LIDL
Send
SYN
COM
PLSM
(D0.Tx)
STB.L
EIDL
COM
Host
SYN SYN SYN SYN SYN SYN SYN SYN SYN SYN SYN SYN SYN SYN SYN LIDL LIDL LIDL LIDL LIDL LIDL
STB.L
Initialize
UHS-II
DLSM
RCLK
After Lock Acquisition
Figure 5-19 : LINK State Transition during PHY Initialization (Point to Point)
(1) At T2, Host starts to send STB.L through D0.Tx. Device receives it on D0.Rx afterwards.
(2) Likewise at T2', Device responds to STB.L through D1.Tx and Host receives it on D1.Rx as a
result. Note that Device shall respond STB.L within Teidl_stb. Afterwards, Host starts to send
SYN LSS iteratively at T3.
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(3) Device can receive SYN LSS after PLL lock and symbol lock. Note that Device shall complete
PLL lock within Tactivate after transiting to Wakeup state.
(4) Host receives SYN LSS from Device, and thus it is ensured that both Host and Device complete
lock acquisition of PLL at this time.
(5) After receiving SYN LSS on Host, it starts to send LIDL LSS at T5.
(6) If Device receives LIDL LSS, it responds by sending LIDL LSS within Tlidl_lidl.
5.3.3 LINK State Transition during PHY Initialization (Ring Connection)
In this section, explanation of PHY Initialization in Ring topology is based on Figure 5-20
Host
Tx Rx
Line A
Line C
Line B
1852
1853
1854
1855
1856
1857
1858
Rx Tx
Device#1
Device#2
Figure 5-20 : Ring Connection Including Two Devices
Figure 5-21 illustrates a LINK state transition during PHY Initialization for Ring Connection described
Figure 5-20. To make simple, PLSM is removed from Figure 5-21. For Link state Transitions during PHY
Initialization with Boot Device option refer to Section 5.9.
time
T1
RCLK
EIDL
Line A
EIDL
Line B
Host
Device#1
Device#2
DLSM
T4
T2' T3
T2
T4' T5
T6
T6'
RCLK Active
STB.L
SYN SYN SYN SYN SYN SYN SYN SYN LIDL LIDL LIDL LIDL LIDL LIDL
STB.L
EIDL
Line C
1859
1860
1861
1862
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1864
1865
Rx Tx
SYN SYN SYN SYN SYN LIDL LIDL LIDL LIDL
STB.L
EIDL
SYN SYN SYN SYN SYN LIDL LIDL
Wakeup
Dormant
Activate
DLSM
Dormant
PLL
(MUL)
Before
Activation
DLSM
Dormant
PLL
(MUL)
Before
Activation
Config
Sync
Wakeup
Activate
Config
Sync
After Lock Acquisition
During Lock Acquisition
Wakeup
Activate
During Lock Acquisition
Sync
Config
After Lock Acquisition
Figure 5-21 : LINK State Transition during Wakeup (Ring)
T1: LINK of Host starts to provide RCLK, drives Tx to STB.L. As a result, DLSM of Host transits to
Wakeup.Activate state.
T2: When Device#1 receives STB.L, it starts PLL lock acquisition and enters to Wakeup.Activate. Then
it responds by driving Tx to STB.L. Note that Device#1 shall respond STB.L within Teidl_stb.
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T2': Same as T2 for Device#2.
T3: If Host receives STB.L, LINK of Host starts to send SYN LSS immediately for LINK synchronization,
and its state transits to Wakeup.Sync.
T4: If Device#1 successfully receives SYN LSS after PLL lock, LINK of Device#1 also starts to send
SYN LSS and its state transits to Wakeup.Sync. Note that Device#1 shall complete PLL lock within
Tactivate after transiting to Wakeup state.
T4': Same as T4 for Device#2.
T5: If Host can receive SYN LSS from Device#2, the DLSM transits from Wakeup.Sync to Config, and
Host starts to send LIDL LSS.
T6: If Device#1 successfully receives LIDL LSS, LINK of Device#1 also starts to send LIDL LSS within
Tlidl_lidl, and its state transits to Config.
T6': Same as T6 for Device#2.
1879
5.4 Power Management
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1916
5.4.1 Overview
For power management, the following two levels of Low Power State (LPS) are defined. Let SI denote
Symbol Interval after PLL locked and it is equal to 10UI.
• EIDL State: Lane-level LPS defined in PLSM (Physical Lane State Machine)
• Both Tx and Rx are synchronously powered off.
• Lane state shall be kept by pull-down by Tx.
• Amplitude Detector on Rx shall monitor the differential amplitude of Line whether it
indicates EIDL (DIF-PD) or not.
• Controlled by H/W
• Dormant State: Link-level LPS defined in DLSM (Data Link State Machine)
• All Data Lanes are EIDL. RCLK is stopped and PLL can be powered off.
• Controlled by S/W as well as H/W
• GO_DORMANT_STATE is to transit to Dormant
During the Valid Transmission Gap (the period that no information is being transferred in Config and
Active state of DLSM), Lane is basically filled with LIDL or DIDL, and EIDL can also be used under
certain conditions described below. The filling rules are as follows.
• Config State: Valid Transmission Gap shall be filled with LIDL.
• Active State: Valid Transmission Gap shall be filled with LIDL, DIDL or EIDL depending on sub
state and CFG_REG setting.
• Active.Control: It is possible to select by setting "Power Control Mode in Active.Control
State" in CFG_REG.
• Fast Mode: LIDL shall be used to keep its synchronization (symbol lock)
• Low Power Mode (LPM): EIDL shall be used during the Valid Transmission Gap to
reduce the power consumption. In transiting from Config to Active.Control ("Config
Completion" = 1), Device shall start outputting EIDL (including STB.H before that) from
Tx after detecting EIDL on Rx.
• In Active.Control sub-state under Low Power Mode, LINK shall not transmit two
different control packets successively without inserting EIDL. For example, though
Device can transmit RES and FCREQ successively in terms of packet transaction
during read transaction, LINK of Device shall instruct Tx to transit to EIDL between
RES and FCREQ transmission in Low Power Mode.
• Support of Low Power Mode is mandatory for Range A and Range B. On the other
hand, it is optional for Range C and Range D.
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•
•
Active.Trans and Active.Stream: DIDL shall be used regardless of above two modes.
Active.Recv: No need to fill the gap because both Lanes become Rx.
5.4.2 Lane-level LPS Management
Figure 5-22 illustrates state transition of Lane-level LPS management. This is available if Power Control
Mode in Active.Control State equals to 1.
VLD
EIDL
T_EIDL_RECOVERY
= 16 SI (min)
N_LSS_SYN
from 4 to 64 LSS
(need to be configured)
STB.L
LSS.SYN
LSS
PKT
1924
1925
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1931
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1959
1960
T_EIDL_ENTRY
= 4 SI (fixed)
T_EIDL_GAP
= 8 SI (min)
STB.H
EIDL
SI : Symbol Interval (=10UI)
Figure 5-22 : State Transition of Lane-level LPS Management (Tx Side)
Transmitter side is responsible for managing Lane-level LPS.
• Recovery from EIDL
• Tx side shall keep STB.L for the duration of T_EIDL_RECOVERY to ensure stable
amplitude detection on Rx.
• Rx side shall detect transition from EIDL (DIF-PD) to STB.L (DIF-L) by some means such
as Amplitude Detector in PHY to transit to STB.
• Recovery from STB (STB.L) to VLD
• Tx side shall transmit N_LSS_SYN * 4 of SYN LSS for synchronization (symbol lock in
Deserializer).
• Rx side can acquire its symbol lock by receiving COM symbol (K28.5) of SYN LSS for an
implementation specific times to transit to VLD state.
• Disparity of 8b/10b decoder can be initialized to the disparity of COM used for symbol
lock.
• N_LSS_SYN is predetermined in CFG_REG during Configuration.
• Entry to STB (STB.H) after VLD
• Just after VLD (LSS or PKT) state, Tx side shall keep STB.H for the duration of
T_EIDL_ENTRY (fixed to 4 SI) to notify Rx of VLD state termination.
• Entry to EIDL
• Tx side can enter to EIDL after the elapse of T_EIDL_ENTRY in STB.H state. After that,
Tx side shall keep EIDL for the duration of T_EIDL_GAP (at least 8 SI) before starting
next transmission.
• Rx side shall enter to EIDL state during T_EIDL_GAP period after STB.H reception.
5.4.3 Link-level LPS Management
Link-level LPS management are realized by Dormant state in DLSM. And this section is also related to
FULL_RESET CCMD (refer to Section 6.2.5).
For D0 and D1 Lanes, Line state shall be DIF-PD and Lane state shall be EIDL state for both Tx and Rx
during Dormant state.
For RCLK Lane in UHS-II mode, Host should disconnect pull-up resistors of Legacy SD interface.
During Dormant state, if the pull-up resistors are disconnected, Tx of RCLK should be DIF-PD to avoid
floating RCLK Lane. If the pull-up resistors cannot be disconnected, Tx of RCLK should be DIF-Z to
avoid consuming the power by the pull-up resistors.
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Note that PLL can be off during Dormant state. Moreover, CFG_REG values including PHY and LINK
parameters (e.g. N_LSS_SYN, N_DATA_GAP, and N_FCU) shall be preserved during Dormant state.
To regulate time duration to stop RCLK, timing parameter T_DMT_ENTRY is defined as 750 [RCLK
cycle].
Host may stop RCLK after the elapse of more than T_DMT_ENTRY from the time that satisfies both of
the following conditions.
• Condition H-1: Host receives broadcast GO_DORMANT_STATE CCMD, or RES of P2P
GO_DORMANT_STATE CCMD.
• Condition H-2: PLSM of Host is EIDL on D1.Rx.
On the other hand, Device shall enter to Dormant state after the elapse of sufficiently less than
T_DMT_ENTRY from the time that satisfies both of the following conditions.
• Condition D-1: Device transmits broadcast GO_DORMANT_STATE CCMD, or RES of P2P
GO_DORMANT_STATE CCMD.
• Condition D-2: PLSM of Device is EIDL on D0.Rx.
Figure 5-23 illustrates a LINK state transition during entry to Dormant state in Fast Mode.
T2
Host
time
T1
T2'
RCLK
D0
T3
T5
T4
LIDL
D1
GO_DORMANT_STATE
(Broadcast CCMD)
LIDL
LIDL
Device
RCLK may be
stopped
RCLK is running
STB.H
D0
EIDL
GO_DORMANT_STATE
(Broadcast CCMD)
LIDL
STB.H
RCLK
D1
EIDL
> T_DMT_ENTRY
VLD
(LSS&PKT)
LSS.LIDL
VLD
(LSS&PKT)
LSS.LIDL
LSS.LIDL
LSS.LIDL
LSS.LIDL
VLD
(LSS&PKT)
LSS.LIDL
EIDL
STB.H
LSS.LIDL
EIDL
Dormant
Active
VLD
(LSS&PKT)
STB.H
Link State
of Device
DLSM
PLSM
(D1.Tx)
EIDL
STB.H
PLSM
(D1.Rx)
PLSM
(D0.Rx)
Dormant
Active
PLSM
(D0.Tx) LSS.LIDL
STB.H
Link State
of Host
DLSM
EIDL
unknown state during transition
between EIDL and STB
1982
1983
1984
1985
1986
1987
1988
1989
<< T_DMT_ENTRY
Figure 5-23 : LINK State Transition during Entry to Dormant State (Fast Mode)
T1: When Host intends to enter Dormant state, it issues GO_DORMANT_STATE CCMD. As described
in Table 6-19, Host can issue GO_DORMANT_STATE CCMD both as P2P and broadcast. In this
example, Host issues the broadcast one.
T2: Device transmits GO_DORMANT_STATE broadcast CCMD from D1.Tx as an acceptance of the
received CMD. In case of P2P CCMD, it transmits RES instead of broadcast CCMD (Condition D-1).
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1998
T2': Host receives GO_DORMANT_STATE broadcast CCMD (Condition H-1).
T3: When PLSM of Device is EIDL on D0.Rx (Condition D-2), timing conditions for Device are satisfied.
Then, Device sets D1.Tx to STB.H and EIDL consequently. In addition, it shall start preparing for entry
to Dormant State as soon as possible and complete it within the elapse of sufficiently less than
T_DMT_ENTRY.
T4: When PLSM of Host is EIDL (Condition H-2) on D1.Rx, then both of timing conditions for Host are
satisfied.
T5: Host may stop RCLK after the elapse of more than T_DMT_ENTRY from T4.
Application Note:
For Fast Mode, if Condition H-2 is not satisfied after the elapse of N * T_DMT_ENTRY period from
Host's driving D0.Tx to EIDL, Host should regard as timeout of entry to Dormant, where N is the
number of connected Devices.
1999
2000
2001
Figure 5-24 illustrates a LINK state transition during entry to Dormant state in Low Power Mode.
Host
RCLK
D0
T3
T3'
T2
T1
time
T4
T5
EIDL
STB.L
SYN
D1
GO_DORMANT_STATE
(Broadcast CCMD)
STB.H
EIDL
Device
RCLK may be
stopped
RCLK is running
D0
EIDL
STB.L
SYN
GO_DORMANT_STATE
(Broadcast CCMD)
RCLK
STB.H
D1
EIDL
> T_DMT_ENTRY
VLD
(LSS&PKT)
EIDL
Dormant
EIDL
EIDL
SYN
VLD
(LSS&PKT)
STB.H
SYN
STB.L
EIDL
VLD
(LSS&PKT)
STB.H
Active
STB.L
Link State
of Device
SYN
STB.H
EIDL
DLSM
PLSM
(D1.Tx)
EIDL
STB.L
VLD
(LSS&PKT)
STB.H
SYN
PLSM
(D1.Rx)
PLSM
(D0.Rx)
Dormant
Active
PLSM
(D0.Tx) EIDL
STB.L
Link State
of Host
DLSM
EIDL
unknown state during transition
between EIDL and STB
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
<< T_DMT_ENTRY
Figure 5-24 : LINK State Transition during Entry to Dormant State (Low Power Mode)
T1: When Host intends to enter Dormant state, it issues GO_DORMANT_STATE CCMD.
T2: PLSM of Device is EIDL on D0.Rx (Condition D-2).
T3: Device transmits GO_DORMANT_STATE broadcast CCMD from D1.Tx as an acceptance of the
received CMD (Condition D-1). At this time D0.Rx is already EIDL, timing conditions for Device are
satisfied. Hence, Device shall start preparing for entry to Dormant State as soon as possible and
complete it within the elapse of sufficiently less than T_DMT_ENTRY.
T3': Host receives GO_DORMANT_STATE broadcast CCMD (Condition H-1).
T4: When PLSM of Host is EIDL (Condition H-2) on D1.Rx, then both of timing conditions for Host are
satisfied.
T5: Host may stop RCLK after the elapse of more than T_DMT_ENTRY from T4.
Note the following items related to Dormant state.
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• Refer to Section G.1 and G.2 if Host detects an error during GO_DORMANT_STATE or
FULL_RESET sequence.
• Host may stop RCLK when all devices are in Dormant state or executed FULL_RESET. The timing
of stopping RCLK shall be after T_DMT_ENTRY from detecting EIDL. Full sequence of recovery
from Dormant state may depend on application specific layer described in Section 3.3 such as SDTRAN (refer to Section 7.2.3 in case of SD-memory).
5.4.4 Detailed Specifications for Low Power Mode
Figure 5-25 illustrates a sample of a block diagram of a Lane with related Tx and Rx.
From LINK
AD
TDS
8 or 16
TD
TxEn
PHY
Logic
(Tx)
SER
Drv
Line
D+
Pad
D+
Rcv
D-
RDS
PHY
Logic
(Rx)
RxEn
Pad
10
DET
DES
10
To LINK
2017
2018
2019
2020
2021
2022
2023
2024
8 or 16
RD
DTerm.
Resistor
SER
SER :: Serializer
Serializer
Drv
Drv:: Differential
DifferentialDriver
Driver
DES
DES :: Deserializer
Deserializer
Rcv
Rcv:: Differential
DifferentialReceiver
Receiver
AD
AD :: Amplituide
Amplituide Detector
Detector
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
TD
TD:: Transmit
TransmitData
Data
TDS
TDS :: Transmit
TransmitData
Data Status
Status Control
Control
TxEn
TxEn :: Tx
Tx Enable
Enable
RD
RD:: Receive
Receive Data
Data
RDS
RDS :: Receive
Receive Data
Data Status
Status
RxEn
RxEn:: Rx
Rx Enable
Enable
DET
DET:: Amplitude
Amplitude Detector
Detector Output
Output
(0:
(0:undetected,
undetected, 1:
1: detected)
detected)
Figure 5-25 : Sample Block Diagram of a Lane
In this example, TD / TDS and RD / RDS are supposed to be defined as PHY-LINK I/F described in
Appendix F.
TDS is generated in LINK and transmitted to PHY to control Tx status. It has 4 states which are same
as those described in Table 5-7.
• OFF:
• Driver is turned off and keeps DIF-Z (e.g. while 2L-HD mode)
• EIDL (Electrical Idle):
• Driver drives DIF-PD.
• STB (Standby):
• Driver is turned on. Tx output is fixed to DIF-L (= STB.L) or DIF-H (= STB.H).
• VLD (Valid Symbol):
• Driver is turned on. Tx output is a valid 8b/10b symbol.
RDS is generated in PHY Logic and transmitted to LINK to notify Rx status. It has the following 4 states
like TDS.
• OFF:
• Receiver and termination resistor are turned off and not in use.
• EIDL (Electrical Idle):
• Receiver is turned off and Amplitude Detector is undetected status (DET = 0). But
termination resistor is turned on.
• STB (Standby):
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•
Receiver is turned on because Amplitude Detector detects active amplitude of STB.L
driven by Tx. Symbol Lock is not established. Moreover all-zeros and all-ones 10 bit
symbol at Deserializer are treated as STB.L and STB.H respectively.
• VLD (Valid Symbol):
• Receiver is turned on and Rx can receive a validly aligned 8b/10b symbol because it has
already acquired Symbol Lock.
RxEn (Rx enable) can be generated by both DET (Amplitude Detector output) and RDS (for example,
RxEn = (DET || (RDS == STB or VLD)). During Wakeup from Dormant State, DET is directly used as
RxEn because RCLK is not available at that time. But after Wakeup, DET should be sampled by RCLK
before utilizing as the transition condition between EIDL and STB.
Note that RCLK.Rx should be enabled by RxEn on D0.Rx during Wakeup from Dormant because
RCLK.Rx does not have Amplitude Detector to avoid unintended wakeup during the period that legacy
SD I/F is used (RCLK+/- of UHS-II I/F are shared with DAT0/1 of legacy SD I/F). After exiting from
Dormant, Link of Device shall keep RCLK.Rx active because RxEn on D0.Rx may be negated during
Active state.
Figure 5-26 illustrates the example sequence for transition from / to EIDL corresponding to the
configuration shown in Figure 5-25.
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(a) For Range A and Range B
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Tx Status
T1 T2
TDS
EIDL
TxEn
Disable
V
T3 T4
STB
T5
T6
VLD (Valid Symbol)
T7
STB
EIDL
Enable
Disable
T_EIDL_ENTRY T_EIDL_GAP
T_EIDL_RECOVERY
(a)
T8
(a)
(b)
Lane Status
Vdh
STB.L
Vcm
SYN
PACKET
STB.H
Vdl
0
VPD
time
|VDP-VDN|
120mV
Detector Threshold (Implementation Specific)
Rx Status
DET
Detector Mask Period (RDS = STB or VLD)
RDS
EIDL
RxEn
Disable
STB
VLD (Valid Symbol)
STB
Enable
EIDL
Disable
Receiver Enabling Period
+ Symbol Lock Period
PHY Timing
(a) Driver Enabling / Disabling Period
(b) Stable STB.L Duration for detection
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LINK Timing
T_EIDL_RECOVERY: Set by configuration
Specified STB.L Transmission Period for EIDL Recovery
T_EIDL_ENTRY = 4SI (fixed)
Specified STB.H Transmission
14 Period for EIDL Entry
T_EIDL_GAP: Set by configuration
Specified Transmission Gap in EIDL
(b) For Range C and Range D
Figure 5-26 : Transition from/to EIDL
For Range A and Range B, T_EIDL_RECOVERY and T_EIDL_GAP are fixed to 16 SI (min) and 8 SI
(min) respectively, regardless of transmission speed range. In addition, (a) Driver Enabling / Disabling
Period and (b) Stable STB.L Duration for detection are also defined as 2 SI (max) and 14 SI (min)
respectively.
For Range C and Range D, on the other hand, these values can be set by Configuration. Refer to Table
6-8 and Table 6-11.
Operations of Tx are as follows.
• LINK instructs the PHY to send STB.L for the period between T1 and T4 (≥ T_EIDL_RECOVERY)
to exit from EIDL.
• T_EIDL_RECOVERY includes the period for Driver Enabling Period required to transit
from DIF-PD to DIF-L (T1-T2) and stable STB.L period for amplitude detection (T2-T4).
•
Stable state by STB.L (T2-T4) requires at least 14 SI for stable amplitude detection.
• After sending STB.L for T_EIDL_RECOVERY, LINK instructs the PHY to send SYN LSS for the
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period between T4 and T5 (= N_LSS_SYN * 4, which is to be configured in Config State of DLSM)
to establish Symbol Lock before starting packet transmission.
• After packet transmission, LINK instructs the PHY to send STB.H for the period between T6 and
T7 (= T_EIDL_ENTRY = 4 SI) before entering to EIDL.
• After sending STB.H for T_EIDL_ENTRY, LINK instructs the PHY to turn off the Tx by setting TDS
= EIDL at T7. After that, LINK shall keep EIDL for the duration of T_EIDL_GAP before starting next
packet transmission.
Operations of Rx are as follows.
• Amplitude Detector on Rx detects transition from DIF-PD (EIDL) to DIF-L (STB.L) at around T3.
After that RDS transits from EIDL to STB and therefore Rx is turned on.
• During T4-T5, Symbol Lock is acquired in Deserializer.
• Note: Amplitude Detector detects DIF-L by T4 at the latest. So, N_LSS_SYN * 4 (T4-T5)
should include not only the period for actual Symbol Lock but also Rx enabling period.
• During T7-T8 (after receiving STB.H), Amplitude Detector on Rx shall be ensured to become
undetected status (DET=0) again to prepare for next amplitude detection. Under the condition of
DET=0 after T7, RDS can transit to EIDL and therefore Rx can be turned off.
• Output of Amplitude Detector (DET) is not used and masked while RDS = STB or VLD except just
after STB.H reception (T7-T8). By T8, DET is required to be "0" (undetected) before RDS transits
to EIDL.
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5.5 Flow Control
2117
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2119
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2121
2122
2123
2124
2125
2126
5.5.1 Flow Control Overview
Fixed window Flow Control (FC) is performed in Link Layer. FC information is transmitted by the
following FC MSGs.
• FCREQ (Flow Control Request): a message packet for indicating "ready to transmit DATA Burst"
and requesting FCRDY
• FCRDY (Flow Control Ready): a message packet for indicating "ready to receive DATA Burst"
Figure 5-27 illustrates the overview of Flow Control sequence.
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Device
Host
DCMD (Write)
RES
RES
FCREQ
Device
Host
DCMD (Read)
T1
FCREQ
Flow Control
handshake
DATA Burst
（DATA×N_FCU）
framed with
SDB and EDB
Flow Control
handshake
FCRDY
T2
FCRDY
DATA
T3
DATA
DATA
DATA
・・・
・・・
DATA
DATA
STAT
FCREQ
T4
T5
DATA Burst
（DATA×N_FCU）
framed with
SDB and EDB
STAT
FCREQ
FCRDY
FCRDY
DATA
DATA
last DATA
last DATA
STAT
T6
STAT
Transaction Layer Packet (TLP)
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
(Duplicated) Message Packet (MSG)
Figure 5-27 : Flow Control Sequence Overview
After DCMD is issued and RES is sent back to Host from Device, FC handshake shall be performed in
Link layer before data transfer.
FC sequence is described as follows;
T1: DATA Initiator issues FCREQ when it is ready for transmitting DATA Burst.
T2: DATA Receiver responds by sending FCRDY when it is ready for receiving DATA Burst. (FC
handshake is completed, and "FC handshake completion" is indicated to TRAN from LINK in both
sides)
T3: DATA Initiator starts data transfer and continues until the end of DATA Burst or more specifically
EDB LSS.
T4: After EDB is received, receiver shall issue STAT (Status) MSG including
UNRECOVERABLE_ERROR and RECOVERABLE_ERROR identifier that represents whether error
had occurred in at least one DATA packet or not.
T5: If there is no error in transmitted DATA Burst, from T1 to T4 is repeated until TLEN sized DATA
transfer is completed.
T6: In the case that the last DATA Burst is received, DATA receiver shall issue STAT MSG as T4.
5.5.2 Flow Control Handshake and Terminating Data Transmission
UHS-II has a capability of terminating data transmission even on the way of transaction. To realize this,
Host issues either TRANS_ABORT or application specific command (encapsulated CMD12 in case of
SD-TRAN). These commands can be issued only during command time slot (CTS) described below.
Figure 5-28 illustrates the overview of CTS during FC and data transmission termination.
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Host
CLK Active
RCLK
D0
Host can terminate Data
transmission by CMD
(e.g. encapsulated CMD12)
DCMD
D1
STAT
FCRDY
Read
RES
DATA
FCREQ
DATA
FCRDY
FCREQ
DATA
DATA Burst
DATA Burst
RCLK
CLK Active
DCMD
FCREQ
RES
DATA
FCRDY
FCREQ
RES
D1
DATA
FCREQ
STAT
DATA
FCRDY
Host can terminate Data
transmission by CMD
(e.g. encapsulated CMD12)
D0
CMD
DATA
STAT
Device
RCLK
RES
D1
Transaction Layer Packet (TLP)
Message Packet (MSG)
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Write
D0
CMD
DATA Burst
DATA Burst
Host
D1
DATA
Command
Time Slot
Command
Time Slot
D0
STAT
Device
RCLK
UHS-II Addendum Version 2.00 Draft
Figure 5-28 : CTS during FC and Terminating Data Transmission
95
As shown in Figure 5-28, CTS during data read/write transaction is set as follows;
Command
Time Slot
Command
Time Slot
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2163
2164
2165
2166
2167
2168
2169
2170
• In case of read transaction:
• Between RES reception and FCRDY transmission
• Between STAT transmission and FCRDY transmission
• In case of write transaction:
• Between RES reception and FCREQ transmission
• Between STAT reception and FCREQ transmission
After sending a command during CTS in read transaction, there are two packet order cases as follows:
(1) Host receives FCREQ after RES of the command, and (2) Host receives FCREQ before RES. Host
shall not ignore the RES that follows FCREQ in such sequence. In case of a Transaction Stop
Command (TRANS_ABORT, CMD12, and FULL_RESET), any mixture of LIDL, EIDL and DIDL may be
sent by Device between the command issued during CTS and its RES.
Detail definition of CTS is described in Section 6.2.13.4.
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5.5.3 Details of Flow Control Sequence
2172
2173
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5.5.3.1 Read Transaction (FD) in Fast Mode
Figure 5-29 illustrates the detailed FC sequence during data read transaction in case of Fast mode.
Host side
T
L P
P L
CMD
CMD
Tx
FDR
T1
N_FCU
BLK 0
BLK 1
…
BLK N-1
Tx Buf
BLK 0
BLK 1
…
BLK N-1
RES
FDR
LIDL/EIDL
LIDL
T3
Rx
N_FCU
FDR
Rx
N_FCU
BLK 0
BLK 1
…
BLK N-1
BLK 0
BLK 1
…
BLK N-1
FCREQ
T5
Rx
N_FCU
FDR
Rx
N_FCU
BLK 0
BLK 1
…
BLK N-1
BLK 0
BLK 1
…
BLK N-1
N_FCU
BLK 0
BLK 1
…
BLK N-1
SDB
FDR
Rx
N_FCU
T7
FDR
Rx
N_FCU
Rx
FDR
BLK 0
BLK 1
…
BLK N-1
DATA
Tx
N_FCU
CMD
LIDL
LIDL/EIDL
T6'
Rx
FDR
Tx Buf
BLK 0
BLK 1
…
BLK N-1
EDB
Tx
N_FCU
CMD
CMD
Tx
T6
Tx Buf
Rx Buf
BLK 0
BLK 1
…
BLK N-1
Tx
N_FCU
CMD
LIDL
LIDL/EIDL
CMD
Tx
Rx
FDR
Tx Buf
Rx Buf
Rx
Tx
N_FCU
CMD
LIDL/EIDL
LIDL
Rx Buf
FDR
Rx
FDR
BLK 0
BLK 1
…
BLK N-1
CMD
Tx
T4
Tx Buf
DIDL
LIDL/EIDL
CMD
Tx
Tx
N_FCU
CMD
FCRDY
Rx Buf
BLK 0
BLK 1
…
BLK N-1
Rx
FDR
Tx Buf
FDR
Tx
N_FCU
CMD
LIDL
LIDL/EIDL
Rx Buf
CMD
Tx
Rx
FDR
BLK 0
BLK 1
…
BLK N-1
LIDL
LIDL/EIDL
CMD
Tx
T2
Tx Buf
Rx Buf
BLK 0
BLK 1
…
BLK N-1
Tx
N_FCU
CMD
CMD
Tx
Rx
FDR
DCMD
Rx Buf
Rx
Device side
T
Rx
FDR
STAT
Rx Buf
Tx Buf
BLK 0
BLK 1
…
BLK N-1
BLK 0
BLK 1
…
BLK N-1
LIDL
LIDL/EIDL
T6"
Tx
N_FCU
time
DATA Burst transfer ( T3-T7) is repeated until completion
of TLEN transfer or termination by TRANS_ABORT CCMD
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
TRAN Layer Packet (TLP)
(Duplicated)Message Packet (MSG)
LINK Layer Symbol Set (LSS)
Figure 5-29 : Flow Control Sequence during Data Read (FD, Fast Mode)
T1: TRAN of Host issues DCMD with "FD mode, Read" setting (i.e. DM = 0 and R/W = 0).
T2: TRAN of Device responds by sending RES with FDR setting.
T3: Before starting FC handshake (FCREQ and FCRDY), both sides of LINK stay in Active.Control
state. So, both Lanes are filled with a series of LIDL LSS including LIDL0 or LIDL1 symbol as a second
symbol in random order.
T4: When Tx Buffer is ready for transmitting DATA Burst (DATA * N_FCU), LINK of Device (= DATA
Initiator) issues FCREQ (Flow Control Request) MSG directed by TRAN and transits its DLSM from
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2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
Active.Control to Active.Trans.WaitRDY. After that, it starts to transmit DIDL LSSes including DIDL0 or
DIDL1 as a second symbol in random order.
T5: When Rx Buffer is ready for receiving DATA Burst, LINK of Host (= DATA Receiver) issues FCRDY
(Flow Control Ready) MSG directed by TRAN and stays in Active.Control state. And after receiving
FCRDY from Host, LINK of Device transits to Active.Trans.TransFD state.
T6: LINK of Device starts to send two SDB (Start of DATA Burst) LSSes in Active.Trans.TransFD state.
T6': TRAN of Device starts to send Flow Control Unit (= N_FCU) of DATA packets through LINK and
PHY.
T6": After sending DATA packets, LINK of Device sends two EDB (End of DATA Burst) LSSes and
transits to Active.Trans.WaitSTAT state.
T7: After receiving at least one EDB, LINK of Host sends STAT (Status) MSG with error identifier
(UNRECOVERABLE_ERROR or RECOVERABLE_ERROR). And after receiving STAT from Host, LINK
of Device goes back to Active.Control state and starts to transmit LIDL LSS.
Note: Fast Mode can be selected in CFG_REG ("Power Control Mode in Active.Control State") during
Configuration and reflected in Active state to minimize the latency during data transfer.
LINK state transition during data read transaction in FD mode and Fast mode is shown in Figure 5-30.
LINK of Device transmits DIDL during Active.Trans state. Otherwise all the gaps are filled with LIDL
because both sides of LINK stay in Active.Control state under Fast Mode condition.
time
T3
T4
T7
T6
T5
Device
Host
RCLK
D0
D1
RCLK
RCLK Active
LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL SOP
LIDL LIDL SOP
FCREQ
FCRDY
EOP LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL SOP
EOP DIDL DIDL DIDL DIDL DIDL DIDL DIDL SDB SDB SOP
DATA
EOP DIDL DIDL SOP
DATA
STAT
(CRC Status)
EOP LIDL LIDL
EOP EDB EDB DIDL DIDL DIDL DIDL DIDL DIDL LIDL LIDL
D0
D1
N_DATA_GAP
DATA Burst
DLSM
of Host
DLSM
of Device
Active.Control
Active.Control
Active.Trans
WaitRDY
TransFD
WaitSTAT
DIDL LSS
LIDL LSS
2206
2207
2208
2209
(including LIDL0 or LIDL1
as a second symbol)
Active.Control
LIDL
(including DIDL0 or DIDL1
as a second symbol)
DIDL
Figure 5-30 : LINK State Transition during Data Read (FD, Fast Mode)
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2212
5.5.3.2 Read Transaction (FD) in Low Power Mode
Figure 5-31 illustrates the detailed FC sequence during data read transaction in case of Low Power
mode.
Host side
T
P L
L P
CMD
CMD
Tx
FDR
T1
Rx
N_FCU
Tx Buf
BLK 0
BLK 1
…
BLK N-1
EIDL
FDR
Rx
N_FCU
Tx Buf
BLK 0
BLK 1
…
BLK N-1
BLK 0
BLK 1
…
BLK N-1
FDR
RES
T3
Rx
N_FCU
FDR
Rx
N_FCU
BLK 0
BLK 1
…
BLK N-1
BLK 0
BLK 1
…
BLK N-1
FCREQ
Rx
N_FCU
FDR
Rx
N_FCU
BLK 0
BLK 1
…
BLK N-1
BLK 0
BLK 1
…
BLK N-1
N_FCU
BLK 0
BLK 1
…
BLK N-1
SDB
FDR
Rx
N_FCU
T7
FDR
Rx
N_FCU
Tx
BLK 0
BLK 1
…
BLK N-1
DATA
Rx
N_FCU
Rx
FDR
BLK 0
BLK 1
…
BLK N-1
Tx
N_FCU
CMD
STAT
BLK 0
BLK 1
…
BLK N-1
DIDL
LIDL/EIDL
Tx
N_FCU
Rx
FDR
EIDL
T6"
Rx
FDR
BLK 0
BLK 1
…
BLK N-1
Tx Buf
Rx Buf
T8
T6'
Tx Buf
EDB
Tx Buf
FDR
Tx
N_FCU
CMD
EIDL
Rx Buf
BLK 0
BLK 1
…
BLK N-1
Rx
FDR
CMD
Tx
T6
Tx Buf
Rx Buf
BLK 0
BLK 1
…
BLK N-1
Tx
N_FCU
CMD
EIDL
CMD
Tx
Rx
FDR
Tx Buf
Rx Buf
Rx
Tx
N_FCU
CMD
EIDL
Rx Buf
FDR
Rx
FDR
BLK 0
BLK 1
…
BLK N-1
CMD
Tx
T4
Tx Buf
DIDL
LIDL/EIDL
CMD
Tx
Tx
N_FCU
CMD
FCRDY
Rx Buf
T5
Rx
FDR
Tx Buf
BLK 0
BLK 1
…
BLK N-1
Tx
N_FCU
CMD
EIDL
Rx Buf
FDR
Rx
FDR
BLK 0
BLK 1
…
BLK N-1
EIDL
CMD
Tx
T2
Tx Buf
CMD
Tx
Tx
N_FCU
CMD
EIDL
Rx Buf
BLK 0
BLK 1
…
BLK N-1
Rx
FDR
EIDL
Rx Buf
CMD
Tx
Tx
N_FCU
CMD
CMD
Tx
Rx
FDR
DCMD
Rx Buf
BLK 0
BLK 1
…
BLK N-1
Device side
T
BLK 0
BLK 1
…
BLK N-1
EIDL
Tx
N_FCU
time
DATA Burst transfer ( T3-T8) is repeated until completion
of TLEN transfer or termination by TRANS_ABORT CCMD
2213
2214
2215
TRAN Layer Packet (TLP)
(Duplicated)Message Packet (MSG)
LINK Layer Symbol Set (LSS)
Figure 5-31 : Flow Control Sequence during Data Read (FD, Low Power Mode)
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2240
2241
2242
2243
2244
2245
2246
T1: TRAN of Host issues DCMD with "FD mode, Read" setting (i.e. DM = 0 and R/W = 0).
T2: TRAN of Device responds by sending RES with FDR setting.
T3: Before starting FC handshake (FCREQ and FCRDY), both sides of LINK stay in Active.Control state
under Low Power Mode condition. So, both Lanes are filled with EIDL.
T4: When Tx Buffer is ready for transmitting DATA Burst (DATA * N_FCU), LINK of Device (= DATA
Initiator) issues FCREQ MSG directed by TRAN and transits its DLSM from Active.Control to
Active.Trans.WaitRDY. After exiting from Active.Control state, LINK of Device starts to transmit DIDL
LSSes including DIDL0 or DIDL1 symbol as a second symbol in random order regardless of the setting
of "Power Control Mode in Active.Control State" in CFG_REG.
T5: When Rx Buffer is ready for receiving DATA Burst, LINK of Host (= DATA Receiver) issues FCRDY
MSG directed by TRAN and stays in Active.Control state. And after receiving FCRDY from Host, LINK
of Device transits to Active.Trans.TransFD state.
T6: LINK of Device starts to send two SDB LSSes in Active.Trans.TransFD state.
T6': TRAN of Device starts to send Flow Control Unit (= N_FCU) of DATA packets through LINK and
PHY.
T6": After sending DATA packets, LINK of Device sends two EDB LSSes and transits to
Active.Trans.WaitSTAT state.
T7: After receiving at least one EDB, LINK of Host sends STAT MSG with error identifier
(UNRECOVERABLE_ERROR or RECOVERABLE_ERROR). And after receiving STAT from Host,
LINK of Device goes back to Active.Control state and PLSM of D1 Lane transits to EIDL again.
Note: Low Power Mode can be selected in CFG_REG ("Power Control Mode in Active.Control State")
during Configuration and reflected in Active state to minimize the power consumption during data
transfer.
LINK state transition during data read transaction in FD mode and Low Power mode is shown in Figure
5-32. LINK of Device transmits DIDL during Active.Trans state. Otherwise all the gaps are filled with
EIDL because both sides of LINK stay in Active.Control state under Low Power Mode condition.
Detailed transition from/to EIDL is described in Section 5.4.4, including definition for T_EIDL_ENTRY or
T_EIDL_RECOVERY.
time
T5
T4
T3
T_EIDL_
RECOVERY
Host
N_LSS_SYN * 4
(set in Host)
RCLK
T_EIDL_
RECOVERY
T_EIDL_
ENTRY
4*N_LSS_SYN
(set in Host)
Device
RCLK Active
D0
D1
T7
T6
T_EIDL_
ENTRY
EIDL
EIDL
STB SYN SYN SOP
T_EIDL_
RECOVERY
STB SYN SYN SOP
FCREQ
FCRDY
RCLK
EIDL
EOP STB
EOP DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL SDB SDB SOP
DATA
N_LSS_SYN * 4
(set in Device)
EOP DIDL DIDL SOP
STB SYN SYN SOP
DATA
STAT
(CRC Status)
EOP STB
EOP EDB EDB DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL STB
EIDL
D0
EIDL
D1
T_EIDL_
ENTRY
N_DATA_GAP
DATA Burst
DLSM
of Host
DLSM
of Device
Active.Control
Active.Control
Active.Trans
TransFD
WaitRDY
DIDL LSS
SYN LSS
2247
2248
2249
2250
Active.Control
WaitSTAT
(including SYN0 or SYN1
as a second symbol)
SYN
(including DIDL0 or DIDL1
as a second symbol)
DIDL
Figure 5-32 : LINK State Transition during Data Read (FD, Low Power Mode)
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5.5.3.3 Write Transaction (FD) in Fast Mode
Figure 5-33 illustrates the detailed FC sequence during data write transaction in case of Fast mode.
Host side
T
L P
P L
CMD
CMD
Tx
FDW
T1
Rx
N_FCU
Rx Buf
BLK 0
BLK 1
…
BLK N-1
RES
FDW
T3
Rx
N_FCU
Rx Buf
BLK 0
BLK 1
…
BLK N-1
LIDL
LIDL/EIDL
FDW
FCREQ
Rx
N_FCU
BLK 0
BLK 1
…
BLK N-1
BLK 0
BLK 1
…
BLK N-1
LIDL
LIDL/EIDL
FDW
DIDL
LIDL/EIDL
Rx
N_FCU
T6
BLK 0
BLK 1
…
BLK N-1
FCRDY
FDW
Rx
N_FCU
Rx Buf
BLK 0
BLK 1
…
BLK N-1
BLK 0
BLK 1
…
BLK N-1
LIDL
LIDL/EIDL
FDW
N_FCU
BLK 0
BLK 1
…
BLK N-1
BLK 0
BLK 1
…
BLK N-1
LIDL
LIDL/EIDL
FDW
T6" Rx
N_FCU
Rx Buf
BLK 0
BLK 1
…
BLK N-1
LIDL
LIDL/EIDL
FDW
N_FCU
BLK 0
BLK 1
…
BLK N-1
Rx
FDW
LIDL/EIDL
LIDL
Rx Buf
Tx Buf
Rx
Tx
N_FCU
CMD
CMD
Tx
Rx
FDW
EDB
Tx Buf
BLK 0
BLK 1
…
BLK N-1
Tx
N_FCU
CMD
CMD
Tx
Rx
FDW
Rx Buf
Tx Buf
T6' Rx
Tx
N_FCU
CMD
DATA
T5
Rx
FDW
SDB
Tx Buf
CMD
Tx
Tx
N_FCU
CMD
CMD
Tx
Rx
FDW
Rx Buf
Tx Buf
BLK 0
BLK 1
…
BLK N-1
Tx
N_FCU
CMD
CMD
Tx
Rx
FDW
Rx Buf
Tx Buf
T4
Tx
N_FCU
CMD
CMD
Tx
T2
Rx
FDW
LIDL/EIDL
LIDL
Tx Buf
BLK 0
BLK 1
…
BLK N-1
Tx
N_FCU
CMD
CMD
Tx
Rx
FDW
DCMD
Tx Buf
BLK 0
BLK 1
…
BLK N-1
Device side
T
BLK 0
BLK 1
…
BLK N-1
STAT
Tx
T7
N_FCU
time
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
DATA Burst transfer ( T3-T7) is repeated until completion
of TLEN transfer or termination by TRANS_ABORT CCMD
TRAN Layer Packet (TLP)
(Duplicated)Message Packet (MSG)
LINK Layer Symbol Set (LSS)
Figure 5-33 : Flow Control Sequence during Data Write (FD, Fast Mode)
T1: TRAN of Host issues DCMD with "FD mode, Write" setting (i.e. DM = 0 and R/W = 1).
T2: TRAN of Device responds by sending RES with FDW setting.
T3: Before starting FC handshake (FCREQ and FCRDY), both sides of LINK stay in Active.Control
state. So, both Lanes are filled with a series of LIDL LSS including LIDL0 or LIDL1 symbol as a second
symbol in random order.
T4: When Tx Buffer is ready for transmitting DATA Burst (DATA * N_FCU), LINK of Host (= DATA
Initiator) issues FCREQ (Flow Control Request) MSG directed by TRAN and transits its DLSM from
Active.Control to Active.Trans.WaitRDY. After that, it starts to transmit DIDL LSSes including DIDL0 or
DIDL1 as a second symbol in random order.
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T5: When Rx Buffer is ready for receiving DATA Burst, LINK of Device (= DATA receiver) issues
FCRDY (Flow Control Ready) MSG directed by TRAN and stays in Active.Control state. And after
receiving FCRDY from Device, LINK of Host transits to Active.Trans.TransFD state.
T6: LINK of Host starts to send two SDB (Start of DATA Burst) LSSes in Active.Trans.TransFD state.
T6': TRAN of Host starts to send Flow Control Unit (= N_FCU) of DATA packets through LINK and PHY.
T6": After sending DATA packets, LINK of Host sends two EDB (End of DATA Burst) LSSes and
transits to Active.Trans.WaitSTAT state.
T7: After receiving at least one EDB, LINK of Device sends STAT (Status) MSG with error identifier
(UNRECOVERABLE_ERROR or RECOVERABLE_ERROR). And after receiving STAT from Device,
LINK of Host goes back to Active.Control state and starts to transmit LIDL LSS.
LINK state transition during data write transaction in FD mode and Fast mode is shown in Figure 5-34.
time
T3
T4
T7
T6
T5
Host
Device
RCLK
D0
D1
RCLK Active
LIDL LIDL LIDL SOP
FCREQ
EOP DIDL DIDL DIDL DIDL DIDL DIDL DIDL SDB SDB SOP
LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL SOP
FCRDY
DATA
RCLK
EOP DIDL DIDL SOP
DATA
EOP EDB EDB DIDL DIDL DIDL DIDL DIDL DIDL LIDL
EOP LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL SOP
STAT
(CRC Status)
EOP LIDL LIDL
D0
D1
N_DATA_GAP
DATA Burst
DLSM
of Host
DLSM
of Device
Active.Control
Active.Trans
WaitRDY
TransFD
WaitSTAT
Active.Control
DIDL LSS
LIDL LSS
2279
2280
2281
2282
Active
.Control
(including LIDL0 or LIDL1
as a second symbol)
LIDL
(including DIDL0 or DIDL1
as a second symbol)
DIDL
Figure 5-34 : LINK State Transition during Data Write (FD, Fast Mode)
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5.5.3.4 Write Transaction (FD) in Low Power Mode
Figure 5-35 illustrates the detailed FC sequence during data write transaction in case of Low Power
mode.
Host side
T
L P
P L
CMD
CMD
Tx
FDW
T1
Rx
N_FCU
Rx Buf
BLK 0
BLK 1
…
BLK N-1
EIDL
FDW
Rx
N_FCU
Rx Buf
BLK 0
BLK 1
…
BLK N-1
BLK 0
BLK 1
…
BLK N-1
FDW
RES
Rx
N_FCU
FDW
Rx
N_FCU
BLK 0
BLK 1
…
BLK N-1
EIDL
FDW
Rx
N_FCU
BLK 0
BLK 1
…
BLK N-1
EIDL
BLK 0
BLK 1
…
BLK N-1
BLK 0
BLK 1
…
BLK N-1
T6
N_FCU
BLK 0
BLK 1
…
BLK N-1
FCRDY
FDW
T6' Rx
N_FCU
FDW
N_FCU
BLK 0
BLK 1
…
BLK N-1
FDW
BLK 0
BLK 1
…
BLK N-1
EIDL
Rx
N_FCU
FDW
Rx
N_FCU
Rx
FDW
Rx Buf
BLK 0
BLK 1
…
BLK N-1
EIDL
Tx
N_FCU
CMD
DIDL
LIDL/EIDL
Rx
FDW
Rx Buf
BLK 0
BLK 1
…
BLK N-1
STAT
Tx
Rx
FDW
EIDL
Tx Buf
Rx Buf
BLK 0
BLK 1
…
BLK N-1
BLK 0
BLK 1
…
BLK N-1
EIDL
T7
N_FCU
CMD
CMD
Tx
Tx
N_FCU
CMD
EDB
Tx Buf
BLK 0
BLK 1
…
BLK N-1
Rx
FDW
Rx Buf
CMD
Tx
Tx
N_FCU
CMD
DATA
Tx Buf
T6" Rx
Rx
FDW
BLK 0
BLK 1
…
BLK N-1
CMD
Tx
T5
Rx Buf
EIDL
Tx Buf
BLK 0
BLK 1
…
BLK N-1
Tx
N_FCU
CMD
SDB
CMD
Tx
Rx
FDW
Rx Buf
Tx Buf
Rx
Tx
N_FCU
CMD
DIDL
LIDL/EIDL
Tx Buf
FDW
Rx
FDW
Rx Buf
CMD
Tx
Tx
N_FCU
CMD
FCREQ
CMD
Tx
Rx
FDW
Tx Buf
BLK 0
BLK 1
…
BLK N-1
T2
Rx Buf
CMD
Tx
T4
BLK 0
BLK 1
…
BLK N-1
Tx
N_FCU
CMD
EIDL
Tx Buf
T3
Rx
FDW
EIDL
Tx Buf
CMD
Tx
Tx
N_FCU
CMD
CMD
Tx
Rx
FDW
DCMD
Tx Buf
BLK 0
BLK 1
…
BLK N-1
Device side
T
Tx
N_FCU
T8
TRAN Layer Packet (TLP)
time
2286
2287
2288
2289
DATA Burst transfer ( T3-T8) is repeated until completion
of TLEN transfer or termination by TRANS_ABORT CCMD
(Duplicated)Message Packet (MSG)
LINK Layer Symbol Set (LSS)
Figure 5-35 : Flow Control Sequence during Data Write (FD, Low Power Mode)
T1: TRAN of Host issues DCMD with "FD mode Write" setting (i.e. DM = 0 and R/W = 1).
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2301
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2303
2304
2305
2306
2307
2308
2309
2310
2311
T2: TRAN of Device responds by sending RES with FDW setting.
T3: Before starting FC handshake (FCREQ and FCRDY), both sides of LINK stay in Active.Control state
under Low Power Mode condition. So, both Lanes are filled with EIDL.
T4: When Tx Buffer is ready for transmitting DATA Burst (DATA * N_FCU), LINK of Host (= DATA
Initiator) issues FCREQ MSG directed by TRAN and transits its DLSM from Active.Control to
Active.Trans.WaitRDY. After exiting from Active.Control state, LINK of Host starts to transmit DIDL
LSSes including DIDL0 or DIDL1 as a second symbol in random order regardless of the setting of
"Power Control Mode in Active.Control State" in CFG_REG.
T5: When Rx Buffer is ready for receiving DATA Burst, LINK of Device (= DATA Receiver) issues
FCRDY MSG directed by TRAN and stays in Active.Control state. And after receiving FCRDY from
Device, LINK of Host transits to Active.Trans.TransFD state.
T6: LINK of Host starts to send two SDB LSSes in Active.Trans.TransFD state.
T6': TRAN of Host starts to send Flow Control Unit (= N_FCU) of DATA packets through LINK and PHY.
T6": After sending DATA packets, LINK of Host sends two EDB LSSes and transits to
Active.Trans.WaitSTAT state.
T7: After receiving at least one EDB, LINK of Device sends STAT MSG with error identifier
(UNRECOVERABLE_ERROR or RECOVERABLE_ERROR). And after receiving STAT from Device,
LINK of Host goes back to Active.Control state and PLSM of D0 Lane transits to EIDL again.
LINK state transition during data write transaction in FD mode and Low Power mode is shown in Figure
5-36.
time
Host
T3
T4
T_EIDL_
RECOVERY
T_EIDL_
ENTRY
D1
Device
RCLK Active
RCLK
D0
T7
T6
T5
N_LSS_SYN *4
(set in Host)
EIDL
STB SYN SYN SOP
FCREQ
EOP DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL SDB SDB SOP
EIDL
STB SYN SYN SOP
T_EIDL_
RECOVERY
N_LSS_SYN * 4
(set in Device)
FCRDY
DATA
RCLK
EOP DIDL DIDL SOP
DATA
EOP EDB EDB DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL STB
EIDL
EOP STB
T_EIDL_
ENTRY
N_DATA_GAP
STB SYN SYN SOP
T_EIDL_
RECOVERY
STAT
EOP STB
(CRC Status)
EIDL
D0
EIDL
D1
T_EIDL_
ENTRY
N_LSS_SYN *4
(set in Device)
DATA Burst
DLSM
of Host
Active.Control
DLSM
of Device
Active.Trans
TransFD
WaitRDY
Active.Control
SYN LSS
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
Active.Control
WaitSTAT
(including SYN0 or SYN1
as a second symbol)
DIDL LSS
SYN
DIDL
(including DIDL0 or DIDL1
as a second symbol)
Figure 5-36 : LINK State Transition during Data Write (FD, Low Power Mode)
As described in this section, Flow Control and associated DATA Burst transfer protocol are defined
symmetrically for both read and write case.
5.5.4 DATA Burst Retry
In order to prevent stalling DATA transaction due to transmission error, the following DATA Burst Retry
function shall be available. All Nodes shall have retry counter and set to 0 at the DCMD transaction.
• During DATA Burst transfer, transmission error causes FRAME_ERROR or CRC_ERROR at the
DATA Receiver side. If the error is detected in the DATA Burst framing, it shall be handled as
FRAME_ERROR. Note that SDB and EDB are placed twice for improving transmission error
tolerance. So, even if either one is corrupted, it does not cause FRAME_ERROR. And if the error
occurs during the actual packet between SOP and EOP, it can be detected as CRC_ERROR in
LINK. LINK can detect those transmission error in accordance with Packet Receiving Flow Chart
described in Section 5.8.
• If DATA Receiver side detects occasional transmission error during DATA Burst reception, it
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2346
2347
2348
2349
2350
2351
2352
2353
2354
notifies the Initiator side of the error via STAT MSG with RECOVERABLE_ERROR = 1. Moreover,
if it detects RETRY_EXPIRE_ERROR, it should notify the Initiator side of the error via STAT MSG
with UNRECOVERABLE_ERROR = 1.
• If DATA Initiator side receives STAT MSG or FCRDY MSG with UNRECOVERABLE_ERROR = 1
during DATA transaction, it means the DATA transaction cannot be recovered by DATA Burst Retry
mechanism regardless of RECOVERABLE_ERROR. In that case, flow control sequences shall be
given up and Host should send TRANS_ABORT CCMD or encapsulated CMD12 (in case of SDTRAN) to terminate the DATA transaction.
• If DATA Initiator side receives STAT MSG with RECOVERABLE_ERROR = 1 and
UNRECOVERABLE_ERROR = 0 after DATA Burst transmission, it compares its retry counter and
"MAX_RETRY_NUM" in CFG_REG. If retry counter is smaller than "MAX_RETRY_NUM", it shall
increment retry counter by 1 and start from a flow control handshake to retransmit the whole DATA
Burst again without any software operation. Otherwise, Initiator shall stop flow control sequence,
and in addition, Host should abort the DATA transaction same as the case of
UNRECOVERABLE_ERROR.
• When Device detects that retry counter reaches to "MAX_RETRY_NUM", it sets
RETRY_EXPIRE_ERROR to 1 in ST_REG. Moreover, it should notify
UNRECOVERABLE_ERROR = 1 by MSG as described in Section 5.2.5.
• In case that DATA Initiator side receives STAT MSG with UNRECOVERABLE_ERROR =
RECOVERABLE_ERROR = 0, it transmits next DATA Burst and sets retry counter to 0.
• DATA Burst Retry function is available only for the DATA Burst, not for control packets.
Figure 5-37 illustrates DATA Burst Retry sequence and its possible implementation related to Tx / Rx
Buffer.
FRAME_ERROR detectable area
SDB SOP
DATA
Host (Initiator side)
CRC EOP LIDL LIDL SOP
…
Device (Receiver side)
Tx Buf0
(3) Initiator side does not flip its Tx
Buffer and starts DATA Burst Retry.
FCREQ
DATA Burst
FCREQ
(face to I/F)
DATA Burst
UHS-II I/F
UHS-II I/F
(face to I/F)
DMA
CRC EOP
CRC_ERROR detectable area
Tx Buf0
DATA
DATA
DATADATA
DATADATA
DATA
(1) Receiver side detects
transmission error.
FCRDY
Tx Buf1
STAT
FCRDY
Backend
(e.g. Memory
Module)
STAT
Tx Buf1
(2) Receiver side sends STAT with
RECOVERABLE_ERROR=1
UNRECOVERABLE_ERROR=0
(face to Backend)
DATA
DATA
DATA
DATA
(face to Backend)
In case of no transmission error
Device (Receiver side)
Host (Initiator side)
Tx Buf1
DATA
DATA
DATA
DATA
FCREQ
DATA Burst
Tx Buf0
2355
2356
2357
2358
2359
2360
2361
2362
2363
Tx Buf1
(face to I/F)
DATA Burst
(1') Receiver side does not
detect transmission error.
FCRDY
(face to Backend)
FCREQ
UHS-II I/F
DMA
(face to I/F)
UHS-II I/F
flip
(3') Initiator side flips its Tx Buffer and
starts next DATA Burst transmission.
STAT
FCRDY
STAT
(2') Receiver side sends STAT with
RECOVERABLE_ERROR=0
UNRECOVERABLE_ERROR=0
flip
DATA
DATA
DATADATA
DATADATA
DATA
DATA
Backend
(e.g. Memory
Module)
Tx Buf0
(face to Backend)
Figure 5-37 : DATA Burst Retry Sequence
If both sides have dual buffer (like ping-pong buffer), one of the dual buffer is supposed to be connected
to UHS-II I/F and the buffers can be flipped only after transferring STAT MSG with
UNRECOVERABLE_ERROR = RECOVERABLE_ERROR = 0 and preparing Tx or Rx Buffer for the
next DATA Burst transfer. If the initiator side receives STAT MSG with RECOVERABLE_ERROR only, it
does not flip the buffer and its remaining source data shall be retransmitted with DATA Burst Retry
mechanism. DATA Burst Retry can be continued until the retry counter reaches to "MAX_RETRY_NUM"
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in CFG_REG.
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5.6 Packet Bypassing
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5.6.1 Overview
2376
2377
2378
2379
5.6.2 Control Packet Bypassing
It is required that both Host and the target Device can communicate as if they are connected Point to
Point regardless of actual topology, in terms of small latency and power consumption. In other words,
non-target (= intermediate) Device shall be transparent from Host and the target Device. Considering
UHS-II Ring topology, LINK is responsible for bypassing the received packet according to SID and DID
in its Header to make more topology-independent protocol of upper layer (= TRAN). And to take full
advantage of UHS-II Ring, DATA Burst Streaming is introduced for transferring DATA Burst to the target
Device with minimum latency.
This section shows how LINK bypasses a control packet (= non-DATA packet) internally.
Figure 5-38 illustrates an example of LINK architecture for packet bypassing.
Buffer Status
etc.
Tx Packet
to LINK
FC Status
etc.
Rx Packet
from LINK
CM-TRAN
MSG Generator
Packet Selector
LINK Packet
Handler
(Header Checker
& MSG Detector)
Bypass Selector
LINK
RxBuffer
LINK
TxBuffer
CRC Checker
Descrambler
CRC Generator
Scrambler
STB/LSS Detector
PLSM
for Tx
DLSM
LINK
PLSM
for Rx
STB/LSS Generator
Rx Byte Stream
from PHY
Tx Byte Stream
to PHY
8b/10b
Dec
8b/10b
Enc
Loopback
Trigger
PHY
Loopback path
for DB Streaming
Loopback Selector
2380
2381
2382
2383
2384
2385
2386
Note: 8b/10b Decoder may notify detecting all-zero symbols
and all-one symbols as STB.L and STB.H respectively.
Figure 5-38 : Example of LINK Architecture for Packet Bypassing
When LINK receives the Rx Byte Stream from PHY, it detects SOP LSS by the STB/LSS Detector and
stores the following packet content in the LINK RxBuffer, with descrambling and CRC calculation.
Afterward, when it detects EOP LSS, it stops CRC calculation and compares the result of the
calculation with CRC embedded in the received packet. If no CRC_ERROR, it checks Header of
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received packet in the LINK Packet Handler and determines either to accept it, to bypass it or to discard
it as an error. Refer to Section 5.8 for details of Packet receiving flows and conditions of Header
checking mentioned above. If the determination is to bypass, it switches the Bypass Selector and
enables to store the packet in the LINK TxBuffer. That packet is treated as to calculate CRC and to
scramble, and added SOP and EOP LSS by STB/LSS Generator, and transmitted to PHY as the Tx
byte Stream.
As the Control Packet Bypassing is taken place in Active.Control state of DLSM, the packet gap is EIDL
if Low Power Mode is selected. If the state of Tx is EIDL before bypassing, the STB/LSS Generator
shall transmit STB.L and SYN LSS for the period of T_EIDL_RECOVERY and N_LSS_SYN * 4
respectively as mentioned in Section 5.4.4. During this period, LINK shall wait to transmit the bypassed
packet in the LINK TxBuffer. Even if the following packet is coming from PHY at this time, LINK does not
need to store it in the LINK RxBuffer immediately because it takes the same period for STB.L and SYN
LSS before starting its reception. So, the size of LINK TxBuffer or RxBuffer can be determined
considering maximum size of one Control Packet.
Device shall bypass Control Packets without any modifications if DID is not its own Node ID. Note that
payload field of DEVICE_INIT, ENUMERATE, and INQUIRY_CONFIG may be modified before these
CMDs are transmitted to the next Node.
5.6.3 DATA Burst Streaming
This section shows how LINK bypasses a DATA Burst in cooperation with PHY by means of DATA Burst
Streaming. As FCREQ always precedes a DATA Burst and it is reliably routed through Ring to the target
Device in accordance with packet receiving flow described in Section 5.8, the pathway for a DATA Burst
is ensured by the corresponding FCREQ. Refer to Figure 5-38 for more architectural information about
DATA Burst Streaming.
If LINK receives FCREQ which is targeted to other Device, LINK Packet Handler determines to bypass
that. Just after bypassing the FCREQ, LINK transits to Active.Stream sub-state and starts to transmit
DIDL LSS from STB/LSS Generator. When entering to this state, LINK instructs to PHY to enable
Loopback path for entering to DATA Burst Streaming mode. When PHY enables Loopback path, plural
DIDL LSS transmitted after FCREQ are removed because Loopback path shortcuts the transmission
route inside PHY and LINK. PHY is responsible for preserving the disparity and LSS boundary before
and after enabling Loopback path. During DATA Burst Streaming, LINK shall continuously monitor Rx
byte stream from PHY in STB/LSS Detector to detect EDB LSS as a condition for exiting from DATA
Burst Streaming mode. Loopback path for Data Burst Streaming is permitted to be located either before
or behind 8b/10b decoder (refer to Appendix F for more details about how to instruct PHY to enable or
disable Loopback path and how to keep the disparity before and after switching Loopback Selector).
If at least one of the two EDB LSSes is certainly detected, LINK instructs PHY again to disable
Loopback path. LINK continues to transmit DIDL LSS during Active.Stream sub-state, and PHY is
responsible for preserving the disparity and LSS boundary before and after disabling Loopback path.
Otherwise, symbol re-lock and the associated re-initialization of the disparity may be additionally
required at the next Device. After disabling Loopback path, LINK continues to transmit DIDL LSS in
Active.Stream sub-state and it goes back to Active.Control sub-state when it detects the following LIDL
LSS (in case of Fast Mode) or EIDL (in case of Low Power Mode). Even if both EDB LSSes are lost,
LINK can exceptionally exit from DATA Burst Streaming mode by detecting LIDL LSS or EIDL.
It is mandatory for PHY to keep the disparity and LSS boundary when switching the Loopback Selector.
In addition, the following rules shall be kept in order to execute DATA Burst Streaming properly.
• LINK shall direct to enable Loopback path when EOP of FCREQ is transmitted.
• LINK shall also direct to disable Loopback path when EDB is received.
• Enabling or disabling Loopback path shall be completed within 20SI after direction from LINK.
Moreover, not only VLD symbols but also STB.H and EIDL shall be bypassed when enabling Loopback
path.
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Figure 5-39 illustrates an entry and exit sequence for DATA Burst Streaming. Suppose that Device#2 is
the target Device in this example.
[b]
Host
Host
Host
TRAN
LINK
PHY
TRAN
LINK
PHY
TRAN
LINK
PHY
Tx
Tx
Target
Rx
Rx
Tx
Rx
EDB
DATA
Tx
Tx
TRAN
LINK
PHY
Device#1
Device#3
Tx
PHY
LINK
TRAN
Rx
STAT
Rx
Device#1
Device#3
Tx
Rx
PHY
LINK
TRAN
Rx
Tx
TRAN
LINK
PHY
Device#1
FCREQ
Rx
Tx
DATA
FCRDY
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Loopback path is
disabled after
detecting EDB
Rx
Device#3
Rx
Tx
Loopback path
is enabled &
LINK starts
monitoring Rx
[c]
PHY
LINK
TRAN
[a]
TRAN
LINK
PHY
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2442
Rx
Tx
Rx
Tx
PHY
LINK
TRAN
PHY
LINK
TRAN
PHY
LINK
TRAN
Device#2
Device#2
Device#2
Figure 5-39 : Packet Handling for DATA Bypassing
In Figure 5-39 [a], as Device#1 is not a target Device, it enters to DATA Burst Streaming mode after it
bypasses FCREQ from its Tx Port. While DATA Burst Streaming mode, DATA Burst is bypassed directly
from Rx to Tx through Loopback path (Figure 5-39 [b]). If Device#1 detects EDB LSS, it exits from the
mode by disabling the Loopback path (Figure 5-39 [c]).
As mentioned in Section 5.4.1, the Valid Transmission Gap between FCREQ transmission and STAT
reception shall be filled with DIDL regardless of the setting of "Power Control Mode in Active.Control
State" in CFG_REG. So, Loopback path is enabled and disabled during DIDL period.
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5.7 Data Integrity
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5.7.1 Overview
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5.7.2 Detection and Notification of CRC Error
2466
5.7.3 CRC16 Generation Polynomial
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5.7.3.1 Overview
The length of CRC for all types of UHS-II packet is fixed to 16bits (CRC16). CRC16 is calculated with all
bits (including reserved bits) of UHS-II packets including PAD (K23.7) if exists. PAD (K23.7) shall be
treated as D23.7 (F7h) in CRC calculation. The generator polynomial is as follows.
All UHS-II packets are added CRC for data integrity. Calculation and verification of CRC are performed
in LINK.
LINK of receiver calculates CRC of incoming packet and compares to its CRC field. When receiver
detects CRC error from at least one DATA packet within DATA Burst, it shall send STAT MSG whose
RECOVERABLE_ERROR = 1 after completing reception of the DATA Burst (Refer to Section 6.2.15.2
for more details). On the other hand, receiver sends nothing if it detects CRC error from packets other
than DATA. Host can detect error by not receiving the expected packet within the predetermined period.
G(X) = X16 + X12 + X5 + 1
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Before starting the CRC16 calculation, the initial value of CRC16 shall be set to 0000h and the CRC16
calculation shall be processed in order from msb to lsb. The result of CRC16 shall be transmitted MSB
first and then LSB.
Figure 5-40 shows a block diagram of CRC16 calculation.
CRC16 polynomial : G(X) = X16 + X12 + X5 + 1
Data in
from msb
to lsb
2479
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2481
X0
X1
X4
X5
X11
X12
X14
X15
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
CRC16 out
Clock
Figure 5-40 : CRC16 Calculation
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5.7.3.2 Example of CRC16 Calculation
Let the input packet containing 4 bytes be as follows (one of FCRDY MSG).
2494
5.7.4 Scrambling
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5.7.4.1 Overview
Both Host and Device shall have scrambling function as mentioned below.
The CRC of a frame is a 2 bytes (16-bit) field that shall follow the last byte of the contents of a Packet
and precede EOP LSS.
The contents of a frame shall be scrambled before transmission.
Scrambling shall be performed by XOR operation on the transmitting data with the output of a linear
feedback shift register (LFSR). The LFSR shall be implemented with the following polynomial:
{a7, a6, ..., a0} = 1111_0001 :
{b7, b6, ..., b0} = 0000_0000 :
{c7, c6, ..., c0} = 0000_0001 :
{d7, d6, ..., d0} = 1000_0000 :
NP = 1, TYP = 111b (MSG), DID=1
SID = 0, TID = 0
CTG = 000b (LMSG), IDX = 0001b (FCRDY)
CODE = 1000000b (UNRECOVERABLE_ERROR)
As the data is input to the CRC16 calculator in the order of a7, a6, ..., a0, b7, ..., d0, the result of
CRC16 calculation is 4B40h. In this case, MSB (4Bh) is transmitted first and LSB (40h) is transmitted
second.
G(X) = X16 + X5 + X4 + X3 + 1
The LFSR shall be initialized with the value of FFFFh before the first shift of the LFSR. The shift register
shall be initialized to the seed value before SOP LSS is transmitted. All data words between the SOP
LSS and EOP LSS shall be scrambled, including the CRC. If PAD (K23.7) is scrambled, the scrambled
PAD data shall be replaced with PAD (K23.7) before transmitting from transmitter.
Figure 5-41 shows a block diagram for LFSR with scrambling polynomial.
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LFSR polynomial : G(X) = X16 + X5 + X4 + X3 + 1
X0
X1
X2
X3
X4
X5
X14
X15
SET
SET
SET
SET
SET
SET
SET
SET
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
Clock
Data in
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2513
b7=H
b6=G
b5=F
b4=E
b3=D
b2=C
b1=B
b0=A
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
Data out
Figure 5-41 : LFSR with Scrambling Polynomial
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5.7.4.2 The Operation Order of CRC, Scrambling and 8b/10b
On the transmitter side, the operation order of CRC, scrambling and 8b/10b shall be as follows. The
CRC calculation shall be applied on the packet data following SOP LSS. The packet data shall be
applied the XOR operation with LFSR output, if the PAD exists in the packet data it shall be replaced
with PAD (K23.7) after the XOR operation of the scrambler. And then, the frame data shall be submitted
to the 8b/10b encoder.
Similarly, on the receiver side, the frame data shall be decoded by a 10b/8b decoder, and the decoded
packet data shall be applied on XOR operation with the scrambler output, if the PAD (K23.7) exists in
the packet data, it shall be reverted to PAD (K23.7) after XOR operation.
And then, the operated packet data presented to the Link layer and subsequently used in calculating the
CRC.
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5.7.4.3 LSS Scrambling
To prevent fixed bit stream repetition, LIDL, DIDL, SYN and BSYN LSS have some variations.
Each LSS consists of 2 symbols, COM = K28.5 symbol and LIDL / DIDL / SYN / BSYN symbol as
described in Section 5.2.2.2.
These second symbols have 2 variations as follows;
LIDL0 / LIDL1 = K28.3 / D16.7
DIDL0 / DIDL1 = K28.6 / D12.2
SYN0 / SYN1 = D31.5 / D26.2
BSYN0 / BSYN1 = D4.5 / D21.2
To ensure randomness of each symbol selection, for example, the selection can be controlled by a
pseudo random bit stream generator.
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SOP
LSS
DAT + CRC
(Scrambled)
LIDL
LIDL
LIDL
or DIDL or DIDL or DIDL
LSS
LSS
LSS
EOP
LSS
LIDL /
DIDL
SOP
LSS
DAT + CRC
(Scrambled)
COM
(K28.5)
LIDL0 (K28.3)
or
LIDL1 (D16.7)
COM
(K28.5)
DIDL0 (K28.6)
or
DIDL1 (D12.2)
SYN
LSS
SOP
LSS
DAT + CRC
(Scrambled)
BSYN
LSS
LIDL
LSS
EOP
LSS
Symbol
SYN
LSS
SYN
LSS
SYN
LSS
Symbol
COM
(K28.5)
SYN0 (D31.5)
or
SYN1 (D26.2)
STB.L
BSYN
LSS
EOP
LSS
SYN
BSYN
LSS
BSYN
LSS
COM
(K28.5)
BSYN0 (D4.5)
or
BSYN1 (D21.2)
LIDL
LSS
LIDL
LSS
BSYN
Symbol
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Figure 5-42 : LSS Scrambling
Application Note:
For the purpose of verification, both Host and Device can have a register in Vendor Unique Register
(described as VU_REG in Section 6.2.1) in order to disable scrambling for contents of packet.
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5.7.4.4 Example of Scrambling Calculation
Let the input packet containing 5 bytes be as follows (DATA packet with 3 byte Payload).
0xB1 :
0x00 :
0xAA :
0xBB :
0xCC :
NP = 1, TYP = 011b (DATA), DID = 1
SID = 0, TID = 0
(Payload0)
(Payload1)
(Payload2)
The output of scrambled data including LSS is as follows.
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Transmission order
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Packet Data
COM
SDB
COM
SDB
COM
SOP
0xB1
0x00
0xAA
0xBB
0xCC
PAD
0xFE
0x1E
COM
EOP
COM
EDB
COM
EDB
Code
K28.5
K28.0
K28.5
K28.0
K28.5
K28.1
D17.5
D0.0
D10.5
D27.5
D12.6
K23.7
D30.7
D30.0
K28.5
K29.7
K28.5
K27.7
K28.5
K27.7
Scramble
pattern
0xFF
0x17
0xC0
0x14
0xB2
0xE7
0x02
0x82
Scrambled
Data
COM
SDB
COM
SDB
COM
SOP
0x4E
0x17
0x6A
0xAF
0x7E
PAD
0xFC
0x9C
COM
EOP
COM
EDB
COM
EDB
Scrambled
Code
K28.5
K28.0
K28.5
K28.0
K28.5
K28.1
D14.2
D23.0
D10.3
D15.5
D30.3
K23.7
D28.7
D28.4
K28.5
K29.7
K28.5
K27.7
K28.5
K27.7
Table 5-13 : Example of Scrambling
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5.8 Packet Receiving Flow Chart
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5.8.1 Overview
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5.8.2 Top Level Flow Chart
This section describes how to handle all received packets in LINK. LINK shall determine whether the
received packet needs to be certainly processed or to be discarded in accordance with the rule
described below.
Figure 5-43 illustrates a top level flow chart for control packet or DATA Burst reception.
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EI DL
(Pulled-up)
(1) Exiting from EI DL
& Symbol locked
Unexpected I dle State
(2) SOP/ SDB
Detection
SDB
SOP
(3) Flow Control Check
(FCRDY issued ?)
NO
YES
(4) Control Packet
Reception (CPR)
(5) DATA Burst
Reception (DBR)
Framing Error
(FRAME_ERROR)
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Figure 5-43 : Top Level Flow Chart for Starting Packet Reception
(1) LINK of receiver side can start receiving a packet only after Rx exits from EIDL and establishes its
symbol lock.
(2) During SOP/SDB Detection step, all incoming symbols are discarded until SOP LSS or SDB LSS is
detected. If the receiver side detects at least one of the two SDB LSSes, it moves to Flow Control
Check step (3). On the other hand if it detects SOP LSS, it moves to Control Packet Reception
(CPR) step (4) and the following packet is regarded as a control packet.
(3) During Flow Control Check step, the receiver side needs to check if Flow Control handshake is
already completed (FCRDY has been issued). If that condition is satisfied (YES), each of the
following packets before receiving EDB LSS can be received as a DATA packet in DATA Burst
Reception (DBR) step (5), and all of them form a DATA Burst. In this step, the receiver side only
considers the packet whose DID is the same as its own Node ID. For, the DATA Burst whose
destination is other Device are bypassed in the CPR step (4) based on the rule of DATA Burst
Streaming described in Section 5.6.3.
Detailed flow charts for CPR (4) and DBR (5) are described in Section 5.8.3 and Section 5.8.4
respectively.
LINK of receiver can detect EOP corruption by an unexpected LIDL or EIDL (unexpected Idle State). For
EDB corruption, Host and Device can detect EDB corruption as the following method (also refer to
Section 6.3 for timing parameters such as Tfcrdy_edb).
• Host detects EDB corruption by Tfcrdy_edb timeout in read transaction, or Tedb_stat timeout in
write transaction.
• Then Host transmits LIDL or EIDL according to the setting of "Power Control Mode in
Active.Control State".
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• Device receives the unexpected Idle State by receiving the LIDL or EIDL mentioned above, and
detects EDB corruption as a result.
When receiving the unexpected Idle State, the receiver side regards it as Framing Error
(FRAME_ERROR) and executes step (2) again. Moreover, it may notify errors detected in DBR step to
the DATA initiator by STAT MSG when exiting from DBR step.
5.8.3 Control Packet Reception Flow Chart
Figure 5-44 illustrates a Control Packet Reception Flow Chart. Note that the handlings of conditions not
described in this section are implementation matter.
Control Packet Reception
(CPR) Start
SOP/ CP_OVF
(1) EOP Detection
EOP
Error
(2) CRC Check
Error
(3) Header Check
(TYPE-1)
Bypass
Accept
(7) Bypass Received Packet
YES
(4) Error Occurred ?
(8) Bypassed Packet
is FCREQ ?
NO
YES
NO
(5) Accept Received Packet
(9) DATA Burst Streaming
(6) Discard Received Packet
Control Packet Reception
(CPR) End
Framing Error (FRAME_ERROR)
incl. Control Packet Overflow (CP_OVF)
2605
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2607
2608
2609
2610
2611
2612
2613
CRC Error
(CRC_ERROR)
Header Check Error
(HEADER_ERROR)
Figure 5-44 : Control Packet Reception Flow Chart
(1) LINK of receiver side starts to buffer incoming byte stream until it detects EOP LSS and
calculates its CRC. When the buffering size exceeds maximum length of control packet, it causes
control packet overflow (CP_OVF). As CP_OVF is typically occurred as a result of EOP
corruption, it is categorized as FRAME_ERROR.
(2) In this step, calculated CRC is compared with CRC field of the received packet. If the receiver
side fails CRC check, (in other words, it detects CRC_ERROR), it will discard the packet in step
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(6). Otherwise, it can move to Header Check (TYPE-1) step (3) because Header of the packet is
reliable.
(3) In this step, Header of the packet is analyzed in accordance with the prioritized conditions shown
in Table 5-14. Note that errors detected during Header Check are categorized as
ILLEGAL_HEADER_ERROR.
(4) The receiver side checks error occurrence from step (1) to (3) which corresponds to any of
FRAME_ERROR, CRC_ERROR, or ILLEGAL_HEADER_ERROR.
(5) If it does not detect any errors in step (4), it accepts the packet.
(6) Otherwise, it discards the packet in this step.
(7) The result of Header Check (step (3)) is "Bypass in LINK" (refer to Table 5-14), it bypasses the
received packet.
(8) If the bypassed packet is not FCREQ MSG, it completes CPR.
(9) Otherwise, it transfers the received packet with DATA Burst streaming described in 5.6.3.
Prioritized
Condition
Number
0
1
2
3
4
5
2628
2629
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2633
2634
2635
2636
Header of Received Packet Results of Header Check
Note
Bypass
TYP
SID
DID
Accept
Error
in LINK
At least either
Host shall remove a packet

one is unused
which has unused ID.
DATA packet is unexpected in

DATA
CPR.
Broadcast CCMD is

CCMD
SID = DID
bypassed in CM-TRAM.
Other than = Own
Issued packet is not received

DATA
ID
in all other Devices.
Other than
!= Own
Packet is targeted to other

DATA
ID
Device.
Other than
= Own
Packet is targeted to own

DATA
ID
Device.
Table 5-14 : Header Check (TYPE-1)
If LINK receives SOP during CPR for any packets, it discards the former packet and starts again the
CPR flow for the packet following the recently received SOP.
5.8.4 DATA Burst Reception Flow Chart
Figure 5-45 illustrates a DATA Burst Reception Flow Chart. Note that the handlings of conditions not
described in this section are implementation matter.
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DATA Burst Reception
(DBR) Start
EDB
(1) SOP/ EDB Detection
SOP
SOP/ DP_OVF
(2) EOP Detection
EOP
Error
(3) CRC Check
Error
(4) Header Check
(TYPE-2)
No Error
YES
(5) Error Occurred ?
NO
(6) Accept Received Packet
(7) Discard Received Packet
DATA Burst Reception
(DBR) End
Framing Error (FRAME_ERROR)
incl. DATA Packet Overflow (DP_OVF)
2637
2638
2639
2640
2641
2642
2643
CRC Error
(CRC_ERROR)
Header Check Error
(I LLEGAL_HEADER)
Figure 5-45 : DATA Burst Reception Flow Chart
(1) LINK of receiver side starts detecting SOP or EDB LSS. If at least one EDB is detected in this
step, then DBR is completed.
(2) If SOP is detected in step (1), LINK of receiver side starts to buffer incoming byte stream until it
detects EOP LSS and calculates its CRC. When the buffering size exceeds MAX_BLKLEN
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defined in CFG_REG, it causes DATA packet overflow (DP_OVF). As DP_OVF is typically
occurred as a result of EOP corruption, it is categorized as FRAME_ERROR.
(3) In this step, calculated CRC is compared with CRC field of the received packet. If the receiver
side fails CRC check, (in other words, it detects CRC_ERROR), it discard the packet in step (7).
Otherwise, it can move to Header Check (TYPE-2) step (4) because Header of the packet is
reliable.
(4) In this step, Header of the packet is analyzed in accordance with the prioritized conditions shown
in Table 5-15. Note that errors detected during Header Check are categorized as
ILLEGAL_HEADER_ERROR. Note that DATA packet whose destination is other Device shall be
handled as ILLEGAL_HEADER_ERROR because it shall be bypassed as the rule of DATA Burst
Streaming shown in step (9) of CPR.
(5) The receiver side checks error occurrence from step (2) to (4) which corresponds to any of
FRAME_ERROR, CRC_ERROR, or ILLEGAL_HEADER_ERROR.
(6) If it does not detect any errors in step (5), it accepts the packet.
(7) Otherwise, it discards the packet in this step.
Prioritized
Condition
Number
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Header of Received Packet Results of Header Check
Bypass
TYP
SID
DID
Accept
Error
in LINK
0
Other than
DATA
-
-

1
DATA
-
!= Own
ID

2
DATA
-
= Own
ID

Note
Control packet is unexpected
in DBR in UHS-II Addendum
Version 1.00 or later.
DATA packet shall be
bypassed by DATA Burst
Streaming in CPR.
Issued packet is not received
in all other Devices.
Table 5-15 : Header Check (TYPE-2)
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5.9 Details of Boot Code Loading
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5.9.1 LINK State Transition during Wakeup including Boot Device (Ring Connection)
It is optional to have a Boot Device in the UHS-II system. But all Devices shall support state transitions
and packet bypassing considering Boot Code Loading. Moreover, the system can include at most one
Boot Device.
In this section, explanation of Wakeup in Ring topology is based on Figure 5-46. In this example,
Device#2 is supposed to the Boot Device.
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Host
Tx Rx
Line A
Line C
Line B
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Rx Tx
Device#1
Device#2
Boot Device
Figure 5-46 : Ring Connection Including a Boot Device
Figure 5-47 illustrates a LINK state transition during Wakeup for Ring Connection including Boot Device
described Figure 5-46., Only FCREQ is appeared in Figure 5-47, but in fact, flow control described in
Section 5.5 is taken place during Boot Code transmission.
T1
time
RCLK
EIDL
Line A
EIDL
Line B
Host
Device#1
Device#2
DLSM
T3
T2
T4
T5
T5' T6
T8 T9
T7
T10
T11
T12
T13
RCLK Active
STB.L
EIDL
Line C
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Rx Tx
BSYN BSYN BSYN BSYN BSYNBSYNBSYN BSYN LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL SOP STAT
BSYN BSYNBSYN BSYN LIDL LIDL LIDL LIDL LIDL SOP
STB.L
Wakeup
Dormant
Activate
DLSM
Dormant
PLL
(MUL)
Before
Activation
EOP LIDL
BSYNBSYN BSYN BSYN BSYN BSYN LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL
STB.L
EIDL
LIDL SOP Broadcast
CCMD
Config
Sync
Boot
Code
EDB DIDL DIDL DIDL
LIDL LIDL LIDL LIDL LIDL LIDL LIDL
Active
Control
(Config g) Active
Control
Wakeup
Activate
Sync
During Lock Acquisition
FCREQ
Config
After Lock Acquisition
DLSM
Dormant
Wakeup
Activate
PLL
(MUL)
Before
Activation
During Lock Acquisition
(Config g) Active
Control
Sync
After Lock Acquisition
Period for Boot Code Preparation (Example)
Period for Boot Code Loading
Figure 5-47 : LINK State Transition during Wakeup when Including a Boot Device
T1: LINK of Host starts to provide RCLK, drives Tx to STB.L. As a result, DLSM of Host transits to
Wakeup.Activate state.
T2: When Device#1 receives STB.L, it starts PLL lock acquisition and responds by driving Tx drives to
STB.L. Note that Device#1 shall respond STB.L within Teidl_stb. As a result, DLSM of Device#1 transits
to Wakeup.Activate state.
T3 When Device#2 (Boot Device) receives STB.L, it starts PLL lock acquisition and may also start Boot
Code Preparation. Then it responds by driving Tx drives to STB.L and enters to Wakeup.Activate state.
Note that Device#1 shall respond STB.L within Teidl_stb.
T4: If Host receives STB.L LINK of Host starts to send BSYN LSS immediately for LINK synchronization
and Boot Code Loading direction, and its state transits to Wakeup.Sync.
T5: If Device#1 successfully receives BSYN LSS after PLL lock, Device#1 starts to send BSYN LSS to
Device#2 and its state transits to Wakeup.Sync. Note that Device#1 shall complete PLL lock within
Tactivate after transiting to Wakeup state.
T5': Same as T5' for Device#2.
T6: If Host can receive BSYN LSS from Device#2, it makes DLSM to Config (not Active because it has
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not received LIDL or EIDL yet), and it starts to send LIDL LSS.
T7: If Device#1 successfully receives LIDL LSS, it starts to send LIDL LSS within Tlidl_lidl. Moreover, it
shall set "Config Completion" to 1 and "Power Control Mode in Active.Control State" to 0 respectively
before sending LIDL. As a result, its DLSM transits to Active.Control state.
T8: If Device#2 successfully receives LIDL LSS, it starts to send LIDL LSS within Tlidl_lidl. Moreover, it
shall set "Config Completion" to 1 and "Power Control Mode in Active.Control State" to 0 respectively
before sending LIDL. As a result, its DLSM transits to Active.Control state.
T9: Host shall set "Config Completion" to 1 and "Power Control Mode in Active.Control State" to 0
respectively by receiving LIDL. As a result, if Host successfully receives LIDL LSS, its DLSM transits to
Active.Control state."
T10: When Device#2 completes Boot Code Preparation, it loads a temporal Node ID for Boot Code
Loading (which is one of numbers from 1 to 14 and preset by system designer) and sends FCREQ to
start Flow Control for transmitting Boot Code to Host. Note that Boot Device shall send FCREQ within
Tlidl_fcreq_boot after transmitting the first LIDL LSS.
T11: When Host receives the final Boot Code from Device#2, Host transmits STAT for the final DATA
Burst (Boot Code).
T12: Host issues broadcast write CCMD to set "Config Completion" to 0 for all Devices and Host.
T13: When Device#1 receives the broadcast CCMD mentioned above, it makes DLSM to Config state
before transmitting the command to Device#2. Note that also Device#2 and Host execute the same
operation when receiving the broadcast CCMD.
During Wakeup state, Host can transmit either SYN or BSYN LSS alternatively depending on execution
of Boot Code Loading or not.
5.9.2 Protocol for Boot Code Transmission
Boot Code is transmitted from Boot Device to Host with similar manner using Flow Control, but
differences are as follows.
• There is no CMD-RES handshake, so the trigger of Boot Code transmission is done by sending
FCREQ from Boot Device.
• During the Boot Code transmission, Node ID for Host and Non-boot Device are 0 and 15
respectively. On the other hand, that for Boot Device is assigned a value from 1 to 14 as a
temporal Node ID preset by system designer. Such Node IDs for Device are cleared and set again
by Enumeration process.
• NP is 1 and TID is 0 for all MSG and DATA packets during Boot Code Loading.
Parameters for Boot Code transmission are described in Table 5-16. For the recommended values,
Host may use optimized values for Boot Code Loading between specific Host and Boot Device.
Parameter
Block Length (MAX_BLKLEN)
N_FCU
MAX_RETRY_NUM
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Value
512 bytes (mandatory)
1 (recommended)
3 (recommended)
Table 5-16 : Parameters for Boot Code Transmission
If Host detects errors from DATA Burst of Boot Code, DATA Burst retry is also taken place by notifying
errors with STAT MSG. Furthermore, CCMD cannot be issued until Boot Code Loading completes.
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The details of UHS-II protocol including packet format, Configuration, state machine, initialization and
flow control are described in this chapter.
6.1 Transaction Layer Overview
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SD-TRAN
( SD specific)
Application
specific layer
Figure 6-1 shows the overview of Transaction Layer.
Transaction
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6. Transaction Layer Specification
CM-TRAN
( Common layer)
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SD CMD/ RES/ DAT
SD Card Register
* * -TRAN
( extensible TRAN for future use)
SD State Machine
Protocol Bridge (SD< -> CM)
Tran Management
Transactions (Data, Control)
Extended Part
TPSM
Enumeration
CMD Queuing
TBSM
Configuration
Relaxed Ordering
TSSM
Common Packets (DCMD, CCMD, RES, DATA)
I D based Mux/ Demux
Figure 6-1 : Transaction Layer Overview
The key features of Transaction Layer are defined as follows:
• New packet based protocol considering Legacy SD compatibility
• ID based routing for multiple device connectivity
• CM-TRAN for common architecture between Host and Device
Transaction Layer consists of two sub-layers called CM-TRAN (lower sub-layer) and application specific
layer including SD-TRAN (upper sub-layer). This layering is intended to define the common part of
TRAN (CM-TRAN) between Host and Device. As a result, the same CM-TRAN can be used in both
Host and Device side.
CM-TRAN provides basic functions to realize transactions on UHS-II native protocol.
CM-TRAN components are the following;
• Generating UHS-II common packets and processing
• Configuration mechanism
• Transaction management supporting multiple device connection
• Future extension support (e.g. CMD Queuing)
CM-TRAN is also defined to be the common sub-layer between all application specific layers in order to
realize UHS-II specific functions (e.g. multiple device connection, CMD Queuing, etc.) with application
specific protocol.
For example, in Figure 6-1, CM-TRAN can provide SD protocol with a CMD Queuing feature as a future
extension.
SD-TRAN is an application specific layer for compatibility with SD protocol and preserves the same
state machine and registers as Legacy SD protocol. SD-TRAN works as a protocol bridging between
Legacy SD and UHS-II native protocol. (Refer to Chapter 7 for details of SD-TRAN.)
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Other application specific layers (**-TRAN) can be defined for future extension.
In Chapter 6, the details of CM-TRAN are presented.
6.1.1 Packet Types and Format Overview
Figure 6-2 illustrates the Transaction Layer Packet (TLP) types and format overview.
CCMD
Argument
Argument
Header
Header R/W PLEN
Payload
Payload
(only
(only write
write CCMD)
CCMD)
I/O
I/O Address
Address
R/W PLEN
PLEN
DCMD
Header
Header R/W
RES
Header
Header NACK
R/W
NACK
Extended
Extended Argument
Argument
Argument
Argument
TMODE
TMODE
Rsvd
Rsvd
Data
Data Address
Address
Argument
Argument
TLEN
TLEN
Payload
Payload
CMD_ECHO_BACK
CMD_ECHO_BACK
(only
(only read
read CCMD)
CCMD)
PLEN
DATA
Header
Header
: Packet Type
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Payload
Payload
: Existence depends on transaction type
Notes
PLEN : Length of payload field in CCMD or RES
TMODE : Transfer mode to represent detailed transfer settings
TLEN : Transfer Length (total length of data transmitted during a transaction)
CMD_ECHO_BACK : Argument of the preceding CMD is copied
Figure 6-2 : TLP Format Overview
In Transaction Layer, four TLP types are defined to realize Legacy SD-compatible protocol and new
functions of UHS-II native protocol.
• CCMD (Control CMD): control command packet for accessing to control registers in I/O space
• DCMD (Data CMD): data command packet for transferring data
• RES (Response): response packet associated with CCMD or DCMD
• DATA (Data payload): packet for data transmission
TLP consists of Header, Argument and Payload.
Each type of TLP shall have a common "Header". Header includes ID fields for packet identification and
routing information. "Argument" is used for setting supplementary information such as data length
(PLEN, TLEN), address information (I/O address, data address) and other information exchanged
between Host and Device (TMODE). Only DCMD has "Extended Argument" for setting more information
about data length and address. "Payload" is the field for setting data payload to be transmitted.
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Argument in CCMD includes read/write flag, I/O address and payload length (PLEN) field. In the case of
write CCMD, PLEN represents the length of write data which is assigned in Payload of CCMD. In the
case of read CCMD, PLEN basically represents the length of read data which is assigned in Payload of
the following RES.
Argument in DCMD includes read/write flag and transfer mode (TMODE) for representing detailed
transfer settings such as Length Mode (TLEN is specified or not), TLEN Unit Mode (Block Mode or Byte
Mode), etc.
Extended Argument includes transfer length (TLEN) field if Length Mode in TMODE is set to "TLEN is
specified". TLEN represents the total length of data to be transmitted by a DCMD.
Extended Argument in DCMD also includes data address (DADR). The unit of data address is specified
in Data Access Mode (DAM) in TMODE field. DAM also specifies which address space is to be
accessed (refer to DAM explanation in Section 6.2.2.4).
Argument in RES is set to the same value as Argument in the corresponding CMD except read/write
flag (command echo back). NACK field shows whether the associated CMD has an error or not. Only
the case of CCMD read transaction, Payload field in RES exists and its size is shown by PLEN.
Figure 6-3 shows the basic concept of control transaction and data write/read transaction sequence.
Host
D0
D1
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Device
CCMD
(Write)
CCMD
(Read)
DCMD
DATA
(Write)
RES
RES
Control
Trans. (Write)
Control
Trans. (Read)
DCMD
D0
(Read)
RES
RES
DATA
Data Transaction (Write)
Data Transaction (Read)
D1
Time →
Figure 6-3 : Control Transaction and Data Transaction Sequence
The sequences of control transaction and data transaction are defined as follows;
• Control Transaction:
CCMD -> RES (without DATA packet)
• Broadcast control transaction does not bring RES.
• Data Transaction:
DCMD -> RES -> DATA
Control transaction is performed for accessing to UHS-II I/O Registers such as Configuration Register,
Command Register and so on, and consists of CCMD from Host and RES from Device. Note that
broadcast control transaction does not accompany RES, and the transaction completes when Host
receives broadcast CCMD. Special CCMDs such as FULL_RESET or TRANS_ABORT are defined in
Command Register (refer to Section 6.2.12).
Data transaction is performed for transferring data, and consists of DCMD from Host, RES from Device
and DATA from Host or Device. Flow control shall be executed during data transaction.
After issuing a CMD, Host shall not issue all types of packet until RES is received
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6.2 Transaction Layer Protocol
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6.2.1 UHS-II I/O Space and Memory Address Space
Two types of address spaces are defined.
• UHS-II I/O space: Address space for UHS-II I/O Registers expressed by 14bit address number.
• Memory address space: Logical address for the memory Device.
Figure 6-4 shows the layout of UHS-II I/O space.
Vendor Unique
Register
(VU_REG)
VU_BASE
(Reserved)
Command
Register
(CMD_REG)
CMD_BASE
ST_BASE
UHS-II I/O
space
INT_BASE
Status
Register
(ST_REG)
Interrupt
Register
(INT_REG)
Configuration
Register
(CFG_REG)
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IOSPACE_BASE
= 0000h
(Reserved)
Preset
Settings
Capabilities
CFG_BASE
Figure 6-4 : UHS-II I/O Space Layout for Device
UHS-II I/O space consists of Configuration Register (CFG_REG), Interrupt Register (INT_REG), Status
Register (ST_REG), Command Register (CMD_REG) and other areas including Vendor Unique
Register (VU_REG). Host can access to the registers described below only by a CCMD.
• Configuration Register (CFG_REG): Register to assign device-dependent capabilities and
determined operating settings during Configuration.
• Interrupt Register (INT_REG): Register for realizing interrupt.
• Command Register (CMD_REG): Register to assign UHS-II CCMDs (e.g. reset, abort, etc.)
• Vendor Unique Register (VU_REG): Register to be defined by vendors individually.
Register area indicated by "Reserved" means that it is initialized to zero and writing operation to them is
ignored. The followings are Device behavior when accessed to its Reserved bit including bits inside
CMD_REG.
• P2P CCMD Read: Device shall issue RES with NACK=0 and its Payload field corresponding to
the reserved bit is set to 0.
• P2P CCMD Write: Device shall issue RES with NACK=0 and value of reserved bit is not changed.
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• Broadcast CCMD Write: Device shall forward broadcast CCMD to the next node, and value of
reserved bit is not changed.
Table 6-1 shows the map of UHS-II I/O space. Offset means the relative address based on
IOSPACE_BASE = 0000h.
Offset
Byte address
IOADR
0000h : 03FFh
000h : 0FFh
0400h : 05FFh
100h : 17Fh
0600h : 07FFh
180h : 1FFh
0800h : 0BFFh 200h : 2FFh
0C00h : 3BFFh 300h : EFFh
3C00h : 3FFFh F00h : FFFh
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Register
Configuration Register (CFG_REG)
Interrupt Register (INT_REG)
Status Register (ST_REG)
Command Register (CMD_REG)
Reserved
Vendor Unique Register (VU_REG)
Table 6-1 : I/O Address Space Map
During Configuration, CFG_REG values are negotiated between Host and Device by CCMDs. Refer to
Section 6.2.8 for details of Configuration procedure.
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6.2.2 Packet Format Details
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6.2.2.1 Header
Refer to Section 5.2.3 for details of Header structure.
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6.2.2.2 CCMD
Figure 6-5 illustrates CCMD structure.
In this section, msb denotes "most significant bit", lsb denotes "least significant bit" respectively. (Notice
that they are different from MSB or LSB.) Moreover, smaller byte in a packet is transmitted first
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Bit
Byte
7
6
5
4
3
2
0
Header
1
(NP=1, Packet Type = CCMD)
2
R/W Rsvd
PLEN
1
IOADR
(msb)
IOADR
3
0
(lsb)
[4
:
[Payload]
:
]
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Header
Argument
Payload
Figure 6-5 : CCMD Format
• R/W (Read/Write): Indicator for representing read or write command.
• 0: Control read command
• 1: Control write command
• PLEN[1:0] (Payload Length): Length of payload field in CCMD or RES.
• PLEN field represents the length of payload field in CCMD or RES (Definition of PLEN is
shown in Table 6-2)
• In the case of write CCMD (R/W = 1), PLEN represents the length of write data which is
assigned in Payload of CCMD.
• In the case of read CCMD (R/W = 0), PLEN represents the length of read data which is
assigned in Payload of the following RES.
• IOADR[11:0] (I/O Address): Address of register in UHS-II I/O space accessed by CCMD.
• The unit of IOADR is 4 bytes. So quadruple of IOADR represents the absolute address in
UHS-II I/O space.
• It is transmitted in msb first, lsb last.
• Payload: Write data included with CCMD.
• The length of payload field is assigned in PLEN.
• In the case of read CCMD (R/W = 0), Payload field does not exist.
• In the case that PLEN is set to "00b" (payload length is 0 byte), Payload field does not
exist.
• The Payload field is divided into a unit of DWORD (4byte data), and the transmission
order within a DWORD is big endian. Refer to Figure 6-6 and Figure 6-7 for details of the
transmission order of Payload. In these figures, bracketed numbers denote the bit order
within a DWORD.
• Rsvd (Reserved): Reserved bits. Initiator shall set them to '0', and receiver shall ignore them.
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PLEN[1:0]
00b
01b
10b
11b
Payload Length
0 byte
4 bytes
8 bytes
16 byte
Table 6-2 : Definition of PLEN
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Bit
Byte
7
6
5
4
3
2
0
Header
1
(NP=1, Packet Type = CCMD)
2
R/W Rsvd
3
4
PLEN=01b
(msb)
0
IOADR
IOADR = X
[31]
1
(lsb)
[30]
5
[Payload: DWORD to IOADR X]
6
7
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[0]
Header
Argument
Payload
Figure 6-6 : Transmission Order of Payload in CCMD (PLEN = 01b)
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Bit
Byte
7
6
5
4
3
2
0
Header
1
(NP=1, Packet Type = CCMD)
2
R/W
Rsvd
3
4
PLEN=11b
(msb)
0
IOADR
IOADR = X
[31]
1
(lsb)
[30]
5
[Payload: DWORD to IOADR X]
6
7
8
[0]
[31]
[30]
9
[Payload: DWORD to IOADR X+1]
10
11
12
[0]
[31]
[30]
13
[Payload: DWORD to IOADR X+2]
14
15
16
17
[0]
[31]
[30]
[Payload: DWORD to IOADR X+3]
18
19
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[0]
Header
Argument
Payload
Figure 6-7 : Transmission Order of Payload in CCMD (PLEN = 11b)
In the case of application specific protocol (NP = 0), the definition of payload field existence may be
different from the case of native protocol (NP = 1). Refer to Section 7.2.1.1 for details of CCMD format
for SD application.
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6.2.2.3 Broadcast CCMD
Broadcast CCMD operates to all Devices on the bus. On the other hand, CCMD that operates to a
specified Device shown by DID is P2P CCMD.
In case of broadcast commands each Device may either transfer commands transparently (e.g.
GO_DORMANT_STATE) or make some modifications to the continuing command to the following Node
(e.g. ENUMERATE).
Features of broadcast CCMD are as follows.
• Broadcast CCMD issued by Host is represented as DID = SID = 0. In UHS-II Addendum Version
1.XX, broadcast packet is only permitted whose TYPE is CCMD and DID = SID = 0.
• If R/W = 1, broadcast CCMD writes content in its payload to the address in UHS-II I/O space
calculated from IOADR for all connected Devices.
• Basically, broadcast CCMD with R/W = 0 is not available, but INQUIRY_CONFIG described in
Section 6.2.8.3 is admitted as a special case of broadcast read CCMD. In this case, PLEN
represents its payload length even if R/W = 0.
• Each Device shall process broadcast CCMD though DID is not equal to its own Node ID, and
transmit it to the next Device or Host.
• Broadcast CCMD does not accompany RES. So if Host receives broadcast CCMD, Host shall
terminate its transaction.
• If a Device detects some error from broadcast CCMD, it shall not transmit to the next Device or
Host. In this case, Host can detect the error by timeout.
Note that the broadcast command behavior is the same for all topologies. In case of Hub topology the
Hub shall emulate a Ring topology in a way that the CCMD shall be transferred in a serial manner
passing the CCMDs between the Devices through the Hub.
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2957
2958
6.2.2.4 DCMD
Figure 6-8 illustrates DCMD structure.
Bit
Byte
7
6
5
4
0
1
0
Header
R/W
TMODE
Rsvd
Rsvd
3
4
2
(NP=1, Packet Type = DCMD)
1
2
3
(msb)
5
DADR
6
7
8
(lsb)
(msb)
9
[TLEN]
10
(lsb)
11
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
Header
Extended Argument
Argument
Figure 6-8 : DCMD Format
• R/W (Read/Write): Indicator for representing read or write command.
• 0: Data read command
• 1: Data write command
• TMODE[3:0] (Transfer Mode): Parameter settings for data transaction. (Refer to Figure 6-9 and
Table 6-3.)
• DM (Duplex Mode): Duplex mode selection of data transfer associated with DCMD
• LM (Length Mode): Indicator whether TLEN is specified or not
• TLUM (TLEN Unit Mode): Indicator for unit of TLEN
• DAM (Data Access Mode): Data access mode selection.
3
2
DM
LM
1
0
TLUM DAM
TMODE
Figure 6-9 : TMODE Parameters
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2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
• DM (Duplex Mode):
• 0: FD mode
• 1: 2L-HD mode
• If Host issues DCMD with DM = 1 to Device which does not support 2L-HD mode, Device
returns RES with NACK = 1.
• LM (Length Mode):
• 0: Data transfer length is not specified (TLEN field does not exist).
• 1: Data transfer length is specified (TLEN field exists).
• TLUM (TLEN Unit Mode):
• 0: Block Mode
• 1: Byte Mode
• In case of TLUM = 1, LM shall be equal to 1. If TLUM = 1 and LM = 0, the DCMD shall be
handled as an illegal command and RES (NACK = 1) with ARG_ERR is responded (refer
to Section 6.2.2.6).
• In case of DM = 1, TLUM shall be equal 0. If DM = 1 and TLUM = 1, the DCMD shall be
handled as an illegal command and RES (NACK = 1) with ARG_ERR is responded.
• DAM (Data Access Mode):
• 0: Data access with incrementing the address by 1. In this case, DADR represents
address in memory space address and unit of DADR is a block.
• 1: Data access to fixed address, which is used in multiple data transfer to the same
address like FIFO memory access. In this case, DADR represents address for specified
UHS-II I/O address space to support FIFO memory access and unit of DADR is a byte.
• In the case that DAM = 1 and DADR is not for FIFO memory access, the DCMD shall be
handled as an illegal command and RES (NACK = 1) with ARG_ERR is responded. On
UHS-II Addendum Version 1.00 or later, as there are no fields to support FIFO memory
access in the UHS-II I/O space, DCMD cannot access to UHS-II I/O space.
• DADR[31:0] (Data Address): data address in memory address space or I/O address space
accessed by DCMD according to DAM.
• In the case of DAM=0, DADR is for memory address space and its unit is a block.
• In the case of DAM=1, DADR is for UHS-II I/O address space and its unit is a byte.
• It is transmitted in msb first, lsb last.
• TLEN[31:0] (Transfer Length): Total length of data transmitted during a data transaction (unit
depends on TLUM field setting).
• In the case that LM = 0 (data transfer length is not specified), TLEN field does not exist.
• In the case of TLUM = 0 (Block Mode):
TLEN field represents the data length within the range of 1 to (4G – 1) blocks.
If TLEN = 0000000h, it does not effect the data transaction (same as LM = 0).
• In the case of TLUM = 1 (Byte Mode):
TLEN field represents the data length.
Note that TLEN shall be smaller than or equal to Block Length.
If TLEN = 0000000h, it is regarded same as LM = 0, and becomes ARG_ERR as a result.
• It is transmitted in msb first, lsb last.
• Rsvd (Reserved): Reserved bits. Initiator shall set them to '0', and receiver shall ignore them.
Table 6-3 shows availability of TMODE. Marks in 'Availability' column mean as follows.
• X: TMODE is available.
• -: TMODE is not available.
• -(1): TMODE is not available in UHS-II Addendum Version 1.00 or later. (It is subject to change in
the future specification.)
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DM
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TMODE
LM
TLUM
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
AvailDAM ability
0
X
1
-(1)
0
1
0
X
1
-(1)
0
X
1
-(1)
0
X
1
-(1)
0
1
0
X
1
-(1)
0
1
-
FD mode, No TLEN, Block Mode, Memory Access
DCMD cannot access I/O space in Version 1.00 or lator
TLEN shall be specified in Byte Mode
TLEN shall be specified in Byte Mode
FD mode, TLEN, Block Mode, Memory Access
DCMD cannot access I/O space in Version 1.00 or lator
FD mode, TLEN, Byte Mode, Memory Access
DCMD cannot access I/O space in Version 1.00 or lator
2L-HD mode, No TLEN, Block Mode, Memory Access
DCMD cannot access I/O space in Version 1.00 or lator
TLEN shall be specified in Byte Mode
TLEN shall be specified in Byte Mode
2L-HD mode, TLEN, Block Mode, Memory Access
DCMD cannot access I/O space in Version 1.00 or lator
Byte Mode is not available in 2L-HD mode
Byte Mode is not available in 2L-HD mode
Table 6-3 : Availability of TMODE
3026
3027
3028
3029
3030
Remark
6.2.2.5 RES (NACK = 0)
Figure 6-10 illustrates the RES (NACK = 0) structure.
Bit
Byte
7
6
5
4
3
2
0
Header
1
(NP=1, Packet Type = RES)
2
NACK=0
1
0
CMD_ECHO_BACK
(Argument of CMD is copied here)
3
[4
:
[Payload]
:
]
3031
3032
3033
3034
3035
3036
3037
Header
Argument
Payload
Figure 6-10 : RES (NACK = 0) Format
• NACK (Negative Acknowledgement): Indicator whether the corresponding CMD is accepted or
not.
• 0: The corresponding CMD is accepted.
• 1: The corresponding CMD is rejected.
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3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
•
In the case of NACK = 0 (CMD is accepted), the requested operation is in execution or
waiting for execution.
• In the case of NACK = 1 (CMD is rejected), the requested operation is not in execution
(an error has occurred in the corresponding CMD).
• Refer to Section 6.2.2.6 for details of RES with NACK = 1.
• CMD_ECHO_BACK[14:0] (Command Echo Back): Copied field of CMD Argument.
• The same values in Argument field are copied from the corresponding CMD (echo back).
Specifically, [6:0] in the second byte, and [7:0] in the third byte of CMD packet are copied
to the same location of RES packet.
• Payload: Read data for control read transaction.
• The length of payload field is assigned in PLEN of the corresponding read CCMD.
• In the case that PLEN of the CCMD is set to "00b" (payload length is 0 byte), Payload
field does not exist.
• In the case that write CCMD is issued, Payload field in RES does not exist.
• In the case that DCMD is issued (data transaction), Payload field in RES does not exist.
• The Payload field is divided into a unit of DWORD (4byte data), and the transmission
order within a DWORD is big endian. Refer to Figure 6-11 and Figure 6-12 for details of
the transmission order of Payload. In these figures, bracketed numbers denote the bit
order within a DWORD.
Bit
Byte
7
6
5
4
3
2
0
Header
1
(NP=1, Packet Type = RES)
2
NACK=0
[31]
0
CMD_ECHO_BACK
(PLEN=01b, IOADR=X)
3
4
1
[30]
5
[Payload: DWORD from IOADR X]
6
7
3058
3059
3060
[0]
Header
Argument
Payload
Figure 6-11 : Transmission Order of Payload in RES (NACK = 0, PLEN = 01b)
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Bit
Byte
7
6
5
4
3
2
0
Header
1
(NP=1, Packet Type = RES)
2
NACK=0
[31]
0
CMD_ECHO_BACK
(PLEN=11b, IOADR=X)
3
4
1
[30]
5
[Payload: DWORD from IOADR X]
6
7
8
[0]
[31]
[30]
9
[Payload: DWORD from IOADR +1]
10
11
12
[0]
[31]
13
[30]
[Payload: DWORD from IOADR X+2]
14
15
16
17
[0]
[31]
[30]
[Payload: DWORD from IOADR X+3]
18
19
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
[0]
Header
Argument
Payload
Figure 6-12 : Transmission Order of Payload in RES (NACK = 0, PLEN = 11b)
DID field in Header of RES is set to the same value as SID field in Header of the corresponding
command. TID field in Header is set to the same value as TID field in Header of the corresponding
command.
In the case of application specific protocol (NP = 0), the definition of payload field existence may be
different from the case of native protocol (NP = 1). Refer to Section 7.2.1.3 for details of RES format for
SD application.
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3071
3072
3073
6.2.2.6 RES (NACK = 1)
Figure 6-13 illustrates RES (NACK = 1) structure.
Bit
Byte
7
6
5
4
0
NACK=1
ECODE
Rsvd
Argument
Figure 6-13 : RES (NACK = 1) Format
• NACK (Negative Acknowledgement): Indicator whether the corresponding CMD is accepted or
not.
• NACK = 1 means the corresponding CMD is rejected.
• In the case of NACK = 1 (CMD is rejected), the requested operation is not in execution
(an error has occurred in the corresponding CMD).
• ECODE[2:0] (Error Code): Error code to represent error descriptions (refer to Table 6-4).
• Rsvd (Reserved): Reserved bits. Initiator shall set them to '0', and receiver shall ignore them.
Refer to Section 6.2.15 for details of CMD error sequence.
Table 6-4 shows the error descriptions represented by ECODE. If CMD includes multiple errors, RES
with NACK = 1 is generated with the error whose ECODE value is the smallest. For example, when
some command is issued at improper state with illegal argument (e.g. illegal address), the ECODE of its
RES with NACK = 1 is COND_ERR.
010b
011b
others
3094
3095
3096
0
Rsvd
Header
Value
001b
3092
3093
1
Header
3
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
2
(NP=1, Packet Type = RES)
1
2
3
ECODE
Name
COND_ERR
Description
Command is issued in any improper states
defined in all layers in this specification.
ARG_ERR
At least one of parameters in any of Argument
field, Extended Argument field, or Payload field is
improper in the CMD.
GEN_ERR
Other errors not belonging to the errors above.
Reserved
Reserved
Table 6-4 : Error Categories and Descriptions
6.2.2.7 DATA
Figure 6-14 illustrates a basic DATA structure.
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Bit
Byte
7
6
5
4
3
2
0
Header
1
(NP=1, Packet Type = DATA)
1
0
2
:
Payload
:
"Block Length" + 1
or TLEN + 1
Header
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
Figure 6-14 : Basic DATA Format
• Payload: Data included with DATA.
• The length of payload is equal to Block Length in Block Mode and TLEN in Byte Mode.
• It is transmitted in LSB first, MSB last. For the individual byte, it is msb first, lsb last.
6.2.2.8 Operation of Reserved Bits in the Packet
The following table indicates how each Node operates reserved bits in the packet.
Node
Initiator (both Host and
Device)
Device bypassing control
packet
Device handling broadcast
packet
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
Payload
Operation
Reserved bits shall be set to '0' other than in CMD_ECHO_BACK
field
Reserved bits shall be ignored upon reception, and not to be set or
cleared upon transmission.
Reserved bits shall be ignored upon reception, and not to be set or
cleared upon transmission.
Table 6-5 : Operation for the Reserved Bits in the Packet
Host should use Reserved bits considering the specification versions that all devices that exist in the
ring topology.
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3120
3121
3122
3123
3124
6.2.3 Supplements of UHS-II Initialization
In this section, supplements of UHS-II Initialization are described. Refer to Section 3.5 for the basic
specifications.
Figure 6-15 shows UHS-II Initialization flow in case of recovery from Dormant state.
Process name
Outline of process
From Dormant State
PHY Initialization
Device Initialization and
Enumeration may be skipped
when recovering from
Dormant state.
If "Config Completion" is
equal to 1, this process is
skipped and DLSM transits
directly to Active state.
Wakeup State
• PLL Activation
• Establishing synchronization
Config State
Configuration
• Reading and Setting for
CFG_REG
"Config Completion"
is set to 1
Active State
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
Figure 6-15 : UHS-II Initialization Flow When Recovery from Dormant State
If Device receives BSYN LSS after recovering from Dormant State, Device behavior is up to
implementation. Note that Host shall not transmit BSYN LSS after recovering from Dormant State.
Both Device Initialization process and Enumeration process may be skipped when recovering from
Dormant state, for whole functions of each Device and Node ID. If "Config Completion" is equal to 0,
Configuration process can be done, but otherwise, that process is skipped and DLSM transits to Active
state.
Figure 6-16 shows an example of Initialization flow in case of using Range B as a transmission speed
range (refer to Section 6.2.9.2.5 for the definition of tansmission speed range).
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Power On
Process name
FULL_RESET
Host can provide RCLK with
different frequency from that before
issuing GO_DORMANT_STATE.
Outline of process
PHY Initialization
• PLL Activation
• Establishing synchronization
• PLL Activation
• Establishing synchronization
• Starting Device wakeup
Enumeration
• Device ID assignment
Configuration
"Selected Transmission Speed
Range" shall be set to 01b in
this process.
Config State
GO_DORMANT_STATE
Device Initialization
These processes are
mandatory after power cycle
or FULL_RESET.
Wakeup State
PHY Initialization
Device Initialization and
Enumeration may be skipped
when recovering from
Dormant state. In addition,
Configuration is also skipped
because "Config Completion"
is equal to 1.
• Reading and Setting for
CFG_REG
"Config Completion" is set to 1
Active State
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
Figure 6-16 : An Example of UHS-II Initialization Flow (in Case of Using Higher Speed Range)
Host shall set "Selected Transmission Speed Range" in CFG_REG to the desire range (01b, in this
case) at the Configuration process. After setting "Config Completion" to 1, Host issues
GO_DORMANT_STATE in order to enable "Selected Transmission Speed Range". Afterwards, it
provides RCLK to do PHY Initialization again. Note that frequency of RCLK may be changed during
Dormant state only. At the end of PHY Initialization, DLSM transits to Active State where higher speed
range is available because "Config Completion" has been already set to 1. Note that this sequence is
also available when switching to arbitrary transmission speed range from Range A to Range D.
3150
6.2.4 Transition to Dormant State
3151
3152
3153
3154
3155
3156
3157
3158
3159
6.2.4.1 General
When Device receives GO_DORMANT_STATE CCMD, it makes its DLSM transit to Dormant state for
interface power saving. During Dormant state, state machines defined in Chapter 6 get back to the
initial state. On the other hand, all registers defined in Chapter 6 are kept and some Settings Registers
in CFG_REG are reflected by transiting to Dormant state (refer to Section 6.2.9.2).
Refer to Section 5.4.3 for the detailed transition to Dormant state.
Figure 6-17 illustrates a format of GO_DORMANT_STATE CCMD.
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Bit
Byte
7
6
5
4
3
2
0
Header
1
(NP=1, Packet Type = CCMD)
2 R/W=1 Rsvd
PLEN = 01b (msb)
0
IOADR
IOADR
3
4
1
(lsb)
HBR
5
Reserved
6
7
3160
3161
3162
3163
3164
3165
3166
3167
Header
Argument
Payload
Figure 6-17 : GO_DORMANT_STATE CCMD Format
• HBR (Entry to Hibernate Mode): This value indicates entry to Hibernate mode (refer to Section
6.2.4.2 for more details). If Host intends to enter to Hibernate mode during Dormant state, it issues
GO_DORMANT_STATE CCMD with HBR = 1. If Device not supporting Hibernate mode receives
GO_DORMANT_STATE CCMD with HBR = 1, Device shall handle it as an illegal CMD.
3168
6.2.4.2 Hibernate Mode
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
6.2.4.2.1 Overview
Hibernate mode is an enhanced power saving mode by turning off VDD1 (refer to Chapter 4 for the
details) during Dormant state, and optional by UHS-II Device. Time for recovering from Hibernate mode
is much shorter than that in case of power cycle. To realize Hibernate mode, Device will indicate if
Hibernate mode is supported through "Supporting Hibernate Mode" field located in PHY Capabilities
Register, bit position #15 (refer to Table 6-8 for more details).
Host shall inquire if Device or system is capable of Hibernate mode. In case that Hibernate mode is
supported, Host may activate this mode. Activation of Hibernate mode is done through setting HBR bit
in GO_DORMANT_STATE CCMD payload.
Note that in case of Multi-device connection such as Ring, the condition to operate Hibernate mode is
that all connected Devices support Hibernate mode. If Device not supporting Hibernate mode is turned
off VDD1 during Dormant state, its behavior is not guaranteed.
Figure 6-18 illustrates a brief sequence of transition from / to Hibernate mode. When Host turns off
VDD1, VDD1 should be less than 0.5V within 250 [msec]. Once VDD1 is less than 0.5V, this voltage
level should be kept for at least 1 [msec]. In case of exit from Hibernate mode, ramp up of VDD1 shall
comply with "Power up" specifications (refer to SD Specifications Part 1 Physical Layer Specification
Version 4.00 or later for "Power up").
During Hibernate mode, D0, D1 and RCLK signals shall comply with DORMANT state specifications to
avoid a situation in which the operating current is drawn through the Lines. Different from in case of
Dormant state, Host shall settle the RCLK Lane to DIF-PD during Hibernate mode.
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3190
VDD2
Dormant
(Hibernate mode)
Active
DLSM
Active
Wakeup
VDD2max
VDD2min
0.2V
VDD1
≥ 1 [msec]
VDD1max
VDD1min
0.5V
RCLK
D0
D1
Active
LIDL
GO_DORMANT
LIDL
LIDL
GO_DORMANT
Stopped
EIDL
STB.H
LIDL
STB.L
EIDL
STB.H
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
STB.L
SYN
LIDL
SYN
D0
LIDL D1
(*) Ramp up of VDD1 shall comply to
“Power Up” specifications
< 250 [msec]
3191
3192
3193
RCLK
Active
(*)
Figure 6-18 : Transition from / to Hibernate Mode
6.2.4.2.2 Entry to Hibernate Mode
As mentioned before, Host shall inquire if Hibernate mode is supported by all connected Devices.
Sequence of entering to Hibernate mode is as follows.
(1) Host inquires HBR field from PHY Capabilities Register of Device.
(2) If all connected Devices indicate that Hibernate mode is supported, Host may activate Hibernate
mode.
(3) To activate Hibernate mode, Host sends GO_DORMANT_STATE CCMD with HBR = 1. After
sequence of enter to DORMANT state is completed and after RCLK is stopped, Host may turn off
VDD1 (refer to Figure 6-19).
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VDD2max
VDD2
VDD2min
0.2V
Host may turn off
VDD1 only after T5
VDD1max
VDD1
VDD1min
0.5V
T2
Host
time
T1
T2'
HBR = 1
RCLK
D0
T3
LIDL
GO_DORMANT_STATE
(Broadcast CCMD)
LIDL
LIDL
STB.H
GO_DORMANT_STATE
(Broadcast CCMD)
LIDL
STB.H
Dormant
Active
PLSM
(D1.Rx)
VLD
(LSS&PKT)
LSS.LIDL
EIDL
VLD
(LSS&PKT)
LSS.LIDL
STB.H
PLSM
(D0.Tx) LSS.LIDL
DLSM
LSS.LIDL
LSS.LIDL
LSS.LIDL
VLD
(LSS&PKT)
LSS.LIDL
EIDL
STB.H
LSS.LIDL
EIDL
Dormant
Active
VLD
(LSS&PKT)
STB.H
Link State
of Device
D1
EIDL
> T_DMT_ENTRY
STB.H
Link State
of Host
DLSM
RCLK
D0
EIDL
HBR = 1
PLSM
(D1.Tx)
Device
RCLK is
stopped
RCLK is running
D1
PLSM
(D0.Rx)
T5
T4
EIDL
unknown state during transition
between EIDL and STB
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
<< T_DMT_ENTRY
Figure 6-19 : Entry to Hibernate Mode
6.2.4.2.3 Exit from Hibernate Mode
Sequence of exiting from Hibernate mode is as follows (refer to Figure 6-20).
(1) Host ramps up VDD1 according to "Power Up" specifications.
(2) Host starts PHY initialization of Device.
(3) After Wakeup state is completed and LIDL is received, Device transits to Active state if "Config
Completion" flag is already set to 1 before enter to Hibernate mode. In case of "Config
Completion" flag is 0 before enter to Hibernate mode, Device transits to Config state after
wakeup.
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Host shall complete power up of
VDD1 before starting PHY
Initialization (before T1).
VDD2max
VDD2
VDD2min
0.2V
VDD1max
VDD1
VDD1min
0.5V
time
T3
T2'
T1 T2
T4
T3'
T5
T6
Host
Device
RCLK
EIDL
D0
EIDL
D1
RCLK Active
SYN SYN SYN SYN SYN SYN SYN SYN SYN SYN SYN SYN SYN SYN SYN LIDL LIDL LIDL LIDL LIDL LIDL
STB.L
STB.L
EIDL
Initialize
UHS-II
DLSM
Dormant
PLSM
(D0.Tx)
EIDL
SYN SYN SYN SYN SYN SYN LIDL LIDL LIDL
Send
SYN
Start RCLK
Send STB.L
Wakeup
LIDL
LIDL
COM
LIDL
COM
LIDL
COM
LIDL
COM
LIDL
COM
LIDL
COM
LIDL
COM
COM
SYN
LIDL
COM
SYN
COM
SYN
COM
SYN
COM
SYN
COM
SYN
COM
COM
SYN
SYN
COM
SYN
COM
SYN
COM
COM
SYN
SYN
COM
SYN
COM
SYN
COM
SYN
COM
LSS
(2)
Receive
STB.L
(3)
Send
STB.L
PLL
Lock
DLSM
Dormant
Wakeup
Activate
PLSM
(D0.Rx)
EIDL
STB.L
PLSM
(D1.Tx)
EIDL
STB.L
PLL
(MUL)
Before Activation
COM
SYN
SYN
COM
SYN
(5)
(4)
Receive
SYN
COM
SYN
COM
STB.L
COM
LSS
EIDL
(1)
“Config Completion”
flag is already 1.
(6)
Receive
LIDL
Send
SYN
Send LIDL
Enter to Active
(Config)gActive
Sync
LIDL
COM
LIDL
COM
COM
LIDL
COM
LIDL
LIDL
COM
LIDL
COM
LIDL
COM
LIDL
LIDL
COM
COM
SYN
COM
SYN
COM
SYN
COM
SYN
COM
SYN
COM
COM
LSS
Device
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
D1
Active
Config
Sync
STB.L
PLSM
(D1.Rx)
3218
3219
3220
D0
Send LIDL
Enter to Config
Receive
SYN
Activate
COM
SYN
COM
SYN
COM
SYN
COM
SYN
COM
COM
LSS
SYN
Host
RCLK
After Lock Acquisition
During Lock acquisition
Figure 6-20 : Exit from Hibernate Mode
6.2.5 Reset
FULL_RESET CCMD is used for resetting all components in Device. After it transmits the CCMD or
RES to the next node, all state machines defined in this specification get back to the initial state, and in
addition, all registers in all layers defined in this specification are reset to the initial value.
After receiving FULL_RESET CCMD or RES, state transitions takes place as described in Figure 5-23
for Fast Mode, and in Figure 5-24 for Low Power Mode, equivalent to those of GO_DORMANT_STATE
CCMD. Host outputs LIDL (in case of Fast Mode), STB.H, and EIDL in this order on D0 lane after
issuing FULL_RESET CCMD. When Device receives FULL_RESET CCMD, it transmits FULL_RESET
CCMD or RES, and then it outputs STB.H and EIDL on D1 lane after detecting EIDL on
D0.Rx.Sequence of restarting the reset Device is same as wakeup described in Section 3.5.1.
Execution of FULL_RESET is completed by T5 in Figure 5-23 or Figure 5-24 to accept the next PHY
Initialization sequence after T5.
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6.2.6 Device Initialization Mechanism
3235
3236
3237
3238
3239
3240
3241
3242
3243
6.2.6.1 General
Device initialization mechanism enables Host system to optimize initialization time considering power
consumption. Under Multi-device connection Host may perform initializations for multiple Devices at the
same time with in a range of a Host's power supply capability. Device Initialization is taken place by
issuing the broadcast CCMD called DEVICE_INIT iteratively, and the Host's power supply capability is
provided by the argument of DEVICE_INIT to each Device.
Figure 6-21 illustrates a format of DEVICE_INIT CCMD.
Bit
Byte
7
6
5
4
3
2
1
0
Header
1
(NP=1, DID = SID = 0, Packet Type = CCMD)
2 R/W=1 Rsvd
PLEN = 01b (msb)
IOADR
IOADR
3
4
GD
5
DAP
6
0
(lsb)
GAP
CF
Reserved
7
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
Header
Argument
Payload
Figure 6-21 : DEVICE_INIT CCMD Format
• GD[3:0] (Group Descriptor): This value indicates the group number to be initialized. The start
value is 0 and incremented when all Devices in the group are initialized.
• GAP[3:0] (Group Allocated Power): This value indicates the maximum Host's power supply
capability that is allowed to certain group. A Device which starts initialization updates this value by
subtracting own power consumption from this value. In such a way this field represents the
currently remained power resource for a given group.
• 0: Reserved
• 1: 360 [mW] (3.6Vx100mA)
• 2: 720 [mW]
• 3: 1080 [mW]
:
• n: 360n [mW] (n ≤ 15)
• DAP[3:0] (Device Allocated Power): This value is the maximum Host's power supply capability
that is allowed to a certain Device.
• 0: 360 [mW] Default (Host does not know own power capability)
• 1: 360 [mW] (3.6Vx100mA)
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3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
•
•
2: 720 [mW]
3: 1080 [mW]
:
n: 360n [mW] (n ≤ 15)
•
•
• CF (Completion Flag): Device shall clear this bit to "0" if it is not initialized yet. Host uses this
value to check whether all Devices are initialized in the system. If Host detects CF = 0 (not all
Devices are initialized) from the received DEVICE_INIT, Host continues to issue DEVICE_INIT
CCMD.
• 0: Not all Devices complete initialization.
• 1: All Devices complete initialization.
Device can accept DEVICE_INIT CCMD only in Config state. So Device shall regard it as an illegal
CMD and shall not transmit it to the next Node in case of other than Config state.
Application Note:
Host should estimate at least 0.72W power supply capability for a UHS-II SD memory card until
Power Limit is set, including settings of DAP and GAP (refer to SD Specifications Part 1 Physical
Layer Specification Version 4.00 or later).
When DAP or GAP is set to 0.36W, whether device can be initialized or not is dependent on
implementation.
PHY
Initialization
Device
Initialization
Enumeration
Configuration
SD Tran
Initialization
Power Limit
setting by CMD6
DAP=0.72W (1)
0.054W
0.72W (Throughout Initialization Period)
Power Limit
set by CMD6
Note (1) : Host should set DAP to 0.72W (=<GAP).
Figure 6-22 : Power Consumption during Initialization
In case of embedded devices, device manufacturer should provide detail power consumption
specification to host system vendor if necessary so that host system vendor can calculate required
power budget.
(1) Power consumption during PHY Initialization (Ppi).
(2) Power consumption during packet bypassing (Ppb).
(3) Power consumption in Dormant State (Pds)
Host system calculates required power budget by using device information for all embedded
devices and reserves additional power 0.72W for a UHS-II memory card.
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
6.2.6.2 Operation of Device
Let DCP (Device Consumed Power) be the 4 bits index of power actually consumed by each Device
Initialization. Device can support multiple DCPs, but it shall support at least DCP = 1 Unit of DCP is 360
[mW] (3.6Vx100mA).
• 1: 360 [mW]
• 2: 720 [mW]
• 3: 1080 [mW]
:
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3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
• n: 360n [mW] (n ≤ 15)
Device shall have the following two parameters in the Preset field in CFG_REG by system
manufacturer.
• CDCP[3:0] (Candidate DCP): This parameter indicates the candidate DCP used in actual
initialization procedure, including power consumption in UHS-II interface. Removable Devices
shall set it to 0. In case of embedded Devices, system manufacturer can preset the parameter
considering DCPs supported by the Device.
• 0: Device may select one of supported DCPs according to DAP and GAP (Default).
• n: Device shall use the DCP = n. (It is necessary for the Device to support DCP = n.)
• GN[3:0] (Group Number): This parameter indicates the group number of the Device. The default
number is 0. Removable Devices shall set this parameter to 0. In case of embedded Devices,
system manufacturer can preset this parameter (GN ≥ 0).
Figure 6-23 shows the operation flow of a Device in receiving DEVICE_INIT. Note that when Device
receives the command during its initialization, it shall not transmit the command until its initialization
completes. When the Device starts initialization by the command, it shall transmit the command to the
next Node without waiting initialization completion of the Device.
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DEVICE_INIT Command Received
Yes
Now initializing?
No
Wait Init completion
Yes
Already initialized?
No
Set CF = 0
No
GD=GN?
Yes
If DAP=0, regardYes
it as DAP=1
Yes
CDCP=0?
No
No
Yes
GAP≥CDCP &
DAP≥CDCP?
Yes
DCP=CDCP
GAP=0?
No
Select one of supported
DCPs which satisfies
GAP≥DCP & DAP≥DCP
GAP=GAP-DCP
Start Initialization
Send DEVICE_INIT Command
3310
3311
3312
3313
End
Figure 6-23 : Device's Operation Flow of Receiving DEVICE_INIT
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3315
3316
3317
6.2.6.3 Operation of Host
GAP and CF denote the parameters in DEVICE_INIT command issued by Host. GAP' and CF' denote
the parameters in DEVICE_INIT command received by Host (refer to Figure 6-24).
CCMD
DEVICE_
(SID = DID = 0)
INIT
CCMD
DEVICE_
(SID = DID = 0)
INIT
GD GAP DAP CF
GD GAP' DAP CF'
Host
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
Device1
Device2
Device3
DeviceN
Figure 6-24 : DEVICE_INIT Broadcast CCMD Issued by Host
Figure 6-25 shows the Host's operation flow when it receives DEVICE_INIT CCMD from the last Device.
GAP and CF may be modified to GAP' and CF' by Devices. Host sets initial values to GAP, DAP and CF
(= 1) every time the DEVICE_INIT command is issued and checks the GAP' and CF' in the received
DEVICE_INIT command. If CF' = 1, it means all Devices are initialized and Host stops issuing the
DEVICE_INIT command. If GAP is equal to GAP', it means that the current group completed its
initialization. Therefore Host increments GD by 1 in order to initialize the next group.
Start
(GD=0)
GAP and DAP are
set in every
command issuing
Send DEVICE_INIT with
GD, GAP, DAP, CF=1
No
Wait receiving DEVICE_INIT
With GD, GAP', DAP, CF'
No
CF'=0?
Yes
No
GAP'=GAP?
Yes
Yes
GD = GD+1
3328
3329
3330
Initialization Done
Figure 6-25 : Host's Operation Flow of Receiving DEVICE_INIT
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3332
3333
3334
3335
3336
3337
When the number of the DEVICE_INIT commands is reached to 30 times, Host shall stop issuing the
DEVICE_INIT command and regard it as an error.
Figure 6-26 and Figure 6-27 illustrate some examples of Device Initialization process with different
parameters. Note that DAP shall be set by Host greater than or equal to the maximum CDCP in the
system.
CCMD
DEVICE_
(SID = DID = 0)
INIT
CCMD
DEVICE_
(SID = DID = 0)
INIT
GD GAP DAP CF
GD GAP' DAP CF'
Host
=Transmitted after
the Device initialized
Device1
Device2
Device3
Device4
Supported DCP: 1
Supported DCP: 1
Supported DCP: 1
Supported DCP: 1
0 2 0 1
3338
3339
3340
3341
3342
3343
3344
=Transmitter starts
initialization
GN=0,
CDCP=0
GN=0,
CDCP=0
GN=0,
CDCP=0
GN=0,
CDCP=0
0 1 0 0
1
0 0 0 0
1
0 2 0 1
0 2 0 1
0 2 0 1
0 2 0 1
0 2 0 1
0 2 0 1
0 0 0 0
0 1 0 0
1
1
0 2 0 1
=Actually consumed
DCP
0 0 0 0
GD is kept as
GAP != GAP'
0 0 0 0
GD is kept as
GAP != GAP'
0 2 0 1
Host terminates
Initialization as
CF'=1.
Figure 6-26 : Device Initialization Process (Example 1)
Figure 6-26 shows the case when all preset parameters in Device are default. In this case, each Device
is initialized sequentially (As GAP = 2, Device1 and 2 start their initialization by the first CCMD and
Device 3 and 4 start by the second one).
CCMD
DEVICE_
(SID = DID = 0)
INIT
CCMD
DEVICE_
(SID = DID = 0)
INIT
GD GAP DAP CF
GD GAP' DAP CF'
Host
3345
3346
3347
3348
3349
3350
3351
3352
Device1
Device2
Device3
Device4
Supported DCP: 1,2
Supported DCP: 1,2
Supported DCP: 1,2
0 3 2 0
0 3 2 1
1 3 2 1
=Transmitted after
the Device initialized
Supported DCP: 1
0 3 2 1
1 3 2 1
GN=0,
CDCP=0
GN=1,
CDCP=2
GN=0,
CDCP=2
GN=1,
CDCP=0
=Transmitter starts
initialization
1
0 0 2 0
GD is kept as
GAP != GAP'
0 3 2 0
0 3 2 0
GD++ as
GAP == GAP'
1 0 2 0
1 0 2 0
GD is kept as
GAP != GAP'
1 3 2 1
1 3 2 1
Host terminates
Initialization as
CF'=1.
0 1 2 0
0 1 2 0
0 3 2 0
0 3 2 0
1 2 2 0
1 2 2 0
1 3 2 1
1 3 2 1
2
2
=Actually consumed
DCP
1
Figure 6-27 : Device Initialization Process (Example 2)
Figure 6-27 shows the case that the initialization order is managed by settings of GN. Device2 and
Device3 are set DCP = 2. Device 4 selects DCP = 1 because it receives DEVICE_INIT CCMD with GAP
= 1.
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6.2.7 Enumeration Mechanism
3354
3355
3356
3357
6.2.7.1 General
After initialization, Enumeration process is taken place.
Figure 6-28 illustrates a format of ENUMERATE CCMD.
Bit
Byte
7
6
5
4
3
2
1
0
Header
1
(NP=1, DID = SID = 0, Packet Type = CCMD)
2 R/W=1 Rsvd
PLEN = 01b (msb)
4
IOADR
IOADR
3
First Node ID (ID_F)
0
(lsb)
Last Node ID (ID_L)
5
Reserved
6
7
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
Header
Argument
Payload
Figure 6-28 : ENUMERATE CCMD Format
There are two parameters in Payload area named First Node ID (abbreviated to ID_F) and Last Node
ID (abbreviated to ID_L) to perform Enumeration.
The algorithm of Enumeration process from the Device's point of view is as described in Figure 6-29.
Note that Host shall issue ENUMERATE CCMD with ID_L = 0.
• Device receives ENUMERATE CCMD with (ID_F, ID_L).
• If (ID_L == 0h),
• OWN_NODE_ID = (ID_F == Fh) ? ARBITRARY_ID : ID_F + 1.
• Device sets OWN_NODE_ID to its Node ID,
and transmits ENUMERATE CCMD with (OWN_NODE_ID, OWN_NODE_ID).
• Else,
• OWN_NODE_ID = (ID_L == Fh) ? 1 : ID_L + 1.
• If (ID_F == 0h || ID_F == OWN_NODE_ID),
• Device does not transmit ENUMERATE CCMD because of error.
• Else
• Device sets OWN_NODE_ID to its Node ID,
and transmits ENUMERATE CCMD with (ID_F, OWN_NODE_ID).
Note: ARBITRARY_ID is any number from 1 to 15 but different from current OWN_NODE_ID.
Figure 6-29 : Device's Algorithm for Enumeration Process
Device can accept ENUMERATE CCMD only in Config state. So Device shall regard it as an illegal
CMD and shall not transmit it to the next Node in case of other than Config state.
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3372
3373
Note that ENUMERATE CCMD may be repeated if Host would like to change the set of the generated
Node IDs.
3374
3375
3376
6.2.7.2 Enumeration Examples in Point to Point Connection
Figure 6-30 illustrates an example of Enumeration method in case of Point to Point connection.
[a]
[b]
[c]
Host
Host
Host
0
0
0
Tx Rx
Tx Rx
Tx Rx
CCMD
ENUME- ID_F ID_L
(SID = DID = 0) RATE =Fh =0h
CCMD
ENUME- ID_F ID_L
(SID = DID = 0) RATE =4h =4h
Rx Tx
Device
Rx Tx
Rx Tx
4
4
Device
Device
CCMD
ENUMEID_F ID_L
(SID = DID = 0) RATE
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
Fh-> 4h
(arbitrary selected)
0h-> 4h
Figure 6-30 : Enumeration Process in Point to Point Connection (Example 1)
Host is already set number '0' as its Node ID. Host issues ENUMERATE CCMD with (ID_F, ID_L) = (Fh,
0h) as described in Figure 6-30 [a]. When Device receives the CCMD, its Node ID is assigned
distinctively referring ID_F and ID_L included in the CCMD.
In Figure 6-30 [b], as Device receives ID_F = Fh and ID_L = 0h, Device generates its Node ID arbitrarily
(number '4' in this example). Then ID_F and ID_L are modified to 4h and 4h respectively.
After modifying ID_F and ID_L, Device transmits the ENUMERATE CCMD to Host. Since Host detects
DID = SID (= its own Node ID) from the header of CCMD, it terminates to transmit the CCMD and
Enumeration process ends as a result (Figure 6-30 [c]).
Figure 6-31 illustrates another example of Enumeration method in case of Point to Point connection.
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[a]
[b]
[c]
Host
Host
Host
0
0
0
Tx Rx
Tx Rx
Tx Rx
CCMD
ENUME- ID_F ID_L
(SID = DID = 0) RATE =0h =0h
CCMD
ENUME- ID_F ID_L
(SID = DID = 0) RATE =1h =1h
Rx Tx
Rx Tx
Rx Tx
1
1
Device
Device
Device
CCMD
ENUMEID_F ID_L
(SID = DID = 0) RATE
0h-> 1h
3391
3392
3393
3394
3395
3396
3397
3398
3399
0h-> 1h
Figure 6-31 : Enumeration Process in Point to Point Connection (Example 2)
In this example, Host issues ENUMERATE CCMD with (ID_F, ID_L) = (0h, 0h) as described in Figure
6-31 [a]. So Device sets its Node ID to ID_F + 1, that is, number '1' as described the algorithm in Figure
6-29. Other operations are same as in Figure 6-30.
6.2.7.3 Enumeration Examples in Multi-device Connection (Ring)
Figure 6-32 illustrates an example of Enumeration method in case of Multi-device (Ring) Connection.
Host
0
Tx Rx
CCMD
ENUME- ID_F ID_L
(SID = DID = 0) RATE =Eh =1h
CCMD
ENUME- ID_F ID_L
(SID = DID = 0) RATE =Eh =Eh
Rx Tx
1
Device#3
14
Tx Rx
Tx Rx
Node ID: Arbitrary
determined to Eh
because ID_F == Fh
Device#1
CCMD
ENUME- ID_F ID_L
(SID = DID = 0) RATE =Fh =0h
Node ID: 1 (ID_L == Fh)
CCMD
ENUME- ID_F ID_L
(SID = DID = 0) RATE =Eh =Fh
15
Device#2
3400
3401
3402
Node ID: ID_L + 1 (= Fh)
Figure 6-32 : Enumeration Process in Ring Connection (Example 1)
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3403
3404
3405
3406
3407
3408
3409
3410
3411
In this example, Host issues ENUMERATE CCMD with (ID_F, ID_L) = (Fh, 0h). In this case, Device#1
sets its own Node ID '14' arbitrarily according to the algorithm described in Figure 6-29.
Device#2 receives the CMD with (ID_F, ID_L) = (Eh, Eh), so its Node ID is assigned to '15'. Node ID of
Device#3 is assigned to '1' because it receives ID_L = Fh (Node ID '0' is set aside for Host).
Same as in Point to Point connection, the transaction ends when Host receives the broadcast CCMD.
Figure 6-31 illustrates another example of Enumeration method in case of Ring. In this case, Node IDs
of Devices are assigned incrementally from '1' to '3'.
Host
0
Tx Rx
CCMD
ENUME- ID_F ID_L
(SID = DID = 0) RATE =1h =3h
CCMD
ENUME- ID_F ID_L
(SID = DID = 0) RATE =1h =1h
Rx Tx
3
Device#3
1
Tx Rx
Tx Rx
Node ID: ID_L + 1 (=1h)
Device#1
CCMD
ENUME- ID_F ID_L
(SID = DID = 0) RATE =0h =0h
Node ID: ID_L + 1 (=3h)
CCMD
ENUME- ID_F ID_L
(SID = DID = 0) RATE =1h =2h
2
Device#2
3412
3413
3414
3415
3416
3417
Node ID: ID_L + 1 (= 2h)
Figure 6-33 : Enumeration Process in Ring Connection (Example 2)
In Multi-device connection, Host may easily generate a table with all the system's Device IDs out of the
given First and Last IDs.
3418
6.2.8 Configuration Mechanism
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
6.2.8.1 Basic Specification
After Enumeration, Configuration process is taken place.
All UHS-II Host and Device shall have their own Configuration Register (CFG_REG). Its details are
described in Section 6.2.9.
CFG_REG consists of the following fields;
• Capabilities: Device-dependent initial capabilities are set to this field.
• Settings: Negotiated operating values are assigned to this field.
• Preset: Preset values are indicated to this field.
In Capabilities field, device-specific initial capabilities or properties are set, and this field is referred for
deciding operating conditions during Configuration.
In Settings field, negotiated values between Host and Device are assigned as operating conditions after
Configuration.
Moreover, some parameters can be preset by system manufactures or so, and these are indicated in
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3435
3436
3437
3438
Preset field.
Figure 6-34 illustrates Configuration flow in TRAN. The numbers in Figure 6-34 corresponds to the
number of the following Configuration procedure.
Host side
T
L
CFG_REG
Tx
P
1.
[0]
[1]
…
[N-1]
Rx
Device side
P
L
T
CFG_REG
CCMD
[0]
[1]
…
[N-1]
(read)
RES
Rx
Tx
2.
CFG_REG
Tx
Rx
CFG_REG
CCMD
[0]
[1]
…
[N-1]
[0]
[1]
…
[N-1]
(write)
RES
Rx
Tx
3.
4.
CFG_REG
Tx
[0]
[1]
…
[N-1]
Rx
:
:
CFG_REG
CCMD
[0]
[1]
…
[N-1]
(write)
RES
Rx
Tx
5.
time
Register Status
: Not negotiated
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
: Negotiated
Figure 6-34 : Device Configuration Flow
(1) After Enumeration, Host issues a read CCMD to obtain capabilities in CFG_REG of Device.
(2) Host compares the capability of Host and Device, and lower capabilities are determined as
negotiated operating values.
(3) Host issues a write CCMD to assign the determined operating value to Settings field in
CFG_REG of Device. In the case that the operating value to be set by the CCMD is not
supported for Device, the value in CFG_REG is not updated. (Refer to Section 6.2.15 for details
of CMD error sequence.)
(4) From (1) to (3) are repeated until all necessary operating values are determined.
(5) Finally, Host issues a write CCMD in order to set "Config Completion" flag to 1. When a Device
receives the command and succeeds to set the flag to 1, it makes their own DLSM to Active state
before transmitting the RES of the CCMD.
Application Note:
In case of Ring Connection, Host shall use broadcast write CCMD to set "Config Completion" flag to
1.
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3455
3456
3457
3458
3459
3460
3461
3462
"Config Completion" in CFG_REG is set to 0 in I/F power cycle or FULL_RESET.
Host can read values from CFG_REG regardless of "Config Completion". Moreover, DLSM transits from
Active to Config by Host's writing '0' to "Config Completion" only one time after being synchronized by
BSYN LSS (This transition is only taken place after finishing Boot Code Loading. Refer to Section 5.9).
Otherwise, it is possible for Host to write '0' to "Config Completion", but no state transitions in Device
occur. In this case, DLSM stays in Config state after issuing GO_DORMANT_STATE and finishing PHY
Initialization.
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
6.2.8.2 Determination of Block Length
Block Length is determined as follows.
3479
3480
3481
3482
3483
3484
3485
3486
3487
6.2.8.3 Quick Configuration
The basic Configuration mentioned above is taken place for one Device. So it takes much time for
Configuration if there are many Devices connected to Host, because Host shall repeat the process.
In order to make Configuration more efficient, Quick Configuration mechanism is introduced.
Quick Configuration can be established by the following two broadcast CCMDs, one is
INQUIRY_CONFIG and the other is SET_COMMON_CONFIG. Note that these two commands are not
defined in CMD_REG, because IOADR for these commands are set the address for CFG_REG.
Figure 6-35 illustrates a format of INQUIRY_CONFIG.
(1) Host reads "Device-specific MAX_BLKLEN" from LINK/TRAN Capabilities Registers in Device.
(2) Host determines the feasible value for "MAX_BLKLEN" and writes to LINK/TRAN Settings
Registers in Device.
(3) If Device has an application specific layer, Block Length is finally determined by the setting in the
application specific layer. Note that Block Length shall be set smaller than or equal to
"MAX_BLKLEN" in the application specific layer.
(4) Otherwise, Block Length is equal to "MAX_BLKLEN". Only in this case, Block Length is
immediately changed even in Active State when Host writes the value of "MAX_BLKLEN" by
CCMD.
If the application is SD-memory, both "Device-specific MAX_BLKLEN" and "MAX_BLKLEN" shall be
512 bytes.
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Bit
Byte
7
6
5
4
3
2
1
0
Header
1
(NP=1, DID = SID = 0, Packet Type = CCMD)
2 R/W=0 Rsvd
PLEN
IOADR
(msb)
IOADR
3
0
(lsb)
4
:
Data from CFG_REG
:
:
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
Header
Argument
Payload
Figure 6-35 : INQUIRY_CONFIG Format
INQUIRY_CONFIG queries to each Device and returns the values that all Devices satisfy for their
settings. IOADR is set the quarter of the absolute address to access in CFG_REG. The target field of
INQUIRY_CONFIG specified by PLEN and IOADR shall consist entirely of Capabilities registers.
Otherwise, INQUIRY_CONFIG commands are discarded.
Figure 6-36 illustrates an example operation for INQUIRY_CONFIG. In this example, Device-specific
N_DATA_GAP (simply called as "the parameter" in this example) is used. In that case, Host sets the
beginning address of LINK/TRAN Capabilities Register to IOADR and 001b (4 bytes), to PLEN for
instance.
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Host
2
Tx Rx
Tx Rx
CCMD
INQUIRY
2
(SID = DID = 0) _CONFIG
2
Device#3
0
CCMD
INQUIRY
4
(SID = DID = 0) _CONFIG
Tx Rx
MAX(2, 0) = 2
Device#1
CCMD
INQUIRY
2
(SID = DID = 0) _CONFIG
MAX(4, 2) = 4
CCMD
INQUIRY
4
(SID = DID = 0) _CONFIG
Rx Tx
4
Device-specific N_DATA_GAP
Device#2
MAX(X, Y) denotes the larger value between X and Y,
where X is a value in input CMD payload, and Y is in CFG_REG.
Result of MAX(X, Y) is multiplexed to the output CMD payload.
MAX(2, 4) = 4
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
Figure 6-36 : Operation of INQUIRY_CONFIG
Host sets the payload including the parameter and issues INQUIRY_CONFIG. When Device receives
the broadcast CCMD, it compares the parameter in the input CMD payload and that in CFG_REG in its
own, selects appropriate value between them, and overwrites the selected parameter to the broadcast
CCMD. Then Device sends the updated broadcast CCMD from its Tx Port. The comparison conditions
may be different for each parameter and are described in Section 6.2.9.2. No operations are taken
place for some parameters specified in Section 6.2.9.2, and Reserved field.
Bit
Byte
7
6
5
4
3
2
1
0
Header
1
(NP=1, DID = SID = 0, Packet Type = CCMD)
2 R/W=1 Rsvd
PLEN
(msb)
IOADR
IOADR
3
0
(lsb)
4
:
Data to CFG_REG
:
:
3510
3511
3512
3513
3514
3515
Header
Argument
Payload
Figure 6-37 : SET_COMMON_CONFIG CCMD Format
Figure 6-37 illustrates a format of SET_COMMON_CONFIG. This broadcast CCMD writes content of
Payload area to CFG_REG specified by IOADR and PLEN. So Host can set the same parameters to all
Devices by issuing this broadcast CCMD.
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3517
3518
3519
3520
6.2.9 Configuration Register (CFG_REG)
3521
3522
3523
3524
3525
3526
3527
6.2.9.1 Register Map
Table 6-6 shows the map of CFG_REG. Offset means the relative address based on CFG_BASE. The
parenthetic values indicate bit location in each register. In case of writing to Settings Register,
SET_COMMON_CONFIG (broadcast CCMD) shall be used for Generic Settings Register and PHY
Settings Register in case of Ring connection. In other words, common values shall be set for the two
registers among all Devices.
3528
3529
3530
3531
3532
3533
Parameters related to Configuration are assigned to CFG_REG. CFG_REG can be accessed by
CCMD, not DCMD.
Offset
Register
Byte address IOADR
0000h
000h
:
:
Generic Capabilities Register
0007h
001h (63)
0008h
002h
:
:
PHY Capabilities Register
000Fh
003h (63)
0010h
004h
:
:
LINK/TRAN Capabilities Register
0017h
005h (63)
0018h
006h
:
:
Reserved for Capabilities Register
001Fh
007h
0020h
008h
:
:
Generic Settings Register
0027h
009h (63)
0028h
00Ah
:
:
PHY Settings Register
002Fh
00Bh (63)
0030h
00Ch
:
:
LINK/TRAN Settings Register
0037h
00Dh (63)
0038h
00Eh
:
:
Reserved
00FFh
03Fh
0100h
040h
:
:
Preset Register
0107h
041h (63)
0108h
042h
:
:
Reserved
03FFh
0FFh
Table 6-6 : CFG_REG Map
(00)
(00)
(00)
(00)
(00)
(00)
(00)
6.2.9.2 CFG_REG Description
The details of CFG_REG fields are described below. Refer to Appendix D for the details of registers,
and in addition, refer to Table D- 1 for the description of "Attrib" in this specification.
It is recommended for Host to use INQUIRY_CONFIG (whose initial values are set to Host's
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3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
capabilities) and SET_COMMON_CONFIG regardless of topology (P2P or Ring). Refer to Section
6.2.8.3 for the details of INQUIRY_CONFIG and SET_COMMON_CONFIG. For each Capabilities
register, the operation is defined when receiving INQUIRY_CONFIG. Note that the Capabilities field
whose "Attrib" is Rsvd, no operations are taken place when receiving INQUIRY_CONFIG.
The followings are Device behavior when written to the register whose "Attrib" is RO or HwInit.
• P2P CCMD Write: Device shall issue RES with NACK=0 and bit value of such register is not
changed.
• Broadcast CCMD Write: Device shall forward broadcast CCMD to the next node, and bit value
such register is not changed.
Some Settings registers can be written in both Config and Active state as far as Device receives write
CCMD when TSSM is TS_STNBY (refer to Section 6.2.13.1 for the details of TSSM). In following cases,
Device shall not update all Settings Register fields indicated by receiving write command to Settings
Registers, and respond RES with NACK = 1 (in case of P2P write CCMD), or shall not respond (in case
of Broadcast write CCMD).
(1) In Active state, the write command targets Settings registers whose writable states are "Config
only".
(2) The write command includes parameters that Device does not support.
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3557
6.2.9.2.1 Generic Capabilities Register
The table shown below describes Generic Capabilities Register.
Location
Attrib
Register Field Name and Explanation
63-24
23-16
Rsvd
RO
15
14
Rsvd
RO
13-08
RO
-Application Type
This field indicates a type of Application.
Bit 16: 0 = Non-SD memory, 1 = SD Memory
Bit 17: 0 = Non-SDIO, 1 = SDIO
Bit 18: 0 = Card, 1 = Embedded
Others = reserved
No operations are taken place when receiving INQUIRY_CONFIG.
-DADR Length
This field indicates the length of DADR.
0b = 4 bytes
1b = Reserved for the future use
No operations are taken place when receiving INQUIRY_CONFIG.
(See Note (1)).
Device-specific Number of Lanes and Functionality
This field indicates capabilities of number of Lanes and 2L-HD
mode. As Device shall support FD mode, the following table shows
the optional capabilities. If functionality mentioned below is
available, the corresponding bit is set to 1, and otherwise 0.
Device can indicate pluralities of options. Note that bit location 08
indicates capability in Range A and Range B (2L-HD mode is not
available in Range C and Range D).
Bit Location
Mode
08
2L-HD
09
2D1U-FD
10
1D2U-FD
11
2D2U-FD
12, 13
Reserved
Legends:
Bi = Lane is bidirectional
Dn = Lane is fixed to downstream
Up = Lane is fixed to upstream
NA = Not available
07-02
Rsvd
D0
Bi
Dn
Dn
Dn
-
D1
Bi
Up
Up
Up
-
D2
NA
Dn
NA
Dn
-
CMD
category
Broadcast
/P2P
D3
NA
NA
Up
Up
-
Refer to Chapter 8 and 9 for more details.
No operations are taken place when receiving INQUIRY_CONFIG.
--
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3560
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3562
3563
3564
01
RO
00
RO
Ring Topology Support
This field indicates support of functionalities for Ring Topology.
This field is introduced from UHS-II Addendum Version 2.00 and
was reserved in Version 1.02. 0b shall be set if “LINK/TRAN Major
Revision” is equal to 0b, or bit 18 of Generic Capabilities Register
is equal to 1b ("Application Type" is Embedded).
0b = Ring Topology is supported.
1b = Ring Topology is not supported.
Larger value is set on the command payload field when receiving
INQUIRY_CONFIG.
Low Power Mode Support
This field indicates support of Low Power Mode in Range C and
Range D. This field is introduced from UHS-II Addendum Version
2.00 and was reserved in Version 1.02. 0b shall be set for the
Device compliant to UHS-II Addendum Version 1.00 to 1.02. When
this field is set to 1b, both “PHY Major Revision” and “LINK/TRAN
Major Revision” shall be set to 1b (compliant to Addendum 2.00).
0b = Low power mode is supported in Range C and Range D.
1b = Low power mode is not supported in Range C and Range D.
Larger value is set on the command payload field when receiving
INQUIRY_CONFIG.
Note:
(1) Host which handles 4 bytes address cannot access to the Device whose DADR Length is other than 0b.
Table 6-7 : Generic Capabilities Register
6.2.9.2.2 PHY Capabilities Register
The table shown below describes PHY Capabilities Register.
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Location
Attrib
Register Field Name and Explanation
63-44
43-40
Rsvd
RO
-Device-specific T_EIDL_RECOVERY/GAP
This
field
indicates
the
device-specific
period
for
“T_EIDL_RECOVERY” and “T_EIDL_GAP” in order that Rx can
recognize as an exit or entry of EIDL state in case of Range C or
Range D. This field is introduced from UHS-II Addendum Version
2.00 and was reserved in Version 1.02. When this field is set to
other than 0000b, both “PHY Major Revision” and “LINK/TRAN
Major Revision” shall be set to 1b (compliant to Addendum 2.00).
Register T_EIDL_RECOVERY
Value
Range C
Range D
0000b
32SI
64SI
0001b
64SI
128SI
0010b
96SI
192SI
:
:
:
1111b
512SI
1024SI
(See Note (1) and (2))
39-36
RO
35-32
RO
31-16
15
Rsvd
RO
14-06
Rsvd
CMD
category
Broadcast
/P2P
T_EIDL_GAP
Range C
Range D
16SI
32SI
32SI
64SI
48SI
96SI
:
:
256SI
512SI
Larger value is set on the command payload field when receiving
INQUIRY_CONFIG.
In case of Range A or Range B, this field is invalid.
Device-specific N_LSS_DIR
This field indicates the device-specific number of "DIR" LSS in
order that Rx can recognize to have switched 2L-HD mode. It is
indicated in unit of eight (8), and 0000b means 128 (16x8).
Larger value is set on the command payload field when receiving
INQUIRY_CONFIG. (Note that 0000b is regarded as the largest
value.)
Device-specific N_LSS_SYN
This field indicates the device-specific number of "SYN" LSS in
order that Rx can recognize as a trigger of synchronization. It is
indicated in unit of four (4), and 0000b means 64 (16x4).
Larger value is set on the command payload field when receiving
INQUIRY_CONFIG. (Note that 0000b is regarded as the largest
value.)
-Supporting Hibernate Mode
This field indicates whether Device supports Hibernate Mode
(refer to Section 6.2.4.2) or not.
0b = Not supporting Hibernate Mode
1b = Supporting Hibernate Mode
Smaller value is set on the command payload field when receiving
INQUIRY_CONFIG.
--
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05-04
RO
03-00
RO
3565
3566
3567
3568
3569
3570
3571
PHY Major Revision
This field indicates PHY major revision.
00b = UHS156 (Maximum speed of a Lane is 1.56Gbps)
01b = UHS624 (Maximum speed of a Lane is 6.24Gbps)
Others = Reserved.
Note that Device whose PHY Major Revision is equal to 1b shall
also support UHS156 bus mode.
Smaller value is set on the command payload field when receiving
INQUIRY_CONFIG
PHY Minor Revision
It is defined incrementally from 0 to 15 and reset to 0 if PHY Major
Revision is updated.
No operations are taken place when receiving INQUIRY_CONFIG.
Note:
(1) T_EIDL_RECOVERY is calculated by 32*(n+1) [SI] for Range C, and 64*(n+1) [SI] for Range D respectively, where n is
the register value.
(2) T_EIDL_GAP is calculated by 16*(n+1) [SI] for Range C, and 32*(n+1) [SI] for Range D respectively, where n is the
register value.
Table 6-8 : PHY Capabilities Register
Application Note:
Host shall accept Device with any PHY Major Revision. And Host shall use PHY functions which
defined by minimum capability of PHY Major Revision.
e.g. Host whose PHY Major Revision is 00b shall accept Device whose PHY Major Revision is 00b
or more. In this case, Host can use PHY functions which are defined in Revision 00b regardless of
Device's Major Revision.
3572
3573
3574
3575
3576
6.2.9.2.3 LINK/TRAN Capabilities Register
The table shown below describes LINK/TRAN Capabilities Register.
Location
Attrib
63
RO
62-40
Rsvd
Register Field Name and Explanation
CMD
category
CCMD during Data Transfer
Broadcast
This field indicates the capability of receving arbitrary CCMD /P2P
(including write CCMD) during CTS. When this field is set to 1b,
“LINK/TRAN Major Revision” shall be set to 1b (compliant to
Addendum 2.00).
0b = Device does not accept arbitrary CCMD (same definition as
Addendum Version 1.02).
1b = Device accepts arbitrary CCMD.
Smaller value is set on the command payload field when receiving
INQUIRY_CONFIG.
Also refer to Table 7.2.4- 1 in case of SD memory Card or SDIO
Card.
--
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3578
3579
39-32
RO
31-20
RO
19
18-16
Rsvd
RO
15-08
RO
07-06
05-04
Rsvd
RO
03-00
RO
Device-specific N_DATA_GAP
This field indicates device-specific number of DIDL between DATA
packets. N_DATA_GAP is finally determined with reference to this
parameter and set in LINK/TRAN Settings Register during
Configuration.
Larger value is set on the command payload field when receiving
INQUIRY_CONFIG
Device-specific MAX_BLKLEN
This field indicates maximum payload length of one block in byte
supported by the Device (000h is reserved). Block Length is finally
determined with reference to this parameter (refer to Section
6.2.8.2 for more details).
If bit 16 in Generic Capabilities Register is equal to 1 ("Application
Type" is SD-memory), this field shall be 200h (512 bytes).
Smaller value is set on the command payload field when receiving
INQUIRY_CONFIG.
-Device Type
This field indicates a type of Device as follows.
001b = Host
010b = Device
011b = Reserved for CMD issuable Device
Others = Reserved.
No operations are taken place when receiving INQUIRY_CONFIG.
Device-specific N_FCU
This field indicates maximum block number in a flow control unit
(FCU) supported by the Device. 00h means 256. N_FCU is finally
determined with reference to this parameter and set in LINK/TRAN
Settings Register during Configuration.
Smaller value is set on the command payload field when receiving
INQUIRY_CONFIG.
-LINK/TRAN Major Revision
This field indicates LINK/TRAN major revision.
00b = Compliant to UHS-II Addendum Version 1.02
01b = Compliant to UHS-II Addendum Version 2.00
Others = Reserved.
Smaller value is set on the command payload field when receiving
INQUIRY_CONFIG.
LINK/TRAN Minor Revision
It is defined incrementally from 0 to 15 and reset to 0 if
LINK/TRAN Major Revision is updated.
No operations are taken place when receiving INQUIRY_CONFIG.
Table 6-9 : LINK/TRAN Capabilities Register
Application Note:
Host shall accept Device with any LINK/TRAN Major Revision.
e.g. Host whose LINK/TRAN Major Revision is 00b shall accept Device whose LINK/TRAN Major
Revision is 00b or more.
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3582
3583
6.2.9.2.4 Generic Settings Register
The table shown below describes Generic Settings Register.
Location
63
Attrib
62-32
31-12
11-08
Rsvd
Rsvd
RW
07-01
Rsvd
RW
Register Field Name and Explanation
Writable
State
Config Completion
Config/
This field is used for DLSM transition between Active
Config and Active state.
In Config state, DLSM transits to Active state
immediately when this field is set to 1.
In Active state, there are two cases of DLSM
transitions when this field is set to 0. DLSM
transits to Config state immediately after
completing of Boot Code Loading. In other
cases, DLSM does not transit to Config state
(See Note (1)).
-Config
-only
Number of Lanes and Functionality
This field indicates the number of Lanes
determined through Configuration (See Note
(4) and (5)). The default setting is 0000b.
0000b = 2 Lanes – operated by FD mode or
2L-HD mode (if supported)
0010b = 3 Lanes – operated by 2D1U-FD
mode.
0011b = 3 Lanes – operated by 1D2U-FD
mode.
0100b = 4 Lanes – operated by 2D2U-FD
mode.
Others = reserved
--
Effective
Timing
(See Note
(2))
CMD
category
Broadcast
/P2P
(See Note
(3))
--After
exiting
from
Dormant
--
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3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
RW
Power Control Mode in Active.Control
State
This field indicates the mode for power control
in Active state. In other words, it indicates
symbols to be filled in the gaps on VLD state
(refer to Section 5.4, and see Note (6)).
0b = Fast mode (filled with LIDL)
1b = Low power mode (filled with EIDL, STB,
and SYN)
Note that if the value of “Low Power Mode
Support” in Generic Capabilities Register
(including
the
returned
value
by
INQUIRY_CONFIG) is equal to 1b, Host shall
not set this field to 1b when “Selected
Transmission Speed Range” is equal to 10b
(Range C) or 11b (Range D). Otherwise,
Device behavior is undefined.
In Active
Note:
(1) In case of synchronization by BSYN LSS, it is automatically set to 1 for executing Boot Code Loading and DLSM transits
to Active state. After the Boot Code Loading, Host shall set the parameter to 0 in order to make DLSM Config state. (Refer
to Section 3.5.2 and Section 5.9.)
(2) "Config Completion" becomes effective immediately if it is written in Config state. On the other hand, it becomes effective
after exiting from Dormant if it is written in Active State except the case of Boot Code Loading described in Note (1).
(3) In Ring connection, Host shall issue broadcast CCMD for writing Generic Settings Register.
(4) "Number of Lanes and Functionality" becomes valid by transiting to Dormant state. So if more than 2 Lanes are used, Host
shall issue GO_DORMANT_STATE after setting appropriate value to "Number of Lanes and Functionality" (refer to
Section 9.4.1). On the other hand, transition to Dormant state is not necessary in case of using only 2 Lanes.
(5) Even Device supports 2D1U-FD mode, it is impossible to configure 1D2U-FD mode if it does not support 1D2U-FD mode,
and vice versa
(6) In case of synchronization by BSYN LSS, it is automatically set to 0.
Table 6-10 : Generic Settings Register
6.2.9.2.5 PHY Settings Register
The table shown below describes PHY Settings Register.
Location
63-44
43-40
Attrib
Register Field Name and Explanation
Rsvd
RW
-T_EIDL_RECOVERY/GAP
This field indicates the minimum period of
“T_EIDL_RECOVERY” and “T_EIDL_GAP”
for Range C and Range D.
This value is set during Configuration with
reference
to
"Device-specific
T_EIDL_RECOVERY/GAP" field in other side,
and becomes valid in Active state.
This field is introduced from UHS-II
Addendum Version 2.00 and was reserved in
Version 1.02.
Refer to Table 6.2.9- 1 for the detailed register
settings.
Writable
State
Config
only
Effective
Timing
-In Active
CMD
category
Broadcast
/P2P
(See Note
(1))
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39-36
RW
35-32
RW
31-14
13-12
Rsvd
RW
N_LSS_DIR
This field indicates minimum number of "DIR"
LSS to be sent from Tx (refer to Figure 8-10
for more details). This value is set during
Configuration with reference to "Devicespecific N_LSS_DIR" field in other side, and
becomes valid in Active state. It is indicated in
unit of eight (8), and 0000b means 128
(16x8).
N_LSS_SYN
This field indicates minimum number of "SYN"
LSS to be sent from Tx when starting to
synchronize. This value is set during
Configuration with reference to "Devicespecific N_LSS_SYN" field in other side, and
becomes valid in Active state. It is indicated in
unit of four (4), and 0000b means 64 (16x4).
-Config/
Active
Selected Emphasis Level
This field indicates the emphasis level
(indicated by typ value) of Device Tx.
Register
Value
00b
01b
10b
11b
11-08
07-06
Rsvd
RW
05-04
Rsvd
03-00
3602
3603
3604
3605
3606
3607
3608
3609
3610
Rsvd
Range
A, B
0.0 dB
(default)
0.0 dB
0.0 dB
0.0 dB
Range
C
0.0 dB
(default)
1.5 dB
3.0 dB
3.0 dB
In Active
In Active
-After
exiting
from
Dormant
Range
D
0.0 dB
(default)
1.5 dB
3.0 dB
4.5 dB
-Selected Transmission Speed Range
This field indicates the range of transmission
speed.
00b = Range A (default)
01b = Range B
10b = Range C
11b = Range D
(See Note (2))
Selected PHY Major Revision
This field is reserved for future use.
--
-After
exiting
from
Dormant
---
Note:
(1) In Ring connection, Host shall issue broadcast CCMD for writing PHY Settings Register.
(2) Detailed definitions of Transmission Speed Range are shown in Table 6-12. Host may support only Range A and it may
support an arbitrary RCLK frequency from 26 MHz to 52 MHz. On the other hand, Device whose PHY Major Revision is
equal to 00b (UHS156), shall support both Range A and B, and all RCLK frequency from 26 MHz to 52 MHz. In addition,
Device whose PHY Major Revision is equal to 01b (UHS624) shall support all ranges from Range A to Range D, and all
RCLK frequency defined in Table 6-12.
Table 6-11 : PHY Settings Register
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Range
A
B
C
D
3611
3612
3613
3614
Table 6-12 : Detailed Definitions of Transmission Speed Range
0000b
0001b
0010b
:
1111b
3626
3627
3628
RCLK Frequency RCLK:D0/D1
Range [MHz]
Ratio
Min
Max
26
52
1:15
26
52
1:30
48
52
1:60
48
52
1:120
Note:
(1) ±1% margin is allowable for both minimum and maximum RCLK Frequency.
Register
Value
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
Speed Range
[Mbps]
Min
Max
390
780
780
1,560
2,880
3,120
5,760
6,240
T_EIDL_RECOVERY
Range
Range C Range D
A, B
16SI
32SI
64SI
16SI
64SI
128SI
16SI
96SI
192SI
:
:
:
16SI
512SI
1024SI
Range
A, B
8SI
8SI
8SI
:
8SI
T_EIDL_GAP
Range C Range D
16SI
32SI
48SI
:
256SI
32SI
64SI
96SI
:
512SI
Note:
(1) All of them are defined as minimum value.
(2) T_EIDL_RECOVERY is calculated by 32*(n+1) [SI] for Range C, and 64*(n+1) [SI] for Range D respectively, where n is
the register value.
(3) T_EIDL_GAP is calculated by 16*(n+1) [SI] for Range C, and 32*(n+1) [SI] for Range D respectively, where n is the
register value.
(4) The value of “Driver Enabling / Disabling Period” is fixed to 4SI (max) for Range C and 8SI (max) for Range D respectively
regardless of this register value. In case of Range C, for example, as "Driver Enabling / Disabling Period" is equal to 4SI
(max), the value of "Stable STB.L Duration for detection" is 28SI (min) for 0000b and 60SI (min) for 0001b respectively.
Table 6.2.9- 1 : Register Values for T_EIDL_RECOVERY/GAP
6.2.9.2.6 LINK/TRAN Settings Register
The table shown below describes LINK/TRAN Settings Register.
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Location
63-40
39-32
Attrib
Register Field Name and Explanation
Rsvd
RW
31-20
RW
19-18
17-16
Rsvd
RW
15-08
RW
-N_DATA_GAP
This field indicates minimum number of DIDL
between DATA packets determined through
Configuration. Initiator shall send DIDL at
least N_DATA_GAP between EOP and SOP
with in the DATA Burst. It is common for both
read and write transaction.
MAX_BLKLEN
This field indicates maximum payload length
of one block in byte determined through
Configuration (000h is reserved). Block
Length shall be smaller or equal to this value
(refer to Section 6.2.8.2 for more details).
If bit 16 in Generic Capabilities Register is
equal to 1 ("Application Type" is SD-memory),
this field shall be 200h (512 bytes).
Default value is 200h.
-MAX_RETRY_NUM
This field indicates maximum retry times of
DATA Burst Retry (refer to Section 5.5.4). If
MAX_RETRY_NUM = 00b, DATA Burst Retry
becomes disable.
Default value is 11b.
N_FCU
This field indicates maximum number of
blocks in a flow control unit (FCU) determined
through Configuration. 00h means 256.
Default value is 01h. (See Note (3) and (4).)
--
07-00
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
Rsvd
Writable
State
Config/
Active
Effective
Timing
-In Active
(See Note
(1))
CMD
category
Broadcast
/P2P
In Active
(See Note
(2))
-In Active
(See Note
(1))
In Active
(See Note
(1))
--
Note:
(1) It is immediately effective in Active State.
(2) It is immediately effective in Active State if there are no application specific layers. With any application specific layers, this
parameter is not reflected immediately if it is written in Active State.
(3) If bit 16 in Generic Capabilities Register is equal to 1 ("Application Type" is SD-memory), its possible settings are 01h,
02h, 04h, 08h, 10h, 20h, 40h, and 80h.
(4) The length of a DATA Burst obtained by Block Length and N_FCU shall be smaller than or equal to 64K (65,536) bytes
Table 6-13 : LINK/TRAN Settings Register
6.2.9.2.7 Preset Register
The table shown below describes Preset Register.
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Location
63-08
07-04
Attrib
Rsvd
HwInit
03-00
HwInit
Register Field Name and Explanation
CDCP
This field indicates the value of CDCP (Candidate DCP) for Device
Initialization. Refer to Section 6.2.6 for more details.
GN
This field indicates the value of GN (Group Number) for Device Initialization.
Refer to Section 6.2.6 for more details.
Table 6-14 : Preset Register
3641
3642
3643
3644
3645
3646
6.2.10 Status Register (ST_REG)
3647
3648
3649
6.2.10.1 Register Map
Table 6-15 shows the map of ST_REG. Offset means the relative address based on ST_BASE.
Status Register indicates detecting error and states of CM-TRAN. ST_REG can be accessed by CCMD,
not DCMD.
Offset
Byte address
0000h
:
0003h
0004h
:
01FFh
Register
IOADR
000h
:
000h
001h
:
07Fh
(00)
Status in TRANS_ABORT
(31)
Reserved
3650
3651
Table 6-15 : Status Register
3652
3653
3654
3655
6.2.10.2 ST_REG Description
The details of ST_REG fields are described below. Refer to Table D- 1 for the description of "Attrib" in
this specification.
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
6.2.10.2.1 Status in TRANS_ABORT Register
The table shown below describes Status in TRANS_ABORT Register. After I/F power cycle or
FULL_RESET, all bits in this field are set to 0.
Fields of TBSM, TPSM and TSSM are updated only when Device accepts TRANS_ABORT CCMD, and
reflected the last status of each state machine before accepting TRANS_ABORT CCMD.
On the other hand, fields of error identifier (refer to Section 5.2.5) are updated when each error is
detected, and cleared after Device issues RES of the corresponding any P2P commands for that
Device other than TRANS_ABORT. Different from RECOVERABLE_ERROR in MSG (STAT),
RECOVERABLE_ERROR in ST_REG shall be accumulated until its clear condition described above is
satisfied.
This Register can be read by CCMD, but it makes sense only when Host can get RES of the previous
TRANS_ABORT.
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3669
3670
3671
3672
Location
31-25
24
Attrib
Rsvd
RO
23-19
18
Rsvd
RO
17
RO
16
RO
15-12
11-08
Rsvd
RO
07-04
RO
03-00
RO
Register Field Name and Explanation
RECOVERABLE_ERROR
It indicates whether RECOVERABLE_ERROR occurs or not. (See Note (1).)
0b = no error
1b = error
RETRY_EXPIRE_ERROR
It indicates whether RETRY_EXPIRE_ERROR occurs or not. (See Note (1).)
0b = no error
1b = error
DEVICE_SPECIFIC_ERROR
It indicates whether DEVICE_SPECIFIC_ERROR occurs or not. (See Note
(1).)
0b = no error
1b = error
ILLEGAL_HEADER_ERROR
It indicates whether ILLEGAL_HEADER_ERROR occurs or not. (See Note
(1).)
0b = no error
1b = error
TSSM
It indicates the last TSSM when receiving TRANS_ABORT.
0000b = TS_INIT
0001b = TS_STNBY
0011b = TS_SCBSY
0010b = TS_SCRDY
Others = Reserved
TPSM
It indicates the last TPSM when receiving TRANS_ABORT.
0000b = TP_IDLE
0001b = TP_WAIT
0110b = TP_INTERVAL
0010b = TP_DIN
0100b = TP_DOUT
1000b = TP_C_WAIT
Others = Reserved
TBSM
It indicates the last TBSM when receiving TRANS_ABORT.
0000b = TB_BUSY
0001b = TB_IN_REQ
0011b = TB_IN_PREP
0010b = TB_IN_RDY
0100b = TB_OUT_PREP
1100b = TB_OUT_REQ
1000b = TB_OUT_RDY
Others=Reserved
Note:
(1) Refer to Section 5.2.5 for the definition of each error identifier.
Table 6-16 : Status in TRANS_ABORT Register
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3673
3674
3675
3676
6.2.11 Interrupt Register (INT_REG)
3677
3678
3679
6.2.11.1 Register Map
Table 6-17 shows the map of INT_REG. Offset means the relative address based on INT_BASE.
Interrupt can be operated through INT_REG. INT_REG can be accessed by CCMD, not DCMD.
If the application is SD-memory, it is not necessary to implement INT_REG.
Offset
Byte address
0000h
:
0003h
0004h
:
0007h
0008h
:
01FFh
Register
IOADR
000h
:
000h
001h
:
001h
002h
:
07Fh
(00)
INT Enable
(31)
(00)
INT Status
(31)
Reserved
3680
3681
Table 6-17 : Interrupt Register
3682
3683
3684
3685
6.2.11.2 INT_REG Description
The details of INT_REG fields are described below. Refer to Table D- 1 for the description of "Attrib" in
this specification.
3686
3687
3688
3689
3690
6.2.11.2.1 INT Enable
The table shown below describes INT Enable Register. Up to eight kinds of interrupt factors (from
Factor#0 to Factor#7) can be defined in UHS-II. In this specification, all interrupt factors are not defined
and reserved for the future specifications.
Location
31-08
07-00
Attrib
Rsvd
RW
Register Field Name and Explanation
INT Enable
This field indicates enables of each interrupt factors. Location X (0 ≤ X ≤ 7)
corresponds to the enable bit for Factor#X.
0b = Interrupt disable
1b = Interrupt enable
3691
3692
Table 6-18 : INT Enable Register
3693
3694
3695
3696
3697
6.2.11.2.2 INT Status
The table shown below describes INT Status Register. Up to eight kinds of interrupt factors (from
Factor#0 to Factor#7) can be defined in UHS-II. In this specification, all interrupt factors are not defined
and reserved for the future specifications.
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Location
31-08
07-00
3698
3699
3700
3701
3702
3703
3704
Attrib
Rsvd
RO
Register Field Name and Explanation
INT Status
This field indicates status for each interrupt factors. Location X (0 ≤ X ≤ 7)
corresponds to the status bit for Factor#X.
0b = Interrupt is not pending
1b = Interrupt is pending
Table 6-19 : INT Status Register
6.2.12 Command Register (CMD_REG)
UHS-II native commands are executed by "writing" to the specific address in CMD_REG by CCMD, not
DCMD.
Table 6-20 shows CMD_REG. Offset means the relative address based on CMD_BASE.
Offset
Register Field Name and Explanation
Byte
IOADR
address
FULL_RESET
0000h
000h
- To reset all components in Device (same situation
before I/F power up).
- Refer to Section 6.2.5 for more details.
GO_DORMANT_STATE
0004h
001h
- To make DLSM transit to Dormant state for power
saving including Hibernate Mode.
- Refer to Section 6.2.4 for more details.
DEVICE_INIT
0008h
002h
- To start Device Initialization according to the payload
settings.
- Refer to Section 6.2.6 for more details.
ENUMERATE
000Ch
003h
- To perform Device Enumeration.
- Refer to Section 6.2.7 for more details.
TRANS_ABORT
0010h
004h
- To abort outstanding transaction.
- In case of UHS-II native protocol, this command also
terminates the DATA Burst transmission.
- TRANS_ABORT shall terminate all existing
transactions regardless of its TID.
- Refer to Section 3.4.5 for more details.
Others
Reserved
3705
3706
PLEN
CMD
category
00b
Broadcast/
P2P
01b
(4 bytes)
Broadcast/
P2P
01b
(4 bytes)
Broadcast
01b
(4 bytes)
Broadcast
00b
P2P
---
---
Table 6-20 : Command Register
Application Note:
In case of Ring connection, Host shall not issue P2P FULL_RESET CCMD or P2P
GO_DORMANT_STATE CCMD.
3707
3708
3709
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6.2.13 Transaction Control and Management State Machine
3711
3712
3713
3714
3715
3716
3717
3718
6.2.13.1 Transaction Scheduling State Machine (TSSM)
Transaction Scheduling State Machine (TSSM) is the state machine for managing conditions of issuing
commands considering multiple command execution.
TSSM observes execution states of each TID (the execution states are managed in Transaction
Processing State Machine) and controls available timing of issuing commands (for example, available
timing for issuing a TRANS_ABORT CCMD during DCMD execution).
Figure 6-38 shows the state diagram of TSSM.
Initial State
TS_INIT
A
B
TS_STNBY
C
D
TS_SCBSY
E
: Interface is deactivated
(CMD can not be issued)
F
: Interface is activated
(CMD can be issued)
TS_SCRDY
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
Figure 6-38 : State Diagram of TSSM
The TSSM state definitions are the following;
• TS_INIT: Before interface activation.
• TRAN directs LINK to start PHY wakeup process in this state (DLSM is in Dormant, or
Wakeup).
• Any command can not be issued.
• TS_STNBY: Command scheduling standby.
• No transaction is in execution.
• Arbitrary CCMD or DCMD can be issued. However, issuing DCMD is permitted only in
Active State of DLSM.
• TS_SCBSY: Command scheduling busy.
• At least one transaction is in execution and either transaction is not in Command Time
Slot (CTS).
• Host can issue TRANS_ABORT and FULL_RESET CCMD when it detects illegal
situations such as timeout. In addition, Host can not issue any other command than
TRANS_ABORT or FULL_RESET CCMD.
• Device should accept TRANS_ABORT and FULL_RESET CCMD. If Device does not
respond to TRANS_ABORT or FULL_RESET CCMD, Device behavior is undefined.
• TS_SCRDY: Command scheduling ready.
• At least one transaction is in execution and all of transaction is in CTS.
• Specific CCMD can be issued.
• TRANS_ABORT CCMD can be issued in this state to terminate data transaction.
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3745
3746
3747
Transition conditions of TSSM are shown in Table 6-21.
Case
A
TSSM Transition
Current State
Next State
TS_INIT
TS_STNBY
DLSM transition from Wakeup to Config
TS_INIT
DLSM transition from Config to Dormant
DLSM transition from Active to Dormant
C
TS_SCBSY
At least one TPSM is in TP_WAIT (*1)
D
TS_STNBY
All of TPSMs are in TP_IDLE (*1)
TS_SCRDY
Both of the following conditions are met.
- All of transactions are in either CTS or TP_IDLE of TPSM
- At least one transaction is in CTS
TS_SCBSY
At least one transaction is not in CTS and not in TP_IDLE of TPSM
B
TS_STNBY
TS_SCBSY
E
F
3748
3749
3750
3751
3752
3753
3754
3755
3756
Transition Timing (Condition)
TS_SCRDY
*1: During multiple command execution, TPSM is managed for each transaction. For example, two transactions are
executed at the same time, two TPSMs are managed in TRAN.
Table 6-21 : Transaction Conditions of TSSM
6.2.13.2 Transaction Processing State Machine (TPSM)
TRAN controls all transactions by Transaction Processing State Machine (TPSM).
Both Host and Device have TPSM, and the states of TPSM in Host and Device are transferred in
relation to each other through packet transaction and an indication from LINK.
Figure 6-39 shows the state diagram of TPSM.
Initial State
TP_IDLE
H
J
A
B
TP_WAIT
C
L
TP_DIN
D
G
TP_INTERVAL
F
E
I
TP_DOUT
K
TP_C_WAIT
3757
3758
3759
3760
Figure 6-39 : State Diagram of TPSM
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3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
The TPSM state definitions are the following;
• TP_IDLE: Before starting transaction.
• Host can issue arbitrary CCMD or DCMD only in this state.
• TP_WAIT: Expecting response.
• Device will transmit RES or Broadcast CCMD if no errors occur.
• Host is waiting for RES after issuing P2P CCMD or DCMD, or waiting for Broadcast
CCMD.
• Device can issue Broadcast CCMD, RES and MSG.
• Host is not allowed to issue any packet including MSG in this state.
• TP_INTERVAL: Interval period between data transfers.
• Both Host and Device wait for "flow control handshake completion" notification from LINK.
(Refer to Chapter 0 for details of flow control.)
• Host can issue a particular CCMD for controlling transaction before issuing a flow control
MSG.
[e.g. TRANS_ABORT CCMD]
In the case of data read transaction, Host shall issue TRANS_ABORT CCMD before
issuing FCRDY MSG. In the case of data write, Host shall issue TRANS_ABORT CCMD
before issuing FCREQ MSG.
• TP_DIN: Receiving DATA.
• Only DATA packet can be received in this state.
• TP_DOUT: Transmitting DATA.
• Only DATA packet can be transmitted in this state.
• TP_C_WAIT: Waiting for RES to CCMD.
• Host waits for RES to CCMD which is issued during TP_INTERVAL.
• Only RES and MSG from Device can be issued.
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3788
Transition conditions of TPSM are shown in Table 6-22.
Case
A
TPSM Transition
Current State
Next State
TP_IDLE
B
TP_WAIT
Receiving CCMD or DCMD.
TP_IDLE
Transmitting RES for CCMD.
Transmitting RES with NACK = 1 for CMD (See Note (1)).
Transmitting broadcast CCMD.
Detecting error from broadcast CCMD (See Note (2))
TP_WAIT
C
TP_INTERVAL Transmitting RES with NACK = 0 for DCMD.
TP_DIN
TBSM transition from TB_IN_PREP to TB_IN_RDY.
TP_DOUT
TBSM transition from TB_OUT_REQ to TB_OUT_RDY.
F
TP_C_WAIT
Receiving CCMD during TP_INTERVAL.
G
TP_INTERVAL
Transmitting STAT MSG in case of not completing all DATA Bursts reception, including in
case of DCMD with LM = 0. (See Note (3))
H
TP_IDLE
Completing all DATA Bursts reception (in case of DCMD transaction with LM = 1) and
transmitting STAT MSG without any error indications.
I
TP_INTERVAL
Receiving STAT MSG in case of not completing all DATA Bursts transmission, including in
case of DCMD with LM = 0. (See Note (3))
TP_IDLE
Completing all DATA Bursts transmission (in case of DCMD transaction with LM = 1) and
receiving STAT MSG without any error indications.
D
E
TP_INTERVAL
TP_DIN
TP_DOUT
J
K
TP_C_WAIT
L
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
Transition Timing (Condition)
Transmitting RES for CCMD (except FULL_RESET (P2P) and TRANS_ABORT).
TP_INTERVAL Transmitting RES with NACK = 1 for CCMD (See Note (1)).
Detecting error from FULL_RESET (broadcast) (See Note (2))
TP_IDLE
Transmitting RES for FULL_RESET(P2P) or TRANS_ABORT.
Transmitting FULL_RESET broadcast CCMD.
Note:
(1) Refer to Section 6.2.15.1 when detecting errors from P2P CCMD or DCMD.
(2) Refer to Section 6.2.15.3 when detecting errors from broadcast CCMD.
(3) If DATA Burst retry is going to be taken place next time, TPSM transits to TP_INTERVAL, not TP_IDLE.
Table 6-22 : Transaction Conditions of TPSM
In case of timeout, Device may receive TRANS_ABORT or FULL_RESET CCMD in TP_WAIT, TP_DIN
or TP_DOUT. In this case, its TPSM transits to TP_IDLE after it transmits RES to TRANS_ABORT or
FULL_RESET. If Device does not respond to TRANS_ABORT or FULL_RESET CCMD, Device
behavior is undefined.
Examples of TPSM transition during data read and write transactions are shown in Figure 6-40.
Message packet is defined in Section 5.2.4 as a Link Layer Packet. Flow control message (FCREQ and
FCRDY MSG) handshake is performed in LINK. Moreover, detecting "data burst end" is also performed
in LINK.
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Host
Device
time
RCLK
D0
CLK Active
DCMD
(read)
D1
TPSM
(Host)
RES
TP_IDLE
DCMD transfer
TPSM
(Device)
TP_IDLE
DCMD transfer
Host
FC
RDY
TP_WAIT
RES transfer
TP_WAIT
RES transfer
FC
REQ
DATA0
TP_DIN
TP_INTERVAL
TP_INTERVAL
TP_DOUT
[TBSM transition] from
TB_OUT_REQ to TB_OUT_RDY
D1
DATA3
TP_DIN
[LINK]
STAT transmission
[TBSM transition] from
TB_IN_PREP to TB_IN_RDY
TP_INTERVAL
DATA2
TP_IDLE
[LINK] All data reception
and STAT transmission
TP_INTERVAL
TP_DOUT
[LINK]
STAT reception
TP_IDLE
[LINK] All data transmission
and STAT reception
Device
CLK Active
DCMD
(write)
FC
REQ
TP_IDLE
TP_IDLE
DCMD transfer
TP_WAIT
RES transfer
TP_WAIT
RES transfer
DATA0
TP_INTERVAL
TP_DOUT
[TBSM transition] from
TB_IN_PREP to TB_IN_RDY
DATA2
TP_INTERVAL
[LINK]
STAT reception
TP_DIN
TP_INTERVAL
[LINK]
STAT transmission
D0
DATA3
FC
RDY
STAT
[TBSM transition] from
TB_OUT_REQ to TB_OUT_RDY
TP_INTERVAL
RCLK
FC
REQ
DATA1
FC
RDY
RES
DCMD transfer
TPSM
(Device)
FC
REQ
DATA1
D0
STAT
time
D1
TPSM
(Host)
FC
RDY
STAT
RCLK
D0
RCLK
D1
STAT
TP_DIN
TP_IDLE
[LINK] All data transmission
and STAT reception
TP_DOUT
TP_IDLE
[LINK] All data reception
and STAT transmission
: TRAN Layer Packet
: LINK Layer Packet (MSG)
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3812
3813
3814
3815
3816
Figure 6-40 : State Transition of TPSM during Data Transaction
6.2.13.3 Transaction Buffer-management State Machine (TBSM)
Input/Output buffer state is managed by Transaction Buffer-management State Machine (TBSM) in
TRAN.
The states of input/output buffer transmit according to Flow Control sequence performed in LINK. TRAN
informs LINK of the buffer state, and LINK informs TRAN of flow control information such as
FCREQ/FCRDY transmission and reception.
Figure 6-41 shows the state diagram of TBSM.
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Initial State
TB_BUSY
H
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3841
B
A
TB_IN_REQ
TB_OUT_PREP
D
C
TB_IN_PREP
TB_OUT_REQ
F
E
TB_IN_RDY
TB_OUT_RDY
Input Buffer
Output Buffer
G
Figure 6-41 : State Diagram of TBSM
The TBSM state definitions are the following;
• TB_BUSY: Input/Output buffer is busy.
• DCMD is not issued, or DCMD is issued and output buffer is not ready to transmit data.
[Input buffer state]
• TB_IN_REQ: FC handshake is requested
• Data receiver is requested to make input buffer prepared for receiving data and reply
FCRDY MSG.
• TB_IN_PREP: Input buffer is prepared.
• Input buffer is prepared for receiving DATA packets, and TRAN allows LINK to issue
FCRDY MSG in the case that there is no CCMD (e.g. TRANS_ABORT CCMD) to issue.
• TB_IN_RDY: Ready to receive data.
• Data receiver is waiting for receiving DATA packets, or data receiver is currently receiving
DATA packets.
[Output buffer state]
• TB_OUT_PREP: Output buffer is prepared.
• Output buffer is prepared for transmitting DATA packets, and TRAN allows LINK to issue
FCREQ MSG in the case that there is no CCMD (e.g. TRANS_ABORT CCMD) to issue.
• TB_OUT_REQ: FC handshake is requested.
• Data initiator waits for FCRDY MSG from data receiver.
• TB_OUT_RDY: Ready to transmit data.
• Data initiator is currently transmitting DATA packets.
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Transition conditions of TBSM are shown in Table 6-23
Case
TBSM Transition
Current State
Next State
Transition Timing (Condition)
TB_OUT_PREP Output buffer ready
A
TB_BUSY
B
TB_IN_REQ
FCREQ reception in LINK
C
TB_OUT_PREP
TB_OUT_REQ
FCREQ transmission in LINK
D
TB_IN_REQ
TB_IN_PREP
Input buffer ready
E
TB_OUT_REQ
TB_OUT_RDY
FCRDY reception in LINK
F
TB_IN_PREP
TB_IN_RDY
FCRDY transmission in LINK
G
TB_OUT_RDY
Completion of a DATA Burst transmission in LINK
TB_BUSY
H
3844
3845
3846
3847
3848
3849
3850
TB_IN_RDY
Completion of a DATA Burst reception in LINK
Table 6-23 : Transaction Conditions of TBSM
If Device receives TRANS_ABORT CCMD in TB_IN_REQ, TB_IN_RDY, TB_OUT_PREP,
TB_OUT_REQ, and TB_OUT_RDY, its TBSM transits to TB_BUSY after it transmits RES to
TRANS_ABORT.
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Examples of TBSM transition during data read and write transactions are shown in Figure 6-42. This
figure includes TPSM transition as a reference.
Host
Device
time
CLK Active
RCLK
D1
(Host)
TBSM
TPSM
TBSM
TPSM
FC
REQ
RES
TP_IDLE
DCMD
transmission
(Device)
FC
RDY
DCMD
(read)
D0
TB_BUSY
TP_WAIT
RES
transmission
TB_IN_REQ
TB_BUSY
TP_IDLE TP_WAIT
[LINK]
FCRDY transmission
TB_OUT_REQ
TP_INTERVAL
TB_OUT_PREP
Output buffer
ready
[LINK]
FCRDY reception
[LINK]
FCREQ transmission
FC
REQ
DATA1
TB_IN_RDY
TP_DIN
TB_IN_PREP
TP_INTERVAL
[LINK]
FCREQ reception
FC
RDY
STAT
DATA0
Input buffer
ready
RCLK
DATA2
Input buffer
ready
[LINK]
FCREQ reception
TB_OUT_RDY
TP_DOUT
TB_B TB_OUT_
USY PREP
[LINK] Completion of
a DATA burst transmission
Output buffer
ready
D1
DATA3
TB_IN_RDY
TP_DIN
TB_BUSY TB_IN_REQ TB_IN_PREP
TP_INTERVAL
[LINK] Completion of
a DATA burst reception
D0
STAT
[LINK]
FCRDY transmission
TB_OUT_REQ
TP_INTERVAL
TB_BUSY
TP_IDLE
[LINK] Completion of
a DATA burst reception
TB_OUT_RDY
TP_DOUT
[LINK]
FCRDY reception
TB_BUSY
TP_IDLE
[LINK] Completion of
a DATA burst transmission
[LINK]
FCREQ transmission
Host
Device
time
CLK Active
RCLK
D0
(Host)
FC
REQ
DCMD
(write)
D1
RES
Output buffer
ready
TBSM
TPSM
TB_BUSY
TP_IDLE TP_WAIT
TB_OUT_PREP
DATA0
[LINK]
FCREQ transmission
(Device)
TBSM
TPSM
TP_IDLE
TB_BUSY
TP_WAIT
TB_IN_REQ
[LINK]
FCRDY reception
TB_IN_PREP
TP_INTERVAL
[LINK]
FCREQ reception
FC
REQ
DATA1
FC
RDY
TB_OUT_REQ
TP_INTERVAL
Input buffer
ready
[LINK]
FCRDY transmission
RCLK
STAT
TB_OUT_RDY
TP_DOUT
Output buffer
ready
TB_OUT_REQ
TP_INTERVAL
[LINK]
FCREQ transmission
TB_OUT_RDY
TP_DOUT
[LINK]
FCRDY reception
Input buffer
ready
D1
[LINK]
FCRDY transmission
TB_BUSY
TP_IDLE
[LINK] Completion of
a DATA burst transmission
TB_IN_RDY
TP_DIN
TB_BUSY TB_IN_REQ TB_IN_PREP
TP_INTERVAL
[LINK] Completion of
a DATA burst reception
D0
DATA3
STAT
TB_B TB_OUT_
USY PREP
[LINK] Completion of
a DATA burst transmission
TB_IN_RDY
TP_DIN
DATA2
FC
RDY
TB_BUSY
TP_IDLE
[LINK] Completion of
a DATA burst reception
[LINK]
FCREQ reception
: TRAN Layer Packet
: LINK Layer Packet (MSG)
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3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
: CTS
Figure 6-42 : State Transition of TBSM and TPSM during Data Transaction
6.2.13.4 Detail Definition of Command Time Slot
Command Time Slot (CTS) is defined as a time period that FULL_RESET, TRANS_ABORT, and
arbitrary read CCMD are allowed to be issued or accepted on the way of data transmission. Note that
other CCMDs and all DCMDs are prohibited to issue during CTS at UHS-II Addendum Version 1.02.
Moreover at UHS-II Addendum Version 1.02, while Host is executing data transaction for one Device,
Host shall not issue any commands to other Devices, even in CTS period.
From Device's point of view, definition of CTS is as follows.
• During read transaction, CTS is when TPSM is TP_INTERVAL.
• During write transaction, CTS is when TPSM is TP_INTERVAL and TBSM is TB_BUSY.
On the other hand, definition of CTS is as follows from Host's point of view.
• During read transaction, CTS is when TPSM is TP_INTERVAL.
• During write transaction, CTS is when TPSM is TP_INTERVAL and TBSM is either TB_BUSY or
TB_OUT_PREP.
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Figure 6-43 illustrates the relation between CTS and read CCMD.
Host
Device
time
RCLK
CLK Active
DCMD
(read)
D0
FC
RDY
D1
(Host)
TBSM
TPSM
RES
TP_IDLE
DCMD
transmission
(Device)
TBSM
TPSM
FC
REQ
TB_BUSY
TP_WAIT
TB_IN_REQ
TB_OUT_REQ
TP_INTERVAL
TB_IN_REQ
TB_IN_PREP
DATA2
D1
DATA3
TB_IN_RDY
TP_DIN
TP_IDLE
TB_OUT_RDY
TP_DOUT
TP_IDLE
TB_BUSY
RES reception
TB_OUT_REQ
TP_INTERVAL TP_C_WAIT TP_INTERVAL
TB_BUSY
Output buffer
ready
Device
time
CLK Active
DCMD
(write)
D0
FC
REQ
D1
RES
TBSM
TPSM
TB_BUSY
TP_IDLE TP_WAIT
DCMD
transmission
TBSM
TPSM
TB_BUSY
TB_B TB_OUT_
USY PREP
TB_OUT_RDY
TP_DOUT
TB_OUT_PREP
RCLK
(Device)
Input buffer
ready
Read CCMD
transmission
Output buffer
ready
(Host)
RES
D0
STAT
TP_INTERVAL TP_C_WAIT TP_INTERVAL
RES
reception
TB_BUSY
TP_IDLE TP_WAIT
Host
FC
REQ
DATA1
TB_IN_RDY
TP_DIN
TB_IN_PREP
TP_INTERVAL
FC
RDY
CCMD
(read)
STAT
DATA0
Input buffer
ready
RCLK
DATA0
FC
RDY
Output buffer
ready
TB_OUT_REQ
TP_INTERVAL
TB_OUT_PREP
TB_BUSY
TP_WAIT
FC
REQ
CCMD
(read)
DATA1
DATA2
TB_OUT_RDY
TP_DOUT
TB_BUSY
TP_INTERVAL
TB_OUT_PR
EP
TP_C_WAI
T
TB_OUT_REQ
TP_INTERVAL
Read CCMD
transmission
TB_IN_REQ
TB_IN_PREP
TP_INTERVAL
TB_IN_RDY
TP_DIN
Input buffer
ready
D0
DATA3
FC
RDY
RES
STAT
Output buffer
ready
RES
reception
TP_IDLE
RCLK
D1
STAT
TB_OUT_RDY
TP_DOUT
TP_IDLE
TB_IN_RDY
TP_DIN
TP_IDLE
TB_BUSY
RES reception
TB_BUSY
TP_INTERVAL
TP_C_WAI
T
TB_IN_RE TB_IN_PR
Q
EP
TP_INTERVAL
TB_BUSY
Input buffer
ready
: TRAN Layer Packet
: LINK Layer Packet (MSG)
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3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
: CTS
Figure 6-43 : Relation between CTS and TP_C_WAIT
As mentioned above, arbitrary read CCMD can be issued during CTS. In case of read transaction, Host
can transmit it during CTS regardless of FCREQ reception. However, Host shall not transmit MSG
(FCRDY) before receiving RES accompanied with the read CCMD.
In case of write transaction, on the other hand, Host shall not transmit MSG (FCREQ) before receiving
RES if read CCMD issued during CTS.
UHS-II Addednum 2.00 allows issuing arbitrary write CCMD during CTS, if “CCMD during Data
Transfer” is equal to 1b in LINK/TRAN Capabilities Register (refer to Table 6-9).
6.2.13.5 State Machines during Boot Code Loading
As described in Section 5.9, when Boot Device is directed to execute Boot Code Loading by BSYN
LSS, it transits to Active state after PLL lock acquisition. In this time, TBSM, TPSM and TSSM are
defined as follows.
• TBSM:
• Initial State is TB_BUSY.
• For Boot Device, TBSM transits to TB_OUT_PREP, TB_OUT_REQ, TB_OUT_RDY, and
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3910
•
goes back to TB_BUSY again during the period of one FCU transmission, according to
the condition described in Table 6-23.
For Host, TBSM transits to TB_IN_REQ, TB_IN_PREP, TB_IN_RDY, and goes back to
TB_BUSY again during the period of one FCU reception, according to the condition
described in Table 6-23.
• TPSM:
• Initial State is TP_INTERVAL.
• For Boot Device, TPSM toggles between TP_INTERVAL and TP_DOUT according to the
condition described in Table 6-24.
• For Host, TPSM toggles between TP_INTERVAL and TP_IN according to the condition
described in Table 6-24. Note that Host cannot issue any commands even in
TP_INTERVAL during Boot Code Loading.
• TSSM:
• Fixed to TS_SCBSY.
Case
TPSM Transition
Current State
Next State
E’
TP_INTERVAL
I’
TP_DOUT
D’
TP_INTERVAL
G’
TP_DIN
TP_DOUT
Transition Timing (Condition)
Note
TBSM transition from TB_OUT_REQ to TB_OUT_RDY
Applied for Boot Device
TP_INTERVAL Completion of a DATA Burst transmission and STAT MSG reception
TP_DIN
TBSM transition from TB_IN_PREP to TB_IN_RDY.
Applied for Host
3911
3912
3913
3914
TP_INTERVAL Completion of a DATA Burst reception and STAT MSG transmission
Table 6-24 : Transaction Conditions of TPSM while Boot Code Loading
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6.2.14 Transaction Rules
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3923
6.2.14.1 Control Transaction Sequence
Figure 6-44 illustrates an example sequence of control read transaction.
In this section, example sequences of control transaction and data transaction in native protocol (NP =
1) are described. About the error case, refer to Section 6.2.15 for details of error sequence.
Both Host and Device shall set the same TID of the CMD to the corresponding RES, DATA, and MSG
within a transaction. Moreover, Host should transmit packets with TID = 0.
R/W=read
PLEN=read data length
IOADR=I/O address
Node ID=0
Node ID=1
Device
CCMD
(Read)
Host
D0
D0
RES
NACK=CMD is accepted
PLEN=same as CMD
IOADR=same as CMD
D1
D1
Payload=
read data
Control Trans.
START
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3930
3931
3932
3933
3934
3935
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3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
Header
Time →
Control Trans.
END
Argument
Payload
Figure 6-44 : Example Sequence of Control Read Transaction
Host issues a CCMD to obtain the I/O register values from Device (control read operation).
In control read operation, requested read data (I/O register values) is assigned in payload field in RES
associated with the corresponding CCMD, and sent to Host from Device.
The detailed field values of CCMD in Figure 6-44 are as follows;
• Header (CCMD):
• NP = 1 (native protocol)
• Packet Type = CCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (CCMD):
• R/W = read
• PLEN = read data length
• IOADR = the I/O space address to read data
• Payload (CCMD):
• In the case of control read operation, payload field in CCMD does not exist.
The detailed field values of RES associated with CCMD in Figure 6-44 are as follows;
• Header (RES):
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• NP = 1 (native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding CCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID in the corresponding CCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• PLEN = the same value as PLEN in the corresponding CCMD
• IOADR = the same value as IOADR in the corresponding CCMD
• Payload (RES):
• Requested read data by Host.
• In the case that PLEN=0 in the corresponding CCMD, this field does not exist.
Figure 6-45 illustrates an example sequence of control write transaction.
R/W=write
PLEN=write data length
IOADR=I/O address
Node ID=0
Node ID=1
Device
CCMD
(Write)
Host
D0
D0
NACK=CMD is accepted
PLEN=same as CMD
IOADR=same as CMD
RES
Payload=
write data
D1
D1
Time →
Control Trans.
START
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3967
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3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
Header
Control Trans.
END
Argument
Payload
Figure 6-45 : Example Sequence of Control Write Transaction
Host issues a CCMD to configure the I/O register values of Device (control write operation).
In control write operation, write data transferred to I/O register is assigned in payload field in the CCMD,
and sent to Device from Host.
The detailed field values of CCMD in Figure 6-45 are as follows;
• Header (CCMD):
• NP = 1 (native protocol)
• Packet Type = CCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (CCMD):
• R/W = Write
• PLEN = write data length
• IOADR = the I/O space address to write data
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3990
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3992
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3994
3995
3996
3997
3998
3999
4000
4001
4002
• Payload (CCMD):
• Write data to be transferred to I/O register in Device.
• In the case that PLEN=0, this field does not exist.
The detailed field values of RES associated with CCMD in Figure 6-45 are as follows;
• Header (RES):
• NP = 1 (native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding CCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID of the corresponding CCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• PLEN = the same value as PLEN in the corresponding CCMD
• IOADR = the same value as IOADR in the corresponding CCMD
• Payload (RES):
• In the case of control write operation, payload field in RES does not exist.
6.2.14.2 Data Transaction Sequence (Outline)
In this section, some data transaction sequences are described only by TLP.
Figure 6-46 illustrates an example sequence of data read transaction (LM = 1 and TLUM = 0).
Node ID=0
R/W=read
TMODE
Node ID=1
DADR=data address
TLEN=4 blocks
D0
Device
DCMD
(Read)
Host
D0
DATA1
DATA2
DATA
DATA
DATA0
DATA
D1
DATA
RES
NACK=CMD is accepted
TMODE
- same as CMD
Payload=
read data
Data Trans.
START
D1
DATA3
Time →
FCU period
FCU period
Data Trans.
END
Interval
Header
Argument
Extended Argument
Payload
Settings
4003
4004
4005
4006
4007
• N_FCU = 2 blocks (number of packets within a FCU)
• TMODE
- DM = FD mode
- LM = data transfer length is specified
- TLUM = Block Mode
- DAM = memory access mode
Figure 6-46 : Example Sequence of Data Read Transaction (LM = 1, TLUM = 0)
Host issues a DCMD (read) to obtain the data in memory address space or UHS-II I/O address space
(data read operation). The requested read data is assigned in Payload field of DATA and sent to Host
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4014
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4019
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4021
4022
4023
4024
4025
4026
4027
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4029
4030
4031
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4033
4034
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4041
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4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
from Device.
In the case that Host issues a DCMD with LM = 1, and in this case, TLEN field exists.
The detailed field values of DCMD (read) in Figure 6-46 are as follows;
• Header (DCMD):
• NP = 1 (native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (DCMD):
• R/W = Read
[TMODE]
• DM = FD mode (It depends on whether Host chooses "FD mode" or "2L-HD mode" for
data transfer mode.)
• LM = Data transfer length is specified (TLEN field in Extended Argument exists.)
• TLUM = Block Mode.
• DAM = Memory access mode
• Extended Argument (DCMD):
• DADR = Address of Memory address space for read data (DAM = 0)
• TLEN = 4 blocks (total length of data transferred during a data transaction)
The detailed field values of RES associated with DCMD (read) in Figure 6-46 are as follows;
• Header (RES):
• NP = 1 (native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• TMODE = the same value as TMODE of the corresponding DCMD
• Payload (RES):
• In the case of data transaction, payload field in RES does not exist.
The detailed field values of DATA in Figure 6-46 are as follows;
• Header (DATA):
• NP = 1 (native protocol)
• Packet Type = DATA
• DID = 0 (Node ID of Host)
• SID = 1 (Node ID of source Device)
• TID = the same value as TID of the corresponding DCMD
• Payload (DATA): requested read data by Host
In this case, Host is not required to issue TRANS_ABORT CCMD to terminate the data transmission.
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Figure 6-47 illustrates an example sequence of data write transaction (LM = 1 and TLUM = 0).
Node ID=0
R/W=write
TMODE
DADR=data address
TLEN=4 blocks
Node ID=1
Payload=
write data
DATA1
DATA2
DATA
DATA
DATA
DATA
DATA0
D0
DATA3
RES
D0
Device
DCMD
(Write)
Host
D1
D1
NACK=CMD is accepted
TMODE
- same as CMD
Data Trans.
START
Time →
FCU period
FCU period
Data Trans.
END
Interval
Header
Argument
Extended Argument
Payload
Settings
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4062
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4071
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4073
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4075
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4077
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4079
4080
• N_FCU = 2 blocks (number of packets within a FCU)
• TMODE
- DM = FD mode
- LM = data transfer length is specified
- TLUM = Block Mode
- DAM = memory access mode
Figure 6-47 : Example Sequence of Data Write Transaction (LM = 1, TLUM = 0)
Host issues a DCMD (write) to update or store data in memory address space or I/O address space
(data write operation). The prepared write data is assigned in Payload field of DATA and sent to Device
from Host.
The detailed field values of DCMD (write) in Figure 6-47 are as follows;
• Header (DCMD):
• NP = 1 (native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (DCMD):
• R/W = Write
[TMODE]
• DM = FD mode (It depends on whether Host chooses "FD mode" or "2L-HD mode" for
data transfer mode.)
• LM = Data transfer length is specified (TLEN field in Extended Argument exists.)
• TLUM = Block Mode.
• DAM = Memory access mode.
• Extended Argument (DCMD):
• DADR = Address of Memory address space for write data (DAM = 0).
• TLEN = 4 blocks (total length of data transferred during a data transaction)
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4091
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4094
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4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
The detailed field values of RES associated with DCMD (write) in Figure 6-47 are as follows;
• Header (RES):
• NP = 1 (native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• TMODE = the same value as TMODE of the corresponding DCMD
• Payload (RES):
• In the case of data transaction, payload field in RES does not exist.
The detailed field values of DATA in Figure 6-47 are as follows;
• Header (DATA):
• NP = 1 (native protocol)
• Packet Type = DATA
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Payload (DATA): transferred write data to Device
In this case, Host is not required to issue TRANS_ABORT CCMD to terminate the data transmission.
Figure 6-48 illustrates an example sequence of data write transaction (LM = 1, TLUM = 1).
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Node ID=0
R/W=write
TMODE
DADR=data address
TLEN=176 bytes
Node ID=1
Payload size =
176 bytes
DATA
DA
TA0
D0
RES
D0
Device
DCMD
(Write)
Host
D1
D1
NACK=CMD is accepted
TMODE
- same as CMD
Data Trans.
START
Header
FCU period
Argument
Time →
Data Trans.
END
Extended Argument
Payload
Settings
Block Length is determined as 512 bytes
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
• N_FCU = 2 blocks (number of packets within a FCU)
• TMODE
- DM = FD mode
- LM = data transfer length is specified
- TLUM = Byte Mode
- DAM = memory access mode
Figure 6-48 : Example Sequence of Data Write Transaction (LM = 1, TLUM = 1)
As mentioned in Section 5.2.6.2.2 TLEN shall be less than or equal to Block Length. So in this example,
only one DATA whose payload size is 176 bytes is transmitted in FCU period, and then the transaction
finishes without TRANS_ABORT CCMD.
In this case, LM shall be 1. Otherwise, the DCMD shall be regarded as illegal (ARG_ERR).
The detailed field values of DCMD (write) in Figure 6-48 are as follows;
• Header (DCMD):
• NP = 1 (native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (DCMD):
• R/W = write
[TMODE]
• DM = FD mode (It depends on whether Host chooses "FD mode" or "2L-HD mode" for
data transfer mode.)
• LM = Data transfer length is specified (TLEN field in Extended Argument exists.)
• TLUM = Byte Mode
• DAM = Memory access mode.
• Extended Argument (DCMD):
• DADR = Address of Memory address space for write data (DAM = 0).
• TLEN = 176 bytes (total length in byte of data transferred during a data transaction)
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4141
4142
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4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
The detailed field values of RES associated with DCMD (write) in Figure 6-48 are as follows;
• Header (RES):
• NP = 1 (native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
[TMODE]
• TMODE = the same value as TMODE of the corresponding DCMD
• Payload (RES):
• In the case of data transaction, payload field in RES does not exist.
The detailed field values of DATA in Figure 6-48 are as follows;
• Header (DATA):
• NP = 1 (native protocol)
• Packet Type = DATA
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Payload (DATA): Transferred write data to Device. Payload size of the DATA packet (DATA0) is
176 bytes.
In this case, Host is not required to issue TRANS_ABORT CCMD to terminate the data transmission.
Figure 6-49 illustrates an example sequence of data read transaction (LM = 0).
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Node ID=0
R/W=read
TMODE
Node ID=1
TRANS_
ABORT
DADR=data address
DCMD
(Read)
D0
Device
CCMD
(Write)
Host
D0
DATA2
RES
DATA1
DATA
DATA
DATA0
DATA
D1
DATA
RES
NACK=CMD is accepted
TMODE
- same as CMD
DATA3
D1
Payload=
read data
Data Trans.
START
Header
Time →
FCU period
Argument
FCU period
Data Trans.
END
Interval
Interval
Extended Argument
Payload
Settings
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
• N_FCU = 2 blocks (number of packets within a FCU)
• TMODE
- DM = FD mode
- LM = data transfer length is not specified
- TLUM = Block Mode
- DAM = memory access mode
Figure 6-49 : Example Sequence of Data Read Transaction (LM = 0)
In the case that Host issues a DCMD for infinite data transfer, LM in DCMD is set to '0' (data transfer
length is not specified) and TLEN field does not exist. In this case, Host shall issue TRANS_ABORT
CCMD during interval period (CTS in other words) to terminate data transaction.
The detailed field values of DCMD (read) in Figure 6-49 are as follows;
• Header (DCMD):
• NP = 1 (native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (DCMD):
• R/W = Read
[TMODE]
• DM = FD mode (It depends on whether Host chooses "FD mode" or "2L-HD mode" for
data transfer mode.)
• LM = Data transfer length is not specified (TLEN field in Extended Argument does not
exist.)
• TLUM = Block Mode (Note that TLUM shall be Block Mode if LM = 0)
• DAM = Memory access mode.
• Extended Argument (DCMD):
• DADR = Address of Memory address space for read data (DAM = 0)
The detailed field values of RES associated with DCMD (read) in Figure 6-49 are as follows;
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4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
• Header (RES):
• NP = 1 (native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• TMODE = the same value as TMODE of the corresponding DCMD
• Payload (RES):
• In the case of data transaction, payload field in RES does not exist.
The detailed field values of DATA in Figure 6-49 are as follows;
• Header (DATA):
• NP = 1 (native protocol)
• Packet Type = DATA
• DID = 0 (Node ID of Host)
• SID = 1 (Node ID of source Device)
• TID = the same value as TID of the corresponding DCMD
• Payload (DATA): Requested read data by Host
6.2.14.3 Data Transaction Sequence (Detail)
In this section, transaction sequences including both TLP and LMSG (Link Message Packet) are
described to show the order of CMD-RES handshake, flow control, and data transmission
Figure 6-50 illustrates an example sequence of data read transaction including LMSG.
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Host
Device
MSG
(STAT)
DATA
2
D0
DATA
DATA
1
DATA
MSG
(FCREQ)
MSG
(STAT)
DATA
0
DATA
DATA
D1
MSG
(FCREQ)
RES
DCMD
(Read)
D0
MSG
(FCRDY)
Node ID=1
MSG
(FCRDY)
Node ID=0
DATA
3
D1
Time →
Data Trans.
START
Header
4217
4218
4219
4220
4221
Interval period
Argument
Interval period
FCU period
Extended Argument
FCU period
Data Trans.
END
Payload
Transaction Layer Packet
Settings
Link Layer Packet (Link Message Packet)
• N_FCU = 2 blocks (number of packets within a FCU)
• TMODE
- DM = FD mode
- LM = data transfer length is specified
- TLUM = Block Mode
- DAM = memory access mode
Figure 6-50 : Example Sequence of Data Read Transaction with LMSG
Figure 6-51 illustrates an example sequence of data write transaction including LMSG.
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Node ID=1
DATA
DATA
3
D0
MSG
(STAT)
MSG
(FCRDY)
DATA
2
DATA
Device
MSG
(FCREQ)
DATA
DATA
1
MSG
(STAT)
D1
DATA
0
MSG
(FCRDY)
RES
DCMD
(Write)
D0
MSG
(FCREQ)
Host
DATA
Node ID=0
D1
Time →
Data Trans.
START
Header
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
Interval period
Argument
Interval period
FCU period
Extended Argument
FCU period
Data Trans.
END
Payload
Transaction Layer Packet
Settings
Link Layer Packet (Link Message Packet)
• N_FCU = 2 blocks (number of packets within a FCU)
• TMODE
- DM = FD mode
- LM = data transfer length is specified
- TLUM = Block Mode
- DAM = memory access mode
Figure 6-51 : Example Sequence of Data Write Transaction with LMSG
After CMD-RES handshake between Host and Device, flow control handshake is performed by FCREQ
and MSG (FCRDY).
In the case that flow control handshake is done, data transfer is started and continued until N_FCU data
packets are transmitted. (In the above example, data transfer is continued until 2 data blocks are
transmitted.)
After N_FCU data packets transmission, MSG (STAT) including error identifier is issued from data
receiver side. If there are no errors in the transferred data, flow control handshake and data transfer are
performed continuously.
Both cases described in Figure 6-50 and Figure 6-51, Host is not required to issue TRANS_ABORT
CCMD to terminate the data transmission.
4236
6.2.15 Error Handling
4237
4238
4239
4240
4241
4242
4243
4244
6.2.15.1 NACK Notification for Command Error
If CM-TRAN in Device detects a UHS-II command error in TP_IDLE or TP_INTERVAL state, Device
shall send RES with NACK = 1 to Host to notify error occurrence and its descriptions immediately. As a
result, the command is not performed.
ECODE can be assigned in RES (NACK = 1) as described in Table 6-4.
Figure 6-52 illustrates an example of CCMD error sequence.
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Node ID=1
Host
Device
CCMD
Node ID=0
D0
D0
RES
NACK=1
ECODE
D1
D1
Time →
Control Trans.
START
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4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
Header
Control Trans.
END
Argument
Argument field in RES includes
“error descriptions”.
Payload
Figure 6-52 : CCMD Error Sequence
In the case that the corresponding CCMD has an error, Device sends RES with NACK = 1 (Negative
Acknowledgement) to Host to notify error occurrence and its descriptions immediately. After the RES is
issued, the control transaction is finished.
The detailed field values of RES in Figure 6-52 are as follows;
• Argument (RES):
• NACK = 1 (The corresponding CCMD has an error.)
• ECODE = (It depends on the reason of errors.)
• Payload (RES):
• Payload field does not exist.
Other field values in Header are set to the same value as Header in RES (NACK = 0).
In the case of error with read CCMD, read transaction is aborted and Device sends RES (NACK = 1)
without requested data.
In the case of error with write CCMD, write transaction is aborted and Device sends RES (NACK = 1).
The transferred data is not written in register of Device.
Figure 6-53 illustrates an example of DCMD error sequence.
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Node ID=1
Host
Device
DCMD
Node ID=0
D0
D0
RES
NACK=1
ECODE
D1
D1
Time →
Data Trans.
START
Data Trans.
END
Data transaction is aborted.
(DATA packet is not transferred.)
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
Header
Argument
Payload
Figure 6-53 : DCMD Error Sequence
In the case that the corresponding DCMD has an error, Device sends RES with NACK = 1 to Host to
notify error occurrence and its descriptions immediately. After the RES is issued, DATA packet is not
transferred and the data transaction is aborted. Only the RES with error code in its payload field is sent
to Host from Device.
The detailed field values of RES in Figure 6-53 are as follows;
• Argument (RES):
• NACK = 1 (The corresponding DCMD has an error.)
• ECODE = (It depends on error cause.)
• Payload (RES):
• Payload field does not exist.
Other field values in Header are set to the same value as Header in RES (NACK = 0).
6.2.15.2 Error Notification during Data Transaction
DATA Burst error notification is taken place by STAT MSG, and DATA Burst Retry is taken place as
described in Section 5.5.4.
Figure 6-54 illustrates an example of DATA read sequence when Host detects
UNRECOVERABLE_ERROR from receiving DATA Burst. In this example, Host shall issue STAT MSG
with UNRECOVERABLE_ERROR = 1 and should issue TRANS_ABORT CCMD to terminate the data
transaction.
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Node ID=0
UNRECOVERABLE_
ERROR =error
CCMD
(Write)
MSG
(STAT)
D0
RES
DATA
0
DATA
DATA
D1
MSG
(FCREQ)
RES
DCMD
(Read)
D0
Device
MSG
(FCRDY)
Host
Node ID=1
TRANS_
ABORT
DATA
1
D1
Time →
Data Trans.
START
Interval period
Data Trans.
END
FCU period
Interval period
Header
4293
4294
4295
4296
4297
4298
4299
Argument
Extended Argument
Payload
Transaction Layer Packet
Settings
Link Layer Packet (Link Message Packet)
• N_FCU = 2 blocks (number of packets within a FCU)
• TMODE
- DM = FD mode
- LM = data transfer length is specified
- TLUM = Block Mode
- DAM = memory access mode
Figure 6-54 : Example Sequence Including UNRECOVERABLE_ERROR with Read Data Packet
Figure 6-55 illustrates an example of DATA write sequence when Host detects
UNRECOVERABLE_ERROR from receiving STAT MSG. In this example, Host should issue
TRANS_ABORT CCMD to terminate the data transaction.
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Node ID=0
CCMD
(Write)
DATA
DATA
1
MSG
(STAT)
D0
RES
DATA
DATA
0
MSG
(FCRDY)
RES
DCMD
(Write)
D1
Device
MSG
(FCREQ)
Host
D0
Node ID=1
TRANS_
ABORT
D1
UNRECOVERABLE
_ERROR =error
Data Trans.
START
Interval period
Time →
Data Trans.
END
FCU period
Interval period
Header
4300
4301
4302
4303
4304
4305
4306
4307
Argument
Extended Argument
Payload
Transaction Layer Packet
Settings
Link Layer Packet (Link Message Packet)
• N_FCU = 2 blocks (number of packets within a FCU)
• TMODE
- DM = FD mode
- LM = data transfer length is specified
- TLUM = Block Mode
- DAM = memory access mode
Figure 6-55 : Example Sequence Including UNRECOVERABLE_ERROR with Write Data Packet
6.2.15.3 Error Detection from Broadcast CCMD
As mentioned in Section 6.2.2.3, if Device detects some error from receiving broadcast CCMD, it does
not transmit the command to the next node.
Figure 6-56 illustrates a sequence when Device detects error from broadcast CCMD.
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Node ID=1
Host
Device
Broadcast
CCMD
Node ID=0
D0
D0
D1
D1
Host detects Tfwd_bcmd timeout
(in case of P2P connection)
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
Header
Argument
Device does not transmit
broadcast CCMD if it detects
error.
Time →
Payload
Figure 6-56 : Sequence in Case of Error Detection from Broadcast CCMD
In this case, Host can detect the error on the broadcast CCMD by timeout which is estimated by
Tfwd_bcmd (refer to Table 6-25) and the number of connected Devices.
6.2.15.4 Fractional DATA Burst in LM = 0
Figure 6-57 illustrates an example sequence of data write transaction if fractional DATA Burst is
transmitted in LM = 0.
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Fractional DATA Burst
(illegal in LM = 0)
DATA
2
D0
MSG
(STAT)
MSG
(FCRDY)
DATA
MSG
(FCREQ)
DATA
DATA
1
Node ID=1
Device
MSG
(STAT)
D1
DATA
0
MSG
(FCRDY)
RES
DCMD
(Write)
D0
MSG
(FCREQ)
Host
DATA
Node ID=0
RECOVERABLE_E
RROR =error
Data Trans.
START
Header
4318
4319
4320
4321
4322
4323
4324
4325
Interval period
Argument
Interval period
FCU period
Extended Argument
D1
Time →
FCU period
Payload
Transaction Layer Packet
Settings
Link Layer Packet (Link Message Packet)
• N_FCU = 2 blocks (number of packets within a FCU)
• TMODE
- DM = FD mode
- LM = data transfer length is not specified
- TLUM = block unit
- DAM = memory access mode
Figure 6-57 : Example Sequence of Write Transaction with Fractional DATA Burst in LM = 0
As mentioned in Section 5.2.6.2, fractional DATA Burst is permitted only in LM = 1 except when the data
transfer length is determined by another means. So If Device detects that DATA2 is fractional DATA
Burst, Device regards as FRAME_ERROR and transmits MSG (STAT) with RECOVERABLE_ERROR =
error.
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6.3 Timing Rules
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
6.3.1 Overview
Device shall keep the following timing rules and Host should detect errors by timeout.
If Host detects that one of these rules is violated, it transits its DLSM to Active.Control, then it issues
TRANS_ABORT CCMD after transmitting LIDL or EIDL according to the setting of "Power Control Mode
in Active.Control State". If it fails to receive RES of TRANS_ABORT, it should manage to recover from
the illegal situation by other means (for example, by taking place I/F power cycle). These timing rules
are given for a single UHS-II Device, and note that Host shall consider accumulated timings in case of
Multi-device connection.
From Device's point of view, Device shall respond for TRANS_ABORT CCMD during TP_IDLE state or
CTS, and otherwise, it responds if it can recognize the CCMD.
Table 6-25 shows Device timing parameters, and Figure 6-58 and Figure 6-59 illustrates the period for
applying the timing rules for some parameter groups. Host estimates system's timeout values according
to Table 6-25.
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Group
Wakeup
Abbreviation
Teidl_stb
Tactivate
Tlidl_lidl
Tlidl_fcreq_boot
Initialization
Tfwd_init_cmd
Basic
Tcmd_res
Tfwd_bcmd
Flow
Control
Tres_fcreq(r)
Tres_fcreq(w)
Tstat_fcreq(r)
Tstat_fcreq(w)
Tfcrdy_edb
Tfcreq_fcrdy(r)
Tfcreq_fcrdy(w)
Tedb_stat
4340
4341
4342
4343
4344
4345
Note:
Description
Max Value
Time from first STB, after EIDL, on 200 [usec]
Device Rx to STB on Device Tx.
Time from first STB on Device Tx to first 100 [msec] (at the first
SYN LSS on Device Tx.
time after power up, or in
case of recovering from
Hibernate mode. See
Note (1))
2 [msec] (otherwise)
Time from LIDL on Device Rx to LIDL on 750 [RCLK cycle]
Device Tx.
Time from LIDL on Boot Device Rx to the 1 [sec]
first SOP FCREQ for the Boot Code on
Boot Device Tx.
Time from DEVICE_INIT CCMD EOP 1 [sec] (See Note (1))
reception on Device Rx to its SOP
transmission on Device Tx
Time from P2P CCMD or DCMD EOP 5 [msec]
reception on Device Rx to RES SOP
transmission on Device Tx.
Time from broadcast CCMD (except 5 [msec]
DEVICE_INIT) EOP reception on Device
Rx to its SOP transmission on Device Tx.
Time from RES EOP reception to Defined in application
FCREQ SOP transmission in read specific layers (See Note
(2).)
transaction.
Time from RES EOP reception to N/A
FCREQ SOP transmission in write
transaction
Time from STAT EOP reception to Defined in application
FCREQ SOP transmission in read specific layers (See Note
transaction. This is related to read busy (2).)
timeout.
Time from STAT EOP reception to N/A
FCREQ SOP transmission in write
transaction.
From FCRDY EOP reception to DATA 20 [msec]
Burst EDB transmission
Time from FCREQ EOP reception to N/A
FCRDY SOP transmission in read
transaction.
Time from FCREQ EOP reception to Defined in application
FCRDY SOP transmission in write specific layers (See Note
transaction. This is related to write busy (2).)
timeout.
From DATA Burst EDB reception to STAT 200 [usec]
SOP transmission
(1) Device shall also satisfy the inequation Tactivate + Tfwd_init_cmd(s) + Tfwd_init_cmd(c) ≤ 1 [sec], where.
• Tfwd_init_cmd(s) is duration of DEVICE_INIT CCMD by which Device starts its Device Initialization process
• Tfwd_init_cmd(c) is duration of DEVICE_INIT CCMD which Device transmits at the completion of Device
Initialization process.
(2) In case of SD-memory Card, refer to SD-TRAN specification (Chapter 7).
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Table 6-25 : Device Timing Parameters in CM-TRAN
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4347
T1
time
RCLK
EIDL
Line A
EIDL
Line B
T3
T4
STB.L
T8 T9
T7
T10
BSYN BSYN BSYN BSYN BSYNBSYNBSYN BSYN LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL
BSYNBSYN BSYN BSYN BSYN BSYN LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL
STB.L
EIDL
DLSM
Dormant
PLL
(MUL)
Before
Activation
BSYN BSYNBSYN BSYN LIDL LIDL LIDL LIDL LIDL SOP
STB.L
Sync
During Lock Acquisition
DLSM
Dormant
Wakeup
Activate
PLL
(MUL)
Before
Activation
During Lock Acquisition
Tactivate
Teidl_stb
Tlidl_lidl
(Config g) Active
Sync
Control
After Lock Acquisition
Tactivate
Tlidl_lidl
Tlidl_
fcreq_boot
Period for Boot Code Loading
Period for Boot Code Preparation
4348
4349
4350
4351
4352
4353
4354
4355
4356
EDB DIDL
After Lock Acquisition
Teidl_stb
Period for
applying
Timing Rules
Boot
Code
FCREQ
(Config g) Active
Control
Wakeup
Activate
Period for
applying
Timing Rules
Device#2
T5' T6
T5
RCLK Active
EIDL
Line C
Device#1
T2
Note:
(1) All Devices that transmit or bypass Boot Code shall transmit the first FCREQ for Boot Code Loading after the elapse of
more than 16 LSS (32 SI) period from the time transiting from Wakeup to Active state. In addition, Device to bypass Boot
Code shall set its "Config Completion" to 1 after the elapse of less than 16 LSS (32 SI) period from the time receiving
LIDL.
(2) Refer to Figure 5-20 for the definition of Line A, B, and C.
Figure 6-58 : Device Timing Parameters Related to Wakeup Group
Tcmd_res
Tedb_stat
Tfcrdy_edb
Tfcreq_fcrdy(r)
Host
Tfcrdy_edb
Device
time
RCLK
D0
Tedb_stat
Tfcreq_fcrdy(r)
Tstat_fcrec(r)
Tres_fcreq(r)
RCLK
CLK Active
DCMD
(read)
D1
FC
RDY
RES
FC
REQ
STAT
DATA0
FC
RDY
CCMD
(read)
FC
REQ
DATA1
RES
D0
STAT
DATA2
D1
DATA3
Tcmd_res
Tcmd_res
Host
Tres_fcreq(w)
Tfcrdy_edb
Tfcreq_fcrdy(w)
D1
4357
4358
4359
4360
Tstat_fcreq(w)
Tfcreq_fcrdy(w)
Tfcrdy_edb
Tedb_stat
Device
time
RCLK
D0
Tedb_stat
RCLK
CLK Active
DCMD
(write)
FC
REQ
RES
DATA0
CCMD
(read)
DATA1
FC
RDY
STAT
FC
REQ
RES
DATA2
FC
RDY
D0
DATA3
D1
STAT
Tcmd_res
Figure 6-59 : Device Timing Parameters Related to Basic or Flow Control Group
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4361
4362
4363
6.3.2 Example Sequence of Timeout Occurrence
Figure 6-60 illustrates an example sequence when Host cannot receive the RES of CCMD.
Node ID=0
TRANS_
ABORT
Node ID=1
Read
ST_REG
CCMD
(Read)
D1
4364
4365
4366
4367
4368
4369
4370
Header
Missing RES for
the first CCMD
Argument
D1
Payload=
ST_REG
Tcmd_res
Control Trans.
START
D0
RES
RES
CCMD
D0
Device
CCMD
(Write)
Host
Time →
Control Trans.
END
Payload
Figure 6-60 : Example Sequence When Missing RES
When Host detects timeout of Tcmd_res, Host should issue TRANS_ABORT CCMD to terminate the
first CCMD transaction. Then Host should read error identifiers and status of Device indicated in
Device's ST_REG.
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Figure 6-61 illustrates an example sequence when Host cannot receive FCRDY MSG during data
transaction.
Node ID=0
CCMD
(Write)
Payload=
ST_REG
Tfcreq_fcrdy(w)
Data Trans.
START
4374
4375
4376
4377
4378
4379
4380
4381
D0
RES
RES
Missing FCRDY
Header
Node ID=1
Read
ST_REG
Device
MSG
(FCREQ)
DATA
DATA
1
MSG
(STAT)
D1
DATA
0
MSG
(FCRDY)
RES
DCMD
(Write)
D0
MSG
(FCREQ)
Host
DATA
TRANS_
ABORT
CCMD
(Read)
4371
4372
4373
D1
Time →
Data Trans.
END
Argument
Extended Argument
Payload
Transaction Layer Packet
Settings
Link Layer Packet (Link Message Packet)
• N_FCU = 2 blocks (number of packets within a FCU)
• TMODE
- DM = FD mode
- LM = data transfer length is not specified
- TLUM = block unit
- DAM = memory access mode
Figure 6-61 : Example Sequence When Missing FCRDY during Write Transaction
When Host detects timeout of Tfcreq_fcrdy(w) during data transaction, Host should issue
TRANS_ABORT CCMD to terminate this transaction. Note that this TRANS_ABORT also terminates the
outstanding data transmission in UHS-II native protocol. In this case, transmitted data is not
guaranteed. Then Host should read error identifiers and status of Device indicated in Device's ST_REG.
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SD-TRAN rides over CM-TRAN and acts as bridge between Legacy SD protocol and UHS-II common
protocol for SD-compatibility. This chapter presents encapsulated SD packet formats, transaction
sequences, initialization for SD-TRAN, state machine, error handling and timing rules. These are based
on CM-TRAN specification, but SD-memory is applied to some specific rules described in this chapter.
In this case, the specific rules in SD-TRAN are effective instead of those in CM-TRAN.
In this section, UHS-II specifications for SD-memory are described, not included for SDIO.
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
SD-TRAN
( SD specific)
Application
specific layer
7.1 SD-TRAN Overview
Transaction
4390
4391
7. SD-TRAN Specification
CM-TRAN
( Common layer)
4382
4383
4384
4385
4386
4387
4388
4389
SD CMD/ RES/ DAT
SD Card Register
* * -TRAN
( extensible TRAN for future use)
SD State Machine
Protocol Bridge (SD< -> CM)
Tran Management
Transactions (Data, Control)
Extended Part (2nd gen or later)
TPSM
Enumeration
CMD Queuing
TBSM
Configuration
Relaxed Ordering
TSSM
Common Packets (DCMD, CCMD, RES, DATA)
I D based Mux/ Demux
Figure 7-1 : SD-TRAN Overview
The features of SD-TRAN are shown below;
• Preserving Legacy SD infrastructures (CMD, RES, status, errors and etc.)
• Bridging between Legacy SD protocol (e.g. Host/Device register interface) and UHS-II common
protocol (CM-TRAN)
7.1.1 Packet Types and Format Overview
Encapsulated SD packets are defined in SD-TRAN in order to ensure Legacy SD compatibility and
preserve Legacy SD infrastructures.
Conceptual diagram of SD-encapsulation is shown in Figure 7-2.
UHS-II Packet
(abstract)
Header Argument
Payload
SD CMD / RES / DATA
4406
4407
4408
4409
4410
Legacy SD CMD/RES/DATA are
encapsulated in Argument and/or
Payload field of UHS-II packet
Figure 7-2 : Conceptual Diagram of SD-encapsulation
SD-encapsulation formats in each types of TLP are shown in Figure 7-3.
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CCMD
Argument
Argument
Header
Header R/W
Payload
Payload
(only
(only write
write CCMD)
CCMD)
PLEN,
PLEN, I/O
I/O Address
Address
R/W
Cmd
Index
(Rsvd)
PLEN
Argument
CRC7
SD Control Command (e.g. CMD8, 12, etc.)
DCMD
Header
Header R/W
Extended
Extended Argument
Argument
Argument
Argument
R/W TMODE
TMODE
Rsvd
Rsvd
Data
Data Address
Address
TLEN
TLEN
(TMODE)
Cmd
Index
Argument (data address)
TLEN (In case of CMD18, 25)
(Rsvd)
CRC7
SD Data Command (e.g. CMD18, 25, etc.)
RES
Header
Header NACK
Argument
Argument
Payload
Payload
NACK
CMD_ECHO_BACK
CMD_ECHO_BACK
(only
(only read
read CCMD)
CCMD)
(Other than R2)
(NACK)
(CMD_ECHO
_BACK)
PLEN
Res
Content
(R2)
(NACK)
(CMD_ECHO
_BACK)
Res ContentPLEN
incl. internal CRC7
CRC7
SD Response
DATA
Header
Header
Payload
Payload
SD Data Block (typ. 512B)
: Packet Type
4411
4412
4413
4414
4415
4416
4417
CRC16
: Existence depends on transaction type
Figure 7-3 : Encapsulation of Legacy SD Format
Basically, CRC7 or CRC16 for Legacy SD are not overridden in SD-encapsulation format because all
TLPs are added CRC16 in Link Layer.
Details are described in next section.
4418
4419
4420
4421
7.1.2 Registers for Legacy SD
4422
7.2 SD-TRAN Protocol
4423
4424
4425
4426
7.2.1 Packet Format Details
4427
4428
4429
7.2.1.1 CCMD
Figure 7-4 illustrates CCMD on SD-TRAN.
Registers for Legacy SD such as CID or CSD can be accessed only by SD encapsulated CMD. For
example, when Host wants to get CID, Host sends an encapsulated CMD2 (ALL_SEND_CID).
In this section, the bracketed number in the figures denotes the bit position in Legacy SD command or
response format. Note that broadcast packet is not permitted in SD-TRAN.
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Bit
Byte
7
6
5
0
4
3
2
1
0
Header
(NP=0, Packet Type = CCMD)
1
2
Rsvd
3
Rsvd
4
[39]
:
APP [45]
CMD_INDEX
[40]
[32]
SD_ARG
:
7
Header
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
[8]
[15]
Argument
Payload
Encapsulated SD CMD /wo CRC7
Figure 7-4 : CCMD Format on SD-TRAN
• APP: Indicator for application command. APP = 1 means application command, otherwise regular
command. Device shall regard as application command if APP = 1.
• CMD_INDEX[5:0]: CMD Index in Legacy SD Command to be issued.
• SD_ARG: Corresponding argument for the Legacy SD Command.
• Notice the bit order of Payload field.
• Rsvd (Reserved): Reserved bits. Initiator (Host) shall set them to '0', and receiver (Device) shall
ignore them.
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4442
4443
4444
7.2.1.2 DCMD
Figure 7-5 illustrates DCMD on SD-TRAN.
Bit
Byte
7
6
5
0
4
3
2
1
0
Header
(NP=0, Packet Type = DCMD)
1
2
Rsvd
3
Rsvd
4
(msb)
5
TMODE
Rsvd
APP [45]
CMD_INDEX
[40]
SD_ARG
6
7
[8
(lsb)
(msb)
9
[TLEN]
10
11]
(lsb)
Header
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
Argument
Extended Argument
Encapsulated SD CMD /wo CRC7
Figure 7-5 : DCMD Format on SD-TRAN
• TMODE[3:0] (Transfer Mode): Parameter settings for data transaction.
• Host may set DM to 1 for DCMD which supports multi-block read / write regardless of
data transfer length (e.g., CMD18, CMD25). Otherwise, it shall not set DM to 1. (e.g.
CMD6, CMD17, CMD24). These rules are also applied to other multi-block read / write
commands defined in other Part of SD specifications (for example, Host may set DM to 1
for ACMD18 or ACMD25).
• LM is alternative only for CMD18 and 25, and it shall be set to 0 for other DCMDs.
• Both DAM and TLUM shall be set to 0.
• If Host issues DCMD with DM = 1 to Device which does not support 2L-HD mode, Device
returns RES with NACK = 1.
• APP: Indicator for application command. APP = 1 means application command, otherwise regular
command. Device shall regard as application command if APP = 1.
• CMD_INDEX[5:0]: CMD Index in Legacy SD Command to be issued.
• SD_ARG: Corresponding argument for the Legacy SD Command.
• TLEN[31:0] (Transfer Length): Total length of data transmitted during a data transaction
• This field exists only for CMD18 or CMD25 with LM = 1, and unit of TLEN is a block (512
bytes in SD-memory). It is strongly recommended for Host to be set LM = 1 and TLEN > 0
in case of CMD18 and CMD25.
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4467
4468
4469
4470
4471
4472
4473
• If TLEN = 0000000h, it does not effect the data transaction (same as LM = 0).
• It is transmitted in msb first, lsb last.
• Rsvd (Reserved): Reserved bits. Initiator (Host) shall set them to '0', and receiver (Device) shall
ignore them.
7.2.1.3 RES
Figure 7-6 illustrates the generic structure of RES associated with CCMD and DCMD on SD-TRAN.
Bit
Byte
7
0
6
5
4
3
2
1
0
Header
(NP=0, Packet Type = RES)
1
2
NACK=0
CMD_ECHO_BACK
(Argument of CMD is copied here)
3
4
:
CONTENT
:
7 or 19
Header
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
Argument
Payload
Encapsulated SD RES /wo CRC7
Figure 7-6 : RES Format on SD-TRAN (Generic)
• NACK (Negative Acknowledgement): Indicator whether the corresponding CMD is accepted or
not. In case of command error, refer to Section 7.2.1.4 and Section 7.2.8.2.
• CMD_ECHO_BACK[14:0] (Command Echo Back): Copied field of CMD Argument.
• The same values in Argument field such as CMD_INDEX or TMODE are copied from the
corresponding CMD (echo back). Specifically, [6:0] in the second byte, and [7:0] in the
third byte of CMD packet are copied to the same location of RES packet.
• CONTENT: Content of Response. Refer to Figure 7-7 for R2, and Figure 7-8 for other than R2 for
more details. Rsvd in Figure 7-7 is reserved bits, so initiator (Device) shall set it to '0' and receiver
(Host) shall ignore them.
DID field in Header is set to the same value as SID field in Header of the corresponding command. TID
field in Header is set to the same value as TID field in Header of the corresponding command.
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Bit
Byte
7
6
5
4
3
2
0
Header
1
(NP=0, Packet Type = RES)
2
NACK=0
0
CMD_ECHO_BACK
(Argument of CMD is copied here)
3
4
1
[127]
[120]
:
CID or CSD register incl.
internal CRC7
:
:
:
19
[7]
Header
4490
4491
4492
4493
[1]
Argument
Rsvd
Payload
Encapsulated SD RES
Note: In UHS-II mode, field of CRC7 in R2 response is not used to check CRC, and may be set any value
Figure 7-7 : RES Format on SD-TRAN (R2)
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Bit
Byte
7
6
5
4
3
2
0
Header
1
(NP=0, Packet Type = RES)
2
NACK=0
0
CMD_ECHO_BACK
(Argument of CMD is copied here)
3
4
1
[32]
[39]
5
Response Data
6
7
[8]
[15]
Header
4494
4495
4496
4497
4498
4499
4500
Encapsulated SD RES
Figure 7-8 : RES Format on SD-TRAN (Other than R2)
7.2.1.4 RES (NACK = 1)
Unlike the Legacy SD protocol, Device shall respond RES with NACK = 1 if it receives illegal CMD.
Figure 7-9 illustrates the RES with NACK = 1 on SD-TRAN.
Bit
Byte
7
6
0
2
5
4
3
2
1
0
Header
(NP=0, Packet Type = RES)
1
NACK=1
3
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
Payload
Argument
ECODE = 001b
Rsvd
Rsvd
Header
Argument
Figure 7-9 : RES (NACK = 1) Format on SD-TRAN
• NACK (Negative Acknowledgement): indicator whether the corresponding CMD is accepted or
not.
• NACK = 1 means the corresponding CMD is rejected.
• In the case of NACK = 1 (CMD is rejected), Device shall not execute the requested
operation (an error has occurred in the corresponding CMD).
• ECODE[2:0] (Error Code): Error code to represent error descriptions. It shall be set to 001b in
SD-TRAN.
• Rsvd (Reserved): Reserved bits. Initiator shall set them to '0', and receiver shall ignore them.
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4512
4513
4514
4515
7.2.1.5 DATA
Figure 7-10 illustrates DATA on SD-TRAN.
Bit
Byte
7
6
0
5
4
3
2
1
0
Header
(NP=0, Packet Type = DATA)
1
2
<LSB>
:
SD_DATA
:
:
<MSB>
Header
4516
4517
4518
4519
4520
4521
4522
4523
Payload
Encapsulated data payload on SD /wo CRC16
Figure 7-10 : DATA Format on SD-TRAN
• SD_DATA: Data included with DATA
• The length of Payload field depends on CMD_INDEX. Refer to Section 7.2.2 for more
details.
• It is transmitted in LSB first, MSB last.
4524
4525
4526
4527
4528
4529
7.2.1.6 Application Commands
In SD-TRAN, application commands such as ACMD41 shall be realized in one command by setting
APP field to 1b in CCMD or DCMD (refer to Section 7.2.1.1 and Section 7.2.1.2). Device ignores
CMD55 on SD-TRAN. Moreover, unlike Legacy SD, undefined ACMD such as ACMD42 or ACMD55 is
also handled as illegal command on SD-TRAN.
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
7.2.1.7 Note for Legacy SD Commands
Packet Type for each Legacy SD command in order to generate encapsulated UHS-II command
packets is defined as follows. The legacy command whose type is 'adtc' is assigned to DCMD, and
otherwise is assigned to CCMD. If Packet Type is not proper in encapsulated SD command, Device
shall return RES with NACK = 1. At the end of the transaction by CCMDs whose response are R1b or
all DCMDs, MSG (EBSY), which is defined in Section 7.2.6.3, is transmitted. Note that Device does not
send EBSY packet for the corresponding command if responding RES with NACK = 1.
These rules mentioned above are applied to all SD commands not only defined in Part 1 but also
defined in other Part of SD specifications such as Part 3. Note that DCMDs corresponding to security
command defined in such as Part 3 or Part A4 (DPS) shall be set LM to 0 and shall not have TLEN field.
The followings are additional rules for using Legacy SD command on UHS-II interface.
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CMD
CMD0
CMD7
CMD18, CMD25
CMD23
4544
4545
Description
The corresponding RES has no payload (refer to Section 7.2.6.2).
R1 returns when selected, RES without payload (refer to Section
7.2.6.2) returns when deselected.
Value of LM in TMODE is selectable by Host.
If Host would like to specify the data transmission length when issuing
CMD18 or CMD25, it shall set LM = 1 and assign the length to TLEN
field on CMD packet.
Table 7-1 : Additional Rules of Legacy SD Commands in UHS-II
4546
7.2.2 DATA Burst Framing Rules in SD-TRAN
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
7.2.2.1 Multi-block Read / Write Command
DATA Bursts accompanied by multi-block Read / Write command such as CMD18 or CMD25 shall
follow the DATA Burst framing rule in Block Mode described in Section 5.2.6.2.1. Note that Block Length
shall be 512 bytes in case of SD-memory, and the fractional DATA Burst is not permitted when LM = 0
except when the data transfer length for multi-block Read / Write command is determined by another
means. For example, as data transfer length for ACMD18 or ACMD25 is determined by ACMD45
previously, fractional DATA Burst is permitted for ACMD18 or ACMD25 even their LM is equal to 0. In
addition, fractional DATA Burst is also permitted for ACMD43 because its argument includes
'Unit_Count' (the number of blocks to read),
4557
4558
4559
4560
4561
4562
4563
7.2.2.2 CMD42
DATA Burst accompanied by CMD42 shall follow the DATA Burst framing rule in Byte Mode in Section
5.2.6.2.2. The payload length of DATA is equal to the block length set by CMD16 (regulated in Legacy
SD specification). Moreover, if block length set by CMD16 is odd, Host shall insert one PAD (K23.7) at
the end of DATA Packet in order to make the length of Framed DATA Packet even bytes, as shown in
Figure 5-10.
4564
4565
4566
4567
4568
7.2.2.3 Other DCMD on SD-TRAN
For other DCMD, DATA Bursts shall follow the DATA Burst framing rule in Byte Mode described in
Section 5.2.6.2.2. The payload length of DATA depends on the Legacy SD specification. For example,
payload length associated to CMD6 is 64 bytes.
4569
7.2.3 Interface Selection for UHS-II Card and Initialization
4570
4571
4572
4573
4574
4575
4576
7.2.3.1 Overview
As Hosts and Devices supporting UHS-II interface shall also support SD Legacy interface, Host
supporting UHS-II (simply described as "Host") interface may select either UHS-II interface or Legacy
SD interface after power up. Only in Section 7.2.3, "CMD" denotes the command described in SD
Physical Specification Version 4.00 or later, and SD command on UHS-II is described as "encapsulated
CMD".
4577
4578
4579
7.2.3.2 Interface Selection after Power Up
Figure 7-11 shows a concept diagram of initialization flow after power up.
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Power Up
From "data transfer mode in Legacy SD"
Host supplies VDD2, RCLK (and VDD1),
and sets STB.L on D0.Tx
No
CMD0
Host detects STB.L
on D1.Rx?
Host sets RCLK
Lane to DIF-Z
(to stop RCLK)
SD I/F is selected
Yes
UHS-II Initialization
PHY Initialization
• PLL Activation
• Establishing synchronization
• Disabling SD I/F
Host supplies
SDCLK
CMD0 (*1)
UHS-II SD
I/F
I/F
CMD8 (*2)
SEL
Configuration
enables to detect
Application Type is
SD-memory
Device Initialization
SEL
BE
Card Controller
Configuration
Card Controller
UHS-II I/F Deactivation
UHS-II SD
I/F
I/F
Enumeration
ACMD41
BE
Boot Code
Loading may
be executed.
UHS-II I/F is selected
GO_DORMANT_STATE
(*3)
Disabling UHS-II I/F
Initialization for SD-TRAN
(*4)
CMD2
"SD-TRAN card identification mode"
CMD8
ACMD41
CMD2
CMD3
CMD0
(SD-TRAN)
CMD3
"SD-TRAN data transfer mode"
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
"data transfer mode" in Legacy SD
Note:
(*1) CMD0 can be issued before CMD8.
(*2) CMD8 is mandatory because UHS-ll Card is not available over SDSC.
(*3) Refer to SD Specifications Part 1 Physical Layer Specification Version 4.00.
(*4) All CMDs are executed on SD-TRAN.
Figure 7-11 : Initialization Flow after Power Up
If Host intends to use UHS-II interface, it supplies VDD2, RCLK and VDD1 after power up, and sets
STB.L on D0.Tx. As described in Section 5.3, Device connects termination resistors of RCLK Lanes
after power up. Device starts PHY Initialization when receiving STB.L and responds STB.L if it
succeeds.
The method for Host to distinguish whether Device fails to start PHY initialization is through detecting
timeout from Host's setting STB.L on D0.Tx to receiving it on D1.Rx, which can be estimated from
Teidl_stb and UHS-II bus topology.
If Host detects timeout, Host sets RCLK Lane to DIF-Z to stop supplying RCLK, and then Host supplies
SDCLK and issues CMD8 and ACMD41 for Legacy SD protocol to initialize SD interface. Then, Host
proceeds card identification and the card status transits to "data transfer mode" in Legacy SD (same as
data transfer mode defined in SD Specifications Part 1 Physical Layer Specification Version 4.00 or
later) as a result. When Legacy SD interface is selected, UHS-II interface that is activated by power up
is disabled before ACMD41 is completed. Moreover, termination resistors of RCLK Lanes in Device are
disconnected when disabling UHS-II interface. As the sequence to "data transfer mode" in Legacy SD in
Figure 7-11 is simplified, refer to SD Specifications Part 1 Physical Layer Specification Version 4.00 or
later for detailed specifications of Legacy SD initialization. Note that if CMD0 is issued in Legacy SD
card state transits to 'idle'. (Note that it is impossible to execute (UHS-II) PHY Initialization.)
On the other hand, if Device succeeds PHY Initialization, UHS-II interface is available and then, Device
Initialization, Enumeration and Configuration are taken place in this order. If Host detects "Application
Type" is "SD memory" or "SDIO" during Configuration, it can issue the encapsulated SD CMD. Host
shall execute card identification described in Section 7.2.4.1 by encapsulated SD CMDs in case of
detecting "SD memory". If encapsulated CMD0 is issued, card state transits to 'idle' in SD-TRAN. On
the other hand, if FULL_RESET CCMD is issued, Device waits STB.L for PHY Initialization.
If Host intends to use only Legacy SD interface or detects that Legacy SD Card is inserted, it is allowed
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4609
4610
4611
4612
4613
4614
4615
to supply only VDD1 and SDCLK, and issue CMD8 in order to accelerate initialization of Legacy SD
interface. Note that once UHS-II I/F is disabled, Host requires power cycle to enable UHS-II again.
Refer to Section 3.10.4 in SD Specification Part 1 Version 4.00 or later for more details about VDD2
supply.
Note that Device's power consumption during Device Initialization is not regulated by Power Limit
specified by CMD6, but parameters specified by DEVICE_INIT CCMD.
4616
4617
4618
4619
7.2.3.3 Interface Selection after FULL_RESET or GO_DORMANT_STATE
Figure 7-12 shows a concept diagram of initialization flow after executing FULL_RESET or
GO_DORMANT_STATE CCMD.
FULL_RESET
From "SD-TRAN
data transfer mode"
From Dormant State
Host supplies VDD2, RCLK (and VDD1),
and sets STB.L on D0.Tx
No
Host detects STB.L
on D1.Rx?
Yes
UHS-II Initialization
PHY Initialization
Host executes Power Cycle
UHS-II I/F is selected
• PLL Activation
• Establishing synchronization
UHS-II SD
I/F
I/F
Device Initialization
Some of these
operations may be
skipped.
SEL
Enumeration
BE
Card Controller
Configuration
GO_DORMANT_STATE
Initialization for SD-TRAN
"SD-TRAN card identification mode"
CMD8
ACMD41
CMD2
CMD3
CMD0
(SD-TRAN)
"SD-TRAN data transfer mode"
4620
4621
4622
4623
4624
4625
4626
4627
4628
Figure 7-12 : Initialization Flow after FULL_RESET or GO_DORMANT_STATE
Host shall not select Legacy SD interface after issuing these CMDs. Then if Host detects that Device
fails to start PHY Initialization, Host requires power cycle to recover this illegal situation.
Setting of Power Limit specified by CMD6 is kept after recovering from Dormant State. After exiting
Dormant State and until going into Active state, power consumption of Device is up to 0.72W. Setting of
Power Limit which has been specified by CMD6 is effective in Active state again.
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Active state
Power Limit
setting by CMD6
GO_DORMANT
_STATE
PHY
Initialization
Power Limit
set by CMD6
4629
4630
4631
(Configuration)
0.72W
Power Limit
set by CMD6
Figure 7-13 : Power Consumption after Exiting from Dormant State
4632
4633
4634
4635
4636
4637
7.2.4 Transaction Control and Management State Machine
4638
4639
4640
7.2.4.1 Card Identification Mode
Figure 7-14 shows a state diagram for card identification mode on SD-TRAN.
From this section, an "encapsulated CMD" is described as just a "CMD" for simplicity (e.g.
"encapsulated CMD0" is described as "CMD0"). In this section, state diagrams in card identification
mode and data transfer mode for SD-TRAN are shown. They are based on those in Legacy SD, but
some differences exist as described below.
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To “PHY Initialization”
From UHS-II Initialization
“Config Completion” is set to 1.
FULL_RESET
Card Identification Mode
Idle State
(‘idle’)
From all states
in SD-TRAN
CMD0
If Device cannot operate under
supplied voltage, Device returns RES
with NACK = 1 and returns to 'idle'.
Device returns busy (see
Note (1)),
or illegal parameters are set
to ACMD41 (see Note (2)).
CMD8
It is mandatory for Host
to send CMD8 before ACMD41.
ACMD41
Device returns ready by R3.
GO_DORMANT_STATE
No state transition
in card identification mode
(see Note (3))
Ready State
(‘ready’)
CMD11 shall be skipped because Device
sets S18A = 0 in RES of ACMD41.
CMD2
Identification
State(‘ident’)
UHS-II original operation
performed by native CCMD
Device responds with
its Node ID as RCA
CMD3
Data Transfer Mode
Stand-by State
(‘stby’)
Note:
(1) Device returns busy when Device executes internal initialization process
(2) Device always returns RES with NACK = 1 when illegal parameters are set to the CMD
e. g.)
- CMD8 with improper VHS.
- ACMD41 with HCS = 0.
(3) Card status is kept after recovering from Dormant state.
4641
4642
4643
4644
4645
4646
4647
4648
Figure 7-14 : State Diagram on SD-TRAN (Card Identification Mode)
Differences from the Legacy SD are as follows.
• Like Legacy SD, Host shall issue CMD8 and then ACMD41 in order to transit from 'idle' to 'ready'.
• If Device receives CMD with illegal parameters, Device shall return RES with NACK = 1 on SDTRAN.
• RES with NACK = 1 is transmitted in illegal CMD8.
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4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
• Device never returns ready in illegal ACMD41, and the state transits to 'idle' state.
• CMD11 shall be skipped. Related to this Device shall set '0' to S18A field in RES of ACMD41.
• If Device receives CMD3, Device responds with its own Node ID as new RCA. As each Device's
Node ID is guaranteed to be distinctive even in case of multiple-Device connection, Host does not
need to reissue CMD3 for avoiding RCA duplication.
• The 'ina' state and its related transition are removed from SD-TRAN.
During card identification mode, Device operation when receiving native CMD is same as that in Active
state. Host cannot issue arbitrary DCMD during this mode. Note that card status is kept when receiving
GO_DORMANT_STATE CCMD. So Device directly transits to the appropriate card status after UHS-II
Initialization in case of recovery from Dormant state. For example, if card status was 'ready' before
transiting to Dormant state, it is still 'ready' after recovering from Dormant state. This rule is same as for
'idle' and 'ident' (and also same as 'stby' and 'tran' in Data Transfer Mode).
7.2.4.2 Data Transfer Mode
Figure 7-15 shows a state diagram for data transfer mode of SD-TRAN. Differences from the Legacy
SD are as follows.
• Common CMDs with Legacy SD shall be executed through SD-TRAN.
• The 'dis' state and its related transitions are abandoned for simplicity. And transition from 'data'
state to 'stby' state is also removed.
• Transitions by CMD7 are defined as follows.
• Transits to 'tran' if RCA in CMD7 is equal to Device's Node ID.
• Transits to 'stby' if RCA in CMD7 is not equal to Device's Node ID.
• RCA in the argument shall be ignored other than CMD7.
• If Device receives illegal command in 'stby' state, Device shall return RES with NACK = 1.
• CMD13 can be issued only in 'stby' or 'tran' state. In other words, CMD13 cannot be issued during
CTS in case of SD memory. For UHS-II Addendum Vesion 2.00, arbitrary CCMD on SD-TRAN can
be issued during CTS (refer to 7.2.4.5 for more detail).
• When Device receives CMD3 in 'ident' state or 'stby' state, Device shall always return its Device ID
as RCA.
For read transaction, state transits from 'data' to 'tran' at transmission of MSG (EBSY). For write
transaction, state transits from 'rcv' to 'prg' when Device receives all DATA packets specified by TLEN
on write DCMD, or it transmits RES (R1b) of CMD12 corresponding to write DCMD. In addition, state
transits from 'prg' to 'tran' at transmission of MSG (EBSY).
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To “PHY Initialization”
To ‘idle’ state
CMD3
CMD0
FULL_RESET
card identification
mode
from all states in
data-transfer-mode
data transfer
mode
TRANS_ABORT
See Note (1)
no state transition
in data-transfer-mode
CMD12, or
"operation
complete"
CMD7
Stand-by State
(‘stby’)
Sending-data
State (‘data’)
CMD6, 17,18, 56(r)
ACMD13, 22, 51
Transfer
State (‘tran’)
CMD7
CMD13, 16, 32, 33
ACMD23
GO_DORMANT_STATE
CMD9, 10, 3, 13
GO_DORMANT_STATE
"operation
complete"
CMD20, 38
CMD24,25,26,27,42,56(w)
See Note (1)
Receive-data
State (‘rcv’)
UHS-II original operation
performed by native CCMD
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
Programming
State (‘prg’)
CMD12 or
"transfer end"
Note:
(1) In fact, this state transition occurs at transmission of MSG(EBSY) in UHS-II.
Figure 7-15 : State Diagram on SD-TRAN (Data Transfer Mode)
In addition, there are following restrictions for Host to issue native CMDs related to data transfer mode
in SD-TRAN. If Host violates the rules about native CMDs mentioned below, Device behavior is
undefined.
• DEVICE_INIT, ENUMERATE and arbitrary native DCMD cannot be issued in data transfer mode.
• FULL_RESET and TRANS_ABORT can be issued all state in data transfer mode, but they can be
issued only in CTS during data transmission. Also refer to Section 5.2.3 and 6.2.5 for issuing
FULL_RESET,
• Native Read or native Write CCMD other than defined in Table 6-19 can be issued only in 'stby' or
'tran' state. Device shall also accept native Read CCMD in 'data' or 'rcv' if it responds properly to
the preceding TRANS_ABORT.
• GO_DORMANT_STATE are valid in both 'stby' and 'tran' state.
• TRANS_ABORT can be issued only when timeout occurs. Moreover, not TRANS_ABORT but
encapsulated CMD12 shall be used in case of terminating data transmission.
• FULL_RESET will terminate any pending or active programming operation in SD-TRAN. This may
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4703
4704
destroy the data contents on the Device. It is the Host's responsibility to prevent this.
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
7.2.4.3 Relation to State Machines in CM-TRAN and LINK
CMD or RES transmission in SD-TRAN shall be reflected all state machines defined in CM-TRAN and
LINK. In this case, CMD12 is taken as TRANS_ABORT CCMD in CM-TRAN and LINK.
For instance, when CMD18 is issued, TPSM shall transit from TP_IDLE to TP_WAIT. Likewise in case
of read transaction, if Device receives CMD12 during the time period from transmitting FCREQ to
receiving FCRDY, TPSM shall transit from TP_C_WAIT to TP_IDLE and DLSM shall transit from
Active.Trans.WaitRDY to Active.Control at the transmission of RES of CMD12.
Also in case of read transaction, if Device receives CMD0 during the time period from transmitting
FCREQ to receiving FCRDY, TPSM shall transit from TP_C_WAIT to TP_IDLE and DLSM shall transit
from Active.Trans.WaitRDY to Active.Control at the transmission of RES of CMD0.
4716
4717
4718
4719
7.2.4.4 Card State Transition by UHS-II Native Command
Table 7-2 shows card state transition by UHS-II native commands. Mark "*" indicates that Device
behavior is undefined for the command.
UHS-II Native CMD
FULL_RESET
idle
current state (SD-TRAN)
ready ident stby tran
data
rcv
prg
idle
idle
idle
idle
idle
idle
idle
idle
(See Note (2)) (See Note (2))
GO_DORMANT_STATE
DEVICE_INIT
(See Note (1))
ENUMERATE
idle
idle
ready
*
ident
*
idle
*
*
idle
ready
ident
stby tran
*
*
*
*
*
*
*
*
*
*
*
*
*
data
rcv
prg
(See Note (1))
TRANS_ABORT
stby tran
(See Note (2)) (See Note (2))
Other Native Write CCMD
Native Read CCMD
idle
idle
ready
ready
ident
ident
stby tran
stby tran
*
data
*
rcv
*
*
(See Note (3)) (See Note (3))
Native DCMD
*
*
*
*
*
*
*
*
4720
4721
4722
4723
4724
4725
4726
Note:
(1) These commands can be issued in any card states in SD-TRAN if Host sets "Config Completion" flag to 0 before transiting
to Dormant. However, it is strongly recommended that Host should not issue this command after recovering from Dormant.
(2) Host can issue only during CTS period for this state
(3) This transition is available if Device responds properly to the preceding TRANS_ABORT.
4727
4728
4729
4730
7.2.4.5 Capability Indication for Receiving Arbitrary CCMD during CTS
Table 7.2.4- 1 shows how to indicate register values related to the capability of receiving arbitrary
CCMD during CTS.
Table 7-2 : Card State Transition by UHS-II Native Command
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Card Type
Capability of
Compliant
Receiving Arbitrary
to
CCMD during CTS
UHS-II SD
Memory Card
~Ver.1.02
Ver.2.00~
Ver.2.00~
~Ver.1.02
~Ver.1.02
Ver.2.00~
Ver.2.00~
UHS-II
SDIO Card
4731
4732
No
No
Yes
No
Yes
No
Yes
LINK/TRAN
Major
Revision
00b
01b
01b
00b
00b
01b
01b
Register
CCMD during
Data Transfer
SDC
(SDIO spec.)
0b (reserved)
0b
1b
0b (reserved)
0b (reserved)
0b
1b
N/A
N/A
N/A
0b
1b
0b
1b
Table 7.2.4- 1 : Capability Indication for Receiving Arbitrary CCMD during CTS
4733
4734
4735
4736
4737
7.2.5 Basic Transaction Rules
4738
4739
4740
4741
7.2.5.1 CCMD
Figure 7-16 illustrates a sequence for CCMD in SD-TRAN. In this section, CMD9 (SEND_CSD) is used
as an example. Refer to Table 7-1 for other adaptable commands in SD-TRAN.
Needless to say, transaction rules in CM-TRAN shall be kept also in SD-TRAN. In this section, some
examples of basic transaction rules are shown in SD-TRAN. Note that NP in Header field of TLP is 0 on
SD-TRAN.
Node ID=1
Host
Device
CCMD
Node ID=0
D0
D0
CMD9
RES
NACK=CMD is accepted
D1
RES
(R2)
D1
Payload=
Response
data
Control Trans.
START
Header
4742
4743
4744
4745
4746
4747
4748
4749
4750
Time →
Control Trans.
END
Argument
Payload
Encapsulated Legacy SD
CMD/RES/DATA
Figure 7-16 : Sequence of CCMD on SD-TRAN (CMD9)
The detailed field values in Figure 7-16 are as follows;
[CCMD]
• Header (CCMD):
• NP = 0 (not native protocol)
• Packet Type = CCMD
• DID = 1 (Node ID of destination Device)
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4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (CCMD):
• APP = 0 (regular command)
• CMD_INDEX = 9 (command index in Legacy SD)
• Payload (CCMD):
• SD_ARG = Argument of CMD9.
[RES]
• Header (RES):
• NP = 0 (not native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding CCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID of the corresponding CCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• Other field is copied from CCMD
• Payload (RES):
• CONTENT = Content of CSD Register (the length of Payload is 16 in this case)
7.2.5.2 Read DCMD (Fixed Transfer Length)
In the examples shown below, N_FCU is supposed to set to 2.
Figure 7-17 illustrates a sequence for Read DCMD (fixed transfer length) in SD-TRAN. In this case only
CMD18 (READ_MULTIPLE_BLOCK) is available in SD-TRAN.
Node ID=0
TMODE=0100
Node ID=1
SD_ARG=data address
TLEN=4
D0
Device
DCMD
Host
D0
CMD18
DATA1
DATA2
DATA
DATA0
DATA
RES
(R1)
DATA
D1
DATA
RES
NACK=CMD is accepted
TMODE
- same as CMD
Payload=
read data
Data Trans.
START
D1
DATA3
Time →
FCU period
FCU period
Data Trans.
END
Interval
Header
4777
4778
4779
4780
4781
Argument
Extended Argument
Encapsulated Legacy SD
CMD/RES/DATA
Payload
Settings
• N_FCU = 2 blocks (number of packets within a FCU)
Figure 7-17 : Sequence of Read DCMD on SD-TRAN (CMD18, LM = 1)
The detailed field values in Figure 7-17 are as follows;
[DCMD]
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4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
• Header (DCMD):
• NP = 0 (not native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (DCMD):
• TMODE = 0100b (LM = 1, DM = 0)
• APP = 0 (regular command)
• CMD_INDEX = 18 (command index in Legacy SD)
• Extended Argument (DCMD):
• SD_ARG = Argument of CMD18.
• TLEN = 4 blocks (total length of data transferred during a data transaction)
[RES]
• Header (RES):
• NP = 0 (not native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• Other field is copied from DCMD
• Payload (RES):
• CONTENT = Response data of R1 (the length of Payload is 4 in this case)
[DATA]
• Header (DATA):
• NP = 0 (not native protocol)
• Packet Type = DATA
• DID = 0 (Node ID of Host)
• SID = 1 (Node ID of source Device)
• TID = the same value as TID of the corresponding DCMD
• Payload (DATA): Requested read data by Host
In this case, Host is not required to issue CMD12 to terminate the data transmission.
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4821
4822
4823
4824
7.2.5.3 Read DCMD (Infinite Transfer Length)
Figure 7-18 illustrates a sequence for Read DCMD (infinite transfer length) in SD-TRAN. In this section,
CMD18 is used as an example. Refer to Table 7-1 for other adaptable commands in SD-TRAN.
Node ID=0
Node ID=1
SD_ARG=data address
TMODE=0000
CCMD
D0
Device
DCMD
Host
CMD18
CMD
12
D0
DATA2
RES
DATA1
DATA
DATA0
DATA
RES
(R1)
DATA
D1
DATA
RES
NACK=CMD is accepted
TMODE
- same as CMD
DATA3
Payload=
read data
Data Trans.
START
Header
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
D1
Time →
FCU period
Argument
RES
(R1b)
FCU period
Interval
Interval
Extended Argument
Payload
Encapsulated Legacy SD
CMD/RES/DATA
Data Trans. is
terminated by
CMD12
Settings
• N_FCU = 2 blocks (number of packets within a FCU)
Figure 7-18 : Sequence of Read DCMD on SD-TRAN (CMD18, LM = 0)
The detailed field values in Figure 7-18 are as follows;
[DCMD]
• Header (DCMD):
• NP = 0 (not native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (DCMD):
• TMODE = 0000b (LM = 0, DM = 0)
• APP = 0 (regular command)
• CMD_INDEX = 18 (command index in Legacy SD)
• Extended Argument (DCMD):
• SD_ARG = Argument of CMD18.
[RES]
• Header (RES):
• NP = 0 (not native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
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4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
• Other field is copied from DCMD
• Payload (RES):
• CONTENT = Response data of R1 (the length of Payload is 4 in this case)
[DATA]
• Header (DATA):
• NP = 0 (not native protocol)
• Packet Type = DATA
• DID = 0 (Node ID of Host)
• SID = 1 (Node ID of source Device)
• TID = The same value as TID of the corresponding DCMD
• Payload (DATA): Requested read data by Host
CMD12 can be issued only during interval period in order to terminate data transaction.
7.2.5.4 Write DCMD (Fixed Transfer Length)
Figure 7-19 illustrates a sequence for Write DCMD (fixed transfer length) in SD-TRAN. In this case only
CMD25 (WRITE_MULTIPLE_BLOCK) is available in SD-TRAN.
Node ID=0
TMODE=0100
SD_ARG=data address
TLEN=4
Node ID=1
Payload=
write data
D1
DATA1
DATA2
DATA
DATA
DATA0
DATA
DATA
CMD25
RES
D0
Device
DCMD
Host
D0
DATA3
D1
RES
(R1)
NACK=CMD is accepted
TMODE
- same as CMD
Data Trans.
START
Time →
FCU period
FCU period
Data Trans.
END
Interval
Header
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
Argument
Extended Argument
Encapsulated Legacy SD
CMD/RES/DATA
Payload
Settings
• N_FCU = 2 blocks (number of packets within a FCU)
Figure 7-19 : Sequence of Write DCMD on SD-TRAN (CMD25, LM = 1)
The detailed field values in Figure 7-19 are as follows;
[DCMD]
• Header (DCMD):
• NP = 0 (not native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (DCMD):
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4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
• TMODE = 0100b (LM = 1, DM = 0)
• APP = 0 (regular command)
• CMD_INDEX = 25 (command index in Legacy SD)
• Extended Argument (DCMD):
• SD_ARG = Argument of CMD25.
• TLEN = 4 blocks (total length of data transferred during a data transaction)
[RES]
• Header (RES):
• NP = 0 (not native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = The same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• Other field is copied from DCMD
• Payload (RES):
• CONTENT = Response data of R1 (the length of Payload is 4 in this case)
[DATA]
• Header (DATA):
• NP = 0 (not native protocol)
• Packet Type = DATA
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = The same value as TID of the corresponding DCMD
• Payload (DATA): Transferred write data to Device
In this case, Host is not required to issue CMD12 to terminate the data transmission.
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4915
4916
4917
4918
7.2.5.5 Write DCMD (Infinite Transfer Length)
Figure 7-20 illustrates a sequence for Write DCMD (infinite transfer length) in SD-TRAN. In this section,
CMD25 is used as an example. Refer to Table 7-1 for other adaptable commands in SD-TRAN.
Node ID=0
Node ID=1
Payload=
write data
SD_ARG=data address
TMODE=0000
DATA2
CCMD
DATA1
DATA
DATA0
DATA
CMD25
DATA
DATA
D0
Device
DCMD
Host
DATA3
CMD
12
D0
D1
RES
RES
NACK=CMD is accepted
TMODE
- same as CMD
RES
(R1)
RES
(R1b)
D1
Time →
Data Trans.
START
Header
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
FCU period
Argument
FCU period
Interval
Interval
Extended Argument
Payload
Encapsulated Legacy SD
CMD/RES/DATA
Data Trans. is
terminated by
CMD12
Settings
• N_FCU = 2 blocks (number of packets within a FCU)
Figure 7-20 : Sequence of Write DCMD on SD-TRAN (CMD25, LM = 0)
The detailed field values in Figure 7-20 are as follows;
[DCMD]
• Header (DCMD):
• NP = 0 (not native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (DCMD):
• TMODE = 0000b (LM = 0, DM = 0)
• APP = 0 (regular command)
• CMD_INDEX = 25 (command index in Legacy SD)
• Extended Argument (DCMD):
• SD_ARG = Argument of CMD25.
[RES]
• Header (RES):
• NP = 0 (not native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = The same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
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4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
• Other field is copied from DCMD
• Payload (RES):
• CONTENT = Response data of R1 (the length of Payload is 4 in this case)
[DATA]
• Header (DATA):
• NP = 0 (not native protocol)
• Packet Type = DATA
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = The same value as TID of the corresponding DCMD
• Payload (DATA): Transferred write data to Device
CMD12 can be issued only during interval period in order to terminate this transaction.
7.2.5.6 Other DCMD
Figure 7-21 illustrates a sequence for DCMD whose data size is specified by CMD_INDEX. In this
section, ACMD51 is used as an example.
Node ID=0
Node ID=1
TMODE=0000
APP=1
SD_ARG=stuff bits
D0
Device
DCMD
Host
D0
ACMD
51
D1
DATA
RES
NACK=CMD is accepted
TMODE
- same as CMD
RES
(R1)
DATA
(SCR)
D1
Payload=
SCR(8bytes)
Time →
Data Trans.
START
Header
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
FCU period
Data Trans.
END
Argument
Extended Argument
Payload
Encapsulated Legacy SD
CMD/RES/DATA
Figure 7-21 : Sequence of ACMD51 on SD-TRAN
The detailed field values in Figure 7-21 are as follows;
[DCMD]
• Header (DCMD):
• NP = 0 (not native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (DCMD):
• TMODE = 0000b (LM = 0, DM = 0)
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4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
•
•
APP = 1 (application command)
CMD_INDEX = 51 (command index in Legacy SD. Note that ACMD51 is realized by
CMD_INDEX = 51 with APP = 1).
• Extended Argument (DCMD):
• SD_ARG = Argument of ACMD51 (stuff bits).
[RES]
• Header (RES):
• NP = 0 (not native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = The same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• Other field is copied from DCMD
• Payload (RES):
• CONTENT = Response data of R1 (the length of Payload is 4 in this case)
[DATA]
• Header (DATA):
• NP = 0 (not native protocol)
• Packet Type = DATA
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = The same value as TID of the corresponding DCMD
• Payload (DATA): Transferred SCR data to Host. Note that the length of Payload field of DATA is 8
bytes.
5007
5008
5009
7.2.6 SD-TRAN Specific Transaction Rules
5010
5011
5012
7.2.6.1 Definition of Application Specific MSG
Table 7-3 illustrates detailed definitions of application specific MSG for SD-TRAN.
In this section, some examples of SD-TRAN specific transaction rules are shown.
Bits
100b
5013
5014
5015
5016
5017
5018
CTG
Name
AMSG
Bits
0000b
IDX
Name
EBSY
others
Reserved
CODE
Refer to
7-4
Reserved
Description
Table
End of Busy Period for memory access
Reserved
Table 7-3 : Detailed Definition of SD-TRAN Specific MSG
Data transmission on SD-TRAN is based on that on CM-TRAN, so other MSGs such as MSG (FCREQ)
are also used. Refer to Section 5.2.4 for details of other MSG definition.
Table 7-4 describes the CODE definition of EBSY.
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5024
5025
5026
5027
5028
Identifier
MEMORY_ERROR
6:0
Reserved
Value
'0' = no error
'1' = error
Reserved
Description
Memory error occurs during BUSY
period.
Reserved
Table 7-4 : Code Definition of EBSY
• MEMORY_ERROR: Indicates that memory error occurs during BUSY period.
7.2.6.2 CMD0
Figure 7-22 illustrates a sequence for CMD0 (GO_IDLE_STATE). CMD0 in Legacy SD protocol
originally has no response. In UHS-II protocol, however, Device shall transmit RES without payload to
Host before CMD0 operation. This rule is also applied in case of CMD7 (SELECT/DESELECT_CARD)
for deselect.
Node ID=0
Node ID=1
Host
Device
D0
CCMD
5019
5020
5021
5022
Bits
7
D0
CMD0
NACK=CMD is accepted
RES
RES without
Payload
D1
D1
RES is transmitted before Card starts
CMD0 operation
Time →
Control Trans.
START
Header
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
Control Trans.
END
Argument
Payload
Encapsulated Legacy SD
CMD/RES/DATA
Figure 7-22 : Sequence of CMD0 on SD-TRAN
The detailed field values in Figure 7-22 are as follows;
[CCMD]
• Header (CCMD):
• NP = 0 (not native protocol)
• Packet Type = CCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (CCMD):
• APP = 0 (regular command)
• CMD_INDEX = 0 (command index in Legacy SD)
• Payload (CCMD):
• SD_ARG = Argument of CMD0.
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5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
[RES]
• Header (RES):
• NP = 0 (not native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding CCMD)
• SID = 1 (Node ID of Device)
• TID = The same value as TID of the corresponding CCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• Other field is copied from CCMD
• Payload (RES):
• No payloads for RES of CMD0.
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
7.2.6.3 Representing Busy Period and 'prg' State
In SD-TRAN, Busy Period is defined as follows.
• Busy Period starts at the transmission of
• RES (R1b)
• RES (R1) of DCMD, or the last DATA in the DATA Burst in case of read transaction
• MSG (STAT) in case of write transaction
• Busy Period ends at the transmission of
• MSG (EBSY)
• MSG (FCREQ) in case of read transaction
• MSG (FCRDY) in case of write transaction
In addition, 'prg' state (programming state) is regulated as follows.
• From RES (R1b) to MSG (EBSY) in case of write or erase transaction.
• From MSG (STAT) for completing data reception by Device to MSG (EBSY)
Figure 7-23 illustrates a sequence for representing Busy Period and 'prg' state after R1b in SD-TRAN.
In this section, CMD38 (ERASE) is used as an example.
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Node ID=1
Host
Device
D0
D1
MSG
(EBSY)
CMD38
RES
D0
CCMD
Node ID=0
RES
(R1b)
D1
Time →
Control Trans.
END
Control Trans.
START
Header
Argument
Encapsulated Legacy SD
CMD/RES/DATA
Payload
Transaction Layer Packet
Link Layer Packet (Link Message Packet)
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
Busy Period
prg state
Figure 7-23 : Sequence of CMD38 on SD-TRAN
The detailed field values in Figure 7-23 are as follows;
[CCMD]
• Header (CCMD):
• NP = 0 (not native protocol)
• Packet Type = CCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (CCMD):
• APP = 0 (regular command)
• CMD_INDEX = 38 (command index in Legacy SD)
• Payload (CCMD):
• SD_ARG = Argument of CMD38.
[RES]
• Header (RES):
• NP = 0 (not native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding CCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID of the corresponding CCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• Other field is copied from CCMD
• Payload (RES):
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•
CONTENT = Response data of R1b (the length of Payload is 4 in this case)
As mentioned above, Busy Period in SD-TRAN starts at transmitting RES (R1b), and ends at MSG
(EBSY). This example can be adapted to CMD20 in SD-TRAN. Moreover 'prg' state starts at
transmitting RES (R1b), and ends at MSG (EBSY).
Figure 7-24 illustrates a sequence for representing Busy Period by Write DCMD with fixed data length.
Figure 7-24 includes Link Layer Packet not only for representing Busy Period, but also for realizing flow
control.
TMODE=0100
TLEN=4
DATA
3
MSG
(STAT)
D0
MSG
(EBSY)
DATA
DATA
Device
DATA
2
MSG
(FCRDY)
RES
(R1)
DATA
1
MSG
(STAT)
D1
DATA
0
MSG
(FCREQ)
MSG
(FCREQ)
CMD
25
RES
D0
DCMD
Host
DATA
Node ID=1
DATA
Node ID=0
MSG
(FCRDY)
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
D1
Time →
Data Trans.
START
Interval
period
FCU period
Interval
period
FCU period
Data Trans.
END
Header
Argument
Payload
Extended Argument
Encapsulated Legacy SD
CMD/RES/DATA
Settings
• N_FCU = 2 blocks (number of packets within a FCU)
Transaction Layer Packet
Busy Period
prg state
Link Layer Packet (Link Message Packet)
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
Figure 7-24 : Sequence of Write DCMD on SD-TRAN with Busy Period (Fixed Transfer Length)
The detailed field values in Figure 7-24 are as follows;
[DCMD]
• Header (DCMD):
• NP = 0 (not native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (DCMD):
• TMODE = 0100b (LM = 1, DM = 0)
• APP = 0 (regular command)
• CMD_INDEX = 25 (command index in Legacy SD)
• Extended Argument (DCMD):
• SD_ARG = Argument of CMD25.
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5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
•
TLEN = 4 (total length of data transferred during a data transaction)
[RES]
• Header (RES):
• NP = 0 (not native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• Other field is copied from DCMD
• Payload (RES):
• CONTENT = Response data of R1 (the length of Payload is 4 in this case)
[DATA]
• Header (DATA):
• NP = 0 (not native protocol)
• Packet Type = DATA
• DID = 1 (Node ID of source Device)
• SID = 0 (Node ID of Host)
• TID = The same value as TID of the corresponding DCMD
• Payload (DATA): transferred write data to Device
After Device receives DATA specified in TLEN of CMD25, it transmits MSG (STAT), and notifies Busy
Period start to Host. Device transmits MSG (EBSY) at the end of Busy Period.
Figure 7-25 illustrates a sequence for representing Busy Period by Write DCMD in case of infinite
transfer length.
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Node ID=0
Node ID=1
D0
RES
MSG
(STAT)
CMD
12
RES
(R1b)
MSG
(EBSY)
CCMD
DATA
DATA
3
MSG
(FCRDY)
DATA
2
DATA
Device
MSG
(FCREQ)
DATA
1
MSG
(STAT)
RES
(R1)
DATA
0
MSG
(FCRDY)
D1
DATA
MSG
(FCREQ)
CMD
25
RES
D0
DCMD
Host
DATA
TMODE=0000
D1
Time →
Data Trans.
START
Header
Interval
period
Argument
FCU period
Interval
period
FCU period
Payload
Extended Argument
Encapsulated Legacy SD
CMD/RES/DATA
Interval period
Data Trans.
END
Settings
• N_FCU = 2 blocks (number of packets within a FCU)
Transaction Layer Packet
Busy Period
prg state
Link Layer Packet (Link Message Packet)
5163
5164
5165
5166
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187
5188
5189
5190
Figure 7-25 : Sequence of Write DCMD on SD-TRAN with Busy Period (Infinite Transfer Length)
The detailed field values in Figure 7-25 are as follows;
[DCMD]
• Header (DCMD):
• NP = 0 (not native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (DCMD):
• TMODE = 0000b (LM = 0, DM = 0)
• APP = 0 (regular command)
• CMD_INDEX = 25 (command index in Legacy SD)
• Extended Argument (DCMD):
• SD_ARG = Argument of CMD25.
[RES]
• Header (RES):
• NP = 0 (not native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = The same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• Other field is copied from DCMD
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• Payload (RES):
• CONTENT = Response data of R1 (the length of Payload is 4 in this case)
[DATA]
• Header (DATA):
• NP = 0 (not native protocol)
• Packet Type = DATA
• DID = 1 (Node ID of source Device)
• SID = 0 (Node ID of Host)
• TID = The same value as TID of the corresponding DCMD
• Payload (DATA): transferred write data to Device
Host can issue CMD12 after receiving MSG (STAT) from Device (in other word, during Command Time
Slot described in Section 5.5.2). Device sends RES (R1b), and MSG (EBSY) at the end of this
transaction.
Figure 7-26 illustrates a sequence for representing Busy Period by read DCMD with fixed data length.
TMODE=0100
TLEN=4
Node ID=1
MSG
(STAT)
DATA
2
D0
MSG
(EBSY)
DATA
DATA
1
DATA
DATA
0
Device
MSG
(FCRDY)
MSG
(STAT)
MSG
(FCRDY)
RES
(R1)
MSG
(FCREQ)
D1
MSG
(FCREQ)
CMD
18
RES
D0
DCMD
Host
DATA
Node ID=0
DATA
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
DATA
3
D1
Time →
Data Trans.
START
Interval
period
FCU period
Interval
period
FCU period
Data Trans.
END
Header
Argument
Payload
Extended Argument
Encapsulated Legacy SD
CMD/RES/DATA
Settings
• N_FCU = 2 blocks (number of packets within a FCU)
Transaction Layer Packet
5209
5210
5211
5212
5213
5214
5215
5216
5217
5218
5219
Busy Period
Link Layer Packet (Link Message Packet)
Figure 7-26 : Sequence of Read DCMD on SD-TRAN with Busy Period (Fixed Transfer Length)
The detailed field values in Figure 7-26 are as follows;
[DCMD]
• Header (DCMD):
• NP = 0 (not native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
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5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256
• Argument (DCMD):
• TMODE = 0100b (LM = 1, DM = 0)
• APP = 0 (regular command)
• CMD_INDEX = 18 (command index in Legacy SD)
• Extended Argument (DCMD):
• SD_ARG = Argument of CMD18.
• TLEN = 4 (total length of data transferred during a data transaction)
[RES]
• Header (RES):
• NP = 0 (not native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• Other field is copied from DCMD
• Payload (RES):
• CONTENT = Response data of R1 (the length of Payload is 4 in this case)
[DATA]
• Header (DATA):
• NP = 0 (not native protocol)
• Packet Type = DATA
• DID = 0 (Node ID of Host)
• SID = 1 (Node ID of destination Device)
• TID = The same value as TID of the corresponding DCMD
• Payload (DATA): transferred write data to Device
In read transaction, after Host receives DATA specified in TLEN of CMD18, it transmits MSG (STAT).
Then, Device shall transmit MSG (EBSY) when it is able to accept the next command. In other words,
the data transaction terminates when Host receives MSG (EBSY).
This rule is applied for all read SD commands including security commands..
Figure 7-27 illustrates a sequence for representing Busy Period by read DCMD with infinite data length.
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Node ID=0
Node ID=1
TMODE=0000
CCMD
CMD
12
DATA
3
RES
DATA
2
D0
RES
(R1b)
MSG
(EBSY)
DATA
MSG
(STAT)
MSG
(FCRDY)
Device
DATA
DATA
1
MSG
(FCREQ)
DATA
0
DATA
MSG
(STAT)
MSG
(FCRDY)
RES
(R1)
DATA
D1
MSG
(FCREQ)
CMD
18
RES
D0
DCMD
Host
D1
Time →
Data Trans.
START
Header
Interval
period
Argument
FCU period
Interval
period
FCU period
Payload
Extended Argument
Encapsulated Legacy SD
CMD/RES/DATA
Interval period
Data Trans.
END
Settings
• N_FCU = 2 blocks (number of packets within a FCU)
Transaction Layer Packet
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
Busy Period
Link Layer Packet (Link Message Packet)
Figure 7-27 : Sequence of Read DCMD on SD-TRAN with Busy Period (Infinite Transfer Length)
The detailed field values in Figure 7-27 are as follows;
[DCMD]
• Header (DCMD):
• NP = 0 (not native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (DCMD):
• TMODE = 0000b (LM = 0, DM = 0)
• APP = 0 (regular command)
• CMD_INDEX = 18 (command index in Legacy SD)
• Extended Argument (DCMD):
• SD_ARG = Argument of CMD18.
[RES]
• Header (RES):
• NP = 0 (not native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• Other field is copied from DCMD
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5285
5286
5287
5288
5289
5290
5291
5292
5293
5294
5295
5296
5297
5298
5299
• Payload (RES):
• CONTENT = Response data of R1 (the length of Payload is 4 in this case)
[DATA]
• Header (DATA):
• NP = 0 (not native protocol)
• Packet Type = DATA
• DID = 0 (Node ID of Host)
• SID = 1 (Node ID of destination Device)
• TID = The same value as TID of the corresponding DCMD
• Payload (DATA): transferred write data to Device
Different from Figure 7-26, Host shall issue CMD12 when terminating the transaction. Moreover, Device
shall transmit EBSY after RES (R1b).
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312
5313
5314
5315
7.2.6.4 Other Transaction Rules
The following items are other transaction rules on SD-TRAN.
5316
5317
5318
5319
5320
5321
5322
5323
5324
7.2.7 Packet Handling
5325
7.2.8 Error Handling
5326
5327
5328
5329
5330
5331
5332
5333
7.2.8.1 Concept
Same as Legacy SD specifications, Host can know the error of the corresponding CMD from Card
Status Register (CSR). Error registers in CSR are automatically cleared when Host reads them.
In UHS-II, the following two points are different from Legacy SD.
• CMD0, CMD12, FULL_RESET CCMD and TRANS_ABORT CCMD can be issued during the
Command Time Slot (CTS) defined in Section 6.2.13.4. Note that transaction rules related to CTS
is same as in case of CM-TRAN. Also refer to Section 7.2.4.5.
• CMD0 may be issued in any state. In case of during 'prg' or 'data' state, MSG (EBSY) is not
transmitted after RES of CMD0.
• Host shall not use native DCMD but encapsulated command such as CMD18 for Devices with
application type = SD Memory. If Host issues native DCMD to Devices with application type = SD
Memory, then Device behavior is not defined.
• When Host reads data from Device, Host sends MSG (STAT) at the end of each FCU period to
keep compatibility to data read transaction in CM-TRAN (refer to Figure 6-50).
• During the transaction of CMD18 or CMD25, Device shall terminate the transaction when it
receives CMD12 with arbitrary TID.
When Device receives a UHS-II packet whose DID corresponds with its Node ID, acceptability is
defined by following rules.
• CMD (CCMD or DCMD): it follows the Card State Transition Table described in SD Specifications
Part 1 Physical Layer Specification Version 4.00 or later.
• RES: Device shall not accept RES packet.
• DAT: Device accepts DAT only in 'rcv' state in Figure 7-15. It shall not accept in other state.
• Device shall respond RES with NACK = 1 if it receives illegal CMD.
• CRC error is notified by MSG (STAT) only during interval period (Refer to Section 6.2.15 for more
details).
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5335
5336
5337
5338
7.2.8.2 Detecting Illegal CMD
Figure 7-28 illustrates a transaction rule when undefined CMD (ACMD55) is issued, as an example of
detecting illegal command
Device sets ILLEGAL_COMMAND
bit in CSR to “1”.
APP=1
CMD_INDEX=55
Node ID=0
ACMD
55
CMD
13
D1
RES is transmitted even
when CMD is illegal
Control Trans.
START
Header
5339
5340
5341
5342
5343
5344
5345
5346
5347
5348
5349
Control Trans.
END
Argument
D0
RES
RES
(NACK=1)
D0
CCMD
Device
CCMD
Host
Node ID=1
RES
(R1)
Card Status
=00400800h
Control Trans.
START
D1
Time →
Control Trans.
END
Payload
Encapsulated Legacy SD
CMD/RES/DATA
Figure 7-28 : Detecting Illegal CMD (Example 1)
Originally, Device does not respond for illegal command in Legacy SD protocol, but in UHS-II protocol,
Device shall transmit RES with NACK = 1 to Host in this case. The RES format is described in Section
7.2.1.4.
Same as Legacy SD protocol, Host can get the reason of the error from Card Status (00400800h in
above case) by issuing CMD13 (SEND_STATUS).
Figure 7-29 illustrates another example that Host issues CMD12 in 'tran' state.
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Device sets ILLEGAL_COMMAND
bit in CSR to “1”.
Node ID=0
Node ID=1
CMD
12
CMD
13
D0
D1
RES
RES
(NACK=1)
D0
CCMD
Device
CCMD
Host
RES
(R1)
RES is transmitted even
when CMD is illegal
Control Trans.
START
Control Trans.
END
Header
Card Status
=00400800h
Control Trans.
START
Time →
Control Trans.
END
Payload
Argument
Encapsulated Legacy SD
CMD/RES/DATA
5350
5351
5352
Figure 7-29 : Detecting Illegal CMD (Example 2)
7.2.8.3 Reaching Read Address to the End of User Data Area
Figure 7-30 illustrates a sequence for CMD18 if the read address comes at the last block of User Data
Area.
Node ID=0
Node ID=1
TMODE=0000
CCMD
Device
MSG
(STAT)
CMD
18
MSG
(FCRDY)
MSG
(FCRDY)
D0
DCMD
Host
MSG
(STAT)
5353
5354
5355
5356
D1
CMD
12
D0
RES
(R1b)
MSG
(EBSY)
DATA
3
RES
DATA
2
DATA
DATA
DATA
1
MSG
(FCREQ)
DATA
0
DATA
DATA
RES
(R1)
MSG
(FCREQ)
D1
RES
RES
Data in DATA3 is read
from the very last block
of User Data Area
D1
Time →
Data Trans.
START
Interval period
FCU period
Interval period
FCU period
Interval period
Data Trans.
END
Header
Argument
Payload
Extended Argument
Transaction Layer Packet
Settings
• N_FCU = 2 blocks (number of packets within a FCU)
Link Layer Packet (Link Message Packet)
5357
5358
5359
Busy Period
Figure 7-30 : Sequence of Read DCMD (at the End of User Data Area)
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5361
5362
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
Device shall not send MSG (FCREQ) with UNRECOVERABLE_ERROR = 0 if it completes sending the
last block (DATA3, in the above example) after receiving MSG (STAT). Host detects the illegal situation
from timeout defined in Section 7.3. Host is required to issue CMD12 in order to terminate this
transaction.
In addition, Device shall not transmit the whole DATA Burst if the reading address reaches the end of
User Data Area on the way of constructing the DATA Burst. In this case, Device can transmit MSG
(FCREQ) with UNRECOVERABLE_ERROR or give up transmitting MSG (FCREQ). Refer to Section
7.3.2 for the detailed sequence of timeout.
This error can be also occurred in the following cases.
5375
5376
5377
5378
7.2.8.4 Reaching Write Address to the End of User Data Area
Figure 7-31 and Figure 7-32 illustrate sequences for CMD25 if the write address comes at the last block
of User Data Area.
• Other read DCMD
• Reading other memory area such as Protected Area.
• CMD18 with LM = 1 if TLEN is so large as to excess the end of memory area.
• Other errors occur during read operation such as ECC failure.
Node ID=1
MSG
(STAT)
CMD
12
D0
RES
(R1b)
MSG
(EBSY)
CCMD
DATA
DATA
3
MSG
(FCRDY)
DATA
2
DATA
Device
MSG
(FCREQ)
DATA
1
MSG
(STAT)
RES
(R1)
DATA
0
MSG
(FCRDY)
D1
DATA
MSG
(FCREQ)
CMD
25
RES
D0
DCMD
Host
DATA
TMODE=0000
RES
Node ID=0
Data in DATA3 will be
written in the very last
block of User Data Area
D1
Time →
Data Trans.
START
Header
Interval
period
Argument
FCU period
Interval
period
FCU period
Payload
Extended Argument
Encapsulated Legacy SD
CMD/RES/DATA
Interval
period
Data Trans.
END
Settings
• N_FCU = 2 blocks (number of packets within a FCU)
Transaction Layer Packet
Busy Period
prg state
Link Layer Packet (Link Message Packet)
5379
5380
5381
5382
5383
5384
5385
5386
Figure 7-31 : Sequence of Write DCMD (at the End of User Data Area 1)
Like Figure 7-31, Host shall issue CMD12 just after receiving MSG (STAT) associated with the last block
of Use Data Area. In this case, OUT_OF_RANGE flag is not set to 1 in RES of CMD12.
Figure 7-32 illustrates the case that Host accidentally sends DATA Burst or MSG (FCREQ) after the
writing address reaches the end of User Data Area.
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DATA
2
Device
MSG
(FCREQ)
DATA
1
Node ID=1
DATA
DATA
0
DATA
CMD
25
DATA
MSG
(FCREQ)
D0
DCMD
Host
DATA
TMODE=0000
MSG
(FCREQ)
Node ID=0
Data in DATA0 corresponds
to the very last block of
User Data Area
DATA
3
D0
MSG
(STAT)
MSG
(FCRDY)
RES
(R1)
MSG
(STAT)
D1
MSG
(FCRDY)
RES
Missing FCRDY
Host can detect
error by busy
timeout
D1
Time →
Data Trans.
START
Header
Interval
period
Argument
FCU period
Interval
period
FCU period
Payload
Extended Argument
Encapsulated Legacy SD
CMD/RES/DATA
Interval
period
Settings
• N_FCU = 2 blocks (number of packets within a FCU)
Transaction Layer Packet
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
Busy Period
Link Layer Packet (Link Message Packet)
Figure 7-32 : Sequence of Write DCMD (at the End of User Data Area 2)
In this case, Data in DATA0 is written properly, but Data in other DATA packets are not written. Device
notifies the illegal situation to Host by MSG (STAT or FCRDY) with UNRECOVERABLE_ERROR or
MSG (EBSY) with MEMORY_ERROR, or gives up transmitting these MSGs in order to lead timeout
when it becomes possible. Refer to Section 7.3.2 for the detailed sequence of timeout.
This error can be also occurred in the following cases.
• Other write DCMD
• Writing other memory area such as Protected Area.
• CMD25 with LM = 1 if TLEN is so large as to excess the end of memory area.
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7.3 Timing Rules
5403
5404
5405
7.3.1 Overview
Based on the timing rules described in Section 6.3.1, timing rules for SD-TRAN are specified as follows.
Group
Abbreviation
Flow
Tres_fcreq(r)
Control in
SD-TRAN
Tres_fcreq(w)
Tstat_fcreq(r)
Tstat_fcreq(w)
Tfcreq_fcrdy(r)
Tfcreq_fcrdy(w)
Busy MSG Tr_stat_ebsy
operation in
SD-TRAN
Tw_stat_ebsy
Tr_res_ebsy
Tw_res_ebsy
Te_res_ebsy
5406
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421
Description
Time from RES EOP reception to FCREQ SOP
issuing in read transaction. This is related to read
busy timeout or access time.
Time from RES EOP reception to FCREQ SOP
issuing in write transaction
Time from STAT EOP reception to FCREQ SOP
issuing in read transaction. This is related to read
busy timeout or access time.
Time from STAT EOP reception to FCREQ SOP
issuing in write transaction.
Time from FCREQ EOP reception to FCRDY
SOP issuing in read transaction.
Time from FCREQ EOP reception to FCRDY
SOP issuing in write transaction. This is related
to write busy timeout.
Time from MSG (STAT) EOP transmission to
MSG (EBSY) SOP issuing in case of read
operation.
Time from MSG (STAT) EOP reception to MSG
(EBSY) SOP issuing in case of write operation.
This is related to write busy timeout or busy
length
Time from RES (R1b) EOP reception to MSG
(EBSY) SOP issuing in case of read operation.
Time from RES (R1b) EOP reception to MSG
(EBSY) SOP issuing in case of write operation.
This is related to write busy timeout or busy
length.
From RES (R1b) EOP reception to MSG (EBSY)
SOP issuing in case of erase operation. This is
related to erase busy timeout.
Max Value
See Note (1)
N/A
See Note (1)
N/A
N/A
1 [sec]
(See Note (2))
100 [msec]
1 [sec]
(See Note (2))
100 [msec]
1 [sec]
(See Note (2))
See Note (3)
Note:
(1) If the Application Type is SD-memory Card regulated in CFG_REG, they shall be applied the value defined in Section
4.6.2.1 for memory commands, and Section 5.7.2.1 and 5.7.2.4 for extension commands on "SD Specifications Part 1
Physical Layer Specification Version 4.10".
(2) This value is not applied during the "recording period" defined by Speed Grade specification. Refer to "SD Specifications
Part 1 Physical Layer Specification Version 4.10" for more details.
(3) If the Application Type is SD-memory Card regulated in CFG_REG, they shall be applied the value defined in Section
4.10.2 and Section 4.14 of "SD Specifications Part 1 Physical Layer Specification Version 4.10".
Table 7-5 : Device Timing Parameters in SD-TRAN
Note that maximum time from R1b to EBSY not appeared in Table 7-5 (e.g. CMD20) shall be applied
the value defined in "SD Specifications Part 1 Physical Layer Specification Version 4.00 or later".
Total time for Initialization of SD-TRAN Device shall be up to 1 [sec]. To say strictly, when SD-TRAN is
implemented, Device shall satisfy the following inequation:
Tactivate + Tfwd_init_cmd(s) + Tfwd_init_cmd(c) + Tacmd41 ≤ 1 [sec], where,
• Tacmd41 is duration from the first ACMD41 to the completion of Initialization by ACMD41.
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5422
5423
5424
5425
5426
5427
5428
• Other parameters are defined in Section 6.3.1.
7.3.2 Example Sequence of Timeout Occurrence in SD-TRAN
Figure 7-33 illustrates an example sequence when Host cannot receive the RES of encapsulated
CCMD (CMD38 in this example).
Node ID=0
TRANS_
ABORT
Node ID=1
Read
ST_REG
Header
RES
(R1)
D1
Time →
Control Trans.
END
Missing RES for
CMD38
Argument
D0
Payload=
ST_REG
Tcmd_res
Control Trans.
START
CMD
13
RES
RES
D1
CCMD
CCMD
(Read)
CMD38
RES
D0
CCMD
(Write)
Device
CCMD
Host
Encapsulated Legacy SD
CMD/RES/DATA
Payload
Transaction Layer Packet
5429
5430
5431
5432
5433
5434
5435
5436
5437
5438
Link Layer Packet (Link Message Packet)
Figure 7-33 : Example Sequence When Missing RES of CMD38
When Host detects timeout of Tcmd_res after issuing CMD38, Host should issue TRANS_ABORT
CCMD to terminate the transaction of CMD38. Then Host should read error identifiers and status of
Device indicated in Device's ST_REG. Additionally, Host can issue CMD13 to get Card Status.
Figure 7-34 illustrates an example sequence when Host cannot receive FCREQ during data transaction
by CMD18.
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Node ID=0
TRANS_
ABORT
Device
CCMD
CCMD
(Read)
CCMD
(Write)
CMD
18
MSG
(STAT)
MSG
(FCRDY)
D0
DCMD
Host
Node ID=1
Read
ST_REG
CMD
12
D0
Payload=
ST_REG
Tstat_fcreq(r)
RES
(R1b)
MSG
(EBSY)
RES
DATA
1
RES
RES
DATA
0
DATA
DATA
RES
(R1)
MSG
(FCREQ)
D1
RES
RES
Missing FCREQ
D1
Time →
Data Trans.
START
Data Trans.
END
Header
Argument
Payload
Extended Argument
Transaction Layer Packet
Settings
• N_FCU = 2 blocks (number of packets within a FCU)
Link Layer Packet (Link Message Packet)
5439
5440
5441
5442
5443
5444
5445
5446
5447
5448
5449
Busy Period
Figure 7-34 : Example Sequence When Missing FCREQ during Data Transaction by CMD18
Different from the example in UHS-II native protocol (described in Figure 6-61), when Host detects
timeout of Tstat_fcreq(r) during data read transaction, Host should issue TRANS_ABORT CCMD at first
to recover from the illegal situations, read error identifiers and status of Device indicated in Device's
ST_REG, and then it shall issue the encapsulated CMD12 to terminate the outstanding data
transmission. Moreover, Host can issue CMD13 if necessary (not illustrated in Figure 7-34).
Figure 7-35 illustrates an example sequence when Host cannot receive FCRDY during data transaction
by CMD25.
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TRANS_
ABORT
Device
Tfcreq_fcrdy(w)
D0
RES
(R1b)
MSG
(EBSY)
RES
RES
RES
MSG
(STAT)
MSG
(FCRDY)
RES
RES
(R1)
CMD
12
Payload=
ST_REG
Missing FCRDY
D1
Node ID=1
Read
ST_REG
CCMD
DATA
1
CCMD
(Write)
DATA
0
MSG
(FCREQ)
CMD
25
DATA
MSG
(FCREQ)
D0
DCMD
Host
DATA
TMODE=0000
CCMD
(Read)
Node ID=0
D1
Time →
Data Trans.
START
Header
Argument
Payload
Extended Argument
Encapsulated Legacy SD
CMD/RES/DATA
Data Trans.
END
Settings
• N_FCU = 2 blocks (number of packets within a FCU)
Transaction Layer Packet
5450
5451
5452
5453
5454
5455
Busy Period
Link Layer Packet (Link Message Packet)
Figure 7-35 : Example Sequence When Missing FCRDY during Data Transaction by CMD25
Same as the example illustrated in Figure 7-34, when Host detects timeout of Tfcreq_fcrdy(w) during
data write transaction, Host should issue TRANS_ABORT CCMD, read ST_REG, and shall issue
CMD12 in this order. In addition, transmitted data is not guaranteed in this case.
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5456
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470
5471
5472
5473
8. 2L-HD Mode (optional in Range A and B)
8.1 Overview
Lower operating frequency generally provides applicability to a variety of hosts due to easy
implementation of whole system. Duplex mode switching between FD mode and 2L-HDmode achieves
a good balance between easy controllability and higher bus efficiency under I/O pin count restriction as
in SD Memory.
FD mode provides easy controllability by setting D0 and D1 to different directions, because handshake
between Host and Device can be performed anytime. It is the default mode in UHS-II. On the other
hand, 2L-HD mode realizes higher speed data transfer than FD mode by setting D0 and D1 to the same
direction. 2L-HD mode is optional in UHS-II specification.
Basically, CCMD, DCMD, RES and MSG are transmitted in FD mode. Only DATA can be transmitted in
both FD mode and 2L-HD mode. If Host intends to read or write data in 2L-HD mode, duplex mode
switching shall be executed after DCMD and RES handshake.
On the way of data transmission in 2L-HD mode, it suspends data transmission and switches to FD
mode temporarily in order to keep room for sending CCMD or MSG. Then it switches to 2L-HD mode
again and continue data transmission.
Note that 2L-HD mode is not available in Range C and Range D.
Write
2L-HD Data Write
( x2 bandwidth )
Host
D0
D1
DCMD
DATA0
RES
DCMD
RES
S
w
D1
5474
5475
5476
DATA3
DATA4
DATA1
DATA2
DATA3
DATA4
D0
S
w
DCMD
S
w
DCMD
RES
DATA0
RES
D1
Time →
2L-HD Data Read
( x2 bandwidth )
Host
D0
DATA2
Data Transaction
(2L-HD mode)
Data Transaction
(FD mode)
Read
DATA1
Device
DATA1
DATA2
DATA3
DATA4
DATA1
DATA2
DATA3
DATA4
Device
S
w
D0
D1
Figure 8-1 : Overview of FD Mode and 2L-HD Mode
5477
8.2 PHY Layer Specification
5478
5479
5480
8.2.1 Direction Switching
5481
8.3 Link Layer Specification
5482
5483
5484
5485
8.3.1 Framing Rules for 2L-HD Mode
5486
5487
8.3.1.1 Block Mode
Figure 8-2 illustrates a framing rule for DATA packet for 2L-HD mode in case of Block Mode. Payload in
Refer to Chapter 4.
Framing rules for CCMD, DCMD, RES and MSG are identical to those described in Section 5.2.6,
because such packets are transmitted only in FD mode.
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5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502
the original DATA packet in TRAN is divided into two framed DATA packet called "Even Framed DATA
packet" and "Odd Framed DATA packet". That is, Payload[0], Payload[2], ... are assigned to Even
Framed Data Packet, Payload[1], Payload[3], ... are assigned to Odd Framed Data Packet respectively,
where the bracketed number denotes the byte position in each field counted from 0. Note that Header is
not divided and assigned to both Data Packets as it is.
Even Framed DATA packet consists of SOP LSS, Even Data Packet, CRC (Even), and EOP LSS.
Similarly, Odd Framed DATA packet consists of SOP LSS, Odd Data Packet, CRC (Odd), and EOP
LSS. CRC (Even) is calculated from Even Data Packet, and CRC (Odd) is calculated from Odd Data
Packet. Even Framed DATA packet is transmitted through the Direction Fixed Lane (abbreviated to
DFL) whose direction does not change within a transaction of 2L-HD mode (D0 for Host and D1 for
Device). On the other hand, Odd Framed DATA packet is transmitted through the Direction Switched
Lane (abbreviated to DSL) whose direction changes within a transaction of 2L-HD mode (D0 for Device
and D1 for Host). Note that the basic length of Payload in each Framed DATA packet is half of the Block
Length.
Even Framed DATA Packet
DFL SOP LSS
Original DATA Packet in TRAN
Header
2
Data Packet
Payload
[0] [1] [0] [1] [2]
Even Data Packet
Header Header
[1]
[0]
1
Payload (Even Byte)
1
CRC
(Even)
EOP LSS
2
2
(Block Length)/2
LSB
MSB
...
Block Length
Odd Framed DATA Packet
DSL SOP LSS
2
Odd Data Packet
Header Header
[1]
[0]
1
Payload (Odd Byte)
1
CRC
(Odd)
EOP LSS
2
2
(Block Length)/2
5503
5504
5505
5506
5507
5508
5509
5510
5511
5512
Figure 8-2 : DATA Packet Framing Rule for 2L-HD Mode (Block Mode)
The rule illustrated in Figure 8-2 is applicable when Block Length is multiple of 4. Otherwise, PAD shall
be inserted adequately between Data Packet and CRC, for the length of each Framed DATA Packet
shall be even byte. Figure 8-3 illustrates three patterns ([a], [b], and [c]) of framing rule in 2L-HD mode if
the Block Length of original payload is an aliquant of 4. Note that two PADs are inserted in case of
pattern [a].
The CRC calculating and adding rules are same as described in Section 5.2.6.2.1.
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Even Framed DATA Packet
[a]
DFL SOP LSS
Original DATA Packet in TRAN
Even Data Packet
1
2
Header
Data Packet
Payload
[0] [1] [0] [1] [2]
...
PAD
Payload Payload (K23.7)
[22]
[24]
Header Header Payload
[1]
[0]
[0]
1
1
CRC
(Even)
EOP LSS
2
2
13
LSB
MSB
Odd Framed DATA Packet
[24]
DSL SOP LSS
Block Length = 25
Odd Data Packet
Header Header Payload
[1]
[0]
[1]
1
2
PAD
PAD
Payload (K23.7) (K23.7)
[23]
CRC
(Odd)
EOP LSS
1
2
2
CRC
(Even)
EOP LSS
2
2
1
1
12
Even Framed DATA Packet
[b]
DFL SOP LSS
Original DATA Packet in TRAN
Even Data Packet
Header Header Payload
[1]
[0]
[0]
1
2
Header
Data Packet
Payload
[0] [1] [0] [1] [2]
...
PAD
Payload Payload (K23.7)
[24]
[22]
1
1
13
LSB
MSB
Odd Framed DATA Packet
[24] [25]
DSL SOP LSS
Block Length = 26
Odd Data Packet
Header Header Payload
[1]
[0]
[1]
1
2
PAD
Payload Payload (K23.7)
[25]
[23]
1
1
CRC
(Odd)
EOP LSS
2
2
CRC
(Even)
EOP LSS
2
2
13
Even Framed DATA Packet
[c]
DFL SOP LSS
Original DATA Packet in TRAN
Even Data Packet
Header Header Payload
[1]
[0]
[0]
1
2
Header
Data Packet
Payload
[0] [1] [0] [1] [2]
...
Payload Payload Payload
[22]
[24]
[26]
1
14
LSB
[24] [25] [26]
Block Length = 27
MSB
Odd Framed DATA Packet
DSL SOP LSS
Odd Data Packet
Header Header Payload
[1]
[0]
[1]
1
2
PAD
Payload Payload (K23.7)
[23]
[25]
1
1
CRC
(Odd)
EOP LSS
2
2
13
5513
5514
5515
5516
5517
5518
5519
Figure 8-3 : DATA Packet Framing Rule in 2L-HD Mode (Block Length Is Aliquant of 4)
Figure 8-4 illustrates a DATA Burst framing rule in 2L-HD mode. The rule is similar to that in FD mode
described in Section 5.2.6.2. As a result, two DATA Bursts are generated in the same time; one is for D0
and the other is for D1.
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Even framed DATA Packet
SDB LSS
DFL
SDB LSS SOP LSS
2
2
2
DATA Packet (Dxx.x)
CRC
EOP LSS DIDL LSS ... DIDL LSS SOP LSS
(Dxx.x)
Payload
Header
DATA Packet (Dxx.x)
Header
Even framed DATA Packet
DIDL * N_DATA_GAP (≥0)
Payload
2
2
2
2
2
CRC
EOP LSS EDB LSS
(Dxx.x)
2
2
2
EDB LSS
2
2
2
MSB
LSB
Odd framed DATA Packet
DSL
SDB LSS
2
5520
5521
5522
SDB LSS SOP LSS
2
2
DATA Packet (Dxx.x)
CRC
EOP LSS DIDL LSS ... DIDL LSS SOP LSS
(Dxx.x)
Payload
Header
DATA Packet (Dxx.x)
Header
Odd framed DATA Packet
DIDL * N_DATA_GAP (≥0)
Payload
2
2
2
2
2
CRC
EOP LSS EDB LSS
(Dxx.x)
2
2
2
EDB LSS
2
2
2
Figure 8-4 : DATA Burst Framing Rule in 2L-HD Mode
5523
5524
5525
5526
8.3.1.2 Byte Mode
As mentioned in Section 6.2.2.4, Data transmission by Byte Mode is inhibited in 2L-HD mode. So
DCMD with DM = 1 and TLUM = 1 shall be regarded as an illegal command (ARG_ERR).
5527
5528
5529
8.3.2 Sequence for Duplex Mode Switching
Figure 8-5 illustrates a duplex mode switching sequence in case of data read in 2L-HD mode.
TMODE=1000
MSG
(FCRDY)
DIR
MSG
(STAT)
DIR
DIR
EDB
DIR
EDB
EDB
DIR
Odd_
DATA
1
EDB
DATA
SDB
DATA
DIR
SDB
DIR
Switch
MSG
(FCRDY)
DCMD
(Read)
Odd_
DATA
0
DIR
Switch
D0
DIR
DIR * N_LSS_DIR * 8
Host
Device
D0
FD mode
Time →
Header
mode switch
(Fixed)
2L-HD mode
mode switch
(Variable)
Extended Argument
MSG
(FCREQ)
DIDL
DIDL
DIDL
Even_
DATA
1
DIR
DATA
Even_
DATA
0
D1
FD mode
Interval Period
FCU period
Interval Period
Argument
SDB
DATA
SDB
DIR
DIR
DIR
DIDL
DIDL
D1
DIDL
RES
MSG
(FCREQ)
DATA Burst
Payload
LSS
Some LSSes are dropped from this
figure for convenience.
Transaction Layer Packet
Settings
• N_FCU = 2 blocks
- Note that number of DATA packets is twice of N_FCU in 2L-HD mode
5530
5531
5532
5533
5534
5535
5536
5537
5538
5539
Link Layer Packet (Link Message Packet)
Figure 8-5 : Duplex Mode Switching Sequence in Data Read
First, Host (= DATA Receiver) sends Read DCMD with TMODE = 1000b which means 2L-HD mode.
Duplex mode switching from FD mode to 2L-HD mode is triggered by FCRDY transfer via switching
Lane (in this case, D0 Lane) and completed by DIR LSS transfer via both Lanes.
Just after transmitting FCRDY MSG, Host starts switching D0 Lane direction from default Tx to Rx. On
the other hand, when Device (= DATA Initiator) receives the FCRDY MSG, it starts transmitting DIR LSS
on D1 Lane iteratively. Then Device also starts switching D0 Lane direction from default Rx to Tx. To
avoid a contention, the direction switch from Tx to Rx shall always be performed prior to the one from
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5540
5541
5542
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555
5556
5557
Rx to Tx. Refer to Section 8.3.4 for more details. After completing direction switch, Device transmits at
least the predetermined number (N_LSS_DIR * 8) of DIR LSS for each Lane to ensure symbol lock of
the switched D0 Lane.
During FCU period for 2L-HD mode, DATA Bursts are transmitted via both Lanes in parallel. Note that
the number of DATA packets in an FCU is twice as much as N_FCU.
Duplex mode switching from 2L-HD mode to FD mode is triggered by EDB transfer via both Lanes and
completed by DIDL LSS transfer via unswitched Lane (in this case, D1 Lane). At the termination of 2LHD mode, Device shall transmit EDB LSS via both Lanes simultaneously. Just after that, Device starts
switching D0 Lane direction from Tx to default Rx and transmitting DIR LSS on D1 Lane iteratively. If
Host receives at least one of the EDB LSS from two Lanes, and the following DIR LSS via D1 Lane, it
also starts switching D0 Lane direction from Rx to default Tx. This is same for Device in case of write
transaction shown in Figure 8-6. After completing direction switch, Host transmits DIR LSS via D0 Lane.
Then Device transmits DIDL LSS when it succeeds to receive DIR LSS. Host continues to transmit DIR
LSS until it receives DIDL LSS via D1 Lane. After receiving DIDL LSS, Host can send STAT MSG in FD
mode.
Figure 8-6 illustrates a duplex mode switching sequence in case of data write in 2L-HD mode. Except
DCMD - RES handshake, whole operations are symmetrical to the data read case shown in Figure 8-5.
FD mode
Time →
Header
mode switch
(Fixed)
DIR
DIR
DIR
Device
MSG
(FCREQ)
DIR
DIR
DIDL
DIR
DIR
Switch
DIDL
EDB
EDB
DIDL
EDB
EDB
D0
2L-HD mode
mode switch
(Variable)
Extended Argument
MSG
(FCRDY)
Odd_
DATA
1
MSG
(STAT)
DATA
Odd_
DATA
0
D1
FD mode
Interval Period
FCU period
Interval Period
Argument
Even_
DATA
1
DATA Burst
SDB
SDB
SDB
SDB
DATA
DIR
DIR
RES
D1
DIR
Switch
MSG
(FCRDY)
DIR * N_LSS_DIR * 8
Even_
DATA
0
DATA
SDB
DATA
SDB
DIR
DIR
DIR
DIDL
D0
DIDL
DCMD
(Write)
MSG
(FCREQ)
Host
DIDL
TMODE=1000
Payload
LSS
Some LSSes are dropped from this
figure for convenience.
Transaction Layer Packet
Settings
• N_FCU = 2 blocks
- Note that number of DATA packets is twice of N_FCU in 2L-HD mode
5558
5559
5560
5561
Link Layer Packet (Link Message Packet)
Figure 8-6 : Duplex Mode Switching Sequence in Data Write
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5563
5564
5565
5566
5567
5568
8.3.3 PLSM for 2L-HD Mode
In FD mode, Host sets D0 Lane to Tx and D1 Lane to Rx. On the other hand, Device sets D0 Lane to
Rx and D1 Lane to Tx as a default. These default Tx and Rx are controlled in accordance with PLSM
shown in Figure 5-13. On the other hand, non-default Tx, such as D0.Tx of Device, needs not to transit
to EIDL because non-default Rx does not have an Amplitude Detector in PHY.
Figure 8-7 illustrates a PLSM for non-default Tx or Rx in 2L-HD mode.
I/F Power Off
Power Off (from any state)
EIDL
LSS
PKT
VLD
(Power On) Reset
OFF
5569
5570
5571
5572
5573
5574
5575
5576
5577
5578
5579
5580
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593
5594
5595
STB
Note: It is allowed to go through EIDL before transiting to OFF.
Figure 8-7 : PLSM for Non-default Tx or Rx in 2L-HD Mode
For supporting 2L-HD mode, both sides of LINK need to have two different PLSMs for each Lane, one
for default Tx or Rx and the other for non-default Tx or Rx.
8.3.4 Details of Duplex Mode Switching Sequence
To avoid bus conflict, nodes shall comply with the sequence and timing of switching Lane direction.
• Direction Switch from Tx to Rx
• The Node shall transmit STB.H during T_EIDL_ENTRY (4 SI) after transmitting EOP of
FCRDY MSG or EDB.
• The Node shall complete switching direction from Tx to Rx within T_DIR_SWITCH (8 SI)
after completing transmission of STB.H.
• When transmitting FCRDY MSG with UNRECOVERABLE_ERROR=1, the Node shall not
perform duplex mode switching.
• Direction Switch from Rx to Tx
• The Node shall wait completion of direction switching from Tx to Rx for other side. How to
detect whether the other Node completes direction switch from Tx to Rx is up to
implementation.
• When receiving FCRDY MSG with UNRECOVERABLE_ERROR=1, the Node shall not
perform duplex mode switching.
In following subsections, examples of detailed sequence for duplex mode switching are described.
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5597
5598
8.3.4.1 2L-HD Read Transaction
Figure 8-8 illustrates a LINK state transition during duplex mode switching from FD to 2L-HD mode in
case of data read.
T2
T1
time
T4
T3
Host
Device
RCLK
RCLK Active
OFF
(during direction switch)
RCLK
D0
FCRDY
DIR DIR DIR DIR SDB SDB SOP
DATA
EOP DIDL DIDL SOP
DATA
D0
D1
DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR SDB SDB SOP
DATA
EOP DIDL DIDL SOP
DATA
D1
EOP SOP
FCRDY
EOP STB
STB
N_DATA_GAP
LINK State
of Host
T_EIDL_ENTRY
DLSM
Active.Control
PLSM (D0.Tx)
VLD (FCRDY)
PLSM (D0.Rx)
OFF
DATA Burst
≤ T_DIR_SWITCH
Active.Recv
SwtHD
STB
STB
T_EIDL_ENTRY
LINK State
of Device
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629
> T_DIR_SWITCH
VLD (DATA Burst)
PLSM (D0.Tx)
OFF
VLD (DIDL)
T_EIDL_RECOVERY
N_LSS_DIR * 8
SwtHD
STB
VLD (FCRDY)
≤ T_DIR_SWITCH
Active.Trans
Active.Trans.WaitRDY
PLSM (D1.Tx)
PLSM (D1.Rx)
VLD (DATA Burst)
OFF
PLSM (D1.Tx)
DLSM
VLD (DIR)
VLD (DIR)
VLD (DIDL)
PLSM (D1.Rx)
PLSM (D0.Rx)
RecvHD
OFF
OFF (TxàRx)
TransHD
OFF
OFF
(RxàTx)
STB
VLD (DIR)
VLD (DIR)
VLD (DATA Burst)
VLD (DATA Burst)
OFF
Figure 8-8 : Example LINK State Transition during Duplex Mode Switching
(FD to 2L-HD Read)
T1: Just after transmitting FCRDY MSG in Active.Control, LINK of Host (= DATA Receiver) transits its
DLSM to Active.Recv.SwtHD and instructs the PHY to send STB.H for the duration of T_EIDL_ENTRY
(= 4 SI) before entering to OFF state. After that, LINK of Host requests the PHY to start direction switch
of D0 Lane from default Tx to non-default Rx. And PHY of Host performs the direction switch and notify
its completion to the LINK within T_DIR_SWITCH (= 8 SI). After completing direction switch, PLSM for
D0.Rx (non-default Rx) of Host transits from OFF to STB immediately inside PHY to get ready for
receiving valid symbols via switched D0 Lane.
On the other hand, it takes LINK of Device (= DATA Initiator) a while to determine whether the receiving
packet is FCRDY in accordance with Packet Receiving Flow described in Section 5.8. And after
receiving FCRDY MSG, LINK of Device waits T_EIDL_ENTRY and transits its DLSM to
Active.Trans.SwtHD. But prior to starting direction switch, LINK of Device waits for more than
T_DIR_SWITCH to avoid a contention between both sides of Tx in D0 Lane.
T2: After the elapse of more than T_DIR_SWITCH in Active.Trans.SwtHD, LINK of Device starts to send
DIR LSS via unswitched D1 Lane and it also requests the PHY to start direction switch of D0 Lane from
default Rx to non-default Tx. And PHY of Device performs the direction switch and notify its completion
to the LINK within T_DIR_SWITCH (= 8 SI). After completing direction switch, LINK of Device transits its
PLSM for D0.Tx (non-default Tx) from OFF to STB and instructs the PHY to send STB.L for the duration
of T_EIDL_RECOVERY to get ready for transmitting valid symbols via switched D0 Lane.
T3: After the elapse of T_EIDL_RECOVERY in STB.L, LINK of Device transits to Active.Trans.TransHD
and starts to send at least the predetermined number (N_LSS_DIR * 8) of DIR LSS for each Lane to
acquire symbol lock. On the other hand, LINK of Host transits to Active.Recv.RecvHD after receiving
DIR LSS via both Lanes.
T4: After transmitting N_LSS_DIR * 8 of DIR LSS, Device starts to send DATA Burst via both Lanes.
Figure 8-9 illustrates a LINK state transition during duplex mode switching from 2L-HD to FD mode in
case of data read.
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T5
time
T6
T7
T8
T9
T10
Host
Device
RCLK
RCLK Active
OFF
(during direction switch)
D0
DATA
EOP EDB EDB STB
D1
DATA
EOP EDB EDB DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL LIDL LIDL
DATA Burst
LINK State
of Host
DLSM
STB
≤ T_DIR_SWITCH
VLD (DATA Burst)
PLSM (D1.Rx)
VLD (DATA Burst)
STB
STB
OFF
(RxàTx)
VLD (DIR)
VLD (LIDL)
VLD (STAT)
VLD (DIR)
D1
VLD (LIDL)
VLD (DIIDL)
VLD (LIDL)
OFF
T_EIDL_ENTRY
≤ T_DIR_SWITCH
Active.Trans
DLSM
LINK State
of Device
D0
OFF
PLSM (D1.Tx)
TransHD
SwtFD
OFF
PLSM (D0.Tx)
VLD (DATA Burst)
PLSM (D1.Tx)
VLD (DATA Burst)
PLSM (D1.Rx)
EOP LIDL LIDL LIDL
Active.Control
SwtFD
OFF
PLSM (D0.Rx)
STAT
T_EIDL_RECOVERY
Active.Recv
RecvHD
PLSM (D0.Tx)
PLSM (D0.Rx)
DIR DIR DIR DIR DIR LIDL LIDL SOP
T_EIDL_ENTRY
> T_DIR_SWITCH
5630
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
RCLK
STB
WaitSTAT
STB
OFF
(TxàRx)
VLD (DIR)
VLD (LIDL)
VLD (STAT)
Active
.Control
VLD (LIDL)
OFF
VLD (DIR)
VLD (DIIDL)
VLD (LIDL)
OFF
Figure 8-9 : Example LINK State Transition during Duplex Mode Switching
(2L-HD Read to FD)
T5: Just after transmitting EDB LSS via both Lanes, LINK of Device (=DATA Initiator) transits its DLSM
to Active.Trans.SwtFD and starts to send DIR LSS via unswitched D1 Lane and instructs the PHY to
send STB.H via switched D0 Lane for the duration of T_EIDL_ENTRY before entering to OFF state.
After that, LINK of Device requests the PHY to start direction switch of D0 Lane from non-default Tx to
default Rx. And PHY of Device performs the direction switch and notify its completion to the LINK within
T_DIR_SWITCH (= 8 SI). After completing direction switch, PLSM for D0.Rx (default Rx) of Device
transits from OFF to STB immediately inside PHY to get ready for receiving valid symbols via switched
D0 Lane.
On the other hand, after receiving at least one of the EDB LSS via both Lanes, LINK of Host (= DATA
Receiver) waits T_EIDL_ENTRY and transits its DLSM to Active.Recv.SwtFD. But prior to starting
direction switch, LINK of Host waits for more than T_DIR_SWITCH to avoid a contention between both
sides of Tx in D0 Lane.
T6: After the elapse of more than T_DIR_SWITCH in Active.Recv.SwtFD, LINK of Host also requests
the PHY to start direction switch of D0 Lane from non-default Rx to default Tx. And PHY of Host
performs the direction switch and notify its completion to the LINK within T_DIR_SWITCH (= 8 SI). After
completing direction switch, LINK of Host transits its PLSM for D0.Tx (default Tx) from OFF to STB and
instructs the PHY to send STB.L for the duration of T_EIDL_RECOVERY to get ready for transmitting
valid symbols via switched D0 Lane.
T7: After the elapse of T_EIDL_RECOVERY in STB.L, LINK of Host starts to send DIR LSS to acquire
symbol lock in switched D0 Lane.
T8: After receiving DIR LSS from Host via switched D0 Lane, LINK of Device transits to
Active.Trans.WaitSTAT and starts to send DIDL LSS same as in FD mode.
T9: After receiving DIDL LSS from Device via unswitched D1 Lane, LINK of Host transits to
Active.Control and starts to send STAT MSG same as in FD mode. Note that LINK of Host sets D0 Lane
to EIDL before and after transmitting STAT MSG in case of Low Power Mode.
T10: After receiving STAT MSG from Host, Device also transits to Active.Control and starts to send LIDL
LSS in Fast Mode or set to EIDL in Low Power Mode.
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5663
5664
5665
8.3.4.2 2L-HD Write Transaction
Figure 8-10 illustrates a LINK state transition during duplex mode switching from FD to 2L-HD mode in
case of data write.
T2
T1
time
T3
T4
Host
Device
RCLK
RCLK Active
RCLK
D0
DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR SDB SDB SOP
D1
FCRDY
EOP SOP
FCRDY
EOP STB
OFF
(during direction switch)
STB
DIR DIR DIR DIR SDB SDB SOP
DATA
EOP DIDL DIDL SOP
DATA
D0
DATA
EOP DIDL DIDL SOP
DATA
D1
N_DATA_GAP
T_EIDL_ENTRY
> T_DIR_SWITCH
LINK State
of Host
DLSM
TransHD
VLD (DIDL)
PLSM (D0.Tx)
DLSM
VLD (DATA Burst)
VLD (DIR)
OFF
PLSM (D0.Rx)
PLSM (D1.Rx)
DATA Burst
N_LSS_DIR * 8
SwtHD
VLD (FCRDY)
STB
OFF
T_EIDL_ENTRY
LINK State
of Device
T_EIDL_RECOVERY
Active.Trans
Active.Trans.WaitRDY
PLSM (D1.Tx)
5666
5667
5668
5669
5670
5671
5672
5673
5674
5675
5676
5677
5678
5679
5680
5681
5682
5683
5684
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694
5695
≤ T_DIR_SWITCH
OFF
OFF
(RxàTx)
STB
VLD (DATA Burst)
≤ T_DIR_SWITCH
Active.Recv
Active.Control
SwtHD
RecvHD
VLD (DIDL)
PLSM (D0.Rx)
VLD (DIR)
VLD (DIR)
VLD (DATA Burst)
OFF
PLSM (D0.Tx)
PLSM (D1.Tx)
VLD (FCRDY)
PLSM (D1.Rx)
OFF
STB
OFF (TxàRx)
OFF
STB
VLD (DIR)
VLD (DATA Burst)
Figure 8-10 : Example LINK State Transition during Duplex Mode Switching
(FD to 2L-HD Write)
T1: Just after transmitting FCRDY MSG in Active.Control, LINK of Device (= DATA Receiver) transits its
DLSM to Active.Recv.SwtHD and instructs the PHY to send STB.H for the duration of T_EIDL_ENTRY
(= 4 SI) before entering to OFF state. After that, LINK of Device requests the PHY to start direction
switch of D1 Lane from default Tx to non-default Rx. And PHY of Device performs the direction switch
and notify its completion to the LINK within T_DIR_SWITCH (= 8 SI). After completing direction switch,
PLSM for D1.Rx (non-default Rx) of Device transits from OFF to STB immediately inside PHY to get
ready for receiving valid symbols via switched D1 Lane.
On the other hand, it takes LINK of Host (=DATA Initiator) a while to determine whether the receiving
packet is FCRDY in accordance with Packet Receiving Flow described in Section 5.8. And after
receiving FCRDY MSG, LINK of Host waits T_EIDL_ENTRY and transits its DLSM to
Active.Trans.SwtHD. But prior to starting direction switch, LINK of Host waits for more than
T_DIR_SWITCH to avoid a contention between both sides of Tx in D1 Lane.
T2: After the elapse of more than T_DIR_SWITCH in Active.Trans.SwtHD, LINK of Host starts to send
DIR LSS via unswitched D0 Lane also requests the PHY to start direction switch of D1 Lane from
default Rx to non-default Tx. And PHY of Host performs the direction switch and notify its completion to
the LINK within T_DIR_SWITCH (= 8 SI). After completing direction switch, LINK of Host transits its
PLSM for D1.Tx (non-default Tx) from OFF to STB and instructs the PHY to send STB.L for the duration
of T_EIDL_RECOVERY to get ready for transmitting valid symbols via switched D1 Lane.
T3: After the elapse of T_EIDL_RECOVERY in STB.L, LINK of Host transits to Active.Trans.TransHD
and starts to send at least the predetermined number (N_LSS_DIR * 8) of DIR LSS for each Lane to
acquire symbol lock. On the other hand, LINK of Device transits to Active.Recv.RecvHD after receiving
DIR LSS via both Lanes.
T4: After transmitting N_LSS_DIR * 8 of DIR LSS, Host starts to send DATA Burst via both Lanes.
Figure 8-11 illustrates a LINK state transition during duplex mode switching from 2L-HD to FD mode in
case of data write.
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T5
time
T6
T7
T8
T9
T10
Host
Device
RCLK
RCLK Active
RCLK
D0
DATA
EOP EDB EDB DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIR DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL LIDL LIDL
D1
DATA
EOP EDB EDB STB
OFF
(during direction switch)
STB
DIR DIR DIR DIR DIR LIDL LIDL SOP
STAT
EOP LIDL LIDL LIDL
D0
D1
DATA Burst
T_EIDL_ENTRY
LINK State
of Host
DLSM
PLSM (D0.Tx)
≤ T_DIR_SWITCH
Active.Trans
TransHD
SwtFD
VLD (DATA Burst)
VLD (DIR)
PLSM (D1.Tx)
OFF
VLD (DATA Burst)
STB
T_EIDL_ENTRY
LINK State
of Device
DLSM
5697
5698
5699
5700
5701
5702
5703
5704
5705
5706
5707
5708
5709
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720
5721
5722
5723
5724
5725
5726
5727
5728
PLSM (D0.Rx)
STB
OFF
(TxàRx)
VLD (DIIDL)
VLD (LIDL)
> T_DIR_SWITCH
VLD (DIR)
VLD (LIDL)
≤ T_DIR_SWITCH
VLD (LIDL)
T_EIDL_RECOVERY
Active.Recv
RecvHD
Active.Control
SwtFD
VLD (DATA Burst)
VLD (STAT)
OFF
VLD (DIR)
VLD (DIIDL)
VLD (LIDL)
OFF
PLSM (D0.Tx)
PLSM (D1.Tx)
PLSM (D1.Rx)
Active
.Control
OFF
PLSM (D0.Rx)
PLSM (D1.Rx)
WaitSTAT
OFF
VLD (DATA Burst)
STB
OFF
(RxàTx)
STB
VLD (DIR)
VLD (LIDL)
VLD (STAT)
VLD (LIDL)
OFF
Figure 8-11 : Example LINK State Transition during Duplex Mode Switching
(2L-HD Write to FD)
T5: Just after transmitting EDB LSS via both Lanes, LINK of Host (=DATA Initiator) transits its DLSM to
Active.Trans.SwtFD and starts to send DIR LSS via unswitched D0 Lane and instructs the PHY to send
STB.H via switched D1 Lane for the duration of T_EIDL_ENTRY before entering to OFF state. After
that, LINK of Host requests the PHY to start direction switch of D1 Lane from non-default Tx to default
Rx. And PHY of Host performs the direction switch and notify its completion to the LINK within
T_DIR_SWITCH (= 8 SI). After completing direction switch, PLSM for D1.Rx (default Rx) of Host transits
from OFF to STB immediately inside PHY to get ready for receiving valid symbols via switched D1
Lane.
On the other hand, after receiving at least one of the EDB LSS via both Lanes, LINK of Device (= DATA
Receiver) waits T_EIDL_ENTRY and transits its DLSM to Active.Recv.SwtFD. But prior to starting
direction switch, LINK of Device waits for more than T_DIR_SWITCH to avoid a contention between
both sides of Tx in D1 Lane.
T6: After the elapse of more than T_DIR_SWITCH in Active.Recv.SwtFD, LINK of Device also requests
the PHY to start direction switch of D1 Lane from non-default Rx to default Tx. And PHY of Device
performs the direction switch and notify its completion to the LINK within T_DIR_SWITCH (= 8 SI). After
completing direction switch, LINK of Device transits its PLSM for D1.Tx (default Tx) from OFF to STB
and instructs the PHY to send STB.L for the duration of T_EIDL_RECOVERY to get ready for
transmitting valid symbols via switched D1 Lane.
T7: After the elapse of T_EIDL_RECOVERY in STB.L, LINK of Device starts to send DIR LSS to
acquire symbol lock in switched D1 Lane.
T8: After receiving DIR LSS from Device via switched D1 Lane, LINK of Host transits to
Active.Trans.WaitSTAT and starts to send DIDL LSS same as in FD mode.
T9: After receiving DIDL LSS from Host via unswitched D0 Lane, LINK of Device transits to
Active.Control and starts to send STAT MSG same as in FD mode. Note that LINK of Device sets D1
Lane to EIDL before and after transmitting STAT MSG in case of Low Power Mode.
T10: After receiving STAT MSG from Device, Host also transits to Active.Control and starts to send LIDL
LSS in Fast Mode or set to EIDL in Low Power Mode.
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8.4 Transaction Layer Specification
5730
5731
5732
8.4.1 Transaction Control and Management State Machine
5733
8.4.2 Error Handling
5734
5735
5736
5737
8.4.2.1 Handling CRC Error
Same as in FD mode, if CRC error is detected in some DATA packet in FCU, the error is notified by the
next MSG (STAT).
This is common to FD mode. Refer to Section 6.2.13.
5738
8.5 SD-TRAN Specification
5739
5740
5741
5742
5743
8.5.1 Basic Transaction Rules in SD-TRAN
In the examples shown below, N_FCU is supposed to be set to 2.
Figure 8-12 illustrates a sequence for Read DCMD with TMODE = 1100b (fixed transfer length, 2L-HD
mode) in SD-TRAN.
Node ID=0
TMODE=1100
Node ID=1
SD_ARG=data address
TLEN=4
Even _
DATA
2
DATA
Odd_
DATA
2
Odd_
DATA
3
D0
DATA
Even _
DATA
1
DATA
Odd_
DATA
1
DATA
DATA
CMD18
Odd_
DATA
0
DATA
DATA
D0
Device
DCMD
Host
Even _
DATA
3
D1
D1
RES
(R1)
DATA
RES
NACK=CMD is accepted
TMODE
- same as CMD
Even_
DATA
0
Time →
Data Trans.
START
FCU period (2L-HD mode)
FCU period (2L-HD mode)
DS + Interval period
DS period
Header
Argument
Encapsulated Legacy SD
CMD/RES/DATA
5744
5745
5746
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756
Extended Argument
Payload
Data Trans.
END
Settings
• N_FCU = 2 blocks
- Note that number of DATA packets is twice of N_FCU in 2L-HD mode
Figure 8-12 : Sequence of Read DCMD on SD-TRAN (CMD18, TMODE = 1100)
The detailed field values in Figure 8-12 are as follows;
[DCMD]
• Header (DCMD):
• NP = 0 (not native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (DCMD):
• TMODE = 1100b (LM = 1, DM = 1)
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5758
5759
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5762
5763
5764
5765
5766
5767
5768
5769
5770
5771
5772
5773
5774
5775
5776
5777
5778
5779
5780
5781
5782
5783
5784
5785
5786
5787
• APP = 0 (regular command)
• CMD_INDEX = 18 (command index in Legacy SD)
• Extended Argument (DCMD):
• SD_ARG = Argument of CMD18.
• TLEN = 4 (total length of data transferred during a data transaction)
[RES]
• Header (RES):
• NP = 0 (not native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• Other field is copied from DCMD
• Payload (RES):
• CONTENT = Response data of R1 (the length of Payload is 4 in this case)
[DATA]
• Header (DATA):
• NP = 0 (not native protocol)
• Packet Type = DATA
• DID = 0 (Node ID of Host)
• SID = 1 (Node ID of source Device)
• TID = the same value as TID of the corresponding DCMD
• Payload (DATA): requested read data by Host
• The framing rules are described in Section 8.3.1.
Same in FD mode, CMD23 is ignored (Card responds R1 but does not operate).
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5789
5790
Figure 8-13 illustrates a sequence for Write DCMD with TMODE = 1000b (infinite transfer length, 2L-HD
mode) in SD-TRAN.
Node ID=0
Node ID=1
SD_ARG=data address
TMODE=1000
Even_
DATA
1
Odd_
DATA
1
CCMD
Odd_
DATA
0
DATA
Even_
DATA
0
DATA
Odd_
DATA
1
DATA
Even_
DATA
1
DATA
DATA
CMD25
Even_
DATA
0
DATA
DATA
D0
Device
DCMD
Host
CMD
12
D0
RES
(R1)
Odd_
DATA
0
RES
D1
DATA
RES
NACK=CMD is accepted
TMODE
- same as CMD
RES
(R1b)
D1
Time →
Data Trans.
START
FCU period (2L-HD mode)
DS period
Header
Argument
FCU period (2L-HD mode)
Extended Argument
Encapsulated Legacy SD
CMD/RES/DATA
5791
5792
5793
5794
5795
5796
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814
5815
5816
5817
5818
Interval
DS + Interval period
DS + Interval period
Data Trans. is
terminated by
CMD12
Payload
Settings
• N_FCU = 2 blocks
- Note that number of DATA packets is twice of N_FCU in 2L-HD mode
Figure 8-13 : Sequence of Write DCMD on SD-TRAN (CMD25, TMODE = 1000)
The detailed field values in Figure 8-13 are as follows;
[DCMD]
• Header (DCMD):
• NP = 0 (not native protocol)
• Packet Type = DCMD
• DID = 1 (Node ID of destination Device)
• SID = 0 (Node ID of Host)
• TID = Transaction ID decided by Host
• Argument (DCMD):
• TMODE = 1000b (LM = 0, DM = 1)
• APP = 0 (regular command)
• CMD_INDEX = 25 (command index in Legacy SD)
• Extended Argument (DCMD):
• SD_ARG = Argument of CMD25.
[RES]
• Header (RES):
• NP = 0 (not native protocol)
• Packet Type = RES
• DID = 0 (the same value as SID in the corresponding DCMD)
• SID = 1 (Node ID of Device)
• TID = the same value as TID of the corresponding DCMD
• Argument (RES):
• NACK = 0 (the corresponding CMD is accepted)
• Other field is copied from DCMD
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5820
5821
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833
5834
• Payload (RES):
• CONTENT = Response data of R1 (the length of Payload is 4 in this case)
[DATA]
• Header (DATA):
• NP = 0 (not native protocol)
• Packet Type = DATA
• DID = 0 (Node ID of Host)
• SID = 1 (Node ID of destination Device)
• TID = the same value as TID of the corresponding DCMD
• Payload (DATA): transferred write data to Device
• The framing rules are described in Section 8.3.1.
Same in FD mode, CMD12 can be issued only during interval period in order to terminate this
transaction.
5835
8.5.2 Error Handling
5836
5837
5838
5839
8.5.2.1 Handling CRC Error
Same as in FD mode, if CRC error is detected in some DATA packet in FCU, the error is notified by the
next MSG (STAT).
5840
5841
5842
5843
8.5.2.2 Reaching Address to the End of User Data Area
If Host accesses the very last block in User Data Area, Device acts as described in Section 7.2.8.3 or
Section 7.2.8.4.
5844
5845
5846
8.6 Timing Rules
Both Host and Device shall keep the following timing rules related to direction switching.
Group
Direction
Switch
5847
5848
Abbreviation
T_DIR_SWITCH
Description
Timing parameter of duration for direction 8 SI
switching.
In case of switching from Tx to Rx, port shall
complete it within the time period of
T_DIR_SWITCH after transmitting STB.
In case of switching from Rx to Tx, on the other
hand, port shall wait for the time period more
than T_DIR_SWITCH after receiving STB, then
complete direction switching within the time
period within T_DIR_SWITCH.
Value
Table 8-1 : Timing Parameters Related to Direction Switch
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5850
5851
5852
5853
5854
5855
5856
5857
5858
9. Additional Lanes Support (optional)
9.1 Overview
Lower operating frequency generally provides applicability to a variety of Hosts due to easy
implementation of whole system. Adding more Lanes can give a good balance between performance
and complexity.
The basic idea is to extend to concept of FD mode and 2L-HD mode for DATA packets. Host and Device
can have one additional Lane (D2 or D3) or two additional Lanes (D2, D3), both are optional.
Device reports its capabilities in Generic Capabilities Register.
Figure 9-1 shows the entire possible Lane configuration.
mode
Lane
FD
2L-HD
2D1U-FD
1D2U-FD
2D2U-FD
D0
D1
D2
D3
Fixed to downstream
Fixed to upstream
5859
5860
5861
5862
5863
5864
Bidirectional
Figure 9-1 : Possible Lanes Configurations in FD / 2L-HD Mode
Figure 9-2 shows a case of 2D1U-FD mode, which is expected write performance boost. On the other
hand, Figure 9-3 shows a case of 1D2U-FD mode, which is expected double read performance boost.
Write
Host
D0
2 Lanes Data Write
(x2 bandwidth)
DCMD
D1
DATA0
DCMD
RES
DATA1
DATA1
Data Transaction
(FD mode)
D0
D1
DATA2
Data Transaction
(2D1U-FD mode)
Host
Device
D0
DCMD
RES
RES
DATA0
DATA1
DATA2
D2
5865
5866
5867
D2
Time →
1 Lane Data Read
(x1 bandwidth)
DCMD
D0
D1
RES
D2
Read
DATA2
Device
D1
D2
Figure 9-2 : Overview of 2D1U-FD Mode – Write Boost
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Write
Host
D0
Device
1 Lane Data Write
(x1 bandwidth)
DCMD
D1
DATA0
DCMD
RES
DATA1
DATA2
D1
RES
D3
D3
Data Transaction
(FD mode)
Read
Data Transaction
(1D2U-FD mode)
Host
D0
Time →
Device
2 Lanes Data Read
(x2 bandwidth)
DCMD
D1
D0
DCMD
RES
RES
DATA0
D3
5868
5869
5870
5871
5872
5873
DATA1
DATA2
D1
DATA1
DATA2
D3
Figure 9-3 : Overview of 1D2U-FD Mode – Read Boost
Figure 9-4 shows the case of 2D2U-FD mode: D2 is downstream and D3 is upstream – x2 read/write
performance boost.
Write
Host
D0
2 pairs Data Write
(x2 bandwidth)
DCMD
D1
DATA0
DCMD
RES
DATA1
Device
DATA2
DATA1
DATA2
D3
Data Transaction
(2D2U-FD mode)
Host
D0
D1
D2
D3
Data Transaction
(FD mode)
Read
D0
D1
RES
D2
Time →
2 pairs Data Read
(x2 bandwidth)
DCMD
Device
D0
DCMD
RES
RES
DATA0
DATA1
DATA2
D2
D1
D2
D3
5874
5875
5876
5877
D0
DATA1
DATA2
D3
Figure 9-4 : Overview of 2D2U-FD Mode
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5879
5880
5881
5882
9.1.1 Capabilities and Settings
5883
5884
5885
5886
9.1.2 Additional Lanes and Multi-device Topologies
The capabilities of a Device regarding Lanes support is described in Table 6-7 (Device-specific Number
of Lanes and Functionality). Device can indicate more than one option.
The setting is determined by Table 6-10 (Number of Lanes and Functionality)
Additional Lanes can be used also in Multi-device topologies. Figure 9-5 shows Ring topology making
use of additional two Lanes in FD mode for achieving x2 performance boost.
Host
TX
D0
D0
D2
RX
5887
5888
5889
5890
5891
5892
5893
D1
D2
RX
D1
D3
D3
D0
TX
D2
RX
Device A
D1
D3
TX
Device B
Figure 9-5 : Usage of 4 Lanes in Ring Topology
In UHS-II Addendum Version 1.00 or lator, Ring connection is limited to use only in case of FD mode by
2 Lanes and 2D2U-FD mode by 4 Lanes (refer to Figure 9-5). 2D1U-FD mode or 1D2U-FD mode can
be available in P2P or HUB connections.
5894
9.2 PHY Layer Specification
5895
5896
5897
5898
5899
5900
9.2.1 PHY Specification and Direction Switching
5901
5902
5903
5904
5905
5906
5907
5908
5909
5910
9.2.2 Default Behavior
The added Lanes shall use the same PHY as used for D0 and D1 Lanes complying with Chapter 4.
Note that specifications of D2 and D3 shall conform to those of D0 and D1 except the followings.
In order to reduce the number of Amplitude Detectors, the Amplitude Detector output of D0.Rx can be
used also for D2.Rx. And similarly, the Amplitude Detector output of D1.Rx can be used also for D3.Rx.
The state of the additional Lanes before enabled is defined in PHY specification – "Disconnected state".
The Rx and Tx are in power off / Dormant states.
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5912
5913
5914
5915
5916
9.3 Link Layer Specification
5917
5918
5919
5920
5921
5922
5923
5924
5925
5926
5927
5928
5929
9.3.1 Framing Rules
This section shows the case of 2D2U-FD mode, but it is also applied to both 2D1U-FD mode and 1D2UFD mode.
When the Additional Lanes Support is available, synchronization among plural Lanes with same
direction should be considered in state transitions, if necessary.
The Framing rules of DATA packet are similar to those of 2L-HD mode described in Section 8.3.1.
Differences between them are as follows.
• Even Framed DATA Packet is transmitted through D0 or D1, and Odd Framed DATA Packet
thought D2 and D3.
• Byte Mode is also available. Its framing rule is defined by substituting from Block Length to TLEN
in Section 8.3.1.
Figure 9-6 shows read operation in 2D2U-FD mode. The command and responses are sent and
received by D0 and D1. During FCU Period, even bytes are carried on D1 and odd bytes are carried on
D3.
Device
Device
Device
MSG
(FCRDY)
MSG
(STAT)
DCMD
(Read)
D0
MSG
(FCRDY)
TMODE =0000
Host
Host
D0
D0
MSG
(FCREQ)
EDB
(2N+0)
Odd_
Data
DATA
11
EDB
(2N+0)
Odd_
Data
DATA
00
DATA
SDB
DATA
SDB
MSG
(FCREQ)
D1
RES
DATA Burst
D1
D1
D2
EDB
(2N+1)
Odd_
Data
DATA
11
EDB
(2N+1)
Odd_
Data
DATA
00
DATA
DATA
D3
SDB
SDB
D2
D3
FD mode
Time →
Header
FCU period
Argument
Extended Argument
Payload
LS S
Some LSSes are dropped from this
figure for convenience.
Transaction Layer Packet
Settings
• N_FCU = 2 blocks
- Note that number of DATA packets is 2 times of N_FCU in FD 4-pairs mode
5930
5931
5932
5933
5934
5935
Link Layer Packet (Link Message Packet)
Figure 9-6 : Read Operation in 2D2U-FD Mode
Figure 9-7 shows write operation in 2D2U-FD mode. Again, even bytes are carried on D0 and odd bytes
are carried on D2.
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Device
Device
MSG
(FCREQ)
EDB
Even_
(2N+0)
DATA
Data
1
EDB
Even_
(2N+0)
DATA
Data
00
DATA
SDB
DATA
SDB
D0
DCMD
(Write)
Host
Host
MSG
(FCREQ)
TMODE=0000
D0
D0
MSG
(FCRDY)
MSG
(STAT)
EDB
Odd_
(2N+1)
DATA
Data
11
EDB
Odd_
(2N+1)
DATA
Data
00
DATA
DATA
SDB
SDB
D2
SDB
SDB
D1
MSG
(FCRDY)
RES
DATA Burst
D1
D1
D2
D3
D3
FD mode
Time →
Header
FCU period
Argument
Extended Argument
Payload
LS S
Some LSSes are dropped from this
figure for convenience.
Transaction Layer Packet
Link Layer Packet (Link Message Packet)
5936
5937
5938
5939
5940
5941
5942
5943
Settings
• N_FCU = 2 blocks
Note that number of DATA packets is 2 times of N_FCU in FD mode
Figure 9-7 : Write Operation in 2D2U-FD Mode
9.3.2 Lane Direction for 2D2U-FD Mode
Figure 9-8 shows Lane direction for 2D2U-FD mode between Host and Device.
Host sets D0 and D2 Lanes to Tx and D1 and D3 Lane to Rx, on the other hand, Device sets D0 and
D2 Lanes to Rx and D1 and D3 Lanes to Tx as default.
Host
5944
5945
5946
5947
5948
5949
Device
Default D0.TX
Default D0.RX
Default D1.RX
Default D1.TX
Default D2.TX
Default D2.RX
Default D3.RX
Default D3.TX
Figure 9-8 : Lane Direction for 2D2U-FD Mode
D2.Rx in Device can use the Amplitude Detector of D0.Rx. Similarly, the D3.Rx in Host can use the
Amplitude Detector of D1.Rx.
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5951
5952
9.3.3 LINK State Transition for 2D2U-FD Mode during Data Read – Fast Mode
Figure 9-9 illustrates LINK state transition for 2D2U-FD mode during data read in Fast Mode.
time
T1
T2
T3
T5
T4
T7
T6
T8
T9
Host
Device
RCLK
D0
D1
D2
D3
RCLK Active
LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL SOP
LIDL LIDL SOP
FCREQ
FCRDY
RCLK
EOP LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL SOP
EOP DIDL DIDL DIDL DIDL DIDL DIDL DIDL SDB SDB SOP
DATA
EOP DIDL DIDL SOP
DATA
STAT
(CRC Status)
EOP LIDL LIDL
EOP EDB EDB DIDL DIDL DIDL DIDL DIDL DIDL LIDL LIDL
D0
D1
LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL
D2
DATA
D3
LIDL LIDL LIDL LIDL LIDL LIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL SDB SDB SOP
EOP DIDL DIDL SOP
DATA
EOP EDB EDB DIDL DIDL DIDL DIDL DIDL DIDL LIDL LIDL
N_DATA_GAP
DATA Burst
DLSM
of Host
DLSM
of Device
Active.Control
Active.Control
Active.Trans
WaitRDY
TransFD
WaitSTAT
LIDL LSS
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978
(including LIDL0 or LIDL1
as a second symbol)
Active.Control
DIDL LSS
LIDL
(including DIDL0 or DIDL1
as a second symbol)
DIDL
Figure 9-9 : LINK State Transition for 2D2U-FD mode during Data Read – Fast Mode
T1: Before starting FC handshake (FCREQ and FCRDY), both sides of LINK stay in Active.Control
state. So, all Lanes are filled with a series of LIDL LSS including LIDL0 or LIDL1 symbol as a second
symbol in random order.
T2: When Tx Buffer is ready for transmitting DATA Burst (DATA * N_FCU * 2), LINK of Device (= DATA
Initiator) issues FCREQ (Flow Control Request) MSG directed by TRAN and transits its DLSM from
Active.Control to Active.Trans.WaitRDY.
T3: Device starts to transmit DIDL LSSes including DIDL0 or DIDL1 as a second symbol in random
order on D1 and D3
T4: When Rx Buffer is ready for receiving DATA Burst, LINK of Host (= DATA Receiver) issues FCRDY
(Flow Control Ready) MSG directed by TRAN and stays in Active.Control state. And after receiving
FCRDY from Host, LINK of Device transits to Active.Trans.TransFD state.
T6: LINK of Device starts to send two SDB (Start of DATA Burst) LSSes in Active.Trans.TransFD state.
T7: After sending DATA packets, LINK of Device sends two EDB (End of DATA Burst) LSSes and
transits to Active.Trans.WaitSTAT state.
T8: After receiving at least one EDB, LINK of Host sends STAT MSG. And after receiving STAT from
Host, LINK of Device goes back to Active.Control state and starts to transmit LIDL LSS.
Note: Fast Mode can be selected in CFG_REG ("Power Control Mode in Active.Control State") during
Configuration and reflected in Active state to minimize the latency during data transfer.
9.3.4 LINK State Transition for 2D2U-FD Mode during Data Read – Low Power Mode
Figure 9-10 illustrates LINK state transition for 2D2U-FD mode during data read in Low Power Mode.
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time
T1
T2
T3
T4
T_EIDL_
RECOVERY
Host
T5
T6
T7
N_LSS_SYN * 4
(set in Host)
T8
RCLK
EIDL
EIDL
D2
D3
T10 T11
T_EIDL_
RECOVERY
T12
T_EIDL_
ENTRY
4*N_LSS_SYN
(set in Host)
Device
RCLK
RCLK Active
D0
D1
T9
T_EIDL_
ENTRY
T13
T14
T15
T16
UHS-II Addendum Version 2.00 Draft
STB SYN SYN SOP
EIDL
EIDL
STB SYN SYN SOP
FCREQ
FCRDY
EIDL
EOP STB
EOP DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL SDB SDB SOP
DATA
EOP DIDL DIDL SOP
STB SYN SYN SOP
DATA
STB SYN SYN LIDL LIDL LIDL LIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL SDB SDB SOP
DATA
EOP DIDL DIDL SOP
EIDL
EOP STB
EOP EDB EDB DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL STB
EIDL
STB SYN SYN LIDL LIDL LIDL LIDL STB
STAT
(CRC Status)
STB SYN SYN LIDL LIDL LIDL LIDL STB
DATA
EOP EDB EDB DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL STB
D1
EIDL
D2
EIDL
D3
N_DATA_GAP
T_EIDL_
RECOVERY
D0
EIDL
T_EIDL_
ENTRY
N_LSS_SYN * 4
(set in Device)
DATA Burst
DLSM
of Host
DLSM
of Device
Active.Control
Active.Control
Active.Trans
TransFD
WaitRDY
DIDL LSS
SYN LSS
5979
5980
5981
5982
5983
5984
5985
5986
5987
5988
5989
5990
5991
5992
5993
5994
5995
5996
5997
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
Active.Control
WaitSTAT
(including SYN0 or SYN1
as a second symbol)
SYN
(including DIDL0 or DIDL1
as a second symbol)
DIDL
Figure 9-10 : LINK State Transition for 2D2U-FD Mode during Data Read – Low Power Mode
T1: Before starting FC handshake (FCREQ and FCRDY), both sides of LINK stay in Active.Control state
under Low Power Mode condition. So, all Lanes are filled with EIDL.
T2: Before sending the FCREQ message, Device changes D1 and D3 from EIDL to STB.L. The
Amplitude Detector in Host D1.Rx detects the transition from EIDL to STB.L and notifies the PLSM of
D1.Rx and D3.Rx. After STB.L, Device is sending SYN LSS to synchronize the D1.Rx and D3.Rx of
Host.
T3: When Tx Buffer is ready for transmitting DATA Burst (DATA * N_FCU * 2), LINK of Device issues
FCREQ MSG directed by TRAN and transits its DLSM from Active.Control to Active.Trans.WaitRDY.
Device sends the FCREQ message on D1 and LIDL on D3.
T4: After exiting from Active.Control state, LINK of Device starts to transmit DIDL LSSes including
DIDL0 or DIDL1 symbol as a second symbol in random order regardless of the setting of "Power
Control Mode in Active.Control State" in CFG_REG.
T5: When Rx Buffer is ready for receiving DATA Burst, LINK of Host issues FCRDY MSG directed by
TRAN and stays in Active.Control state. And after receiving FCRDY from Host, LINK of Device transits
to Active.Trans.TransFD state. Host starts with sending STB.L followed by SYN LSS on D0 and D2.
T7: Host is sending the FCRDY message on D0 and LIDL LSS on D2.
T8: LINK of Device starts to send two SDB LSSes in Active.Trans.TransFD state. TRAN of Device starts
to send Flow Control Unit (= N_FCU) of DATA packets through LINK and PHY.
T9: After sending DATA packets, LINK of Device sends two EDB LSSes and transits to
Active.Trans.WaitSTAT state.
T10: After receiving at least one EDB, LINK of Host is preparing to send STAT MSG. Host is sending
STB.L and SYN LSS on D0 and on D2 Lanes.
T11: Host sends SYN LSS on D0 and D2.
T12: Host sends the STAT message on D0 and LIDL LSS on D2.
T13: Host sends STB.H on D0 and D2.
T14: Device sends STB.H on D1 and D3
T15: Host sends EIDL on D0 and D2.
T16: Device sends EIDL on D1 and D3
Note: Low Power Mode can be selected in CFG_REG ("Power Control Mode in Active.Control State")
during Configuration and reflected in Active state to minimize the power consumption during data
transfer.
9.3.5 LINK State Transition for 2D2U-FD Mode during Data Write – Fast Mode
Figure 9-11 illustrates LINK state transition for 2D2U-FD mode during data write in Fast Mode.
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time
T1
T2
T3
T4
T5
T6
T8
T7
T9
Host
Device
RCLK
D0
D1
D2
D3
RCLK Active
LIDL LIDL LIDL SOP
FCREQ
EOP DIDL DIDL DIDL DIDL DIDL DIDL DIDL SDB SDB SOP
LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL SOP
FCRDY
DATA
RCLK
EOP DIDL DIDL SOP
DATA
EOP EDB EDB DIDL DIDL DIDL DIDL DIDL DIDL LIDL
EOP LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL SOP
LIDL LIDL LIDL LIDL LIDL LIDL LIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL SDB SDB SOP
T4
DATA
EOP DIDL DIDL SOP
DATA
STAT
(CRC Status)
EOP LIDL LIDL
EOP EDB EDB DIDL DIDL DIDL DIDL DIDL DIDL LIDL
LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL
D0
D1
D2
D3
N_DATA_GAP
DATA Burst
DLSM
of Host
DLSM
of Device
Active.Control
Active.Trans
WaitRDY
TransFD
WaitSTAT
Active.Control
LIDL LSS
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038
Active
.Control
(including LIDL0 or LIDL1
as a second symbol)
DIDL LSS
LIDL
(including DIDL0 or DIDL1
as a second symbol)
DIDL
Figure 9-11 : LINK State Transition for 2D2U-FD Mode during Data Write – Fast Mode
T1: Before starting FC handshake (FCREQ and FCRDY), both sides of LINK stay in Active.Control
state. So, both Lanes are filled with a series of LIDL LSS including LIDL0 or LIDL1 symbol as a second
symbol in random order.
T2: When Tx Buffer is ready for transmitting DATA Burst (DATA * N_FCU * 2), LINK of Host issues
FCREQ MSG on D0 directed by TRAN and transits its DLSM from Active.Control to
Active.Trans.WaitRDY. In same time, Host sends LIDL0 or LIDL1 randomly on D2.
T3: Host starts to transmit DIDL LSSes including DIDL0 or DIDL1 in random order on both D0 and D2.
T4: When Rx Buffer is ready for receiving DATA Burst, LINK of Device issues FCRDY MSG on D1 Lane
directed by TRAN and stays in Active.Control state. And after receiving FCRDY from Device, LINK of
Host transits to Active.Trans.TransFD state. In same time, Device sends LIDL0 or LIDL1 on D3.
T6: LINK of Host starts to send two SDB (Start of DATA Burst) LSSes in Active.Trans.TransFD state and
then Host starts to send N_FCU * 2 of DATA packets through LINK and PHY.
T7: After sending DATA packets, LINK of Host sends two EDB (End of DATA Burst) LSSes and transits
to Active.Trans.WaitSTAT state.
T8: After receiving at least one EDB, LINK of Device sends STAT (Status) MSG.
T9: Device is sending LIDL LSS.
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6040
6041
9.3.6 LINK State Transition for 2D2U-FD Mode during Data Write – Low Power Mode
Figure 9-12 illustrates LINK state transition for 2D2U-FD mode during data read in Low Power Mode.
time
Host
T1
T2
T_EIDL_
RECOVERY
T3
T4
T5
T6
T7 T8
D3
T12
T13
Device
RCLK Active
EIDL
D1
D2
T10 T11
T_EIDL_
ENTRY
RCLK
D0
T9
N_LSS_SYN *4
(set in Host)
STB SYN SYN SOP
FCREQ
EOP DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL SDB SDB SOP
EIDL
EIDL
STB SYN SYN SOP
FCRDY
EOP DIDL DIDL SOP
DATA
EOP DIDL DIDL SOP
N_LSS_SYN * 4
(set in Device)
EOP EDB EDB DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL STB
STB SYN SYN SOP
DATA
T_EIDL_
ENTRY
N_DATA_GAP
STAT
EOP STB
(CRC Status)
EOP EDB EDB DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL STB
EIDL
STB SYN SYN LIDL LIDL LIDL LIDL STB
T_EIDL_
RECOVERY
DATA
EIDL
EOP STB
STB SYN SYN LIDL LIDL LIDL LIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL SDB SDB SOP
EIDL
DATA
RCLK
STB SYN SYN LIDL LIDL LIDL LIDL STB
T_EIDL_
RECOVERY
EIDL
D0
EIDL
D1
EIDL
D2
EIDL
D3
T_EIDL_
ENTRY
N_LSS_SYN *4
(set in Device)
DATA Burst
DLSM
of Host
DLSM
of Device
Active.Control
Active.Trans
TransFD
WaitRDY
Active.Control
DIDL LSS
SYN LSS
6042
6043
6044
6045
6046
6047
6048
6049
6050
6051
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
Active.Control
WaitSTAT
(including SYN0 or SYN1
as a second symbol)
SYN
(including DIDL0 or DIDL1
as a second symbol)
DIDL
Figure 9-12 : LINK State Transition for 2D2U-FD Mode during Data Write – Low Power Mode
T1: Before starting FC handshake (FCREQ and FCRDY), both sides of LINK stay in Active.Control state
under Low Power Mode condition. All Lanes are filled with EIDL.
T2: Host is getting ready to transmit FCREQ by sending STB.L on D0 and D2. On Device side the
STB.L is detected by the Amplitude Detector of D0 and the PLSM of D2 is notified accordingly. After
STB, Host sends SYN LSS on D0 and D2 Lanes.
T3: When Tx Buffer is ready for transmitting DATA Burst (DATA * N_FCU * 2), LINK of Host issues
FCREQ MSG directed by TRAN and transits its DLSM from Active.Control to Active.Trans.WaitRDY.
Host sends FCREQ on D0 Lane and LIDL on D2 Lane.
T4: After exiting from Active.Control state, LINK of Host starts to transmit DIDL LSSes including DIDL0
or DIDL1 as a second symbol in random order regardless of the setting of "Power Control Mode in
Active.Control State" in CFG_REG.
T5: Device is preparing to send FCRDY by transmitting STB and then SYN LSS on D1. On D3 Lane,
Device transmits STB only.
T6: When Rx Buffer is ready for receiving DATA Burst, LINK of Device issues FCRDY MSG directed by
TRAN and stays in Active.Control state. And after receiving FCRDY from Device, LINK of Host transits
to Active.Trans.TransFD state. Device sends the FCRDY message on D1 Lane and LIDL on D3 Lane.
T7: LINK of Device is going back to EIDL.
T8: LINK of Host starts to send two SDB LSSes in Active.Trans.TransFD state. TRAN of Host starts to
send N_FCU*2 of DATA packets through LINK and PHY.
T9: After sending DATA packets, LINK of Host sends two EDB LSSes and transits to
Active.Trans.WaitSTAT state.
T10: LINK of Device is getting prepared to send STAT message by transmitting STB on D1 and D3
Lanes.
T11: Device sends SYN LSS on D1 and D3 Lanes.
T12: LINK of Device sends STAT MSG on D1 Lane and LIDL on D3 Lane.
T13: All Lanes are back to EIDL
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9.4 Transaction Layer Specification
6074
6075
6076
6077
6078
9.4.1 Initialization
Host shall always be connected to D0 and D1 signals. The initialization process shall be carried through
D0 and D1 as described in Chapters 6 and 7. In order to use D2 or D3, an additional stage is required
as described in Figure 9-13.
Init process as in 2-pairs
default mode
Host wants
to activate additional
pairs?
No
Yes
Host reads Generic
Capabilities Register in
CFG_REG
Additional
pairs are
supported?
No
Yes
Host sets number of
differential pairs in
Generic Settings
Register
in CFG_REG
Host sends
GO_DORMANT_STATE
command and goes to
EIDL on all Lanes before
wakeup
6079
6080
6081
6082
6083
6084
6085
6086
Figure 9-13 : Flow Chart of Activating Additional Lanes
Figure 9-14 shows the timing diagram of activating the additional Lanes and entry / exit of Dormant
state. Note that it is also applied to both 2D1U-FD mode and 1D2U-FD mode.
T1: Host sets the desired Lanes configuration in Generic Settings Register by sending write CCMD.
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6087
6088
6089
6090
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
T2: Device sends a response (NACK = 0).
T3: Host sends the GO_DORMANT_STATE command.
T4: Device sends back the GO_DORMANT_STATE command.
T5: Host starts dormant sequence by sending STB.H.
T6: Host sends EIDL.
T7: Device sends EIDL. Then it starts preparing for entry to Dormant State.
T7': Device transits to Dormant State within the elapse of sufficiently less than T_DMT_ENTRY from T7.
T7": PLSM of D1.Rx (Host) is EIDL.
T8: Host transits to Dormant State after the elapse of more than T_DMT_ENTRY from T7", and may
stop RCLK.
Between T1 and T9, D2 and D3 are in EIDL (before activation).
T9: Host activates its RCLK and sends STB.L on D0 and D2. The Amplitude Detector in D0.Rx of
Device detects the STB.L and notifies the PLSM of D0.Rx and D2.Rx.
T10: Device sends STB.L on D1 and D3.
T11: Host sends SYN LSS on D0 and D2 in order to synchronize Device.
T12: The PLL of Device is synchronized and Device can send SYN LSS to Host.
T13: Host sends LIDL (Fast Mode).
T14: Device sends LIDL (Fast Mode).
T7'
Host’s entry timing to
Dormant state
T7"
time T1
Host
T3
T2
RCLK
T4
T7
LIDL
Setting 4 Lanes in
common setting register
(Write CCMD)
D1
LIDL
LIDL
RES (NACK=0)
LIDL
STB.H
LIDL
GO_DORMANT_STATE
(Broadcast CCMD)
LIDL
STB.L
EIDL
STB.H
STB.L
Dormant
approved Send STB.H
Enable 4
lanes
DLSM
Initialize
UHS-II
Active
PLSM
(D0.Tx) LSS.LIDL
PLSM
(D1.Rx)
PLSM
(D2.Tx)
PLSM
(D3.Rx)
VLD
(LSS&PKT)
LSS.LIDL
LSS.LIDL
VLD
(LSS&PKT)
Start RCLK
Send STB.L
LSS.LIDL
VLD
(LSS&PKT)
LSS.LIDL
STB.H
LSS.LIDL
STB.H
Link State
of Device
PLL
LSS.LIDL
LSS.LIDL
VLD
(LSS&PKT)
VLD
(LSS&PKT)
LSS.LIDL
VLD
(LSS&PKT)
STB.H
LSS.LIDL
6111
6112
LSS.LIDL
LSS.LIDL
LSS.LIDL
LSS.SYN
LOCKED
PLL
Lock
Receive
SYN
Send
SYN
Active
LSS.SYN
STB.L
EIDL
STB.L
EIDL
STB.L
EIDL
UNLOCKED/OFF
AQUISITION
LSS.LIDL
LSS.SYN
LSS.SYN
STB.L
LOCKED
LSS.LIDL
LSS.SYN
AQUISITION
EIDL
STB.H
D3
Send LIDL
Enter to Config
LSS.SYN
Dormant
LSS.LIDL
Receive
SYN
STB.L
UNLOCKED
/OFF
unknown state during transition
between EIDL and STB
6108
6109
6110
Send
SYN
LSS.SYN
Send
STB.L
VLD
(LSS&PKT)
D2
SYN SYN SYN SYN LIDL LIDL LIDL
STB.L
Active
LSS.LIDL
SYN SYN SYN SYN SYN LIDL LIDL LIDL LIDL LIDL
STB.L
EIDL
DLSM
D1
Active
<< T_DMT_ENTRY
PLSM
(D0.Rx)
PLSM
(D1.Tx)
PLSM
(D2.Rx)
PLSM
(D3.Tx)
SYN SYN SYN SYN LIDL LIDL LIDL
PLL
Lock
EIDL
LOCKED
Receive
STB.L
D0
STB.L
EIDL
EIDL
PLL
SYN SYN SYN SYN SYN LIDL LIDL LIDL LIDL LIDL
Dormant
VLD
(LSS&PKT)
Device
RCLK
STB.L
EIDL
T14
T13
RCLK is running
STB.L
EIDL
EIDL
D3
T12
T11
RCLK may
be stopped
GO_DORMANT_STATE
(Broadcast CCMD)
D2
T10
T9
> T_DMT_ENTRY
RCLK is running
D0
Link State
of Host
T6
T5
T8
LSS.LIDL
LSS.LIDL
LSS.SYN
LSS.LIDL
LOCKED
Device’s entry timing
to Dormant state
Figure 9-14 : Activating Additional Lanes through GO_DORMANT_STATE Command
9.4.2 Transaction Control and Management State Machine
This is common to FD mode. Refer to Section 6.2.13.
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6113
6114
9.4.3 Error Handling
6115
6116
6117
6118
9.4.3.1 Handling CRC Error
Same as in FD mode, if CRC error is detected in some DATA packet in FCU, the error is notified by the
next MSG (STAT).
6119
9.5 SD-TRAN Specification
6120
9.5.1 Error Handling
6121
6122
6123
6124
9.5.1.1 Handling CRC Error
Same as in FD mode, if CRC error is detected in some DATA packet in FCU, the error is notified by the
next MSG (STAT).
6125
6126
6127
6128
9.5.1.2 Reaching Address to the End of User Data Area
If Host accesses the very last block in User Data Area, Device acts as described in Section 7.2.8.3 or
Section 7.2.8.4.
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6129
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
Appendix A (Normative) : Reference
A.1 Related Documentation
• SD Specifications Part 1 Physical Layer Specification Version 4.00 or later
• SD Specifications Part 1 Standard Size SD Card Mechanical Addendum Version 4.10
• SD Specifications Part 1 microSD Addendum Version 4.10
• SD Specifications Part 2 File System Specification Version 3.00
• SD Specifications Part E1 SDIO Specification Version 4.00 or later
• ANSI X3.230-1994, clause 11 (and also IEEE 802.3z, 36.2.4)
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6141
6142
6143
6144
Appendix B (Normative) : Special Terms
B.1 Terminology
2L-HD mode
8b/10b
Block
Block Length
Boot Code
Boot Code Loading
Boot Device
broadcast
BUSY period
Card
CM
CM-TRAN
Command Time Slot
Configuration
DATA Burst
DATA Burst Streaming
De-embedding
Device
Device Initialization
downstream
Embedded Device
Emphasis
Enumeration
Equalization
FD mode
Flow Control
Flow Control Unit
Fractional DATA Burst
Framing
Full Duplex mode
Half Duplex with 2
Lanes mode
Half Duplex with 2 Lanes mode
One of line coding that maps 8-bit symbols to 10-bit symbols to achieve DCbalance and bounded disparity.
Data unit to be transmitted by one DATA packet
Data length for one Block
Code including initial set of operations using bootstrapping process
Transmitting Boot Code from Boot Device to Host immediately after PHY
Initialization
Device that stores Boot Code
Operating to all connecting nodes (Devices)
Period that Host cannot access to backend (flash memory for SD-memory)
SD memory card
Common Mode
Common transaction layer in UHS-II
Time period that FULL_RESET, TRANS_ABORT, and arbitrary read CCMD
are allowed to be issued on the way of data transmission
An arrangement of functional unit or parameters according to capabilities of
Host and Devices
A unit that consists of one or more DATA packets and related LSS and can
be sent in one flow control unit
Bypassing DATA Bursts to the next Node without passing through LINK.
Removing the effect of unwanted component from the measurement result
The electrical equipment which transmit/receive data to/from Host and
communication is controlled by Host. Device includes Card and Embedded
Device
Process to make Device enable its all functions
Transmission from Host to Device
Non-removable SD Device without form factor
Compensation function of driver for the high speed signals which attenuates
on transmission line
Assigning Node ID for each connecting Device
Compensation function of receiver for the high speed signals which
attenuated on transmission line
Full Duplex mode
Process of managing the data transmission to prevent data overflow or
underflow.
A unit of period for data transmission accompanied by FCREQ-FCRDY
handshake. Also refer to DATA Burst.
A DATA Burst which consists of Framed DATA packet less than N_FCU
Prefixing SOP and postfixing EOP for packets, and prefixing SDB and
postfixing EDB for DATA Burst.
Communication mode that the direction of two Lanes is opposite each other.
Communication mode that the direction of two Lanes is same. It is optional
in Range A and Range B, and unavailable in Range C and Range D.
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Host
Hub
I/F power cycle
I/F power supply
Inter skew
Intra skew
Jitter
Lane
Legacy SD
Line
LINK
Loopback
Node
Node ID
Packet bypassing
Parallel termination
PHY
Return loss
Rx
SD-TRAN
Serializer/Deserializer
skew
TRAN
transaction
Tx
UHS-II Card
UHS-II native
upstream
Wakeup
X5R,X7R
The electrical equipment which transmit/receive data to/from Device (e. g.
SD Card) and control the communication. Only Host can issue commands.
Device that allows many Devices to be connected to a single port on a Host
Act of turning whole UHS-II interface off and then on again by I/F power
supply
Power supplement for UHS-II interface (e.g. VDD2 for SD-memory)
The skew between differential Lanes transmitting in same direction.
The skew between Positive Line signal and Negative Line signal of one
differential pair.
Jitter is undesirable time variation of a periodic signal, which is caused by ISI
and some fluctuations such as voltage supply and temperature etc.
Each set which consists of Tx Port, transmission Line and Rx Port. For
example, D0 consists of D0.Tx in Host, D0 Line and D0.Rx in Device.
SD card not supporting UHS-II interface
Component for connecting a Tx (Transmitter) Port and an Rx (Receiver) Port
and realizing differential transmission
The interface layer above PHY Layer. LINK is in charge of controlling data
flow and making management for LINK and PHY.
Method or procedure of routing electronic signals from their originating
facility quickly back to the same source entity without intentional processing
or modification
Host or Device
Number to identify Nodes
Sending packets to the next Node without any operations in TRAN
Termination connecting positive and negative Lines of a differential Lane
Physical Interface Layer
Reflection ratio of signal power in a transmission Line
Receiver Circuit, which is responsible for outputting differential signal
One of application specific layers in UHS-II. It bridges CM-TRAN and Legacy
SD applications or drivers.
A pair of functional blocks to compensate for limited input/output. These
blocks convert data between serial data and parallel interfaces in each
direction.
Time difference of transmission delay between two transmission Lines
The interface layer above LINK. It is divided into CM-TRAN and an
application specific TRAN.
A unit of communication that is taken place by one command
Transmitter circuit, which is responsible for outputting differential signal
SD card supporting UHS-II Interface
UHS-II without (or not considering) application specific layers
Transmission from Device to Host
PHY initialization state
Symbol for dielectric material of capacitors
6145
6146
6147
6148
B.2 Abbreviations
BSYN
Synchronization for Boot Code Loading
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CCMD
CDCP
CF
CFG_REG
CMD
CMD_REG
COM
CPR
CRC
CTS
DAM
DAP
DATA
DBR
DCMD
DCP
DFL
DID
DIDL
DIF-H
DIF-L
DIF-PD
DIF-Z
DIR
DJ
DLSM
DM
DSL
EDB
EIDL
EMI
EOP
ESD
FC
FCRDY
FCREQ
FCU
GAP
GD
GN
INT
INT_REG
IP
ISI
LFSR
LIDL
LM
Control Command
Candidate DCP
Completion Flag of Device Initialization
Configuration Register
Command
Command Register
Comma Symbol
Control Packet Reception
Cyclic Redundancy Check
Command Time Slot
Data Access Mode
Device Allocated Power
DATA packet
DATA Burst Reception
Data Command
Device Consumed Power
Direction Fixed Lane
Destination ID
Data Idle
Differential High state
Differential Low state
Pull-down state
High-Z (high impedance)
Direction
Deterministic jitter
Data Link State Machine
Duplex Mode
Direction Switched Lane
End of DATA Burst
Electrical Idle
Electromagnetic interference
End Of Packet
Electrostatic Discharge
Flow Control
Flow Control Ready
Flow Control Request
Flow Control Unit
Group Allocated Power
Group Descriptor
Group Number
Interrupt
Interrupt Register
Intellectual Property
Inter Symbol Interference
Linear Feedback Shift Register
Logical Idle
Length Mode
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LPM
LPS
lsb
LSB
LSI
LSS
MAX_BLKLEN
MLCC
msb
MSB
MSG
NACK
N_FCU
P2P
PAD
PLEN
PLL
PLSM
PM
RCLK
RES
RJ
SDB
SI
SID
SOP
SSC
STAT
STB
ST_REG
SYN
TBD
TBSM
TDR
TID
TJ
TLEN
TLP
TLUM
TPSM
TSSM
UI
VLD
VU_REG
Low Power Mode
Low Power State
Least Significant Bit
Least Significant Byte
Large Scale Integration
Link Symbol Set
Maximum payload length of one block
Mult i- Layer ceram ic capacit or
Most Significant Bit
Most Significant Byte
Message
Negative-acknowledge
Number of blocks in a FCU
Point to Point
Padding Symbol
Payload Length
Phase-Locked Loop
Physical Lane State Machine
Power Management
Referential Clock
Response
Random jitter
Start of DATA Burst
Symbol Interval, equal to 10 * UI
Source ID
Start Of Packet
Spread Spectrum Clocking
Status Message
Standby
Status Register
Synchronization
To Be Determined
Transaction Buffer-management State Machine
Time Domain Reflection
Transaction ID
Total jitter
Transfer Length
Transaction Layer Packet
TLEN Unit Mode
Transaction Processing State Machine
Transaction Scheduling State Machine
Unit Interval or data bit time interval
Valid State
Vendor Unique Register
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6150
6151
6152
6153
6154
6155
6156
6157
6158
Appendix C (Normative) :
Test Condition of Measuring Output Signals
C.1 Test Condition for Host Output Signal at TP2
By using Host test fixture, illustrated in Figure C- 1, a measurement for output waveform of Host
transceiver is performed. The Test fixture is designed to be as ideal as possible (100ohm differential
impedance and 25ohm common-mode impedance as the target). A detailed description of the test
fixture and the test procedure is defined in UHS-II PHY Test Guidelines document
Host
Host Test Fixture PCB
RCLK
LSI
D0
D1
Socket
Host PCB
6159
6160
6161
6162
6163
6164
6165
6166
TP1
TP2
Figure C- 1: Host Test Fixture Illustration (Concept)
C.2 Test Condition for Card Output Signal at TP2
By using Card test fixture, illustrated in Figure C- 2, a measurement for output waveform of Card
transceiver is performed. The test fixture is designed to be as ideal as possible (100ohm differential
impedance and 25ohm common-mode impedance as the target). A detailed description of the test
fixture and the test procedure is defined in UHS-II PHY Test Guidelines document
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Card Test Fixture PCB
RCLK
LSI
D0
PCB
UHS-II SD Card
Socket
D1
6167
6168
6169
TP2
Figure C- 2: Card Test Fixture Illustration (Concept)
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Appendix D (Normative) : Register
6170
6171
D.1 Register Summary
6172
6173
6174
6175
6176
6177
D.1.1 Register Types
Attribute of register field should be defined as an example shown below. It may help easy to understand
register specification
Register fields are assigned one of the attributes described below:
Register
Attribute
RO
ROC
ROW1C
RW
RWAC
HwInit
Rsvd
6178
6179
6180
6181
6182
6183
6184
Description
Read-only register:
Register bits are read-only and cannot be altered by software or any reset operation.
Writes to these bits are ignored.
Read-only status:
These bits are cleared to zero at reset. Writes to these bits are ignored.
Read-only status, Write-1-to-clear status:
Register bits indicate status when read, a set bit indicating a status event may be
cleared by writing a 1. Writing a 0 to ROW1C bits has no effect.
Read-Write register:
Register bits are read-write and may be either set or cleared by software to the
desired state. These bits are cleared to zero at reset.
Read-Write, automatic clear register:
Software requests an operation by setting the bit. The hardware shall clear the bit
automatically when the operation completes. Writing a 0 to RWAC bits has no effect.
Hardware Initialized:
Register bits are initialized by firmware or hardware mechanisms. Bits are read-only
after initialization, and writes to these bits are ignored.
Reserved. Device shall initialize to zero on reserved bits and ignore writes to these
bits. Host shall ignore these bits. The bit can be defined for future use.
Table D- 1 : Register Attribute Table
D.1.2 Register Initial Values
Hardware should set registers to their initial values at power-on reset. Initial values for RO and HwInit
are specified by each Device. Those for other types of register shall be set to zero except parameters
used in Boot Code Loading.
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6185
6186
6187
6188
6189
Appendix E (Informative) : Design Guide
For the ease of Host transmitter and receiver design, the informative specifications and eye masks at
TP1 are defined below and shown at Figure 4-6.
6190
E.1 Host Design
6191
6192
6193
6194
6195
E.1.1 Informative Specification of Host Transmitter at TP1
For the design of Host transceiver, an informative electrical specification and eye mask at TP1 are
shown in Table E- 1, Table E- 2 and Figure 4-6 (1). When designing Host transceiver, these
specification and eye mask may be used as a reference.
Item
Symbol
Range
A,B
Differential
voltage
Vdiff
C
D
Rise/Fall time
of Differential
signal
Tr,Tf
Empashis
TxEmp0
TxEmpL
TxEmpM
TxEmp0
TxEmpL
TxEmpM
TxEmpH
Common
mode voltage
EIDL state
differential
voltage
EIDL state
common mode
voltage
Intra skew
Inter skew
A,B,
C,D
C
Min
140
135
(140)
90
(140)
value
Typ
200
Max
280
-
350
-
350
25
1.0
2.5
-
-
0
1.5
3.0
0
1.5
3.0
4.5
200
-
2.0
3.5
5.0
250
350
350
Unit
mV
ps
Absolute value.Note.1
Absolute value.
140mV min is for STB.L period.
Note.1
Informative.
From 20% to 80% of voltage
swing.
Note 2
Disable Emphasis.Note 8,9
2.0
3.5
Note 8,9
dB
VCM
A,B
C
D
1.0
2.5
4.0
150
200
160
Vdiff_PD
A to D
-10
0
10
mV
VCM_PD
A to D
-10
0
10
mV
Skintra
A to D
A,B
C,D
-
-
25
0.35
1.4
ps
D
Note
Disable Emphasis.Note 8,9
Note 8,9
Note 1, 7
mV
Note 3
Note. 3,7
Skinter
UI
Note. 4,Note 5
Note 6
Note 1: With a differential termination of 100Ω.
Note 2: Designers should consider improvement of signal integrity and reduction of EMI to determine rise/fall time of
Host and Device output. Use of slower rise/fall time in Range A compare with Range B is an example implementation.
Note 3: In EIDL state, both positive and negative lines of D0 Lane are pulled down by Tx.
Note 4: This spec is tested by using a differential termination of 100Ω.
More details in UHS-II PHY Test Guidelines document.
Note 5: Intra skew means the skew between D0+ and D0- (and also D1+ and D1- when transmit from Host to Device in
2L-HD mode), as measured between half voltage swing of both signals.
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Note 6: Inter skew means the skew between D0 and D1, when both transmitters transmit from Host to Device, as
measured between cross points of each differential pair in 2L-HD mode.
Note 7: VCM_PD and VCM are measured in reference to its local GND.
(more details in UHS-II PHY Test Guidelines document).
Note 8: Host is strongly recommended to implement these Emphasis Strengths in the table and select appropriate strength
according to the Transmission Line condition and instruct Device to use same Emphasis strength for getting same
signal integrity on Downstream and Upstream.
Note 9: Output wave form shall comply with the Eye mask spec even in the case applying Emphasis. Applying PreEmphasis or
DeEmphasis is implementation
6196
6197
6198
6199
Table E- 1: D0, D1 Output Requirement for Host Transmitter at TP1 (Informative)
Item
Symbol
Min
value
Typ
Max
Unit
Differential voltage
Vdiff
140
200
280
mV
Rise/Fall time of
Differential signal
Tr,Tf
-
-
0.2
TRCLK
Common mode voltage
VCM
150
200
280
mV
Total Jitter
TJ
-
-
0.25
UI
Intra skew
Duty cycle
Skintra
TCKH
42.5
-
200
57.5
ps
%
Note
Absolute value.
Note.1
From 20% to 80% of voltage
swing.
Refer to Section 4.11 for low
EMI.
Note.2
Note.1,4,5
Refer to section 4.3.4.
Note 7
Note 3,6
Of TRCLK
Note.1: With a differential termination of 100Ω.
Note.2: TRCLK means the period time of RCLK
Note 3: Intra skew means the skew between RCLK+ and RCLK- as measured between half voltage swings of both signals.
Note 4: VCM is measured in reference to its local GND. (more details in UHS-II PHY Test Guidelines document)
Note 5: It is recommended for Host to disconnect legacy DAT0 DAT1 pull up resistors by switch in UHS II mode.
Note 6: Refer to Section 4.11 for reducing EMI.
Note 7: RCLK jitter for Host transmitter is measured related to itself using a 2nd order soft PLLwith BW of 2.34MHz/Sf
inside the test equipment. Detailed measurement procedure is described in UHS-II PHY Test Guidelines
document.
6200
6201
6202
6203
6204
6205
6206
6207
Table E- 2: RCLK Output Specification for Host Transmitter at TP1 (Informative)
E.1.2 Informative Specification of Host Receiver at TP1
For the design of Host receiver, an informative electrical specification and eye mask at TP1 are
shown in Table E- 3 and Figure 4-6 (6). When designing Host receiver these specification and eye
mask may be used as a reference.
Item
A,B
C
D
Min
95
80
40
Value
Typ
-
Max
-
A to D
95
-
-
A,B
C
D
A,B
50
150
95
-110
200
0
400
400
400
160
Symbol
Range
Vdiff
Differential
voltage of STB.L
Vdiff_STB.L
Common mode
voltage
VCM
Differential
voltage
EIDL state
common mode
voltage
Total Jitter
VCM_PD
TJ
C,D
-60
0
110
A to D
-
-
0.5
Unit
Note
Absolute value.
mV
mV
mV
Absolute value.
Note 4
The allowed common mode
voltage under any condition.
Note 1,2
mV
UI
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Inter skew
Skinter
A,B
C,D
-
-
1.25
5.0
UI
Note 3
Note 1: In EIDL state, both positive and negative lines of D1 Lane are pulled down by Tx.
Note 2:VCM_PD and VCM are measured in reference to its local GND.( more details in UHS-II PHY Test Guidelines document)
Note 3: Host Receiver shall tolerate the inter skew spec defined at Table 4-10 and additional inter skew caused in Host PCB.
Note 4: Amplitude Detector (optional for Host) shall detect 95mV STB.L at least (90mV as Detection threshold of Amplitude
Detector is recommended, though it's implementation specific).
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6209
Table E- 3: D0, D1 Input Specification for Host Receiver at TP1 (Informative)
6210
6211
6212
6213
6214
6215
E.1.3 Host PCB Design
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229
E.1.4 Multi-Reflection of the Signal
The difference of the trace length between positive and negative of a differential Line causes intra skew.
Intra skew relates to Eye opening and EMI. The less Intra Skew is, the much more eye openes. For the
target of Host PCB design, it is recommended the difference between the length of positive and
negative in the Host PCB is less than 1mm.
The signal multi-reflection shoud be cared at Host Desing since the lane length would be shorter than
that of other high speed serial interfaces. Besides, it gets worse under the actual inter-operability
compared to test condition with test fixture. This jitter caused by multi-reflection is difficult to be
eliminated by the receiver Equalization.
Thus, at PCB desing stage, it is strongly recommended to make Host and Device connected simulation
models, then simulate how large eye opens in front of the receiver in silicon (not Host Rx TP1 and
Device Rx TP2). If eye doesn’t open enough due to multi-reflection, the followings are option:
• Improve impedance discontinuities in Host
• Select appropriate PCB material and socket for attenuating high frequency reflection signal
• Employ filter components for attenuating high frequency reflection signal
6230
6231
6232
6233
6234
6235
6236
6237
6238
6239
6240
6241
6242
6243
6244
E.1.5 Care for the Floating Input
In below 2 cases, Host receivers might face with floating input or Hi-Z. Host designer should take care
for these cases in order to avoid the false operation:
 Empty socket (No Card inserted)
In this case Host input Lines is floating and uncertain state should be avoided.
Host may use Card detect indication to enable/disable its input receiver and amplitude detector.
 Power cycle
When Host issues power cycles, it turns off VDD2 and input Lines become Hi-Z or floating.
Power cycle is under Host control, so it may easily enable/disable its input receiver and
amplitude detector to prevent uncertain state.
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6249
6250
6251
6252
6253
6254
6255
6256
6257
6258
6259
6260
6261
6262
6263
6264
6265
6266
6267
6268
6269
6270
6271
6272
6273
6274
E.1.6 Spread Spectrum Clocking (SSC)
Host may use SSC modulation with down spreading method which modulates the carrier frequency
toward only lower frequency.
The SSC is treated as in-band clock spectrum and therefore not filtered out by the Host and Device
PLLs. The one sided SSC (down spreading in UHS-II) is slightly decrease the average RCLK rate.
Therefore the average data transfer rate is also decreased accordingly with half of the SSC deviation
frequency e.g. ΔfRCLK/2.
If SSC is supported, there should be on/off configuration options. The SSC should be at "on" state
during power up and wakeup from Dormant state. The SSC is modulated by the Host side and no
special configuration is needed at the Device side. Nevertheless, Device designer should consider the
influence of SSC on Rx PLL, data recovery function and Device Tx. For example: Certain amount of
additional jitter is expected to appear on Device Rx PLL output, depending upon various PLL design.
Host that utilizes SSC should be aware that the SSC goes through the Device Tx circuitry. The SSC
received with the signal on Host Rx may be reduced (dependant on Device implementation, and Device
Tx circuitry BW).
Three cases should be considered:
I.
SSC may not appear at all on the data transmitted by Device.
II.
SSC may partially appear on the data transmitted by Device.
III.
SSC may fully appear on the data transmitted by Device.
SSC may be implemented as a method of reducing EMI. It is up to Host implementation to choose the
amount of RCLK spreading, ΔfRCLK, between 0ppm (equal to no spreading) to -5000ppm maximum
frequency spreading. The modulation frequency shall be within the 30 kHz – 33 kHz range.
.
Item
SSC modulation frequency
SSC peak frequency deviation
SSC Deviation rate
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6276
6277
6278
6279
6280
6281
6282
6283
Symbol
fssc
ΔfRCLK
(df/dt)
Value
Min
30
0
-30
Max
33
-5000
30
Unit
Note
kHz
ppm
kHz/usec
Table E- 4: SSC Parameters
The exact modulation shape for the SSC is Host implementation.
An example of the frequency modulation by triangular SSC waveform is shown in Figure E- 1 for the
maximum RCLK frequency of 52 MHz, data rate of 1.5GHz and SSC modulation frequency = 30KHz.
The frequency of the RCLK is varying by time according to triangular modulation.
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ΔfRCLK frequency deviation
0
6284
6285
6286
t0
t0+1/2fssc
t0+1/fssc
Time
ΔfRCLK(max)
=-5000ppm
~16.66μs
~33.33μs
Figure E- 1: Example Period Modulation for Triangular SSC
6287
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E.2 Device Design
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6291
6292
E.2.1 Device Transmitter Design
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6295
6296
6297
6298
6299
6300
6301
E.2.2 Device Receiver Design
The less Intra Skew is, the wider eye openes. It is recommended Intra Skew of D1 (and D0 in 2L-HD
mode) transferred from Device is less than 30ps for the target of Device design.
The following steps are useful for designing Receiver.
(Step.1) Calibrate the eye opening of signal source so as to close to (3) eye-mask of Figure 4-6, Figure 4-7
and Figure 4-8 at SI simulation.
In this calibration, output impedance of signal source is 50ohm as single-ended (100ohm as
differential) and Rterm for output calibration is 100ohm.
100ohm
Differential Swing [mV]
(3) Eye-mask for Device Receiver at TP2
Tx
0
Rx
-95
0
Signal source
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315
6316
0.6UI
95
0.2
0.5
Unit Interval [UI]
0.8
Figure E- 2: Calibration of Signal Source
(Step.2) Verify that the worst characteristic of Device Rx Lane components meets RLDD specification.
Device Rx Lane components mean Card Pin, PCB trace, LSI package and Termination resistor of
Receiver, Center-Tap capacitor, parasitic capacitance, etc.
(Step.3) Connect the signal source calibrated at step.1 to the Device Rx Lane model at SI simulation.
And measure the eye opening at the Termination resistor of Receiver.
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LSI package
Card pin
Tx
LSI DIE
Rx
PCB trace
Signal source
Differential Swing [mV]
Measured Eye pattern at Device receiver of LSI DIE
Device
y
x
0
-x
0
6317
6318
6319
6320
6321
6322
6323
6324
6325
6326
6327
6328
6329
6330
6331
6332
6333
6334
6335
6336
6337
6338
6339
6340
6341
6342
6343
6344
6345
6346
6347
6348
6349
0.5
Unit Interval [UI]
Figure E- 3: SI Simulation for Checking the Eye Opening at Receiver Termination
(Step.4) The eye opening measured at the Step.3 is helpful for designing Receiver input sensitivity since it
reflects the eye opening resulting at the Rx LSI after Device Rx Lane losses.
E.2.3 Device System Level CM Noise
In a Device, UHS-II PHY is integrated in a system that may cause CM noise to be experienced by the
PHY circuitry.
An example for typical CM noise source is the Device internal IO toggling. Other noise sources should
be considered as well, depending on specific device system implementation.
It is strongly recommended that Device designer would take the CM noise phenomenon into account.
The CM noise is generated inside the device, and its amount is dependent on the specific Device
implementation. Device designer should make sure that the Rx design is tolerable to this noise and Tx
signals meet Device Tx specification.
It is recommended to take the 'worst case' device operating conditions into account. Since 'worst case'
operation condition is individual per specific Device implementation, it is not defined herein. Device
designer is responsible to define the 'worst case' operation condition for a specific Device.
Nevertheless, it is recommended that 'worst case' operating condition will include also the Device
system internal IO toggling.
The following aspects should be taken into account when designing the Device:
Device Tx output – In order to address Vcm_noise and Vcm_pd_noise, it is recommended to take the
impact of the socket into account. For Device that supports Half Duplex, Device
designer should take into account that D0 and D1 transmitters might be differently
affected by CM noise.
Device Rx input (on LSI) – Since the Device internal CM noise is very strongly dependent with the
Device system implementation, there is no specific parameter defined for it in the
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6350
6351
UHS-II PHY specification. Device designer should assure that the CM noise
generated by the Device may be tolerated by the device PHY Rx design.
6352
6353
Other Device elements – In addition to the CM noise, it should be taken into account, otherwise it may
affect very strongly other elements inside the device (e.g. analog circuits)
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6355
Appendix F (Informative) : PHY-LINK I/F
6356
6357
6358
6359
F.1 Overview
6360
F.2 I/F Detail
6361
6362
6363
6364
F.2.1 Block Diagram
PHY-LINK I/F is defined to abstract the vendor-specific implementation of UHS-II PHY for the purpose
of distributing PHY and Protocol IP separately.
Figure F- 1 illustrates the block diagram of PHY-LINK I/F for Device. Signals or parameters with brace
mean that they are required in case of supporting 2L-HD mode.
PHY
PCLK
MODE
RCLK
PHY Logic
(PLL, SERDES, etc.)
RD (8/16 bit)
PHY Serial I/O
D0
RDM (1/2 bit)
{ RDTM (1/2 bit) }
{ RDT (8/16 bit) }
LINK
ST (6/ {8} bit)
CT (6/ {8} bit)
D1
TDM (1/2 bit)
TD (8/16 bit)
{ TDRM (1/2 bit) }
Vendor Specific
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
{ TDR (8/16 bit) }
NRST
Figure F- 1 : Block Diagram of PHY-LINK I/F for Device
PHY control and status signals are encoded by CT (Control) and ST (Status) signals respectively, and
these signals are transferred across PHY-LINK I/F based on PCLK. PHY-Logic is responsible for
converting CT and ST to meet the vendor-specific I/F of Serial I/O including PLL, SERDES, and so on.
The interface signals are divided into the following three categories.
• Transmit / Control data
• Receive / Status data
• Miscellaneous data
F.2.2 Definition of Interface Signal
From Table F- 1 to Table F- 3 show the detailed descriptions of the interface signals. In addition, Table
F- 4 shows the external signals provided from external part of PHY-LINK I/F. Note that P, L, and Ex in
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6382
6383
"Direction" column stand for PHY, LINK, and external part respectively. Moreover, signals and
explanations with asterisk mean that they are required in case of supporting 2L-HD mode.
Name
Direction
Width
(P: P HY , L: LINK )
Description
TD
LàP
8 or 16 Transmit Data for Tx Block †1
TDM
LàP
1 or 2 TD Coding Mode (0: D-Symbol, 1: K-Symbol) †2
TDR*
LàP
8 or 16 Transmit Data for Rx Block †1
TDRM*
LàP
1 or 2 TDR Coding Mode (0: D-Symbol, 1: K-Symbol) †2
PHY Control (CT[3:0] = PINIT/PCMD depending on MODE)
PHY Initialization parameter in Dormant state
[3:0]: PINIT
(when MODE=0)
[1:0]: Selected PHY Major Revision
Reserved (set 00b)
[3:2]: Selected Transmission Speed Range
00: Range A (390 – 780 Mbps per Lane)
01: Range B (780 – 1,560 Mbps per Lane)
10: Range C (2,880 – 3,120 Mbps per Lane)
11: Range D (5,760 – 6,240 Mbps per Lane)
PHY Command
CT
LàP
6 or 8*
[3:0]: PCMD
(when MODE=1)
0000: No Command Operation
0001: Enter to Loopback mode for DB Streaming
0011: Exit from Loopback mode for DB Streaming
0101: Enter to (2L-)HDIN mode (Default TxàRx) *
0110: Enter to (2L-)HDOUT mode (Default RxàTx) *
0111: Exit from (2L-)HD mode *
11XX : Reserved for Vendor Unique Command
others: Reserved
TD State Control
[5:4]: TDS
00: EIDL (Electrical Idle state with DIF-PD)
01: OFF (Electrical Off state with DIF-Z)
10: STB (Standby state with fixed DIF-L or DIF-H)
11: VLD (Valid 8b/10b Symbol state with DIF-L or DIF-H)
TDR State Control
[7:6]: TDRS*
6384
6385
6386
00: EIDL (Electrical Idle state with DIF-PD)
01: OFF (Electrical Off state with DIF-Z)
10: STB (Standby state with fixed DIF-L or DIF-H)
11: VLD (Valid 8b/10b Symbol state with DIF-L or DIF-H)
†1: When TDS/TDRS = STB, TD/TDR[0] = 0 and TD/TDR[0] = 1 indicate STB.L and STB.H
respectively, and TD/TDR[15:1] can be set arbitrary values.
If the width of TD/TDR is 16bit, "COM" symbol is always transmitted on TD/TDR[7:0].
†2: If the width of TD/TDR is 16bit, TDM/TDRM[0] and TDM/TDRM[1] corresponds to TD/TDR[7:0]
and TD/TDR[15:8] respectively.
Table F- 1 : Interface Signals (Transmit / Control Data)
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Name
Direction
Width
(P: PHY, L: LINK)
Description
RD
PàL
8 or 16 Receive Data of Rx Block †3
RDM
PàL
1 or 2 RD Coding Mode (0: D-Symbol, 1: K-Symbol) †4
RDT*
PàL
8 or 16 Receive Data of Tx Block †3
RDTM*
PàL
1 or 2 RDT Coding Mode (0: D-Symbol, 1: K-Symbol) †4
PHY Status
[0]: DET
Amplitude Detector Output (high active) †5
[1]: LOCK
PLL Lock (high active)
[2]: PACK
PCMD acknowledge (high active)
[3]: ERR
PHY Receive Error Status (0: No Error, 1: Error occurs on
at least one data Lane) †6
RD Status
ST
PàL
6 or 8*
[5:4]: RDS
00: EIDL (Electrical Idle state with DIF-PD)
01: OFF (Electrical Off state with DIF-Z)
10: STB (Invalid 8b/10b Symbol with DIF-L or DIF-H)
11: VLD (Valid 8b/10b Symbol with DIF-L or DIF-H)
RDT Status
[7:6]: RDTS*
00: EIDL (Electrical Idle state with DIF-PD)
01: OFF (Electrical Off state with DIF-Z)
10: STB (Invalid 8b/10b Symbol with DIF-L or DIF-H)
11: VLD (Valid 8b/10b Symbol with DIF-L or DIF-H)
†3: When RDS/RDTS = STB and ERR = 0, RD/RDT[0] = 0 and RD/RDT[0] = 1 indicate STB.L and
STB.H respectively, and RD/RDT[15:1] can be ignored.
If the width of RD/RDT is 16bit, "COM" symbol is always transmitted on RD/RDT[7:0].
†4: If the width of RD/RDT is 16bit, RDM/RDTM[0] and RDM/RDTM[1] correspond to RD/RDT[7:0]
and RD/RDT[15:8] respectively.
†5: DET is negated during DIF-PD and asserted when Amplitude Detector detects fixed DIF-L of
STB.L. And DET is asynchronous signal because it may be used without RCLK during Wakeup.
6387
6388
6389
†6: PHY Receive Error includes 8b/10b decode error (notified to LINK by ERR=1, RDS=STB, RD=0)
and 8b/10b disparity error (notified to LINK by ERR=1, RDS=VLD, RD=decoded data).
Table F- 2 : Interface Signals (Receive / Status Data)
Name
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
Direction Width
Description
PCLK
PàL
1
Parallel Interface Clock for LINK
MODE
LàP
1
PHY Power Mode (0: Dormant state, 1: After exiting from Dormant)
Table F- 3 : Interface Signals (Miscellaneous Data)
Name
Direction Width
CLK
ExàP
1
Source Clock (Only for Host)
NRST
ExàP&L
1
Asynchronous Reset (low active)
e.g. Power On Reset
Description
Table F- 4 : External Signals
F.2.3 Details of PCMD and PACK
PCMD stands for PHY Command and is used to perform specific functions directed by LINK.
Its value is "0000b" when no commands are requested. When LINK requests PHY to perform a function,
it set PCMD to the defined value other than "0000b". Note that PCMD is valid after exiting from Dormant
state (MODE = 1). Before that, CT[3:0] is used as PINIT to configure PHY speed range. PHY shall be
configured by PINIT at the last positive edge of PCLK before MODE assertion.
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6402
6403
6404
6405
6406
PACK is a pulse signal transferred from PHY to LINK as a PCMD acknowledgement. Assertion timing of
PACK depends on each PCMD. Just after receiving PACK, LINK shall set PCMD to "0000b" for at least
one cycle before requesting next PCMD.
Figure F- 2 shows an example sequence of PCMD and PACK.
PCLK
MODE
CT[3:0]
PCMD
(0000b)
PINIT
PCMD
(0000b)
PCMD-A
PCMD-B
PCMD
(0000b)
PACK
6407
6408
6409
Figure F- 2 : An Example Sequence of PCMD and PACK
6410
F.3 Clock Generation
6411
6412
6413
F.3.1 Clock Generation in Host
Figure F- 3 shows an example of clock generation in Host.
Selected Transmission Speed Range
(configured throgh PINIT)
CLK
MUX
PCLK
(MUX-ed)
Clock
From / To LINK
(source clock)
Generated PCLK
(1/10N of bit clock)
Host
PLL
LOCK
(=ST[1])
RCLK
(1/15, 1/30, 1/60 or 1/120
of bit clock)
MODE
bit clock
6414
6415
6416
6417
6418
6419
6420
6421
6422
6423
6424
6425
6426
6427
6428
6429
6430
(target rate)
Figure F- 3 : Clock Generation in Host
Host PLL generates bit clock based on source clock (CLK) before starting Wakeup sequence. MODE
signal is asserted when Host wants to exit from Dormant and start PHY activation. Moreover, MODE
signal is used as a trigger for starting PLL lock. Before asserting MODE signal, PLL shall be configured
by the setting of "Selected Transmission Speed Range" in CFG_REG through CT[3:0] (= PINIT).
After bit clock generation, RCLK shall be generated by dividing bit clock for the purpose of having a
correlation with it. Divider ratio is regulated by the setting of "Selected Transmission Speed Range" in
CFG_REG. In addition, bit clock is divided by 10N to generate PCLK, where N is a data width of TD and
RD in bytes.
LOCK signal (= ST[1]) is asserted when PLL completes all clock generation (i.e. bit clock, RCLK and
PCLK). CLK (source clock) and generated PCLK are multiplexed into PCLK which interface PHY and
LINK. Clock MUX shall switch these clocks with glitch-free manner triggered by LOCK or MODE signal
transition as described later in this chapter. During Dormant state, RCLK output is gated by LOCK
signal. And therefore, RCLK distribution is started after LOCK is asserted.
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6431
6432
6433
F.3.2 Clock Generation in Device
Figure F- 4 shows clock generation in Device.
MUX
(1/10N of bit clock)
Clock
Generated PCLK
PCLK
(MUX-ed)
RCLK
(received clcok)
Device
PLL
LOCK
From / To LINK
Selected Transmission Speed Range
(configured throgh PINIT)
(=ST[1])
MODE
bit clock
6434
6435
6436
6437
6438
6439
6440
6441
6442
6443
6444
6445
6446
6447
6448
(x15, x30, x60, or x120 of
RCLK)
Figure F- 4 : Clock Generation in Device
Device PLL shall generate bit clock by multiplying RCLK. MODE signal is asserted when Device
receives RCLK and exits from Dormant. Moreover, MODE signal is used as a trigger for starting PLL
lock. Before asserting MODE signal, PLL shall be configured by the setting of "Selected Transmission
Speed Range" in CFG_REG through CT[3:0] (= PINIT). Multiplier ratio is regulated by the setting of
"Selected Transmission Speed Range".
After bit clock generation, bit clock is divided by 10N to generate PCLK, where N is a data width of TD
and RD in bytes.
LOCK signal (= ST[1]) is asserted when PLL completes all clock generation (i.e. bit clock and PCLK).
Received RCLK and generated PCLK are multiplexed into PCLK which interface PHY and LINK. Clock
MUX shall switch these clocks with glitch-free manner triggered by LOCK or MODE signal transition as
described later in this chapter.
6449
6450
6451
6452
6453
F.4 I/F Timing Sequence
6454
6455
6456
F.4.1 Reset and Activation (Exiting from Dormant state)
On the I/F timing sequences described in this section, "D" in TDM, RDM, TDRM and RDTM rows mean
D-Symbol (in other words, TDM = 0 if "D" is indicated in TDM row). Moreover, "C0" in TD and RD rows
indicates MSB of (scrambled) CRC16, and "C1" does LSB of (scrambled) CRC16.
Figure F- 5 illustrates the I/F timing sequence of packet transfer in reset and activation for Host.
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DLSM
(LINK internal state)
Wakeup.Activate
Dormant
CLK
(= Source CLK)
Clock MUX latency (Implementation Specific)
NRST
RCLK output is masked
during LOCK=0
RCLK output
Generated
PCLK
PCLK
(MUX-ed)
(1)
MODE
PHY
LINK
TDM[0]
TD[0]
CT[3:0]
= PINIT/PCMD
D
0b
PINIT=0000b
(UHS156, Range A)
CT[5:4]
= TDS
EIDL
RDM[0]
RD[0]
D
0b
PCMD=0000b
(No Command)
(3)
STB
(4)
ST[0]
= DET
(2)
ST[1]
= LOCK
ST[5:4]
= RDS
6457
6458
6459
6460
6461
6462
6463
6464
6465
6466
6467
6468
6469
6470
6471
6472
EIDL
STB
Figure F- 5 : I/F Timing Sequence (Reset and Activation for Host)
(1) PHY shall be configured by CT[3:0] (=PINIT) at the last positive edge of PCLK before MODE
assertion. LINK asserts MODE signal when Host wants to start PHY activation. And then, Host PLL
starts bit clock generation according to PINIT setting. Note that LINK shall keep MODE signal
negated at least one PCLK period after it receives PCLK from PHY.
(2) When Host PLL completes all clock generation (i.e. bit clock, RCLK and PCLK), it asserts LOCK
signal. Then, Host starts to distribute RCLK to Device and PCLK is switched to the generated one
which can be used for valid symbol transfer across PHY-LINK I/F.
(3) After PCLK is certainly switched, LINK instructs PHY to send STB.L by setting TDS = STB, TDM[0]
= 0 and TD[0] = 0. Moreover, TDM[1] is also equal to 0 when width of TD is 2 bytes.
(4) Host can detect STB.L sent from Device with DET assertion or the following STB via RDS.
Figure F- 6 illustrates the I/F timing sequence of packet transfer in reset and activation for Device.
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DLSM
(LINK internal state)
Dormant
Wakeup.Activate
Clock MUX latency (Implementation Specific)
NRST
RCLK input
Generated
PCLK
RCLK input is masked during
MODE=LOCK=DET=0
PCLK
(MUX-ed)
(2)
MODE
PHY
LINK
TDM[0]
TD[0]
CT[3:0]
= PINIT/PCMD
D
0b
PINIT=0000b
(UHS156, Range A)
CT[5:4]
= TDS
EIDL
RDM[0]
RD[0]
D
0b
PCMD=0000b
(No Command)
STB
(1)
ST[0]
= DET
(3)
ST[1]
= LOCK
ST[5:4]
= RDS
6473
6474
6475
6476
6477
6478
6479
6480
6481
6482
6483
6484
6485
6486
6487
6488
6489
6490
6491
6492
6493
6494
6495
EIDL
STB
Figure F- 6 : I/F Timing Sequence (Reset and Activation for Device)
(1) Device detects STB.L sent from Host with DET assertion or the following STB via RDS. DET is used
for enabling RCLK.Rx and therefore, Device starts to receive RCLK. Note that RCLK.Rx does not
have Amplitude Detector because RCLK+/- are supposed to be shared with DAT0/1 of Legacy SD
I/F. So, RCLK.Rx is enabled by DET on D0.Rx and kept enable by MODE or LOCK after exiting
from Dormant.
(2) PHY shall be configured by CT[3:0] (= PINIT) until MODE assertion. LINK asserts MODE signal
after the PHY configuration using PINIT. Note that LINK shall keep MODE signal negated at least
one PCLK period after it receives PCLK from PHY. Then, Device PLL starts bit clock generation
according to the PINIT setting. At this time, LINK instructs PHY to send STB.L by setting TDS =
STB, TDM[0] = 0 and TD[0] = 0. Moreover, TDM[1] is also equal to 0 when width of TD is 2 bytes.
Device PHY needs to be capable of sending STB.L even if its PLL is not locked.
(3) When Device PLL completes all clock generation (i.e. bit clock and PCLK), it asserts LOCK signal.
Before LOCK assertion, PCLK is same as input RCLK. But after LOCK is asserted, PCLK is
switched to the generated one which can be used for valid symbol transfer across PHY-LINK I/F.
Before exiting from Dormant state, LINK of both Host and Device shall hold MODE to "0b" and CT[3:0]
(= PINIT) to the desired value in order to configure PHY initial parameter (i.e. Speed Range). Note that
PINIT shall be set to "0000b" as a default value just after power on.
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6496
6497
6498
6499
F.4.2 Packet Transfer in Fast Mode
In the examples described from Figure F- 7 to Figure F- 9, data width of TD and RD is 16 bits.
Figure F- 7 illustrates the I/F timing sequence of packet transfer in Fast Mode.
FD Mode Packet Transfer in Fast Mode <Tx side>
PCLK
Packet Gap shall be filled
with LIDL in Fast Mode
PHY
LINK
CT[5:4]
= TDS
VLD
TDM[0]
TD[7:0]
COM COM COM COM
D
D0
D
D2
D
D4
D
D6
D
C0
COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM
TDM[1]
TD[15:8]
LIDL LIDL LIDL SOP
D
D1
D
D3
D
D5
D
D7
D
C1
EOP LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL
CT[3:0]
= PCMD
0h (No Command)
ST[0]
= DET
unknown period
ST[1]
= LOCK
ST[2]
= PACK
ST[3]
= ERR
ST[5:4]
= RDS
VLD
RDM[0]
RD[7:0]
COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM
D
D0
D
D2
D
D4
D
D6
D
C0
COM COM COM
RDM[1]
RD[15:8]
LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL SOP
D
D1
D
D3
D
D5
D
D7
D
C1
EOP LIDL LIDL
FD Mode Packet Transfer in Fast Mode <Rx side>
PCLK
PHY
LINK
CT[5:4]
= TDS
VLD
TDM[0]
TD[7:0]
COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM
D
D0
D
D2
D
D4
D
D6
D
C0
COM COM COM COM
TDM[1]
TD[15:8]
LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL SOP
D
D1
D
D3
D
D5
D
D7
D
C1
EOP LIDL LIDL LIDL
CT[3:0]
= PCMD
0h (No Command)
ST[0]
= DET
unknown period
ST[1]
= LOCK
ST[2]
= PACK
ST[3]
= ERR
ST[5:4]
= RDS
6500
6501
6502
6503
6504
VLD
RDM[0]
RD[7:0]
COM COM COM COM COM
D
D0
D
D2
D
D4
D
D6
D
C0
COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM
RDM[1]
RD[15:8]
LIDL LIDL LIDL LIDL SOP
D
D1
D
D3
D
D5
D
D7
D
C1
SOP LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL
Figure F- 7 : I/F Timing Sequence (Packet Transfer in Fast Mode)
Note that the packet gap shall be filled with LIDL in Fast Mode as described in Section 5.4.
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6505
6506
6507
F.4.3 Packet Transfer in Low Power Mode
Figure F- 8 illustrates the I/F timing sequence of packet transfer in Low Power Mode.
FD Mode Packet Transfer Protocol in Low Power Mode <Tx side>
≥ T_EIDL_RECOVERY
PCLK
(2)
(1)
CT[5:4] EIDL
= TDS
PHY
LINK
T_EIDL_ENTRY
(2)
(3)
STB
VLD
TDM[0]
TD[7:0]
D
00h
COM COM COM COM COM
D
D0
D
D2
D
D4
D
D6
D
C0
COM
TDM[1]
TD[15:8]
D
00h
SYN SYN SYN SYN SOP
D
D1
D
D3
D
D5
D
D7
D
C1
EOP
CT[3:0]
= PCMD
0h (No Command)
ST[0]
= DET
unknown period
(4)
T_EIDL_GAP
(5)
STB
EIDL
D
01h
D
00h
D
00h
ST[1]
= LOCK
ST[2]
= PACK
ST[3]
= ERR
ST[5:4]
= RDS
EIDL
RDM[0]
RD[7:0]
D
00h
RDM[1]
RD[15:8]
D
00h
FD Mode Packet Transfer Protocol in Low Power Mode <Rx side>
PCLK
CT[5:4]
= TDS
EIDL
TDM[0]
TD[7:0]
D
00h
TDM[1]
TD[15:8]
D
00h
PHY
LINK
CT[3:0]
= PCMD
0h (No Command)
(1)
ST[0]
= DET
ST[1]
= LOCK
ST[2]
= PACK
(3)
(4)
ST[3]
= ERR
(5)
ST[5:4]
= RDS
EIDL
RDM[0]
RD[7:0]
D
00h
D
00h
COM COM COM COM COM
D
D0
D
D2
D
D4
D
D6
RDM[1]
RD[15:8]
D
00h
D
00h
SYN SYN SYN SYN SOP
D
D1
D
D3
D
D5
D
D7
(6)
STB
STB to EIDL
transition period
EIDL
D COM
C0
D
01h
D
- (don’t care)
D
00h
D EOP
C1
D
00h
D
- (don’t care)
D
00h
VLD
STB
(2)
6508
6509
6510
6511
6512
Receiving all-0 10bit symbol is treated as STB.L (RDS = STB & RD[0] = 0 & ERR = 0).
Receiving all-1 10bit symbol is treated as STB.H (RDS = STB & RD[0] = 1 & ERR = 0).
ERR is asserted when receiving all other symbols described above during RDS = STB.
Figure F- 8 : I/F Timing Sequence (Packet Transfer in Low Power Mode)
For Tx side:
(1) During TDS = EIDL, TDM = 00b and TD = 00h.
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6513
6514
6515
6516
6517
6518
6519
6520
6521
6522
6523
6524
6525
6526
6527
6528
6529
(2) During TDS = STB, TD[0] = 0 and TD[0] = 1 indicate STB.L and STB.H respectively.
(3) After elapsing of T_EIDL_RECOVERY in STB.L, Tx enters to VLD.
(4) After elapsing of T_EIDL_ENTRY (4 SI) in STB.H, Tx enters to EIDL.
(5) Tx shall be in EIDL at least T_EIDL_GAP before starting next transmission.
For Rx side:
(1) DET assertion is reflected to RDS transition from EIDL to STB after the implementation specific
period of sampling. After transition to STB, DET is not used until STB.H reception.
(2) Leading SYN LSS may be corrupted until symbol lock is acquired. During this period, ERR is
asserted because receiving data is neither all-zero nor all-one symbol.
(3) After symbol lock, Valid 8b/10b symbols are transferred from PHY to LINK with RDS = VLD.
(4) Between SOP and EOP, LINK shall monitor ERR to detect the PHY Receive Error.
(5) RDS may be unknown because Lane state is during transition from STB to EIDL. Before EIDL
transition, DET is required to be negated to prepare for next STB.L detection.
(6) After receiving STB.H, RDS transits from STB to EIDL.
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6530
6531
6532
F.4.4 Error Occurrence during Packet Transfer
Figure F- 9 illustrates the I/F timing sequence of error occurrence during packet transfer in Fast Mode.
Error Occurrence during Packet Transfer <Tx side>
PCLK
CT[5:4]
= TDS
VLD
TDM[0]
TD[7:0]
COM COM COM COM
D
D0
D
D2
D
D4
D
D6
D
C0
COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM
TDM[1]
TD[15:8]
LIDL LIDL LIDL SOP
D
D1
D
D3
D
D5
D
D7
D
C1
EOP LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL
PHY
LINK
CT[3:0]
= PCMD
(1)
0h (No Command)
ST[0]
= DET
unknown period
ST[1]
= LOCK
ST[2]
= PACK
ST[3]
= ERR
ST[5:4]
= RDS
VLD
RDM[0]
RD[7:0]
COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM
D
D0
D
D2
D
D4
D
D6
D
C0
COM COM COM
RDM[1]
RD[15:8]
LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL SOP
D
D1
D
D3
D
D5
D
D7
D
C1
EOP LIDL LIDL
Error Occurrence during Packet Transfer <Rx side>
PCLK
PHY
LINK
CT[5:4]
= TDS
VLD
TDM[0]
TD[7:0]
COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM
D
D0
D
D2
D
D4
D
D6
D
C0
COM COM COM COM
TDM[1]
TD[15:8]
LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL SOP
D
D1
D
D3
D
D5
D
D7
D
C1
EOP LIDL LIDL LIDL
CT[3:0]
= PCMD
0h (No Command)
ST[0]
= DET
unknown period
ST[1]
= LOCK
ST[2]
= PACK
ST[3]
= ERR
ST[5:4]
= RDS
6533
6534
6535
6536
6537
6538
6539
6540
6541
(3)
VLD
(4)
STB
VLD
RDM[0]
RD[7:0]
COM COM COM COM COM
D
D0
D
D2
Unknown
COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM
RDM[1]
RD[15:8]
LIDL LIDL LIDL LIDL SOP
D
D1
D
D3
Unknown
LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL
(2)
Figure F- 9 : I/F Timing Sequence (Error Occurrence during Packet Transfer)
(1) Packet Gap shall be filled with LIDL in Fast Mode.
(2) If Rx detects PHY Receive Error, ERR is asserted. And if the error is 8b/10b decoded error except
all-zero and all-one 10bit symbol, RDS and RD indicates STB.L. On the other hand, if the error is
8b/10b disparity error, RDS stays in VLD and RDM / RD indicates decoded data same as valid data
reception.
(3) Above mentioned ERR state continues until valid symbol reception is recovered.
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6542
6543
6544
6545
6546
6547
6548
6549
6550
6551
6552
6553
6554
6555
6556
6557
6558
6559
6560
6561
(4) If symbol lock is lost during ERR state, it can be recovered by receiving a series of COM. In this
case, LINK can detect packet loss by receiving LIDL without EOP
F.4.5 Loopback Control for DATA Burst Streaming
There are two possible locations for implementing the Loopback path for DATA Burst streaming.
(1) 8bit region (behind the 8b/10b decoder.
(2) 10bit region (before the 8b/10b decoder.
In both Loopback cases, PHY shall adjust the position of "COM" between loopbacked LSS and
generated LSS before switching Loopback Selector to keep the LSS boundary of transmitting data.
When implementing option (1), PHY does not need to take care of the disparity continuity when it
switches Loopback Selector.
When implementing option (2), PHY shall keep the disparity continuity when it switches Loopback
Selector. The rest of this section (Appendix F.4.5 ) explains what need to be done in order to implement
this option.
Figure F- 10 illustrates ensuring disparity continuity when PHY toggles Loopback Selector in 10bit
Loopback case.
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Just After Enabling Loopback path
Generated LSS
Serializer
Driver
Loopback
Selector
COMCOM+
COM-
DIDL1-
DIDL0+
DIDL1-
COM-
DIDL0+
EOP of bypassed
FCREQ
DIDL0- COM+ DIDL1+ COM- DIDL1- COM+ DIDL0- COM+ EOP+ COMAfter enabling Loopback
Before enabling Loopback
Loopback Selector
is toggled
Loopbacked LSS
LINK
Deserializer
Receiver
COM+
DIDL0-
DIDL1+
COM-
DIDL0+
COM-
COM-
8b/10b
Dec
Loopback path
LINK
“COM-” is expected to keep
the disparity continuity
(Disparity is controlled by other Device)
DIDL0+
8b/10b
Enc
(Disparity is calcutated at local 8b/10b Enc)
PHY
COM+ DIDL0- COM+ DIDL1- COM- DIDL0+ COM- DIDL1+ COM+ DIDL1-
Transmission Lane
Just After Disabling Loopback path
Generated LSS
Serializer
Driver
Loopback
Selector
COM+
COM-
DIDL1+
DIDL0+
DIDL0+
COMCOM-
DIDL1-
EDB of loopbacked
DATA Burst
DIDL1- COM+ DIDL1- COM+ DIDL0- COM+ DIDL1- COM+ EDB+ COMAfter disabling Loopback
Before disabling Loopback
Loopback Selector
is toggled
Loopbacked LSS
Deserializer
Receiver
DIDL0-
COM+
DIDL1+
COM-
DIDL1-
COM+
COM+
8b/10b
Dec
Loopback path
LINK
LINK
6562
6563
6564
6565
6566
6567
6568
6569
6570
6571
6572
“COM+” is expected to keep
the disparity continuity
(Disparity is controlled by other Device)
DIDL0-
8b/10b
Enc
(Disparity is calculated at local 8b/10b Enc)
PHY
COM+ DIDL0- COM+ DIDL1- COM- DIDL1+ COM+ DIDL0- COM+ DIDL1-
Transmission Lane
Figure F- 10 : Ensuring Disparity Continuity
In case of 10bit Loopback path, the disparity of loopbacked LSS is controlled by other Device. On the
other hand, the disparity of generated LSS is calculated at local 8b/10b Encoder. So, these LSSes may
have the opposite disparity. In this case, PHY is responsible for adjusting both loopbacked LSSes and
generated LSS to have the same disparity when it switches Loopback Selector. To realize this, PHY
shall compare disparities of "COM" and symbol types of the following "DIDL" (i.e. either "DIDL0" or
"DIDL1") between loopbacked DIDL LSS and generated DIDL LSS at Loopback Selector. And PHY may
need to swap the symbol type of "DIDL" between "DIDL0" and "DIDL1" according to the following rules.
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Loopback Selector rules:
Rule A. If both "COM" have the same disparity, Loopback Selector is toggled just after that "COM".
Rule B.
If both "COM" have the opposite disparity and both of the following "DIDL" are not the same
symbol type, Loopback Selector is toggled just after that "DIDL".
Rule C.
If both "COM" have the opposite disparity and both of the following "DIDL" are the same
symbol type, that "DIDL" is swapped its symbol type between "DIDL0" and "DIDL1" while its
disparity is kept. And Loopback Selector is toggled just after swapped "DIDL".
Figure F- 11 illustrates example of Loopback Selector operation (Rule A.) during Loopback entry.
Loopback
Selector
COM+
COM+
DIDL0-
COM+
DIDL0-
COM-
DIDL1-
COM+
DIDL1+
COM+
COMCOM-
DIDL0-
DIDL1+
DIDL0+
COM-
COM+
COM+
Selected LSS (= Generated LSS)
DIDL1-
COM+
DIDL0-
COM+
DIDL0-
COM-
DIDL1DIDL1-
DIDL1+
COM-
DIDL1+
Loopback
path
8b/10b
Encoder
Generated LSS
DIDL0+
6573
6574
6575
6576
6577
6578
6579
6580
6581
6582
6583
6584
Loopbacked LSS
Toggle Timing (Rule A.)
After Enabling Loopback path
Loopback
Selector
6585
6586
6587
6588
6589
6590
6591
6592
COM+
COM+
DIDL0-
COM-
DIDL1-
COM-
DIDL0+
COM+
Selected LSS
(= Generated LSS)
DIDL0+
COM+
DIDL0-
DIDL1-
DIDL1+
…
COM-
Selected LSS
(= Loopbacked LSS)
…
Toggle Timing
Figure F- 11 : Example of Loopback Selector Operation (Rule A.)
In this case, both "COM" have the minus disparity at Loopback Selector. So, toggle timing is just after
"COM-" in accordance with Rule A. described above.
Figure F- 12 illustrates example of Loopback Selector operation (Rule C.) during Loopback exit.
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Loopback
Selector
COM+
COM+
DIDL0-
COM+
DIDL0-
COM-
DIDL1-
COM+
DIDL1+
COM-
COM+
COM+
COM-
DIDL0-
DIDL0DIDL0+
DIDL1-
COM+
COM-
Selected LSS (= Loopbacked LSS)
DIDL0+
COM+
DIDL0-
COM+
DIDL1+
COM-
DIDL1DIDL1-
DIDL1+
COM-
DIDL1+
Loopback
path
8b/10b
Encoder
Generated LSS
“DIDL0+” will be replaced with “DIDL1+”
in Loopback Selector
Loopbacked LSS
Toggle Timing (Rule C.)
After Disabling Loopback path
Loopback
Selector
6594
6595
6596
6597
6598
6599
6600
6601
6602
6603
6604
6605
6606
COM+
COM+
DIDL0-
COM-
DIDL1-
COM-
DIDL0+
COM+
Selected LSS
(= Loopbacked LSS)
DIDL1+
COM+
DIDL0-
DIDL1-
DIDL1+
…
COM-
Selected LSS
(= Generated LSS)
…
Toggle Timing
Figure F- 12 : Example of Loopback Selector Operation (Rule C.)
In this case, both "COM" have the opposite disparity and both of the following "DIDL" are "DIDL0" at
Loopback Selector. So, "DIDL0+" is replaced with "DIDL1+" and Loopback Selector is toggled just after
replaced "DIDL1+" in accordance with Rule C. described above.
Note that Loopback latency of PHY can be minimized by 10bit Loopback path and that path can be
commonly used for both Data Burst Streaming and Loopback Test, although it is required to ensure the
disparity continuity.
Figure F- 13 illustrates the I/F timing sequence of Loopback control for DATA Burst streaming.
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DLSM
(LINK internal state)
Active
.Control
Active.Stream
PCLK
CT[5:4]
= TDS
TDM[0]
TD[7:0]
D
C0
COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM
TDM[1]
TD[15:8]
D
C1
EOP DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL
CT[3:0] 0000b (No
= PCMD Command)
PHY
LINK
VLD
(1)
0001b (Enter to
Loopback mode)
0011b (Exit from
Loopback mode)
0000b
(No Command)
0000b
(No Command)
ST[0]
= DET
ST[1]
= LOCK
ST[2]
= PACK
(2)
≤ 20SI
≤ 20SI
(4)
ST[3]
= ERR
ST[5:4]
= RDS
6607
6608
6609
6610
6611
6612
6613
6614
6615
6616
6617
6618
6619
6620
6621
6622
6623
(3)
VLD
RDM[0]
RD[7:0]
D
D
COM COM COM COM COM COM COM COM COM COM COM D508 D510
D
C0
COM COM COM COM COM COM COM COM COM COM COM COM
RDM[1]
RD[15:8]
D
D
DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL D509 D511
D
C1
EOP EDB EDB DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL
Figure F- 13 : I/F Timing Sequence (Loopback Control for DATA Burst Streaming)
(1) LINK transits from Active.Control to Active.Stream when it completes FCREQ bypassing. At this
time, LINK starts to send DIDL LSS and PCMD is set to "0001b" to enter to Loopback mode.
(2) PHY is responsible for enabling its Loopback path considering continuity of transmitting data in
terms of running disparity and LSS boundary before and after enabling Loopback path. PACK is
asserted as an acknowledgement of PCMD when Loopback path is certainly enabled. Note that
duration of PCMD for "Enter to Loopback mode" shall be asserted within 20 SI. Even after enabling
Loopback path, LINK shall monitor RD signals to detect EDB as a trigger for disabling Loopback
path.
(3) After LINK detects EDB, PCMD is set to "0011b" to exit from Loopback mode.
(4) PHY is responsible for disabling its Loopback path considering continuity of transmitting data, same
as in the case of enabling Loopback path. PACK is asserted when Loopback path is certainly
disabled. Note that duration of PCMD for "Exit from Loopback mode" shall be asserted within 20 SI.
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6624
6625
F.4.6 Switching of Duplex Mode
Figure F- 14 illustrates the I/F timing sequence of switching from FD mode to 2L-HD mode.
Switching from FD to HDIN Mode
(LINK internal state) DLSM
Active
.Control
Active.Recv.RecvHD
Active.Recv.SwtHD
TDR signals
(for Non-default Tx)
TD signals
(for Default Tx)
PCLK
CT[5:4]
= TDS
VLD
TDM[0]
TD[7:0]
D
C0
COM
TDM[1]
TD[15:8]
D
C1
EOP
OFF
D
01h
D
00h
D
00h
(1)
CT[7:6]
= TDRS
OFF
D
00h
TDRM[0]
TDR[7:0]
TDRM[1]
TDR[15:8]
CT[3:0]
= PCMD
D
00h
(2)
No Command
(0000b)
Enter to HDIN
(0101b)
No Command
(0000b)
ST[0]
= DET
PHY
LINK
STB
T_EIDL_ENTRY
unknown period
DET is stable only when EIDL
and STB.L on Default Rx
ST[2]
= PACK
ST[1]
= LOCK
T_EIDL_ENTRY
≤ T_DIR_SWITCH
RDT signals
(for Non-default Rx)
RD signals
(for Default Rx)
ST[3]
= ERR
ST[5:4]
= RDS
VLD
RDM[0]
RD[7:0]
COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM
D
D0
RDM[1]
RD[15:8]
DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIR
D
D2
ST[7:6]
= RDTS
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
VLD
STB
OFF
(3)
RDTM[0]
RDT[7:0]
RDTM[1]
RDT[15:8]
DIR SDB SDB SOP
DIR
D
00h
COM COM COM COM COM COM COM COM COM COM
D
00h
DIR
DIR
DIR
DIR
DIR
DIR
DIR SDB SDB SOP
(4)
D
D1
D
D3
(5)
Switching from FD to HDOUT Mode
(LINK internal state) DLSM
Active.Trans.SwtHD
Active.Trans.WaitRDY
Active.Trans.TransHD
TDR signals
(for Non-default Tx)
TD signals
(for Default Tx)
PCLK
= RCLK/2
CT[5:4]
= TDS
TDM[0]
TD[7:0]
TDM[1]
TD[15:8]
VLD
DIR
DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIDL DIR
CT[7:6]
= TDRS
DIR
DIR
DIR
D
D4
D
D2
DIR
DIR
DIR
DIR
DIR
D
D6
COM COM COM COM COM COM COM COM COM COM
D
D1
D
D5
DIR SDB SDB SOP
D
D3
D
D7
DIR
DIR
DIR
DIR
DIR
DIR
(3)
(5)
Enter to HDOUT
(0110b)
PHY
ST[0]
= DET
DIR
DIR SDB SDB SOP
VLD
T_EIDL_RECOVERY
D
00h
No Command
(0000b)
DIR
(4)
D
00h
TDRM[1]
TDR[15:8]
DIR
STB
OFF
TDRM[0]
TDR[7:0]
CT[3:0]
= PCMD
LINK
D
D0
COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM
DIR
DIR
DIR
DIR
No Command
(0000b)
DIR
(6)
unknown period
ST[2]
= PACK
DET is stable only when EIDL
and STB.L on Default Rx
(2)
ST[1]
= LOCK
T_EIDL_ENTRY
> T_DIR_SWITCH
N_LSS_DIR * 8
≤ T_DIR_SWITCH
6626
6627
6628
RDT signals
(for Non-default Rx)
RD signals
(for Default Rx)
ST[3]
= ERR
ST[5:4]
= RDS
VLD
STB
STB to EIDL
transition period
RDM[0]
RD[7:0]
D
D2
D
C0
COM
D
01h
D
- (don’t care)
D
00h
RDM[1]
RD[15:8]
D
D3
D
C1
EOP
D
00h
D
- (don’t care)
D
00h
ST[7:6]
= RDTS
OFF
EIDL
(1)
OFF
RDTM[0]
RDT[7:0]
D
00h
RDTM[1]
RDT[15:8]
D
00h
Figure F- 14 : I/F Timing Sequence (Switching from FD to HDIN or HDOUT)
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6629
6630
6631
6632
6633
6634
6635
6636
6637
6638
6639
6640
6641
6642
6643
6644
6645
6646
6647
6648
6649
6650
6651
6652
6653
6654
6655
6656
6657
6658
6659
For data receiver (Switching from FD to HDIN):
(1) EOP of FCRDY is a trigger for direction switch
(2) Just after transmitting FCRDY, LINK transits from Active.Control to Active.Recv.SwtHD, and it
instructs PHY to start direction switch from default Tx (TD) to non-default Rx (RDT) by setting
PCMD = "0101b" after transmitting STB.H for the duration of T_EIDL_ENTRY (= 4 SI).
(3) PHY completes the direction switch within the period of T_DIR_SWITCH and notifies LINK of its
completion by PACK. And the state of non-default Rx (RDTS) transits from OFF to STB to prepare
for receiving valid symbols.
(4) Non-default Rx (RDT) acquires symbol lock. LINK transits to Active.Recv.RecvHD and starts to
receive DIR LSS via both data Lanes.
(5) LINK starts to receive DATA Burst via both data Lanes.
For data initiator (Switching from FD to HDOUT):
(1) EOP of FCRDY is a trigger for direction switch
(2) Just after receiving FCRDY, LINK transits from Active.Trans.WaitRDY to Active.Trans.SwtHD after
the duration of T_EIDL_ENTRY. And before starting direction switch, LINK waits for more than
T_DIR_SWITCH to avoid a contention between both sides of Tx in a same Lane. During this period,
RDS transits from STB to EIDL.
(3) After the elapse of more than T_DIR_SWITCH, LINK starts to transmit DIR LSS via default Tx. LINK
instructs PHY to start direction switch from default Rx (RD) to non-default Tx (TDR) by setting
PCMD = "0110b". After receiving the PCMD, RDS transits to OFF.
(4) PHY completes the direction switch within the period of T_DIR_SWITCH and notifies LINK of its
completion by PACK. After completing direction switch, LINK instructs PHY to transmit STB.L for
T_EIDL_RECOVERY to prepare for transmitting valid symbols.
(5) After the elapse of T_EIDL_RECOVERY in STB.L, LINK transits to Active.Trans.TransHD and starts
to transmit at least the predetermined number (= N_LSS_DIR * 8) of DIR LSS for each Lane to
acquire symbol lock.
(6) LINK starts to transmit DATA Burst via both data Lanes.
Figure F- 15 illustrates the I/F timing sequence of switching from 2L-HD mode to FD mode.
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Switching from HDIN to FD Mode
(LINK internal state) DLSM
Active.Recv
.SwtFD
Active.Recv.RecvHD
Active.Control
TDR signals
(for Non-default Tx)
TD signals
(for Default Tx)
PCLK
CT[5:4]
= TDS
VLD
T_EIDL_RECOVERY
TDM[0]
TD[7:0]
D
00h
TDM[1]
TD[15:8]
D
00h
(4)
COM COM COM COM COM COM COM COM COM COM COM COM
DIR
CT[7:6]
= TDRS
OFF
TDRM[0]
TDR[7:0]
D
00h
TDRM[1]
TDR[15:8]
Exit from HDIN
(RxàDefault Tx)
No Command
DIR
DIR
DIR
DIR
DIR
DIR
DIR LIDL LIDL LIDL LIDL
(5)
(7)
D
00h
(3)
CT[3:0]
= PCMD
ST[0]
= DET
PHY
LINK
STB
OFF
No Command
unknown period
ST[2]
= PACK
(2)
ST[1]
= LOCK
T_EIDL_ENTRY
≤ T_DIR_SWITCH
> T_DIR_SWITCH
RDT signals
(for Non-default Rx)
RD signals
(for Default Rx)
ST[3]
= ERR
ST[5:4]
= RDS
VLD
RDM[0]
RD[7:0]
D
D508
D
C0
COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM
RDM[1]
RD[15:8]
D
D510
D
C1
EOP EDB EDB DIR
ST[7:6]
= RDTS
RDTM[0]
RDT[7:0]
D
D509
RDTM[1]
RDT[15:8]
D
D511
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
VLD
STB
STB to EIDL
transition period
D
C0
COM COM COM
D
01h
D
- (don’t care)
D
00h
D
C1
EOP EDB EDB
D
00h
D
- (don’t care)
D
00h
DIR
EIDL
DIR
DIR
DIR
DIR
DIR DIDL DIDL DIDL DIDL DIDL DIDL
(6)
OFF
(1)
Switching from HDOUT to FD Mode
(LINK internal state) DLSM
Active.Trans
.TransHD
Active.Trans.SwtFD
Active.Trans.WaitSTAT
TDR signals
(for Non-default Tx)
TD signals
(for Default Tx)
PCLK
= RCLK/2
CT[5:4]
= TDS
D
C0
COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM COM
TDM[1]
TD[15:8]
D
C1
EOP EDB EDB DIR
CT[7:6]
= TDRS
VLD
TDRM[0]
TDR[7:0]
D
C0
COM COM COM
TDRM[1]
TDR[15:8]
D
C1
EOP EDB EDB
CT[3:0]
= PCMD
No Command
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
STB
D
01h
DIR
DIR
DIR
DIR
DIR
DIR
DIR DIDL DIDL DIDL DIDL DIDL DIDL DIDL
(5)
D
00h
D
00h
(2)
(1)
DIR
OFF
T_EIDL_ENTRY
Exit from HDOUT
(TxàDefault Rx)
No Command
ST[0]
= DET
PHY
LINK
VLD
TDM[0]
TD[7:0]
unknown period
ST[2]
= PACK
ST[1]
= LOCK
T_EIDL_ENTRY
≤ T_DIR_SWITCH
6660
6661
RDT signals
(for Non-default Rx)
RD signals
(for Default Rx)
ST[3]
= ERR
ST[5:4]
= RDS
RDM[0]
RD[7:0]
RDM[1]
RD[15:8]
VLD
STB
OFF
(3)
D
00h
COM COM COM COM COM COM COM COM COM COM COM
D
00h
DIR
ST[7:6]
= RDTS
OFF
RDTM[0]
RDT[7:0]
D
00h
RDTM[1]
RDT[15:8]
D
00h
DIR
DIR
(4)
DIR
DIR
DIR
DIR
DIR LIDL LIDL LIDL
(6)
Figure F- 15 : I/F Timing Sequence (Switching from HDIN or HDUT to FD)
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For data receiver (Switching from HDIN to FD):
(1) EDB of DATA Burst is a trigger for direction switch.
(2) Just after receiving EDB, LINK receives DIR LSS as an in-band direction switch request and transits
from Active.Recv.RecvHD to Active.Recv.SwtFD after the duration of T_EIDL_ENTRY (= 4 SI). In
addition, before starting direction switch, LINK waits for more than T_DIR_SWITCH to avoid a
contention between both sides of Tx in a same Lane. During this period, RDTS transits from STB to
EIDL.
(3) After the elapse of more than T_DIR_SWITCH, LINK instructs PHY to start direction switch from
non-default Rx (RDT) to default Tx (TD) by setting PCMD = "0111b". After receiving the PCMD,
RDTS transits to OFF.
(4) PHY completes the direction switch within the period of T_DIR_SWITCH and notifies LINK of its
completion by PACK. After completing the direction switch, LINK instructs PHY to transmit STB.L for
T_EIDL_RECOVERY to prepare for transmitting valid symbols.
(5) After the elapse of T_EIDL_RECOVERY in STB.L, LINK starts to transmit DIR LSS as an in-band
direction switch acknowledge until it receives DIDL LSS.
(6-7) After receiving DIDL via default Rx (RD), LINK transits to Active.Control and starts to transmit LIDL
via default Tx (TD) in Fast Mode or EIDL in Low Power Mode.
For data initiator (Switching from HDOUT to FD):
(1) EDB of DATA Burst is a trigger for Duplex mode switching. And LINK starts to transmit DIR LSS via
default Tx (TD) as an in-band direction switch request.
(2) Just after transmitting EDB, LINK transits from Active.Trans.TransHD to Active.Trans.SwtFD. LINK
instructs PHY to start direction switch from non-default Tx (TDR) to default Rx (RD) by setting
PCMD = "0111b" after transmitting STB.H for the duration of T_EIDL_ENTRY.
(3) PHY completes direction switch within the period of T_DIR_SWITCH and notifies LINK of its
completion by PACK. And the state of default Rx (RDS) transits from OFF to STB to prepare for
receiving valid symbols.
(4) Default Rx (RD) acquires symbol lock and LINK receives DIR LSS as an in-band direction switch
acknowledgement.
(5) After completing DIR handshake, LINK transits to Active.Trans.WaitSTAT and starts to transmit
DIDL LSS until it receives STAT MSG.
(6) After transmitting DIDL LSS, LINK receives LIDL in Fast Mode or EIDL in Low Power Mode.
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F.4.7 Entering to Dormant State
Figure F- 16 illustrates the I/F timing sequence of entering to Dormant state. Refer to Section 5.4.3 for
details of Dormant state entry.
Host Sequence for Entering to Dormant
DLSM
Active.Control
(LINK internal state)
Dormant
CLK
(= Source CLK)
Clock MUX latency (Implementation Specific)
NRST
RCLK output is masked
during MODE=LOCK=0
RCLK output
Generated
PCLK
PCLK
(MUX-ed)
(4)
MODE
CT[3:0]
= PINIT/PCMD
PHY
LINK
PCMD=0000b
(No Command)
(2)
CT[5:4]
= TDS
PINIT=0000b
(UHS156, Range A)
VLD
STB
EIDL
TDM[0]
TD[7:0]
COM COM COM
D
01h
D
00h
TDM[1]
TD[15:8]
LIDL LIDL LIDL
D
00h
D
00h
ST[0]
= DET
(5)
ST[1]
= LOCK
(3)
ST[5:4]
= RDS
STB
STB
(transision)
EIDL
COM COM COM COM COM COM COM COM COM COM
D
01h
D
(unknown)
D
00h
EOP LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL
D
00h
D
(unknown)
D
00h
(1)
RDM[0]
RD[7:0]
D
C0
RDM[1]
RD[15:8]
D
C1
VLD
> T_DMT_ENTRY
H-1
H-2
Device Sequence for Entering to Dormant
DLSM
(LINK internal state)
Active.Control
Dormant
Clock MUX latency (Implementation Specific)
NRST
RCLK input is masked during
MODE=LOCK=DET=0
RCLK input
Generated
PCLK
PCLK
(MUX-ed)
(4)
PHY
LINK
MODE
CT[3:0]
= PINIT/PCMD
PCMD=0000b
(No Command)
CT[5:4]
= TDS
PINIT=0000b
(UHS156, Range A)
(3)
VLD
STB
EIDL
TDM[0]
TD[7:0]
COM COM COM COM COM COM COM COM COM COM
D
01h
D
00h
TDM[1]
TD[15:8]
EOP LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL LIDL
D
00h
D
00h
ST[0]
= DET
(1)
(5)
ST[1]
= LOCK
(2)
ST[5:4]
= RDS
VLD
RDM[0]
RD[7:0]
COM COM COM COM COM
RDM[1]
RD[15:8]
LIDL LIDL LIDL LIDL LIDL
STB
STB
(transision)
EIDL
D
01h
D
(unknown)
D
00h
D
00h
D
(unknown)
D
00h
<< T_DMT_ENTRY
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D-1
D-2
Figure F- 16 : I/F Timing Sequence (Entering to Dormant State)
For Host:
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(1) Host receives GO_DORMANT_STATE CCMD issued from Device (Condition H-1).
(2) Host sets its TDS to STB and TD to 0001h respectively. Then Host sets its TDS to EIDL.
(3) RDS of Host becomes EIDL (Condition H-2). Then both Condition H-1 and H-2 are satisfied.
(4) After the elapse of more than T_DMT_ENTRY from the time detecting EIDL on RDS (Condition H2), Host instructs its PHY to enter to Dormant state by negating MODE signal. And Host PHY starts
to switch PCLK from generated one to CLK (source clock).
(5) When PCLK is certainly switched, Host PHY negates LOCK signal and stops RCLK distribution to
Device(s). Note that RCLK output is supposed to be masked when LOCK = 0.
For Device:
(1) Device transmits GO_DORMANT_STATE CCMD (Condition D-1).
(2) RDS of Device becomes EIDL (Condition D-2). Then both Condition D-1 and D-2 are satisfied.
(3) Device sets its TDS to STB and TD to 0001h respectively. Then Device sets its TDS to EIDL.
(4) After the elapse of sufficiently less than T_DMT_ENTRY from the timing detecting EIDL on RDS
(Condition D-2), Device instructs its PHY to enter to Dormant state by negating MODE signal to
avoid an unexpected stop of RCLK distribution from Host. And Device PHY starts to switch PCLK
from generated one to received RCLK.
(5) When PCLK is certainly switched, Device PHY negates LOCK signal and stops RCLK input. Note
that RCLK input is supposed to be enabled with the signal generated by (DET || MODE || LOCK).
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Appendix G (Informative) :
Host's Operation in Detecting Timeout
G.1 P2P CMD of UHS-II Native Protocol
Figure G- 1 illustrates Host's operation when it detects timeout in case of P2P CMD for UHS-II native
protocol.
Start
(detecting timeout)
Issue
TRANS_ABORT
to the target
See Note (1)
No
Success to
receive RES of
TRANS_ABORT?
Yes
Read ST_REG
Other method for recovery
(e.g. I/F power cycle)
End
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Note:
(1) Host can repeat to issue TRANS_ABORT when it detects timeout again.
(2) Host can issue TRANS_ABORT for all connected Devices for debugging.
(3) Error identifiers in the intermediate Device are cleared if it responds to the P2P commands
other than TRANS_ABORT.
Figure G- 1 : Host's Operation for Timeout in Case of P2P CMD for UHS-II Native Protocol
When Host detects timeout, Host should issue TRANS_ABORT CCMD to terminate the outstanding
transaction. If it succeeds to receive RES of TRANS_ABORT, it should read error identifiers and status
of Device indicated in Device's ST_REG.
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G.2 Broadcast CCMD
Figure G- 2 illustrates Host's operation when it detects timeout in case of Broadcast CCMD.
Start
(detecting timeout)
Reissue the same
broadcast CCMD
No
See Note (2)
Success to
receive the same broadcast
CCMD from Device?
See Note (1)
Yes
Other method for recovery
(e.g. I/F power cycle)
End
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Note:
(1) Host can repeat to issue the same broadcast CCMD when it detects timeout again.
(2) Host can issue TRANS_ABORT for all connected Devices for debugging before other
method for recovery.
Figure G- 2 : Host's Operation for Timeout in Case of Broadcast CCMD
Different from the case of P2P CMD, Host also detects timeout when the broadcast CCMD includes
COND_ERR, ARG_ERR, or GEN_ERROR described in Table 6-4. This is because Device does not
transmit the broadcast CCMD any more when it detects at least one of these errors.
Therefore, Host should reissue the same broadcast CCMD to recover from the illegal situation. If Host
can receive the RES after some times trial, it can make judgment that the system recovers from the
illegal situation. Note that in case of FULL_RESET CCMD and GO_DORMANT_STATE CCMD, another
method for recovery should be used instead of issuing retry command. Host should execute power
cycle if FULL_RESET sequence is not completed.
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G.3 CMD of SD-TRAN
Figure G- 3 illustrates Host's operation when it detects timeout in case of CMD for SD-TRAN. Note that
the encapsulated CMD12 is required when Host detects timeout during data transaction.
Start
(detecting timeout)
Issue
TRANS_ABORT
No
Note: Host can repeat to issue
TRANS_ABORT when it
detects timeout again.
Success to
receive RES of
TRANS_ABORT?
Yes
Read ST_REG
No
Success to
receive RES of
Read ST_REG?
Yes
The outstanding
CMD is DCMD?
Other method for recovery
(e.g. I/F power cycle)
No
Yes
Issue CMD12
Success to
receive RES with
NACK = 0 of
CMD12?
Yes
No
Other method for recovery
(e.g. I/F power cycle)
End
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Figure G- 3 : Host's Operation for Timeout in Case of SD-TRAN
The Last Page
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