Analog IC Design – Cadence Tools (Lab 01)
Name: Ali Mohamed Hanafi
PART 1: Low Pass Filter Simulation (LPF)
1- Transient analysis:
1) Design a first order low pass filter that has R = 1kΩ and 1ns time
constant.
Figure 1:First order low pass filter
2) Apply a square wave input with V1=0 ,V2=Vdd, Tclk = Period =
25ns(from link), with Thigh = Pulse Width =Tclk/2 and Trise = Tfall =
Tclk/200.
Figure 2 vpulse properties
3) Report transient analysis results for two periods (use max time
step = Tclk/100).
Figure 3 transient analysis
4) Calculate rise and fall time (10% to 90%) using Cadence
calculator expressions. Export the expressions to adexl.
5) Compare simulation with analytical results in a table.
Analytical results
Thigh=Tlow=1.098 ns
Simulation results
Thigh=Tlow=1.103 ns
Analytical derivation: (first order system)
𝑉𝑂𝑈𝑇 (𝑡) = 𝑉𝑓𝑖𝑛𝑎𝑙 + (𝑉𝑖𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙 )𝑒 −𝑡/𝑅𝐶
Find the time t1 when VOUT = 0.1Vdd:
0.1𝑉𝐷𝐷 = 𝑉𝐷𝐷 (1 − 𝑒 −𝑡1/𝑅𝐶 )
𝑒 −𝑡1/𝑅𝐶 = 0.9
𝑡1 = −𝑅𝐶 ln(0.9)
Find the time t2 when VOUT = 0.9Vdd:
0.9𝑉𝐷𝐷 = 𝑉𝐷𝐷 (1 − 𝑒 −𝑡2/𝑅𝐶 )
𝑒 −𝑡2/𝑅𝐶 = 0.1
𝑡2 = −𝑅𝐶 ln(0.1)
Calculate the rise time tr = t2 - t1:
0.9
𝑡𝑟 = −𝑅𝐶 ln(0.1) − (−𝑅𝐶 ln(0.9)) = 𝑅𝐶 ln ( ) = 𝑅𝐶 ln(9) ≈ 2.2𝑅𝐶
0.1
tr=1.098 ns
(due to the symmetric in charging and discharging the capacitor so
tlow=t rise=1.098 ns)
6) Do parametric sweep for R = 1: 1: 5kΩ . Report overlaid results.
Comment on the results.
Figure 4 voltage transient
Figure 5 current transient
. The Voltage Transient: A higher resistance (moving toward the blue
curve) creates more curvature. It takes more time for the charge carriers
to charge the capacitor through the resistive path Therefore, the rise and
fall times are increased.
. The Current Transient: The red curve has the highest peak current. This
means it has the lowest resistance R. Because the flow is very large and
minimally restricted, it fills the fastest (which aligns perfectly with the red
curve in the first graph rising the fastest).
-The blue curve has the lowest peak current. The higher resistance
severely limits the initial flow, resulting in the slowest charging time.
- The Exponential Decay due to the capacitor fills with charge, its internal
voltage VOUT builds up. The accumulated charge generates an opposing
potential difference that decreases the charging current. The flow of
current slows down, eventually decaying to exactly zero once the
capacitor is fully charged and in steady-state.
Figure 6 T Fall versus R
Figure 7 T Rise vs R
-As R increases from 1kΩ to 5kΩ, the rise and fall times will linearly
increase. Physically, a larger resistor creates more collisions for the
charge carriers, limiting the current that is available to charge the
capacitor. Consequently, it takes more time to reach 90% of the input
voltage.
2- Ac Analysis:
1) Report Bode Plot (magnitude and phase) for the previous LPF.
Figure 8 magnitude v
Figure 9 magnitude (db)
Figure 10 phase
2) Calculate DC gain and 3dB bandwidth using Cadence calculator
expressions. Export the expressions to adexl.
3) Compare simulation with analytical results in a table.
Analytical result
BW=318.3M
Simulation result
BW=317.6
Analytical Expression for Bandwidth:
Step1:The continuous-time transfer function of a simple RC low-pass
filter is:
1
1
|𝐻(𝑗𝜔)| =
=
√1 + (𝜔𝑅𝐶)2 √2
Step 2: To find the 3dB bandwidth, we evaluate the magnitude and set
it to 1/root(2):
1
1
|𝐻(𝑗𝜔)| =
=
√1 + (𝜔𝑅𝐶)2 √2
Step 3: Solve for the 3dB angular frequency:
1
1 + (𝜔3𝑑𝐵 𝑅𝐶)2 = 2 ⟹ (𝜔3𝑑𝐵 𝑅𝐶)2 = 1 ⟹ 𝜔3𝑑𝐵 =
𝑅𝐶
Therefore
𝑓3𝑑𝐵 =
1
2𝜋𝑅𝐶
4) Do parametric sweep for R = 1,10,100,1000kΩ . Report overlaid
results. Comment on the results.
Figure 11 mag(v) mag(db)
Figure 12 band width versus poles
1.The Passband (Low Frequencies)
-On the left side of the figure 11 (10^1 to roughly 10^4 Hz), all curves sit
flat at 1V.
-Physically: At these slow alternating frequencies, the charge carriers
have chance of time to pass the resistor and fill up the capacitor before
the voltage direction reverses. Because it fully charges, the capacitor
effectively acts as an open circuit to these slow signals.
2. The Stopband (High Frequencies)
On the far-right side of the graph, all curves drop off toward V≈0.
-Physically: The charge cannot get through the resistor fast enough to
build up any charge on the capacitor. The capacitor acts almost like a
short circuit to ground, killing the output voltage.
3. The Parametric Sweep (The Cutoff Shift)
-The curves represent a parametric sweep, most likely sweeping the
resistor R from a high value to a low value.
-The cutoff frequency F(3db) is the point where the output voltage drops
to roughly 0.707V (which correlates to half power, or -3dB). This is the
exact frequency where the capacitor's opposition to flow C becomes
equal to the resistor's opposition to flow R.
•
The Light Blue Curve (Lowest Cutoff): This curve starts dropping
early, around 10^5 Hz. This corresponds to the highest resistance
in your sweep. The resistor is so big, making the capacitor too slow
to react to even slow signals.
•
The Red Curve (Highest Cutoff): This curve maintains a 1V output
all the way up to roughly10^8 Hz. This corresponds to the lowest
resistance. current can rush in and out, allowing the capacitor to
track the signals, before it finally fails to keep up.
PART 2: MOSFET Characteristics
Figure 13 design of NMOS and PMOS
1-ID vs VGS:
Plot ID − VGS characteristics for NMOS and PMOS devices. Set VDS =
VDD, and VGS = 0: 10m: VDD. Use VDD = 1.2V for 130nm technology and
VDD = 1.8V for 180nm technology.
Plot the results overlaid for the following:
• Short channel device: L = 200nm
• Long channel device: L = 2μm.
• W=21L (from link)
Figure 14 ID for NMOS short(red),long(yellow)
Figure 15ID for PMOS short(red),long(yellow)
2) Comment on the differences between short channel and long
channel results.
• Which one has higher current? Why?
-The long channel device produces a higher current at maximum Vgs.
-Because the lateral electric field driving the current from source to drain
is calculated by dividing the voltage by the physical distance (E =
Vds/L).This physical distance is tiny, creating a large, concentrated
electric field. The high lateral electric field causes severe lattice
scattering, leading the carrier velocity to saturate at a maximum limit.
-Even though both devices have the same W/L ratio, the short channel
device's current has more curvature because its carriers cannot move
any faster. In the long channel device, the field is stretched over a much
larger distance, the carriers do not collide as violently, and they avoid
hitting this speed limit.
• Is the relation linear or quadratic? Why?
1-Long Channel: Quadratic
-Because it is affected by two increasing factors velocity and amount of
charge.
-𝐼𝐷 ∝ (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 .
2-Short Channel: Linear
-Because the current increases in direct, straight-line proportion to the
amount of charge you add.
-𝐼𝐷 ∝ (𝑉𝐺𝑆 − 𝑉𝑇𝐻 ).
3) Comment on the differences between NMOS and PMOS.
• Which one has higher current? Why? NMOS transistors have higher
current than PMOS transistors, for the exact same physical dimensions
W and L and the exact same applied voltages, Because the mobility of
electron larger than of holes.
•What is the ratio between NMOS and PMOS currents at Vgs= Vdd?
-For short channel, the ratio between NMOS and PMOS is
175.4/60.85=2.88
-For long channel, the ratio between NMOS and PMOS is
234.48/57.65=4.067
Which one is more affected by short channel effects?
•
The NMOS device, A primary short-channel effect is velocity
saturation, which occurs when charge carriers accelerate so fast
under a strong electric field, because electrons mobility accelerate
more compared to holes, they reach this destructive speed limit
at much lower electric field.
2. gm vs VGS
1) Plot gm vs VGS for NMOS device. Set VDS = VDD, and VGS = 0: 10m: VDD. Plot
the results:
Figure 16 NMOS gm vs vgs short(red),long(yellow)
Figure 17 PMOS gm vs Vgs long (green) , short (blue)
- Does gm increase linearly? Why? Yes, in NMOS it increases linearly
in the long-channel device (yellow curve).
-Because in a long channel, the lateral electric field is relatively weak,
so the charge carriers are traveling well below their maximum speed
limit. As you increase the vertical field Vgs, you simultaneously pull
more carriers into the channel and increase their velocity. This causes
the total current to grow quadratically:𝐼𝐷 ∝ (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 .
- Transconductance is the rate of change (derivative) of the current with
respect to the gate voltage:𝑔𝑚 =
𝜕𝐼𝐷
𝜕𝑉𝐺𝑆
.(the derivative of quadratic
function is linear function)
-Does gm saturate? Why?
-Yes, in NMOS it strongly saturates in the short-channel device (red
curve).
-Because the electric field is so intense that the electrons crash into the
silicon lattice and hit their terminal velocity (velocity saturation). Once
they are moving at this speed limit, increasing the gate voltage vgs can
only pull more carriers into the channel, it can no longer make them
travel any faster, so the current grows in a linear:𝐼𝐷 ∝ (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )
3. ID vs VDS
1) Plot ID − VDS characteristics for NMOS device. Set VDS = 0: 10m:
VDD, and VGS = 0: 0.2:VDD (nested sweep). Plot the results overlaid
for the following:
Figure 18first graph is NMOS, second is PMOS
2) Comment on the differences between short channel and long
channel results.
. Which one has higher current? Why?
-The long-channel device has higher current.
-Because the short-channel device suffers from velocity saturation. The
distance L is so small, the lateral electric field Vds/L is large, the high
lateral electric field causes severe lattice scattering, leading the carrier
velocity to saturate at a maximum limit. The total volume of current is
restricted. The long-channel device spreads that voltage over a distance
ten times larger, meaning the carriers experience a regular field, avoid
violent scattering, and successfully scale to higher currents.
. Which one has higher slope in the saturation region? Why?
-The short-channel device steeper slope in the saturation region.
-This is caused by Channel Length Modulation. Once the transistor
enters saturation, the channel pinches off at the drain side. As VDS
increases beyond VDSsat, the pinch-off point moves towards the
source, expanding the depletion region and effectively reducing the
channel length Delta L
. The effective length of the channel the electrons becomes L = L - Delta
L.
4. [Optional] gm and ro in Triode and Saturation
1) Plot gm and ro vs VDS for NMOS device. Use W = 10μm and L =
2μm, VDS = 0: 10m: VDD, and VGS ≈ VTH + 0.5V. (VGS≈0.54)
Figure 19 GM VS VDS
. In the first part of the curve, is the relation linear? Why?
-Yes, the relation is linear. At low Vds (the far left of the graph), the
transistor operates deep in the triode region. Here, the channel acts like
a voltage-controlled resistor.
. Does gm saturate? Why?
-Yes, it saturates heavily, flattening out completely on the right side of
the graph.
- As you continue to increase Vds, the high voltage at the drain depletes
the channel, causing it to pinch off. The transistor enters the saturation
region. Once the channel is pinched off, increasing the lateral field Vds,
any further does not push the carriers through any faster. The current
becomes constrained by the initial vertical force of the gate. Since the
total current ceases to depend on Vds, The transconductance gm
stabilizes at a constant maximum value.
.
-In the saturation region, the drain current equation simplifies to:
1
𝑊
𝐼𝐷 = 𝜇𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2
2
𝐿
-Taking the derivative with respect to Vgs yields:
𝜕𝐼
𝑊
𝑔𝑚 = 𝐷 = 𝜇𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 ).
𝜕𝑉𝐺𝑆
𝐿
-Vds has completely disappeared from the equation. Because gm no longer
relies on Vds.
. Where do you want to operate the transistor for analog amplifier
applications? Why?
-You must operate the transistor deep in the saturation region, because you
want the transistor to act as an ideal Voltage-Controlled Current Source. The
intrinsic voltage gain of an amplifier is physically defined as Ai = gm*ro.
Operating in saturation gives you the absolute highest possible gm.
Ro vs Vds
Figure 20 Ro vs VDS
. Does Ro saturate just after the transistor enters saturation like gm?
Why?
-No, it does not
- Ro is the inverse slope of the ID curve so ID still noticeably changing at
the edge of saturation, Ro remains relatively low and actively changing.
. Does Ro increase if the transistor is biased more into saturation?
-Yes, significantly
- As you apply a much stronger lateral field, the depletion region grows
wider, it becomes harder for the voltage to push that pinch-off point
further toward the source. The expansion of the depletion region slows
down. Because the effective channel length stops shrinking so
aggressively, the drain current ID becomes much more stable and
constant. A constant current against a changing voltage physically
translates to a climbing output resistance Ro.
. Should we operate the transistor at the edge of saturation?
-No
. Where do you want to operate the transistor for analog amplifier
applications? Why? -You want to operate deep in the saturation region
- The intrinsic voltage gain of an amplifier is defined as Av = gm*Ro. To
get the highest possible gain, you need Ro to be as physically large as
possible.