Programmable Interrupt
Controller 8259
Programmable Peripheral Devices
Features
i.
8 levels of interrupts.
ii.
Can be cascaded in master-slave configuration to handle 64 levels of interrupts.
iii.
Internal priority resolver.
iv.
Fixed priority mode and rotating priority mode.
v.
Individually maskable interrupts.
vi.
Modes and masks can be changed dynamically.
vii.
Accepts IRQ, determines priority, compare priority of current service routine, issues interrupt signal.
viii. In 8085 mode, provides 3 byte CALL instruction.
ix.
In 8086 mode, provides 8 bit vector number.
x.
Polled and vectored mode.
xi.
Starting address of ISR or vector number is programmable.
xii.
No clock required.
Pin & Block
Diagram
Description of different blocks-I
Block
Description
Data Bus This block is used to communicate between 8259 and 8085/8086 by acting as
Buffer buffer. It takes the control word from 8085/8086 and send it to the 8259. It
transfers the opcode of the selected interrupts and address of ISR to the other
connected microprocessor. It can send maximum 8-bit at a time.
R/W This block works when the value of pin CS is 0. This block is used to flow the
Control data depending upon the inputs of RD and WR. These are active low pins for
Logic read and write.
Control It controls the functionality of each block. It has pin called INTR. This is
Logic connected to other microprocessors for taking the interrupt request. The INT pin
is used to give the output. If 8259 is enabled, and also the interrupt flags of other
microprocessors are high then this causes the value of the output INT pin high,
and in this way this chip can responds requests made by other microprocessors.
Description of different blocks-II
Interrupt Request It stores all interrupt level that are requesting for interrupt service.
Register (IRR)
Interrupt Service It stores interrupt level that are currently being execute.
Register (ISR)
Interrupt Mask It used for masking one or more interrupts.
Register (IMR)
Priority Resolver It checks all three registers, and set the priority of the interrupts.
Interrupt with the highest priority is set in the ISR register. It also reset
the interrupt level which is already been serviced in the IRR.
Cascade Buffer To increase number of interrupt pin, we can cascade more number of
pins, by using cascade buffer. When we are going to increase the
interrupt capability, CSA lines are used to control multiple interrupts.
Basic Interrupt Operation - I
To implement interrupt, the interrupt enable flip-flop in the microprocessor should be enabled by
writing the EI instruction in 8085/86 and the 8259A should be initialized by writing control words in
the control register. The 8259Arequires two types of control words:
(a) Initialization Command Words(ICWS)
(b)Operational Command Words(OCWs)
➢ ICWs are used to set up the proper conditions and specify RST vector address.
➢ The OCWs are used to perform functions such as masking interrupts, setting up status-read operations etc.
Step-1: The IRR of 8259A stores the request.
Step-2: The priority resolver checks 3 registers-
* The IRR for interrupt requests.
* IMR for masking bits and
*the ISR for interrupt request being served.
It resolves the priority and sets the INT high when appropriate.
Basic Interrupt Operation - II
Step-3: The MPU acknowledges the interrupt bysending signals in 𝐼𝑁𝑇𝐴.
Step-4: After the 𝐼𝑁𝑇𝐴 is received, the appropriate priority bit in the ISR is set to indicate which interrupt level is
being served and the corresponding bit in the IRR is reset to indicate that the request for the CALL instruction is
placed on the data bus.
Step-5: When MPU decodes the CALLinstruction, it places two more 𝐼 𝑁𝑇𝐴 signals on the data bus.
Step-6: When the 8259A receives the second 𝐼𝑁𝑇𝐴 it places the low-order byte of the CALLaddress on the data
bus. At the 3rd 𝐼𝑁𝑇𝐴 it places the high order byte on the data bus. The CALLaddress is the vector memory location
for the interrupt, this address is placed in the control register during the initialization.
Step-7: During the 3rd 𝐼 𝑁𝑇𝐴pulse, the ISR bit is reset either automatically (Automatic-End-of- Interrupt-AEOI) or
by a command word that must be issued at the end of the service routine (End of Interrupt-EOI). This option is
determined bythe initialization command word (ICW).
Step-8: The program sequence is transferred to the memory location specified by the CALL instruction.
Modes of 8259
Interrupt Priority
How the interrupt priority is determined?
• Fully Nested mode
• Automatic Rotation
• Specific Rotation
End-of-Interrupt
How the interrupt service completion is indicated?
• Non specific EOI
• Specific EOI
• Automatic EOI
Special Mask Mode How to mask the interrupts?
Poll Method
When INT line not to used?
Interrupt Triggering How the interrupt is triggered?
Interrupt Priority
• Fully nested mode
This is a general purpose mode where all IR’s are arranged in highest to lowest. IR0
highest and IR7 lowest. Moreover any IR can be assigned as highest priority level.
• Automatic Rotation
In this mode a device after being serviced receives the lowest priority.
• Specific Rotation
In this user can select any IR for lowest priority thus fixing all priorities.
End-of-Interrupt (EOI)
After completion of the interrupt service, the corresponding ISR bit needs to be reset to
update the information in the ISR. This is call End-of-Interrupt (EOI) command. This
can be issued in the following three formats;
•
Non specific EOI: A command sent by the interrupt service procedure to signal the
end of interrupt. When this command is sent to the 8259A, it resets the highest priority ISR
bit (lowest numbered IS bit, suppose IR4 and IR6 are now in service, IR4 has the highest
priority than IR6). This allows the interrupt to take action again or a lower priority interrupt
to take effect.
• Specific EOI: A command that allows a specific interrupt request to be reset. The
exact position is determined with bits L2-L0 of OCW2
• Automatic EOI: In this mode, no command is necessary. During the 𝐼𝑁𝑇𝐴, the
ISR bit is reset. Disadvantage is the ISR do not have information on which IR is
being serviced. Thus any interrupt irrespective of priority can interrupt the current
service routine.
Other Modes
❑ Special Mask Mode
When a mask bit is set in OCW, it inhibits further interrupts at that level and
enables interrupt from other levels, which are not masked.
❑ Poll command
The INT output is neglected, though it functions normally by not connecting
INT output or by masking INT input of the microprocessor.
➢ This mode is entered by setting P=1 in OCW3.
➢ Poll command may give more than 64 priority levels.
❑ Interrupt Triggering
Interrupt with either edge or level trigger can be set by initializing command
word.
Programming 8259
❑ The 8259A is programmed by initialization and operation command words.
❑ Initialization command words (ICWs) are programmed before the 8259A is able to function in the
system and dictate the basic operation of 8259A. There are four initialization command words (ICWs) for the
8259A that are selected when A0 pin is logic one. If a single 8259A is used in a system, ICW1, ICW2 and
ICW4 must be programmed. If cascade mode is used in a system then all four ICWs must be programmed.
❑ Operation command word (OCWs) are programmed during the normal course of operation. The
OCWs control the operation of the 8259A. There are three OCWs. The operational command words
(OCWs) are used to direct the operation of the 8259A once it is programmed with ICW. The ICWs are
selected when A0= 0 level, expect for OCW1, which is selected forA0=1.
ICW1
ICW3
ICW2
ICW4
OCW1
OCW2
OCW3
Allows the setting of the lowest
priority interrupt (L2-L0)
Problem-1: Determine the control word ICW2 required for the PIC so that inputs IRQ0 to IRQ7 correspond to type numbers 40H to
47H. From which memory locations will the processor fetch the interrupt vectors?
Don’t cares
Solution:
ICW2
0
15
1
0
0
0
0
0
0
Input
Type Number output by PIC
Interrupt vector location
IRQ0
40H
00100:00103H (4X40=100H)
IRQ1
41H
00104:00107H
IRQ2
42H
00108:0010BH
IRQ3
43H
0010C:0010FH
IRQ4
44H
00110:00113H
IRQ5
45H
00114:00117H
IRQ6
46H
00118:011BH
IRQ7
47H
0011C:0011FH
Problems related to ICWs
Problem-2: Determine the value for ICW1 for 8086 mode, if it is triggered by rising edge trigger and
there is a single PIC. Also use interval 4 and note that ICW4 is needed .
Solution:
Don’t cares
ICW1
A0
A7
A6
A5
1
LTIM
ADI
0
0
0
0
1
0
1
Don’t care for 8086
Address bitA0=0,
for ICW1
(not part of ICW)
16
Edge
triggered)
Fixed
(always1)
Interval 4
SNGL IC4
1
1
Single
mode
ICW4
needed
Interfacing and Programming 8259A
Problem-3: Show 8259A interfacing connections with 8086 at the address 074x. Write an ALP (Assembly language procedure) to initialize the
8259Ain single level triggered mode with call address interval of 4, non-buffered on special fully nested mode. Then set the 8259Ato operate with
IR6 masked, IR4 as bottom priority level with rotate on specific EOI mode. Set special mask mode of 8259A. Also, read IRR and ISR into registers
BHand BLrespectively. Baseaddress=80H.
Solution:
Solution of Problem 3(Cont.)
Step-1: FindingAddress
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address of Port
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0740H (ICW1, OCW2,
OCW3)
0
0
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0742H
(ICW2,ICW4,OCW
1)
Don’t cares
Step-2: Finding the ICW1
A0
A7
A6
A5
1
LTIM
ADI
0
0
0
0
1
1
1
Don’t care for 8086
Address bitA0=0,
for ICW1
(not part of ICW)
(Level
triggered)
Fixed
(always1)
Call
address
Interval 4
SNGL IC4
1
1
Single
mode
ICW4
needed
ICW1= 1FH
Solution of Problem 3(Cont.)
Don’t cares
Step-3: Finding ICW2
1
0
0
0
0
0
0
0
ICW2=80H
ICW3 is not needed as 8259A is set in single mode.
Don’t cares
Step-4: Finding the ICW4
A0
D7
D6
D5
SFNM
BUT
M/S
1
0
0
0
1
0
0
Non-buffered
mode
Fixed
A0=1, forICW4
For special fully
nested mode
masking
AEOI uPM
0
1
ICW4= 11H
For 8086
microprocessor
Normal
EOI
Solution of Problem 3(Cont.)
Step-5: Finding OCW1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
0
0
0
0
OCW1= 40H
IR6 is masked
Step-6: Finding the OCW2
A0
D7
D6
D5
D4
D3
D2
D1
D0
10
1
1
1
0
0
1
0
0
Rotate on Specific
A0=0, for OCW2 EOI command
Fixed
Bottom priority
level set at IR4
OCW2= E4H
Solution of Problem 3(Cont.)
Step-8: Finding OCW3
The OCW3 sets the special mask mode and reads ISR and IRR using the following control wordsFor reading IRR:
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
1
0
1
0
fixed
Special masked
mode
Fixed
OCW3= 6AH
Read IRR
No poll command
For reading ISR:
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
1
0
1
1
fixed
Special masked
mode
Fixed
Read ISR
No poll command
OCW3= 6BH
Solution of Problem 3(Cont.)
Assembly Language Procedure
INTERRUPT PROC NEAR
MOVAL,AFH ; Loading ICW1 toAL
MOVDX, 0740H ; Loading Address of ICW1 to DX (Variable port addressing)
OUT DX, AL; Sending ICW1 to port (address: 0740H ) of8259A
MOVDX, 0742H ; address ofICW2
MOVAL, 80H ; Loading ICW2 to ALwhich select the vector address
MOV DX, AL; Sending ICW2 to port (address: 0742H ) of 8259A
MOV AL, 11H ; Loading ICW4 toAL
OUT DX,AL
; Sends ICW4 to 0742H
MOVAL, 40H ; Loading OCW1 to AL
OUT DX,AL ; Sends OCW1 to 0742H
MOVAL, E4H ; Loading OCW2 to AL
MOVDX, 0740H ; Address ofOCW2
Solution of Problem 3(Cont.)
Assembly Language Procedure (Cont.)
MOVDX, AL; Sending OCW2 to 0740H address.
MOVAL, 6AH ; Loading OCW3 for reading IRR
OUT DX, AL; Sending OCW3 to 0740H address.
IN AL, DX ; Reading IRR and store toAL
MOVBH, AL; Store IRR into BH
MOV AL, 6BH ; Loading OCW3 for reading ISR
OUT DX, AL; Sending OCW3 to 0740H address.
INAL, DX; Reading ISRand store toAL
MOVBL,AL;Store ISRintoBL
RET
INTERRUPT ENDP
References:
1. https://www.youtube.com/watch?v=TxX_mP_qDLI
2. https://www.youtube.com/watch?v=IAMpcsGDlGo
3. https://www.youtube.com/watch?v=FgkdNCuySDI
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