DEBRE BERHAN UNIVERSITY
College of Computing — Department of Computer Science
Course: Digital Logic Design (EENG2041)
Assignment I
By Getaneh Dagnachew
Weight: 15 Marks
Due Date: May 16
Academic Year: 2026
GENERAL INSTRUCTIONS
ˆ Originality: This is an individual assignment. Any form of academic dishonesty
will result in a grade of zero.
ˆ Technical Standards: All logic circuits must utilize standard logic symbols.
ˆ Documentation: You must provide all Truth Tables, Excitation Tables, and KMap simplifications to receive full credit.
PART 1:
MSI COMPONENT DESIGN
Question 1: Multi-bit Magnitude Comparison
Design a 2-bit Magnitude Comparator circuit that takes two 2-bit binary numbers,
A(A1 A0 ) and B(B1 B0 ), as inputs.
a ) Construct the complete Truth Table for the three logical outputs: A > B, A < B,
and A = B.
b ) Utilizing 4-variable Karnaugh Maps, derive the minimized Sum-of-Products (SOP)
expressions for each of the three outputs.
c ) Implement the finalized design using basic logic gates (AND, OR, NOT).
PART 2:
SEQUENTIAL SYSTEM DESIGN (COUNTERS)
Question 2: Synchronous Sequential Design Challenge
Design a Synchronous MOD-6 Counter using JK Flip-Flops that transitions through
the following irregular sequence:
0→2→3→5→6→7→0
a ) Determine the minimum number of Flip-Flops required to represent the highest
state in the sequence.
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b ) Construct the State Transition Table and include the JK Flip-Flop Excitation
Table columns for each Flip-Flop (JA KA , JB KB , JC KC ).
c ) Use K-Maps to find the minimized logic expressions for the J and K inputs of each
stage.
d ) Analyze the Unused States (1 and 4). Determine if the counter is “Self-Starting”—meaning,
if it accidentally enters state 1 or 4, will it eventually return to the valid sequence?
PART 3:
SYSTEM INTEGRATION & FREQUENCY ANALYSIS
Question 3: Practical Frequency Division
A high-frequency square wave signal of 16 kHz is provided by a crystal oscillator. You
are required to design a Frequency Divider that reduces this signal to exactly 1 kHz.
a ) Calculate the required Modulus (N ) for this division.
b ) Propose a design using a cascade of Flip-Flops or MSI Counter ICs (such as the
7490 or 7493).
c ) Draw the block diagram of the system and provide a brief explanation of how the
“Carry” or “Terminal Count” signal is used to trigger the subsequent stage.
d ) Sketch the timing diagram for the first three stages of the divider to illustrate how
the frequency is halved at each successive Flip-Flop output.
“Practice is the silent architect of brilliance.”
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