Stability Study of PC Power System *
Pit-Leong Wong, Fred C. Lee and Xunwei Zhou
Center for Power Electronics Systems
The Bradley Department of Electrical and Computer Engineering
Virginia Polytechnic Institute and State University
Blacksburg, VA 24061 USA
-
Abstract In this paper, the computer power system is
studied from the point of view of system integration stability.
The Voltage Regulator Module (VRM) and silver-box are
modeled and analyzed. The computer power system is unlikely
to have stability problems based on today’s structure, although
there can be strong interactions in multiple VRM system.
Future trends of the PC power system are also analyzed. With
power level increases, VRMs will have stronger interactions at
lower frequencies. An example of conditional stability is shown
to challenge the impedance stability criterion of integrated
systems. Possible solutions to this problem are provided.
I. INTRODUCTION
With the rapid development of the computer industry, the
power supply of the computer is also facing challenges. With
the emergence of the Intel Pentium TM processor, the power
supplies for the processors generated a growing interest in the
whole power supply system of a computer. Today’s Pentium
series processors demand a large full-load current of 13 A at
a low voltage of 2.8 V. They require a dynamic from 0.1 A to
13 A at a high current slew rate of 30 Nus, with the transient
voltage tolerance at only about 150 mV. These specifications
make it impossible for the centralized bulky silver-box to
provide energy for the processor directly, because the silverbox is too far away from the processor. The large parasitic
inductance (0.1-0.2 uH) of the long connection cable (about
1 foot) prevents the silver-box from providing current
quickly. That a dedicated converter, a Voltage Regulator
Module (VRM), to be physically located very close to the
processor, becomes a necessity in the computer power
system.
away from the load. The tremendous increase in memory
capacity and speed would impose increasing steady-state and
dynamic requirements on the power supply. The supply
voltage of the next generation of RDRAM is expected to be
around 2.5 V [l]. These requirements will result in the
emergence of another kind of VRM dedicated to the memory.
The bus in the computer system is expected to experience the
same trend as the memory, with increasing load and dynamic
requirements. The supply voltage of the bus is also
decreasing to be lower than 1.5 V [l]. A dedicated VRM for
the bus may also become a necessity in future computers.
Briefly, with the increasing speed, integration density and
voltage decreasing in digital processing technology,
computers will require more than one dedicated VRM to be
located very close to the load to provide energy. The structure
of the power system in PCs is illustrated in Fig. 1. The silverbox provides standard voltages of 5 V, 12 V, 3.3 V, etc.
Several VRMs are used in the system.
In this paper, the system stability and interaction of the
PC power system is investigated and analyzed.
#1
-11-
1-
VRM
VRM
#3
Silver Box
-
11
In the future, with increasing speed and integration
density, the requirements for VRMs will be more stringent.
The full-load current will increase to as high as 70 A with a
lower supply voltage of 1.1 V to 1.8 V. The transient current
slew rate can be 1 N n s with a voltage tolerance about 2% of
the supply voltage [l]. Research on high performance VRM
is receiving more interest.
5v
12 v
1-
e
e
e
3.3v
VRM
#4
Fig. 1 Structure of a PC power system with multiple VRMs.
Moreover, the processor will not be the only component
in a computer that causes problems in the traditional power
supply structure with a centralized silver-box located far
*
This work was supported by INTELCORPORATION,
DELTAELECTRONICS,
NATIONAL
SEMICONDUCTORS,
SGS THOMSON
and TEXAS
INSTRUMENTS.
0-7803-5589-X/99/$10.00
0 1999 IEEE
1646
11. VRM INPUTIMPEDANCE
In order to study the system's stability, the impedance at
the interfaces between the silver-box and the VRMs needs to
be studied. In this section, VRM input impedance will be
studied. Both the measurement and modeling results will be
shown. The VRM is basically a Buck converter with an L-C
input filter. The input impedance of a Buck converter with
voltage loop feedback can be given by
--.l+Tv R,
+-.l + T v Zi
where Reg is the equivalent open loop input resistance which
can be estimated by the converter load level, as given by
Vi,'
R =-=-.
eq
Po
R
Dz
R is the converter load resistance; D is the steady state duty
cycle; T, is the gain of the voltage feedback loop; and Zi is
the open-loop input impedance of the converter. Zi is
basically the output L-C filter of the converter together with
the load resistance by a turn ration of 1:D. It can be explained
in Fig. 2.
------I
Input Filter;
c _ _ _ _ _ _ _
I
I_______-------
BuckConverter
I
I I, I
Buck Converter
I
--------------
Fig. 2 Open-loop input impedance Zi of Buck converter.
If both the current feedback and voltage feedback are
applied to the converter, the closed-loop input impedance is
given by:
z,=
1
1
1
T
I
-A.-+-.-
1+T, R ,
This means that the feedback control effectively
increases the input impedance up to the bandwidth of the
feedback loop. At these frequencies, the effect of the
converter input filter begins to appear.
The VRM input filter is used to limit the input current
slew rate. The input filter is a second-order system. The
current transfer function from Zz to Zi, is
where SR(ZiJ is the current slew rate limitation of the VRM
input, which is 0.1 N u s for a single VRM system and 0.04
N u s for a multiple VRM system. LIZ, is the current difference
of Zz between full load and light load. From (8), the corner
frequency of the VRM input filter is around 1 KHz, which is
much lower than the feedback bandwidth of the VRM. The
feedback bandwidth is usually designed as high as possible to
meet the fast response requirements of the VRM.
R
-- - - - - -
This is valid at low frequencies. At that frequencies, it is
reasonable to consider the VRM input impedance as a
negative resistor. The resistance is determined by the load
level. For higher frequencies, where Ziis much smaller than
Reg. (1) or (3) can be approximated as:
It illustrates how Zi, responses with a perturbation on ZZ.
can be considered the step response of the second-order
system because Zz is much faster than Zi.. Based on this, the
corner frequency of the input filter can be estimated as:
!
I
2, z -R,
Zi,
-_------------
I
~
Input Filter I
impedance is close to a negative resistor. This is clear from
(1) or (3). With Ti >>1 or TI >>1, (1) or (3) can be
approximated as:
(3)
The input capacitors need to hold the voltage during the
transient. The unbalanced charge is caused by the current
slew rate difference between ZZ and Zi,. Because the slew rate
of Zl is much larger than the slew rate of Zin, The required
input capacitance can be estimated by the following:
l+T, 'Zi
where
T, = q+ T v ,
Ti being the current feedback loop gain.
'in
(4)
Despite whatever control method is used, as long as the
feedback loop gain is high enough, the converter input
>
PoZ
2 . SR(Z, ) *AV,, *V,,,'
(9)
Ci,is in the range of several mF. It makes the input
impedance so low at a higher frequency that the feedback
control effect can only be seen at a very low frequency as
shown in Fig. 3. At a very low frequency, the VRM input
impedance is a negative resistor. Beyond that, the input
impedance is actually the input filter because the feedback
1647
control effectively increases the converter input impedance.
Thus, the VRM input impedance can be simplified as a
negative resistor paralleled with the input filter as shown in
fig. 4. The negative resistor is adjustable according to the
load level.
am
I
d
In,
-
1.20'
1.d
111. SILVER-BOX
OUTPUT IMPEDANCE CHARACTERISTICS
In order to have multiple output voltage effectively,
weighted control and coupling inductors are used in the
silver-box. Part of the circuitry of the silver-box for 5 V and
12 V output is shown in Fig. 6. These are the major power
outputs of the silver-box, and are also the source for the
VRMs. Modeling of weighted control and the coupling
inductors are studied comprehensively in [3]. For this specific
application, the small signal model block diagram for
weighted control and the coupling inductors is shown in Fig.
7.
I.,$
R S(2.1
u4MD
Fig. 3 Control efftxt on VRM input impedance is concealed by input filter.
d
Weighted
Control
Fig. 6 Circuitry of a typical silver-box.
.The measurement of VRM input impedance is shown in
Fig. 5. The close agreement between the measurement and
the model illustrates the validity of the model.
I
I
20
g
-o
g -20
Fig. 7 Small signal block diagram of silver-box.
40
IO'
10'
.
.
10'
10'
10"
* , Frequency(fiz)
.
From the block diagram, the closed-loop output
impedance of these two outputs can be derived as shown in
the following formulas, respectively:
.
z,,
* < l + T , )K- L * T*ZZl
,
10'
loz,
10'
Frequency(M)
10'
Kl
(10)
l+T
K
z,,-(l+T,)---*T,
.z,,
K,
zozc =
(11)
l+T
where TI and T2 are the loop gains of 5 V and 12 V outputs,
Zolc =
1o5
Fig. 5 Measurement of VRM input impedance (Io=5, 10, 13 A).
respectively. T is the sum of TI and T2. Kl and K2 are the
weighted factors of these two outputs. Zo1 and ZO2are the
1648
.
open-loop output impedance of these two outputs,
respectively, which are basically the corresponding output
filter. 2 1 2 and ZZ1are the trans-impedance between these two
outputs, which depend on the coupling effect of the coupling
inductor. Their definitions are given in the following
formulas:
Weighted control is a loose control. It cannot effectively
shape the output impedance. The impedance magnitude level
is basically determined by the parasitic parameters. The
resistive output impedance results in regulation problems if
the load level of the different output is not balanced for the
high power level. However, from the viewpoint of system
stability, resistive output impedance is desirable.
I v . INTERACTION BETWEEN THE SILVER-BOX
AND THE VRM
Modeling of the 5 V output impedance based on (10) is
shown in Fig. 8. The measurement result is also shown in Fig.
8. The close agreement between them illustrates the validity
of this .model. For the 12 V output impedance, the
characteristic is similar.
When comparing the silver-box output impedance with
the VRM input impedance, there exists some overlap
between these two curves at the comer frequency of the VRM
input filter as shown in Fig. 9. This overlapping is similar to
the overlapping between an L-C filter and a resister. This
overlapping would not cause stability problems because there
exists enough phase margin, also shown in Fig. 9. However,
the overlapping can result in strong current interactions for a
system with multiple VRMs. Transient interactions of a
system with two VRMs is shown in Fig. 10. The strongest
interaction happens when one VRM has a "step-up" transient
while the other has a "step-down'' transient. Because the
system is still stable, the interaction will finally settle down
as expected. The interaction frequency is the corner
frequency of the VRM input filter, which is about 1KHz.
--"
10'
10'
10'
Frequency[M)
10'
10'
1o4
Frequency (Hz)
1o5
_."
10'
I IO'
"I,
-
I 10'
I to'
Fig. 9: VRM input impedance vs. silver-box 5V output impedance.
RlqnnCHLI
Fig. 8: Measurement and modeling of the silver-box 5V output impedance.
From Fig. 8 it can be seen that the silver-box output
impedance is almost constant in magnitude and close to zero
in phase for the interested frequency range. This
characteristic is close to a resistor because of the weighted
control. Compared to single voltage loop feedback, weighted
control cannot regulate both the outputs, which means the
impedance at very low frequencies cannot be suppressed as it
can by single voltage loop feedback. Because of the
weighting factor, weighted control cannot effectively
suppress the impedance at mid-frequency range either. In
order to have reasonable output impedance, a very large
output capacitor is used in the silver-box output. It is usually
several mF, about ten times larger than a traditional design
based on the ripple requirement.
,' . I . ,
,
I
,
. ~, .~. , . ' L ' . .
, I
I
.
,
I
.
.
,-. . d , , .
.-p-r*
Fig. 10: Current interaction: the worst case is when "step-up"and "stepdown" transients happen at the same time.
For future computer systems, the load levels of VRMs
are expected to increase 111. From (8), it can be seen that the
corner frequency of the VRM filter will decrease, which
1649
implies a lower frequency of interaction. From (9) it can be
seen that the input capacitance of the VRM needs to increase
proportionally to the square of the load level, which means a
lower input impedance of the VRM. This results in larger
overlapping area. Although the overlapping is unlikely to
cause instability because of the phase margin, future
computer power systems are expected to see stronger current
interactions at lower frequencies for increasing power levels.
This is not desirable.
However, this criterion may not be so “safe”. The small
signal model of a design example is shown in Fig. 13. The
load converter input impedance is the VRM input impedance
discussed before. The output impedance of the front-end
converter shown in Fig. 13 is also a reasonable one for a
voltage loop feedback Buck converter. There is at least 6 dB
distance between the impedance curves. The root locus of T,,,
is shown in Fig. 14. It is well out of either forbidden region. It
should therefore be “safe” to connect these two converters.
Moreover, it will also be difficult for weighted control to
maintain both the outputs within regulation requirements over
wide load ranges [2]. Studies in [2] show that for high power
level computers such as servers, Distributed Power System
(DPS) seems to be a better solution. With DPS, the VRMs are
connected to a well-regulated DC bus. In the next section of
this paper, stability considerations of this situation will be
analyzed.
v . STABILITY CONSIDERATIONS FOR W
S IN DPS
Fig 12 The forbidden region defined in [5]and [6].
The front end of a typical Distributed Power System is a
boost PFC circuit with a 400 Vdc output followed by an
isolated Buck-type converter such as Forward, Half-bridge or
Full-bridge, which provides a tightly regulated DC bus. The
simplified structure is shown in Fig. 1 1 . The front end is
simplified as a Buck converter with voltage loop feedback.
The input voltage of “n*VB” represents the 400 Vdc PFC
output and the isolation transformer. “VO” is the tightly
regulated DC bus. The VRM is still simplified as an L-C
input filter paralleled with a negative resistor. Ro in Fig. 11
represents the loads in the system other than the VRM. Zin is
the input impedance of the VRM. ZOC is the closed-loop
output impedance of the front-end converter.
\
\
,.Id
Freqsncy (Hz)
Fig. 13 The YO impedance and Tm of the integrated system.
Fig. 1 1 An integrated system considered.
The small signal stability of the integrated system shown
in Fig. 1 1 can be examined by the impedance criterion as
defined in [4] and also shown in (16). Based on this criterion,
two different forbidden regions are defined in [5] and [6]
respectively as shown in Fig. 12. As long as the root locus of
T,,, is kept out of the forbidden region, it should be safe to
connect these two converters.
-J
?
7 5
-3
a,
0
OJ
1
I5
I
2
uTmll,(l),,
Fig. 14 The root locus of T, is well out of the forbidden region
From another point of view, the simplified VRM can be
considered part of the load of the front-end converter. The
stability of the system is thus defined as the stability of the
front-end converter with a special load. As shown in Fig. 11,
the original load is the output capacitor paralleled with Ro,
named as Zc. The idea is to check whether the front-end
1650
converter is still stable with a load of Zi,, paralleled. Or in
other words, if the converter can still remain stable with the
load changed from Zc to Zc’ where
I
7
applied to the system. For-every load, a different system
transfer function must be derived.
7
20 is the open-loop output impedance of the front-end
converter; G, is the transfer function of the compensater; Gd,
and Gdv’ are the transfer function from duty cycle d to VO
without Zi,, and with Zi,,respectively; and T and T’ are the
loop gains of the front-end converter without Zi,,
and with Zi,,
respectively.
6
T=Gdv-Gc.
z =- 20
OC
= nV,
l+T *
Irn
1.103
1.1”’
,.IO‘
Freqency (Hz)
Fig. 15 An integrated system results in conditional stable.
zc.zi
=
A second method of identifying conditional stability
problem is to include the gain information in the impedance
criterion. The output impedance of the front-end converter is
no longer a single curve but becomes a set of curves of
different system gains. The root locus of T,,, also becomes a
set of curves, as shown in Fig. 16. It can be seen that with the
decrease of the system gain the root locus enlarges and finally
clockwise circles the point of (-1, 0). With this method, the
conditional stability problem can be identified.
Gd”
1 T” (1 T )
+
+
Transfer functions of Gd,’ and T’ are shown in Fig. 15. It
is obvious that after Zi,, is added to the load, the front-end
converter becomes conditional stable. Conditional stability is
potentially unstable because of nonlinear factors in the
system as shown in [8]. Thus practical designs always avoid
it. Obviously, the impedance criterion cannot identify this
problem. The only peculiarity of the example is that the load
is slower than the front end. This is common in computer
power systems with VRMs.
Conditional stability is stable in the mathematical sense.
It becomes unstable when the gain of the system drops
because of start-up, saturation, etc. However, the impedance
criterion only considers one point of the steady state. It
cannot predict the large signal system behaviors. This is the
reason why this undesirable character cannot be identified by
the impedance criterion. That is the limitation of this method.
As can be seen, more work is required into reliably
integrated system stability criteria. As the author can see
now, the most reliable method identifying the conditional
stability problem is to derive the system transfer function
with different loads as is discussed above. However, it can
turn out to be very complicated if many different loads are
I
I
t
“9
-1
0
I
2
3
4
I
6
Fig. 16 Root locus of T,,,under different system gain.
In practical designs, in order to avoid the conditional
stability problem, it has been found that increasing the output
capacitance of the front-end converter can help a great deal.
By using a large capacitance, the impact of Zi, to the transfer
function of Gd,’ can be alleviated. In other words, Gd,’ will
not change much from Gdvbecause of Zin.Thus, conditional
stability is unlikely to occur if the original system is stable.
It has also been found that conditional stability can be
avoided by applying a current feedback loop. With a current
feedback loop, the phase of the output impedance can be
1651
limited to within &go0. Thus the phase of T,,, can be limited to
f1800.onemay argue that with the decrease of the
current feedback loop the phase will no longer be limited to
within f90°, and therefore the conditional stability problem is
still present. That is true. The phase curves of the front-end
converter output impedance under different current loop
gains are shown in Fig. 17. However, current loop is usually a
low gain loop. The chance of gain decrease is lower than the
voltage loop. Moreover, the effect of the current loop gain
decrease on the impedance is smaller than that of the voltage
loop on the impedance. From Fig. 17, it can be seen that the
phase of the output impedance can still be limited within
f90” even with five times decrease in current loop gain. Of
course, more research is required into the large signal
stability of integrated systems to resolve this problem.
im
1.d
I .to’
Freqency (Hr)
Fig. 17 The phase of output impedance under different current-loop gain.
VI. CONCLUSION
VRM and silver-box have been modeled and analyzed.
They are unlikely to have stability problems based on there
current structure,.although there can be strong interactions in
multiple VRM systems. With increased power levels, future
VRMs will have stronger interactions at lower frequencies.
Conditional stability problems can happen between VRMs
and well-behaved front-end converters with tightly regulated
outputs. These problems can not be identified by the
impedance criterion for integrated system stability. Possible
solutions to this problem have been given.
REFERENCE
[ 11 S. Goodfellow, “Processor Road Maps,” Intel Power Supply
Technology Symposium, June 1998.
[2] “VRM Consortium Quarterly Progress Report,” VPEC,
1997- 1998.
[3] Qing Chen, “Analysis and Design of Multiple-output Forward
Converter with Weighted Voltage Control”, dissertation,
VPI&SU, Blacksburg, VA, 1994.
[4] R. D. Middlebrook, ”Input Filter Considerations in Design and
Application of Switching Regulators, IEEE IAS Rec. 1976.
[5] Carl M. Wildrick, “Stability of Distributed Power Supply
Systems, ” Thesis, VPI&SU, Blacksburg, VA, 1993.
[6] X. Feng, 2. Ye, K. Xing, F. C. Lee, D.Borojevic, “Individual
I‘
Load Impedance Specification for a Stable DC Distributed
Power System”, pp. 923-929, APEC 1999.
1652
[7] R. B. Ridley, B. H.Cho, F. c . Lee, “Analysis and Interpretation
of Loop Gains of Multiloop-Controlled Switching Regulators”,
IEEE TransactionsOn ‘Owe‘
Oct. 19”.
[8] Phuong Huynh, “Stability analysis of large-scale power
electronics systems,,, dissertation, vpI&su,
VA,
1994.