Understanding the 8086 Microprocessor
Architecture
1. Introduction to the 8086 Architecture
The 8086 microprocessor represents a pivotal moment in computer architecture, primarily due
to its efficient internal organization. Unlike simpler processors that perform tasks sequentially,
the 8086 architecture is split into two primary functional units: the Execution Unit (EU) and the
Bus Interface Unit (BIU).
This division of labor allows the processor to fetch instructions and execute them
simultaneously. By permitting these two units to operate independently and in parallel, the 8086
implements an early form of pipelining, which significantly increases throughput and ensures the
processor hardware is utilized to its maximum potential.
2. The Execution Unit (EU):
The Execution Unit is the heart of the processor's computational power. Its primary
responsibility is to decode instructions and carry them out using its internal 16-bit Arithmetic
Logic Unit (ALU). The EU does not connect directly to the system bus; instead, it receives its
instructions from the BIU.
General Purpose Registers
The EU contains four 16-bit general-purpose registers that are essential for data manipulation.
A key architectural feature is their flexibility: each can be treated as a single 16-bit register or as
two independent 8-bit registers (High and Low bytes).
Register
Name
Abbreviation
Common Specific Uses
8-bit Split (High/Low)
Accumulator
AX
Multiply, divide, I/O operations.
AH / AL
Base
BX
Pointer to base addresses (data).
BH / BL
Count
CX
Counter for loops and shift
operations.
CH / CL
Data
DX
Multiply, divide, I/O operations.
DH / DL
Pointer and Index Registers
To manage memory offsets effectively, particularly for the stack and complex data structures,
the EU utilizes four specialized 16-bit registers:
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Stack Pointer (SP): Maintains a pointer to the current "top" of the stack.
Base Pointer (BP): Used to point to a base address specifically within the stack
segment.
Source Index (SI): Used as a source string or index pointer for data operations.
Destination Index (DI): Used as a destination string or index pointer for data
operations.
3. The Flag Register: Status and Control
The 16-bit Flag register is a status register that reflects the current state of the CPU and the
results of arithmetic operations. A crucial point for any architect to understand is that you
generally cannot access these registers directly; they are modified automatically by the CPU
following mathematical operations to determine the next steps in program control.
8086 Processor Flags
The 8086 utilizes nine active flags, which we categorize by their function:
Flag Name
Abbrev.
Description of Bit Function
Carry Flag
CF
Set on high-order bit carry or borrow; cleared otherwise.
Parity Flag
PF
Set if low-order 8 bits of result contain an even number of 1s.
Auxiliary
Carry
AF
Set on carry or borrow to/from the low-order 4 bits of the result.
Zero Flag
ZF
Set if result is zero; cleared otherwise.
Sign Flag
SF
Set equal to high-order bit of result (0 for positive, 1 for negative).
Trap Flag
TF
Once set, a single-step interrupt occurs after the next instruction.
Interrupt Flag
IF
When set, maskable interrupts cause CPU to transfer control to a
vector.
Direction Flag
DF
Set causes string instructions to auto-decrement; clear causes
auto-increment.
Overflow Flag
OF
Set if the signed result cannot be expressed within the destination
operand.
Categorization:
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Status Flags: CF, PF, AF, ZF, SF, and OF. These reflect the outcome of the ALU's
operations.
Control Flags: TF, IF, and DF. These control the operating mode of the processor.
4. The Bus Interface Unit (BIU):
While the EU focuses on execution, the BIU manages the flow of data and instructions between
the processor and the rest of the system. Its primary roles include fetching instructions,
reading/writing data, and computing the 20-bit physical addresses. To perform these
calculations, the BIU contains a dedicated 20-bit adder component.
BIU Registers
The BIU handles five key registers that define the current memory environment:
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Instruction Pointer (IP): An index pointer that indicates the offset of the next instruction
in memory.
Code Segment (CS): Points to the memory segment containing the current program
instructions.
Data Segment (DS): Points to the segment where program data is typically stored.
Stack Segment (SS): Points to the segment reserved for stack operations.
Extra Segment (ES): An additional segment used for string or auxiliary data storage.
The Instruction Queue and Parallelism
The BIU features an Instruction Queue, a First-In, First-Out (FIFO) buffer. This queue is a
brilliant solution to a classic bottleneck: memory access is significantly slower than the EU’s
internal calculations. The BIU pre-fetches instructions from memory while the EU is busy
executing the current instruction. This effectively "hides" memory latency, ensuring the EU
always has a steady stream of instructions to process, allowing the two units to work in parallel.
5. Memory Addressing: From Logical to Physical
The 8086 can address up to 1 MB of memory using a 20-bit physical address. However,
because its internal registers are only 16 bits, it uses a "Segment:Offset" model known as a
Logical Address.
Physical Address Calculation
The BIU's 20-bit adder calculates the Physical Address (or Absolute Address) using a two-step
process:
1. Shift: The 16-bit Segment Register value is left-shifted by 4 bits (effectively appending a
'0' in hexadecimal).
2. Add: The 16-bit Offset (the effective address) is added to the shifted value.
Calculation Example
Consider a logical address defined by CS:IP = 0400H:0056H:
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Step 1: Shift the Segment (0400H) left 4 bits \rightarrow 04000H
Step 2: Add the Offset (0056H) \rightarrow 04000H + 0056H = 04056H
Result: The actual hardware address used to access memory is 04056H.
6. The Stack Segment and Operations
The Stack is a section of memory utilized for temporary storage, governed by the Last-In, FirstOut (LIFO) algorithm. It is managed primarily by the SS (Stack Segment) and SP (Stack
Pointer) registers.
Stack Instructions and Usage
The processor provides two primary instructions for stack interaction:
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PUSH: Stores a 16-bit value onto the stack.
POP: Retrieves the most recently pushed 16-bit value.
The stack is critical for program flow. The CALL instruction uses it to store return addresses,
which the RET instruction later retrieves. More comprehensively, when an INT (Interrupt)
instruction is triggered, the processor automatically pushes the Flag Register, the Code
Segment, and the Instruction Pointer (Offset) onto the stack. These are subsequently
restored using the IRET (Interrupt Return) instruction, ensuring the processor returns exactly to
its pre-interrupt state.
7. Conclusion
The enduring legacy of the 8086 microprocessor lies in its dual-unit architecture. By separating
the "Doing" (EU) from the "Communicating" (BIU), the 8086 introduced a level of efficiency
previously unseen in microprocessors. This design allows for the calculation of complex 20-bit
physical addresses and the pre-fetching of instructions to occur while the execution unit remains
focused on data processing. This synergy between fetching and execution creates a parallel
processing environment that maximizes throughput and provides a robust foundation for
modern computing.