Lecture 8:
Combinational Circuit Design
Mark McDermott
Electrical and Computer Engineering
The University of Texas at Austin
9/25/18
VLSI-1 Class Notes
Verilog to Gates
module mux(input
s, d0, d1,
output y);
assign y = s ? d1 : d0;
endmodule
Sketch a design using AND, OR, and NOT gates.
D0
S
Y
D1
S
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VLSI-1 Class Notes
Page 2
Example
2) Sketch the design using NAND, NOR, and NOT gates. Assume ~S
is available.
D0
S
Y
D1
S
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VLSI-1 Class Notes
Page 3
Example 3
3) Sketch a design using one compound gate and one NOT gate.
Assume ~S is available.
D0
S
D1
S
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Y
VLSI-1 Class Notes
Page 4
Sizing Compound Gates
§ Inverter equivalence
AOI21
AOI22
Y=A
Y = A! B + C
Y = A! B + C ! D
Y = A!( B + C ) + D ! E
A
B
C
D
D
E
A
B
C
A
Y
A
B
C
A
A
Complex AOI
unit inverter
2
1
Y
Y
4 B
C
A
2
B
2
4
4
C
Y
1
Y
A
4 B
4
C
4 D
4
A
2 C
2
B
2 D
2
Y
Y
B
6
C
6
A
3
D
6
E
6
E
2
A
2
D
2
2
C
B
gA = 3/3
gA = 6/3
gA = 6/3
gA = 5/3
p = 3/3
gB = 6/3
gB = 6/3
gB = 8/3
gC = 5/3
gC = 6/3
gC = 8/3
p = 7/3
gD = 6/3
gD = 8/3
p = 12/3
gE = 8/3
Y
2
p = 16/3
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VLSI-1 Class Notes
Page 5
Input Order Matters
§ Our parasitic delay model was too simple
– Calculate parasitic delay for Y falling
• If A arrives latest?
– 2t
• If B arrives latest?
– 2.33t
2
A
B
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2
2
x
2
VLSI-1 Class Notes
6C
Y
2C
Page 6
Inner & Outer Inputs
§ Outer input is closest to rail (B)
§ Inner input is closest to output (A)
2
2
A
2
B
2
Y
§ If input arrival time is known
– Connect latest input to inner terminal
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VLSI-1 Class Notes
Page 7
Asymmetric Gates
§ Asymmetric gates favor one input over another
§ Example: Suppose input A of a NAND gate is most
critical
– Use smaller transistor on A (less capacitance)
– Boost size of noncritical input
– So total resistance is same
A
reset
Y
2
A
reset
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VLSI-1 Class Notes
2
Y
4/3
4
Page 8
Symmetric Gates
§ Inputs can be made perfectly symmetric
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2
2
A
1
1
B
1
1
VLSI-1 Class Notes
Y
Page 9
Skewed Gates
§ Skewed gates favor one edge over another
§ Ex: suppose rising output of inverter is most critical
– Downsize noncritical NMOS transistor
HI-skew
inverter
A
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2
1/2
unskewed inverter
(equal rise resistance)
Y
A
2
1
Y
VLSI-1 Class Notes
unskewed inverter
(equal fall resistance)
A
1
1/2
Y
Page 10
HI- and LO-Skew
§ Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that
gate to the input capacitance of an unskewed inverter
delivering the same output current for the same
transition
§ Skewed gates reduce size of noncritical transistors
– HI-skew gates favor rising output (small nMOS)
– LO-skew gates favor falling output (small pMOS)
§ Logical effort is smaller for favored direction
§ But larger for the other direction
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VLSI-1 Class Notes
Page 11
Catalog of Skewed Gates
Inverter
NAND2
2
unskewed
A
2
1
Y
gu = 1
gd = 1
gavg = 1
A
2
B
2
2
HI-skew
A
2
Y
1/2 g = 5/6
u
gd = 5/3
gavg = 5/4
LO-skew
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A
1
Y
gu = 4/3
gd = 2/3
gavg = 1
2
A
1
B
1
1
1
2
1
A
2
B
2
VLSI-1 Class Notes
NOR2
Y
B
4
A
4
1
gu = 4/3
gd = 4/3
gavg = 4/3
Y
B
4
A
4
1/2
gu = 1
gd = 2
gavg = 3/2
Y
gu = 2
gd = 1
gavg = 3/2
1
1/2
B
2
A
2
1
1
Y
gu = 5/3
gd = 5/3
gavg = 5/3
Y
gu = 3/2
gd = 3
gavg = 9/4
Y
gu = 2
gd = 1
gavg = 3/2
Page 12
Asymmetric Skew
§ Combine asymmetric and skewed gates
– Downsize noncritical transistor on unimportant input
– Reduces parasitic delay for critical input
A
reset
Y
1
A
reset
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2
Y
4/3
4
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Page 13
Best P/N Ratio
§ We have selected P/N ratio for equivalent rise and fall resistance
– (µ = 2-3 for an inverter).
§ Alternative: choose ratio for least average delay
§ Ex: inverter
– Delay driving identical inverter
– tpdf = (P+1)
– tpdr = (P+1)(µ/P)
– tpd = (P+1)(1+µ/P)/2 = (P + 1 + µ + µ/P)/2
A
P
1
– Differentiate tpd w.r.t. P
– Least delay for P =
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µ
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Page 14
P/N Ratios
§ In general, best P/N ratio is square root of that giving equal delay
– Only improves average delay slightly for inverters
– But significantly decreases area and power
Inverter
NAND2
2
fastest
P/N ratio
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A
1.414
Y
1
gu = 1.15
gd = 0.81
gavg = 0.98
2
A
2
B
2
VLSI-1 Class Notes
NOR2
Y
gu = 4/3
gd = 4/3
gavg = 4/3
B
2
A
2
1
1
Y
gu = 2
gd = 1
gavg = 3/2
Page 15
Device Sizing
§ Device sizing is one of the key techniques for circuit optimization
– For standard cell type of designs, gate sizing
• For example of inverters, INV-A, INV-B, INV-C, …, INV-N, …, each having a different
driving capabilities.
– For microprocessor or custom designs, more fine-grained control, transistor
sizing
• For each transistor
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VLSI-1 Class Notes
Page 16
Driver Sizing
§ Given:
– A chain of cascaded drivers driving a load
– Ignore the interconnect between drivers (i.e. assume driver and load CL is
closer enough)
§ Obtain:
– Optimize the driver sizes to minimize delay, or minimize total area while
meeting target delay
§ Delay and area/power tradeoff
d1
Cg1
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d2
dk
Cgk
Cg2
VLSI-1 Class Notes
CL
Page 17
Driver Sizing using stage ratios
d1
Cg1
d2
dk
Cgk
Cg2
Constant stage ratio:
where
!"#$
!"
!"#$
!"
CL
'( $/,
=( )
')
≈ . (i.e. 2.78)
We will use 3-4 in this class
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VLSI-1 Class Notes
Page 18
Stage ratio example
A
120
B
60
Inverter equivalent
stage ratio = 3
beta ratio = 2
40
20
Sized NAND
beta ratio = 2
A
40
B
40
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120
60
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Page 19
Sizing example
§ Size these three circuits.
– Load on node Y: 40/20 inverter
– Use stage ratio of 4
– Use beta ratio of 2
Y
40
Y
40
20
20
40
20
VLSI-1 Class Notes
Stage ratio example HW #3
Use stage ratio of 3
Use beta ratio of 2
F
120
G
60
A
B
C
180
90
D
E
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VLSI-1 Class Notes
Page 22
Backup: Logical Effort
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VLSI-1 Class Notes
Introduction
§ Chip designers face a plethora of choices
– What is the best circuit topology for a function?
– How many stages of logic give least delay?
– How wide should the transistors be?
§ Logical effort is one method to make these decisions
– Uses a simple model of delay
– Allows back-of-the-envelope calculations
– Helps make rapid comparisons between alternatives
– Emphasizes remarkable symmetries
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VLSI-1 Class Notes
Page 24
Example
§ Design the decoder for a register file.
Decoder specifications:
– 16 word register file
– Each word is 32 bits wide
– Each bit presents load of 3 unit-sized transistors
– True and complementary address inputs A[3:0]
– Each input may drive 10 unit-sized transistors
§ Need to decide:
VLSI-1 Class Notes
32 bits
16
Register File
16 words
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A[3:0] A[3:0]
4:16 Decoder
– How many stages to use?
– How large should each gate be?
– How fast can decoder operate?
Page 25
Delay in a Logic Gate
§ Express delays in process-independent unit
d=
d abs
t
τ = 3RC
» 12 ps in 180 nm process
3 ps in 65nm µm process
§ Delay has two components: d = f + p
§ Effort delay f = gh (a.k.a. stage effort)
g: logical effort
h: electrical effort = Cout / Cin
Measures relative ability of gate
Ratio of output to input caps.
to deliver current
Sometimes called fanout effort
g = 1 for inverter
§ Parasitic delay p
– Represents intrinsic delay of gate driving no load
– Set by internal parasitic capacitance
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Page 26
Delay Plots
2-input
NAND
6
Normalized Delay: d
d=f+p
d = gh + p
Inverter
5
g = 4/3
p=2
d = (4/3)h + 2
3
g=1
p=1
d=h+1
2
Effort Delay: f
4
1
Parasitic Delay: p
0
0
1
2
3
4
5
Electrical Effort:
h = Cout / Cin
What about a NOR2?
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VLSI-1 Class Notes
Page 27
Computing Logical Effort
§ Logical effort is the ratio of the input capacitance of a gate to
the input capacitance of an inverter delivering the same output
current
§ Measure from delay vs. fanout plots
§ Or estimate by counting transistor widths
2
A
2
1
Y
Cin = 3
g = 3/3
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2
A
2
B
2
Cin = 4
g = 4/3
VLSI-1 Class Notes
Y
A
4
B
4
1
1
Y
Cin = 5
g = 5/3
Page 28
Computing Logical Effort for a NAND2 Gate
Recall that delay = tpd/τ and
For the 2-NAND gate below
2
A
B
2
2
2x
τ ≈ 3RC
Y
4hC
6C
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Y
(6+4h)C
2C
The rising propagation delay is: t pdr =
Therefore
Recall
R
( 6 + 4h ) RC
d = tpd/τ = (6 + 4h)RC/3RC = 4/3h +2
d = gh + p therefore g=4/3
VLSI-1 Class Notes
Page 29
Computing Logical Effort for a NAND2 Gate (cont)
The logical effort for the falling signal is the same, however the
intrinsic delay is not.
2
A
B
2
2
2x
Y
4hC
6C
x
R/2
R/2
2C
Y
(6+4h)C
2C
t pdf = ( 2C ) ( R2 ) + éë( 6 + 4h ) C ùû ( R2 + R2 )
= ( 7 + 4h ) RC
Where
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d = tpd/τ = (7 + 4h)RC/3RC = 4/3h +7/3
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Page 30
Catalog of Gates
Logical effort of common gates
Gate type
Number of inputs
1
2
3
4
n
NAND
4/3
5/3
6/3
(n+2)/3
NOR
5/3
7/3
9/3
(2n+1)/3
2
2
2
2
4, 4
6, 12, 6
8, 16, 16, 8
Inverter
Tristate / mux
XOR, XNOR
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1
2
VLSI-1 Class Notes
Page 31
Catalog of Gates
§ Parasitic (intrinsic) delay of common gates
– In multiples of pinv (»1)
Gate type
Number of inputs
1
2
3
4
n
NAND
2
3
4
n
NOR
2
3
4
n
4
6
8
2n
4
6
8
Inverter
Tristate / mux
XOR, XNOR
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1
2
VLSI-1 Class Notes
Page 32
Example: Ring Oscillator
§ Estimate the frequency of an N-stage ring oscillator
31 stage ring oscillator in
0.6 µm process has
frequency of ~ 200 MHz
Logical Effort:
g = 1
Electrical Effort: h = 1
Parasitic Delay:
p = 1
Stage Delay:
d = 2
Frequency: fosc = 1/(2*N*d) = 1/4N
Recall that the signal has to propagate through the
inverter chain twice to make a complete waveform
Page 33
VLSI-1 Class Notes
9/25/18
Example: FO4 Inverter
§ Estimate the delay of a fanout-of-4 (FO4) inverter
d
Logical Effort:
g = 1
Electrical Effort: h = 4
Parasitic Delay: p = 1
Stage Delay:
d = 5
The FO4 delay is about
200 ps in 0.6 µm process
60 ps in a 180 nm process
f/3 ns in an f µm process
(f/3 ps in an f nm process)
Page 34
VLSI-1 Class Notes
9/25/18
Multistage Logic Networks
§ Logical effort generalizes to multistage networks
Path Logical Effort à G =
Path Electrical Effort à
g1 = 1
h1 = x/10
H=
i
Cout-path
Cin-path
F = Õ f i = Õ gi hi
Path Effort à
10
Õg
x
g2 = 5/3
h2 = y/x
y
g3 = 4/3
h3 = z/y
z
g4 = 1
h4 = 20/z
20
§ Can we write F = GH in general?
Page 35
VLSI-1 Class Notes
9/25/18
Paths that Branch
§
No! Consider paths that branch:
G
H
GH
h1
h2
F
Page 36
=1
= 90 / 5 = 18
= 18
= (15 +15) / 5 = 6
= 90 / 15 = 6
= g1g2h1h2 = 36 = 2GH
VLSI-1 Class Notes
15
90
5
15
90
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Branching Effort
§ Introduce branching effort
– Accounts for branching between stages in path
b=
Con path + Coff path
Con path
Note:
B = Õ bi
Õ h = BH
i
§ We compute the path effort
– F = GBH
Page 37
VLSI-1 Class Notes
9/25/18
Multistage Delays
§ Path Effort Delay
DF = å f i
§ Path Parasitic Delay
P = å pi
§ Path Delay
D = å d i = DF + P
Page 38
VLSI-1 Class Notes
9/25/18
Designing Fast Circuits
D = å d i = DF + P
§ Delay is smallest when each stage bears same effort
fˆ = gi hi = F
1
N
§ Thus minimum delay of N stage path is
1
N
D = NF + P
§ This is a key result of logical effort
• Find fastest possible delay
• Doesn’t require calculating gate sizes
Page 39
VLSI-1 Class Notes
9/25/18
Gate Sizes
§ How wide should the gates be for least delay?
ˆf = gh = g Cout
Cin
gi Couti
Þ Cini =
fˆ
§ Working backward, apply capacitance transformation to find
input capacitance of each gate given load it drives
§ Check work by verifying input cap spec is met
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VLSI-1 Class Notes
Page 40
Example: 3-stage path
§ Select gate sizes x and y for least delay from A to B
x
x
A
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8
x
VLSI-1 Class Notes
y
y
45
B
45
Page 41
Example: 3-stage path
x
y
x
A
8
Logical Effort
Electrical Effort
Branching Effort
Path Effort
Best Stage Effort
Parasitic Delay
Delay
Page 42
x
y
45
B
45
G = (4/3)*(5/3)*(5/3) = 100/27
H = 45/8
B=3*2=6
F = GBH = 125
fˆ = 3 F = 5
P=2+3+2=7
D = 3*5 + 7 = 22 = 4.4 FO4
VLSI-1 Class Notes
9/25/18
Example: 3-stage path
§ Work backward for sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10
45
A P: 4
N: 4
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P: 4
N: 6
VLSI-1 Class Notes
P: 12
N: 3
B
45
Page 43
Best Number of Stages
§ How many stages should a path use?
– Minimizing number of stages is not always fastest
§ Example: drive 64-bit datapath with unit inverter
InitialDriver
D
1
= NF1/N + P
= N(64)1/N + N
1
1
1
8
4
2.8
16
8
23
DatapathLoad
N:
f:
D:
Page 44
VLSI-1 Class Notes
64
1
64
65
64
2
8
18
64
3
4
15
64
4
2.8
15.3
Fastest
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Derivation
§ Consider adding inverters to end of path
– How many give least delay?
n1
D = NF + å pi + ( N - n1 ) pinv
1
N
i =1
§ Define best stage effort
r=F
Logic Block:
n1Stages
Path Effort F
N - n1 ExtraInverters
1
N
1
1
1
¶D
= - F N ln F N + F N + pinv = 0
¶N
pinv + r (1 - ln r ) = 0
Page 45
VLSI-1 Class Notes
9/25/18
Best Stage Effort
§
pinv + r (1 - ln r ) = 0 has no closed-form solution
§ Neglecting parasitics (pinv = 0), we find r = 2.718 (e)
§ For pinv = 1, solve numerically for r = 3.59
Page 46
VLSI-1 Class Notes
9/25/18
Sensitivity Analysis
§ How sensitive is delay to using exactly the best
number of stages?
D(N) /D(N)
1.6
1.51
1.4
1.26
1.2
1.15
1.0
(r =2.4)
(r=6)
0.0
0.5
0.7
1.0
1.4
2.0
N/ N
§ 2.4 < r < 6 gives delay within 15% of optimal
– We can be sloppy!
– For example, use r = 4
Page 47
VLSI-1 Class Notes
9/25/18
Let’s revisit the decoder specifications
§ Design the decoder for a register file.
Decoder specifications:
– 16 word register file
– Each word is 32 bits wide
– Each bit presents load of 3 unit-sized transistors
– True and complementary address inputs A[3:0]
– Each input may drive 10 unit-sized transistors
§ Need to decide:
VLSI-1 Class Notes
32 bits
16
Register File
16 words
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A[3:0] A[3:0]
4:16 Decoder
– How many stages to use?
– How large should each gate be?
– How fast can decoder operate?
Page 48
Decoder Ex: Number of Stages
§ Decoder effort is mainly electrical and branching
Electrical Effort:
H = (32*3) / 10 = 9.6
Branching Effort: B = 8
§ If we neglect logical effort (assume G = 1)
Path Effort:
F = GBH = 76.8
Number of Stages: N = log4F = 3.1
§ Try a 3-stage design based on rough estimation
Page 49
VLSI-1 Class Notes
9/25/18
Decoder: Gate Sizes & Delay
Logical Effort: G = 1 * 6/3 * 1 = 2 (not an estimation)
Path Effort:
F = GBH = 154
1/ 3
ˆ
Stage Effort: f = F = 5.36
Path Delay:
D = 3 fˆ + 1 + 4 + 1 = 22.1
Gate sizes:
z = 96*1/5.36 = 18;
y = 18*2/5.36 =
6.7
A[3] A[3]
A[2] A[2]
A[1] A[1]
A[0] A[0]
10
10
10
10
10
10
10
10
y
z
word[0]
96 units of wordline capacitance
y
Page 50
VLSI-1 Class Notes
z
word[15]
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Decoder: Comparison
Compare many alternatives with a spreadsheet
Design
N G
P
D
NAND4-INV
2
2
5
29.8
NAND2-NOR2
2
20/9
4
30.1
INV-NAND4-INV
3
2
6
22.1
NAND4-INV-INV-INV
4
2
7
21.1
NAND2-NOR2-INV-INV
4
20/9
6
20.5
NAND2-INV-NAND2-INV
4
16/9
6
19.7
INV-NAND2-INV-NAND2-INV
5
16/9
7
20.4
NAND2-INV-NAND2-INV-INV-INV
6
16/9
8
21.6
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VLSI-1 Class Notes
Page 51
Review of Definitions
Term
number of stages
logical effort
electrical effort
branching effort
effort
effort delay
parasitic delay
delay
Page 52
Stage
Path
1
N
g
G = Õ gi
h = CCoutin
H = Cout-path
in-path
C
off-path
b = on-path
Con-path
B = Õ bi
f = gh
F = GBH
f
DF = å f i
p
P = å pi
d= f +p
D = å d i = DF + P
C
+C
VLSI-1 Class Notes
9/25/18
Logical Effort Methodology Summary
§ Compute path effort
F = GBH
§ Estimate best number of stages
N = log 4 F
§ Sketch path with N stages
§ Estimate least delay
1
N
D = NF + P
§ Determine best stage effort
§ Find gate sizes
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fˆ = F
1
N
gi Couti
Cini =
fˆ
VLSI-1 Class Notes
Page 53
Limits of Logical Effort
§ Chicken and egg problem
– Need path to compute G
– But don’t know number of stages without G
§ Simplistic delay model
– Neglects input rise time effects
§ Interconnect
– Iteration required in designs with wire
§ Maximum speed only
– Not minimum area/power for constrained delay
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VLSI-1 Class Notes
Page 54
Summary
§ Logical effort is useful for thinking of delay in circuits
– Numeric logical effort characterizes gates
– NANDs are faster than NORs in CMOS
– Paths are fastest when effort delays are ~4
– Path delay is weakly sensitive to stages, sizes
– But using fewer stages doesn’t mean faster paths
– Delay of path is about log4F FO4 inverter delays
– Inverters and NAND2 best for driving large caps
§ Provides language for discussing fast circuits
– But requires practice to master
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