DLD
ADP Assignment 3
Proposed By: Punjab Group of Colleges (UCP)
Content: Digital Logical Design
Title: SR Latches
Submitted By: Zimal Ishtiaq
Submitted To: Sir Waqas
Submission date: 24 Jan 2026
QUESTION # 1:
S-R Latch.
Definition:
In digital electronics, a latch is a fundamental,
asynchronous memory element that stores one bit
of binary and holds it until triggered to change by
an input signal.
It involves the NAND and NOR gates.
The circuit diagram of R-S latch
By using NAND gates.
Working:
Case#1:
When the S is 0 and R is 0 .So, the output will be
invalid.
Case#2:
 When the S is 0 and R is 1 .So, the output will
be 1.
Case#3:
 When the S is 1 and R is 0 .So, the output will
be 1.
Case#4:
 When the S is 1 and R is 1 .So, the output will be
hold.
Truth table:
S
0
0
1
1
R
0
1
0
1
Q(n+1)
Invalid
1
1
Hold