COMPSCI 458: Computer
Architecture
Handout: Pipelined Datapath
Fall 2025, Jerald Thomas
For questions 1-2, refer to the incomplete preliminary pipeline design shown below, which includes the
interstage buffers needed to synchronize signals and data with the instructions, but has no support for
forwarding operands, hazard detections, or adding stalls. This datapath supports correct execution of
any sequence of the following MIPS instructions: add, sub, and, or, slt, lw, sw, and beq. The is true
assuming that data and control hazards are handled by having the assembler insert nop instructions.
Note that the AND gate in the MEM stage is executed prior to the multiplexor in the IF stage, permitting
one fewer nop during the evaluation of branch hazards.
COMPSCI 458: Computer
Architecture
Handout: Pipelined Datapath
Fall 2025, Jerald Thomas
1. With the above incomplete pipeline design, the assembler should insert nop instructions to
execute the sequence of instructions with data and/or control hazards correctly
a. Explain where and how many minimal nop instructions the assembler should insert in
order to run the following sequence of instructions correctly.
add
sub
lw
sw
add
$s1, $s2, $s3
$s1, $s1, $s4
$s3, 0($s1)
$s1, 8($s5)
$s2, $s1, $s2
#1
#2
#3
#4
#5
b. Explain where and how many minimal nop instructions the assembler should insert in
order to run the following sequence of instructions correctly.
L1:
add
sub
beq
sw
sw
$s1, $s2, $s3
$s2, $s3, $s4
$s3, $zero, L1
$s4, 8($s5)
$s4, 16($s5)
#1
#2
#3
#4
#5
COMPSCI 458: Computer
Architecture
Handout: Pipelined Datapath
Fall 2025, Jerald Thomas
2. Suppose that a wrong implementation of the MIPS pipeline does not forward the Write Register
number through the ID/EX, EX/MEM, and MEM/WB interstage buffers. Instead, it directly
receives the output of the multiplexer controlled by RegDst as shown here:
Everything else in the pipeline is implemented as shown on the diagram from page 1. For the
sw instruction, the control signal RegDst is actual X (don’t care), but we will assume that it is
set to 0 on this specific instance. Suppose that, initially, $t1 = 0x4000, $t2 =
0x1000, $t3 = 0x3000, and $t4 = 0x2000. Consider the execution of the following
code in this buggy pipeline. Determine the final values of $t1, $t2, and $t3 after all the
instructions leave the pipeline. You can assume that nop signals will follow instruction #7, and
that an attempt to write to register $zero is treated as a discard value, similar to returning a
value from a function but not capturing that value in a variable.
add
sw
sw
add
sw
sw
add
$t2, $t3, $t4
#1
$t2, 0x3000($t4) #2
$t2, 0x2000($t4) #3
$t1, $t2, $t3
#4
$t3, 0x1000($t4) #5
$t3, 0x0000($t4) #6
$t5, $t2, $t4
#7
COMPSCI 458: Computer
Architecture
Handout: Pipelined Datapath
Fall 2025, Jerald Thomas
For questions 3 and 4, refer to the pipeline design with forwarding and (load-use) hazard
detection, shown below, which supports execution of any sequence of the following MIPS
instructions: add, sub, and, or, slt, lw, and sw. The datapath is simplified by omitting the signextend immediate and the logic for changing the PC to PC+4. Note that the datapath does not
support branch or jump instructions.
3. How many clock cycles would be required to execute the following sequence of instructions?
add
lw
lw
add
add
$t2, $t1, $t3
$t3, 0($t1)
$t2, 8($t1)
$t2, $t2, $t3
$t3, $t1, $t2
#1
#2
#3
#4
#4
4. The forwarding unit performs the following checks to detect a hazard in which data is forwarded
from the MEM/WB interstage buffer, or more specifically, the multiplexor controlled by the
MemtoReg signal.
COMPSCI 458: Computer
Architecture
Handout: Pipelined Datapath
Fall 2025, Jerald Thomas
// Check for Register Rs (Check for Rt is similar)
//
if (MEM/WB.RegWrite
// Condition #1
and (MEM/WB.RegisterRd != 0)
// Condition #2
and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd !0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRs))
// Condition #3
and (MEM/WB.RegisterRd = ID/EX.RegisterRs)
// Condition #4
a. Why should the forwarding unit check condition #1? Be precise.
b. Why should the forwarding unit check condition #1? Be precise.
c. Why should the forwarding unit check condition #1? Be precise.
d. Why should the forwarding unit check condition #1? Be precise.