Introduction
i.
Computer Architecture and Organization
ii.
Number system and Binary Arithmetic
iii.
assembly language.
Design of instruction sets:
i.
Classification of instruction sets architectures
ii.
Characteristics and functions
iii.
Memory addressing
iv.
Encoding an instruction set
v.
data path, hardwired control and microprogramming.
Memory hierarchy:
i.
The Memory System and its Organization
ii.
Memory hierarchy, Organization of internal memories
iii.
Cache memories, Memory Management.
iv.
External and Virtual memory organization and its management,
v.
paging and segmentation.
vi.
Associative memories and caches
vii.
memory design and analysis.
Reduced Instruction Set Computer (RISC)
Architectures:
i.
Analysis of instruction execution for code generated from high-level language
programs
ii.
Compiling for RISC architectures
iii.
Main characteristics of RISC architectures
iv.
RISC, CISC trade-offs.
Look ahead systems and pipeline computers:
i.
Systolic arrays.
ii.
Complex and reduced instruction set processors.
Instruction Pipelining:
i.
Organization of pipelined UNITS
ii.
pipeline hazards
iii.
Reducing branch penalties
iv.
Branch prediction strategies
v.
Data and Control hazards
vi.
Hardware support. Superscalar
Architectures:
i.
Instruction level parallelism and machine parallelism
ii.
Hardware techniques for performance enhancement
iii.
Data dependencies
iv.
Policies for parallel instruction execution
v.
Limitations of the Superscalar approach.
Fault tolerant computing:
i.
Overview of fault tolerant Computing
ii.
Hardware Fault-Tolerance,fault masking
iii.
dynamic recovery, software fault tolerance.
iv.
Long-Life, Unmaintained Computers.
v.
Ultra-dependable Real-Time Computers.
vi.
High availability computers and Validation of fault tolerance.