Quantus Extraction Users Manual
Product Version 20.11
April 2020
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Quantus Extraction Users Manual
Table of Contents
Contents
1
Preface
15
15
Quantus Product Licensing
Supported Operating Systems
Software Installation
Configuring the Quantus UI
Typographic and Syntax Conventions
16
42
42
43
46
2
Quantus Introduction
47
47
Quantus Overview Flow
Required Inputs
Parasitic Extraction
Outputs
Quantus in the Overall Design Flow
Timing Closure
Signal Integrity Analysis
48
49
51
51
52
53
54
3
Running Quantus
56
56
Setting up the Environment
Design Input Restrictions
Starting Quantus
Creating a Command File
Specifying Distributed Processing
Specifying a Temp Directory
Specifying the Log File Name
Specifying State File Locations
Specifying Techgen Compilation Restriction
Specifying Crash Report Directory
Specifying Inputs
DEF Input
OA Input
Assura Input
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Pegasus Input
Calibre Input
Technology Files and Process Variation
Managing Process Corners
Sensitivity Extraction
Double Patterning Technology (DPT)
Parasitic Extraction
Selecting Nets to Extract
Resistance Extraction
Capacitance Extraction
Transistor-Level Inductance Extraction
Cell-Level Inductance Extraction
Hierarchical Extraction
Substrate Extraction with Quantus AoT
Obtaining Output
Setting up the Output
Supported Output Formats
DSPF Output
SPEF Output
SPICE Output
Extracted View Output
Smart View Output
OA Output
Output Reports
85
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4
Quantus Graphical User Interface
161
161
Accessing the Quantus GUI
Quantus UI and Assura LVS Input
Quantus UI and Pegasus/PVS Input
Quantus UI and Calibre LVS Input
Quantus Resistance Analysis
The Quantus Run Form
Setup Tab
Technology Selector and Rule Sets
Output Format
Spice Output
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Spice Options
Extracted View Output
LVS Extracted View Output
Smart View Output
Cell-level DSPF Output
DSPF Netlist Output
Cell-level SPEF Output
DSPF and SPEF Command Options
Transistor-level DSPF Output
Transistor-level SPEF Output
XDSPF and XSPEF Command Options
Extraction Tab
Extraction Type
Name Space
Resistance Commands
Non-Manhattan Resistance
Layer Setup Customization
Capacitance Commands
Inductance Commands
NET Selection Mode
How to Input Net Names
Quantus Field Solver Capacitance Extraction
Hierarchical Extraction
Filtering Tab
Netlisting Tab
Run Details Tab
Quantus Run Mode
Substrate Tab
The Command File
Standalone Quantus UI
Launching the Standalone Quantus UI
Running Standalone Quantus UI in Replay Mode
Standalone Quantus UI Restrictions
5
Substrate Extraction
304
304
Setup Substrate Extraction
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Substrate Tab - Substrate Extraction in Quantus AoT
Enabling Substrate Extraction
Substrate Technology Selection
Substrate Extraction Controls
Log Files
6
Quantus Substrate AC Analysis
322
322
Introduction
The Substrate Abstract View
Running Quantus Substrate AC Analysis
Quantus Substrate AC Analysis Menu and Form
Load Substrate Abstract View Form
Defining Details of the Design
Backside
Global Package Impedance
Define Region
Define Access Ports
Define External Nodes
Search
Saving the Substrate Abstract View
Surface Noise Distribution Analysis
Surface Noise Distribution Analysis
Computing a Surface Noise Distribution
Perturbing Path Analysis
7
Quantus Command-Line
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Quantus Command Syntax
Quantus Command-line Options
Restarting a Quantus Extraction Run
Cell-Level Extraction
Transistor-Level Extraction
Comparing Resistance and Capacitance
Examples
Output File Formats
Quantus Compatibility Modes
Standalone Quantus UI Command-line Options
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Quantus Command Files
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Introduction
Format of the Quantus Command File
Case Sensitivity of Commands
Included Command Files
Quantus Command Syntax and Input Restrictions
Command File Commands
capacitance
Description
Options
device_reduction
Description
Options
distributed_processing
Description
Standard Options
extract
Description
Options
extraction_setup
Description
Options
filter_cap
Description
Options
filter_coupling_cap
Description
Options
filter_res
Description
Options
global_nets
Description
Options
graybox
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Description
Options
hierarchical_extract
Description
Options
inductance
Description
Options
input_db
Description
Options
layer_blocking
Description
Options
log_file
Description
Options
metal_fill
Description
Options
mos_diffusion_parameter_extraction
Description
Options
output_db
Description
Options
output_setup
Description
Options
parasitic_reduction
Description
Options
process_technology
Description
Options
substrate_connection
Description
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Options
substrate_extract
Description
Options for Lightly Doped Substrates
Option for Heavily Doped Substrates
Example Quantus Command Files
DEF / DSPF Flow
DF2 / SPICE flow
GDS2 / DSPF flow
Substrate Extraction Flow
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9
Running Quantus with Pegasus and Calibre Inputs
Quantus with Calibre® Input
Calibre Rule Translation
Quantus Data Preparation
Calibre Database Query
Running Quantus with Calibre Input
Quantus with Pegasus/ PVS Input
Tool Flow
Pegasus Rule Translation
Quantus Data Preparation
Running Quantus with Pegasus Input
Creating an Extracted View from Pegasus and Calibre LVS Inputs
Libraries
The Device and Layer Control File (extview.rul)
Example extview.rul
The Transfer Property Control File (extview.trp)
Transfer Property File Format (trp_version_1)
Transfer Property File Format (trp_version_2)
Hierarchical Extracted View
Back Annotation and Cross-Probing
Back Annotation to the Schematic Net
Other Pegasus and Calibre Information
Blackbox Macrocells in a Flat Design
Changing Device Prefixes in the Netlist Output
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Quantus Capacitance Extraction Field Solver
About Quantus Capacitance Extraction Field Solvers
Quantus and Quantus Field Solver Extraction Combinations
Running Quantus FS
Using Pre-defined Accuracy Options
Using the Convergence Control Options
Using the Threshold Control Options
Use Model and Additional Scenarios
Guidelines for Running Quantus FS
Field Solver Extraction in the GUI Mode
Running Field Solver in the Distributed Mode
11
Standalone Reduction
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Introduction to Standalone Reduction
qreduce Options
Recommendations for Specifying Standalone Reduction Parameters
Reduction Accuracy
Frequency and Delay Based Reduction
Resistor Handling
Use Model Examples
Resistance and Capacitance Reporting
Pin-to-Pin Resistance Report
Net-to-Net Capacitance Report
Total Capacitance Report
Key Considerations
Device-to-Device Resistance Reporting
Standalone Reduction in the GUI Mode
The Input Files Tab
The Output Files Tab
The Report and Log Files Tab
The Advanced Settings Tab
The Canonical Devices Tab
Common Settings
Sample Log File
Sample Ouput Report File
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Voltus-Fi Hierarchical IR Drop and EM Analysis
Introduction to Voltus-Fi Hierarchical EMIR Analog on Top (AOT) Flow
Recommended CCL Setting for the Hierarchical EMIR Flow
Summary of the Hierarchical EMIR Flow
13
Checking Connectivity of Output
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752
Overview
Checking Connectivity of Output when Postprocessing is Used
14
sSPEF2SPEF Utility
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Converting the sSPEF netlist into SPEF format
Corner File for sSPEF2SPEF
Creating a Corner File from Two ICT Files
15
Using Wildcards with Quantus
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Regular Expression for DEF or OA Input
Wildcards and Regular Expression for Assura, Pegasus, or Calibre Input
Specifying Cell Names using Wildcards
Specifying Net Names using Regular Expressions
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767
768
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Setting Up the Quantus User Interface
771
771
Configuring the Quantus UI
Defining Quantus UI Templates
Common Features
Quantus Setup Form Layout
Quantus Setup Form - Setup Tab
Quantus Setup Form - Extraction Tab
Quantus Setup Form - Filtering Options Tab
Quantus Setup Form - Netlisting Options Tab
Quantus Setup Form - Run Details Tab
Quantus Setup Form: Substrate Tab
Using Skill to preset Assura DRC and LVS
Setting Fields Before Displaying Forms
Writing Information to the RSF File
Capturing Run Information
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Altering Form Field Values and Editability
Sample Program
SKILL User-Defined Program
Using Skill to preset Calibre Pre Run Form
Setting Fields Before Displaying Forms
Sample User-Defined Skill Program
Using Skill to preset the Quantus UI
Setting Fields Before Displaying Forms
Quantus Run Form
Sample Program
Quantus Run Form Fields
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814
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818
17
Maximum Operating Frequency
18
LPE Printing
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827
829
829
Overview
Use Model
lpe_confile for Multiple Devices
lpe_confile for SNA Support
Quantus Output with LPE Information
LPE Parameter Keywords
Description
830
830
832
832
833
834
834
19
3DIC Extraction
837
837
License Requirements
Micro-Bump Extraction for LEF/DEF Flow
Bump Mapping File Format
3DIC/TSV in Quantus Transistor-level Flow
Interposer Technology
TSV and Micro-Bump Extraction with Quantus model
TSV and Micro-bump Extraction with Pre-defined subckt Model
uBump Connectivity
TSV Via with Substrate Bottom Layer
Long TSV Extraction
LVS Requirements
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TSV Cc Model
Selectable TSV Model
TSV/uBump Stitching with Temperature Effects
Advanced 3DIC Packaging Technologies
Integrated FanOut 3DIC Extraction
Wafer-on-Wafer 3DIC Extraction
Through-Dielectric-Via (TDV) Extraction with Partial Second Ground for LEF/DEF Flow
Chip-on-Wafer-on-Substrate 3DIC Extraction
853
856
857
858
858
863
869
871
20
LVS Device Property Editing
877
877
Overview
Use Model
LVS Property Editing Functions
878
878
879
21
Appendices
883
883
Quantus and Quantus Field Solver Extraction Combinations
Mapping Quantus Commands to RCX Parameters
22
Glossary
Index
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Preface
1
Preface
Quantus Product Licensing
Supported Operating Systems
Software Installation
Configuring the Quantus UI
Typographic and Syntax Conventions
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Preface
Quantus Product Licensing
The following product configurations are available with Quantus:
Cadence Quantus Extraction L (QTS100) - This product includes both cell-level and
transistor-level extraction capabilities. It provides the accuracy required for analog and mixed
signal designs associated with the Virtuoso platform, and provides the performance required
for very large digital designs associated with the Innovus platform. It provides parasitic
extraction of resistance and capacitance from multiple process technology files, and supports
distributed processing on multiple machines or multiple processors. It is unlimited in terms of
transistors, but limited to 300,000 cell-level instances, and is best if Virtuoso is your platform of
choice.
Cadence Quantus Extraction XL (QTS300) - This product includes both cell-level and
transistor-level extraction capabilities. It provides the accuracy required for analog, mixed
signal, and RF designs associated with the Virtuoso platform, and provides the performance
required for very large digital designs associated with the Innovus platform. It provides
parasitic extraction of resistance and capacitance from multiple process technology files, and
supports distributed processing on multiple machines or multiple processors. This product
configuration has no limits on the size of transistor-level or cell-level designs that can be
extracted. In addition, this product also supports the manufacturing requirements of 65
nanometer technology, performs hierarchical transistor-level extraction, includes an integrated
Field Solver for more accurate capacitance extraction, adds inductance extraction, and also
performs integrated substrate extraction.
DFM_Core_Technology is a base license that comes with the QTS100 (L) and QTS300 (XL)
licenses. That is, if you have a QTS100 or a QTS300 license, you will automatically get a
DFM_Core_Technology license. This license is required to run Techgen and the ViewICT
utility.
The XL licensing scheme has the following options:
Cadence Quantus Advanced Analysis (AA) GXL Option (QTS310): The Quantus
Advanced Analysis GXL option (QTS310) covers all the existing XL/GXL features (See the
table titled, "Features of Quantus Product Configurations" for details). Each feature in Quantus
AA GXL option consumes one XL license per Quantus session and one Quantus AA GXL
option. For example, if you invoke both temperature sweeping and RLCK reduction (both AA
GXL option features) features at the same time, you require two Quantus XL licenses and two
Quantus AA GXL options. That is, one AA GXL option for each feature. If an XL license or a
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Preface
Quantus AA GXL option is not available, then Quantus exits with an error message.
Cadence Quantus Advanced Modeling (AM) GXL Option (QTS320): The Quantus
Advanced Modeling GXL option (QTS320) covers the advanced technology modeling
features (See the table titled, "Features of Quantus Product Configurations" for details). For
the features covered by Quantus AM GXL option, license checking is done for both the celllevel and transistor-level extraction. At the cell-level, some of the features (such as 3D
transistor device) may be available in just the advanced mode. However, as long as the
techfile supports that feature, even for the cell-level default mode, an XL license and an AM
GXL option are checked out. For example, though the techfile supports copper contacts and
cell-level extraction does not support copper contacts, still an XL license and an AM GXL
option are checked out.
You can use multiple features of the Quantus AM GXL option at the same time as this is
related to enabling the technology through the techfile. For example, you can use the 3D
transistor device and OPC table features in Quantus AM GXL option (QTS320) at the same
time. In this case, one XL license and one Quantus AM GXL option are checked out.
Cadence Quantus Display Technology (DT) GXL Option (QTS330): The Quantus Display
Technology GXL option (QTS330) is used to support the LCD feature in Quantus. The
Quantus LCD feature is activated explicitly in the Quantus technology file preparation by the
Techgen -simulation -non_planar option. When Quantus runs on a techfile that contains the
Techgen –simulation –non_planar option, then it checks out the XL license and the DT GXL
option. If the techfile contains both the –thick_substrate and -non_planar simulation
options, then Quantus checks out two XL licenses and two DT GXL options. This license
behavior holds true for both the Quantus (GDSII) and Quantus (LEF/DEF) flows. Even if
Quantus is run in the DP mode, it does not check out more DT GXL option licenses.
Consider the examples in the following table:
Techgen
Quantus
Licenses required
thick_substrate
Dual Bias
Contact
1XL license is required for dual bias contact.
thick_substrate
Advanced
Coupling
Inductance
2XL+1AA
April 2020
Reason: Advanced coupling will require 1XL+ 1AA GXL
option. One more XL license is required for inductance.
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thick_substrate
thick_substrate
Advanced
Coupling
Inductance
Field
Solver
3XL+1AA
meshR
1XL+1AA
Reason: Advanced coupling will require 1XL+ 1AA GXL
option. Two more XL licenses are required for inductance
and Field Solver.
Reason: 1XL + 1AA for meshR.
thick_substrate
non_planar
meshR
3XL+3DT
thick_substrate
non_planar
meshR
4XL+ 2DT+2AA
Advanced
Coupling
Reason: 1XL+1DT for thick_substrate, 1XL+1DT for
non_planar, 1XL+1AA for meshR, and 1XL+1AA for
Advanced Coupling.
Reason: 1XL + 1DT for each of the features.
Cadence Quantus Advanced Modeling20 (AM20) GXL Option (QTS520): The Quantus
Advanced Modeling20 GXL option (QTS520) covers the 20nm features. The 20nm features
require the check out of the XL license, the AM GXL option, and the AM20 GXL option. For
example, if you want to run parasitic extraction at 20nm, you require the AM20 license in
addition to the base license and the AM license. Like the AM license, only one single AM20
license needs to be checked out for one or more related features detected in a run. The
following is the list of the 20nm features:
LithoBias
Coplanar dielectric
Coplanar poly liner (that is, height_over ICT dielectric syntax).
Via Resistance Based on Via Overhangs
Double Patterning Technology (DPT) support
Note: Starting with the PVE 12.1.1 HF6 release, the licensing for the Raised Diffusion feature
has been changed from 20nm licenses (XL+AM+AM20) to 28nm licenses (XL+AM).
Cadence Quantus Advanced Node Modeling (AN) GXL Option (QTS530): The Quantus
Advanced Node Modeling GXL option (QTS530) is used to support Advanced Node
processes. The Advanced Node processes require the check out of the XL license, the AM
GXL option, and the AN GXL option. The license applies to all 16/14nm processes.
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For a single Quantus run (whether SP/DP or MPC) based on these advanced 16/14nm
processes, only one AN GXL option is checked out. The AN GXL option will cover both the
20nm features and 16/14nm features. The AM20 GXL option is not required in this case. That
is, Quantus 20nm features can work with the AN GXL option when the AM20 GXL option is
not available.
Cadence Quantus 32/28nm to 10nm Option (QTS600): The Cadence Quantus 32/28nm to
10nm Option (QTS600) is a consolidated license that is formed by the following licenses:
Cadence Quantus Advanced Modeling (AM) GXL Option (QTS320)
Cadence Quantus Advanced Modeling20 (AM20) GXL Option (QTS520)
Cadence Quantus Advanced Node Modeling (AN) GXL Option (QTS530)
The QTS600 license allows you to run designs from 32/28nm down to 16/14/12/10nm. The
license feature string is 32_28nm_to_10nm. The 32/28nm to 10nm features require the
checkout of the XL license and the QTS600 GXL option. This will enable 4 CPUs to perform
extraction. That is, you can run Quantus on 4 CPUs with a QTS300+QTS600 pair. For
example, you will need (two QTS300) + (two QTS600) for 8 CPUs.
The use model for QTS600 is as follows:
For a 32/28nm design, Quantus first checks for the availability of
the QTS320 license. If QTS320 is present, then that is used, otherwise QTS600 is used.
For a 22/20nm design, Quantus first checks for the availability of
the QTS320 + QTS520 licenses. If these licenses are not present as a whole or if one of
the licenses is missing, QTS600 is used.
For a 16/14/12/10nm design, Quantus first checks for the availability of
the QTS320 + QTS530 licenses. If these licenses are not present as a whole or if one of
the licenses is missing, QTS600 is used.
Cadence Quantus 7nm Option (QTS700): The Cadence Quantus 7nm Option (QTS700)
covers the 7nm features. The 7nm features require the checkout of the XL license and the
QTS700 GXL option. This will enable 4 CPUs to perform extraction. That is, you can run
Quantus on 4 CPUs with an XL+QTS700 pair. For example, you will need (two QTS300) + (two
QTS700) for 8 CPUs.
The QTS700 GXL licensing option allows you to run the 32nm, 28nm, 22nm, 20nm, 16nm,
14nm, 12nm, 10nm, and 7nm designs. Quantus will use the same use model as specified for
the QTS600 license to check for the appropriate licenses first before checking out QTS700 for
the 32/28/22/20/16/14/12/10nm designs only.
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Cadence Quantus 5nm and 4nm Option (QTS750): The Cadence Quantus 5nm and 4nm
Option (QTS750) covers the 5nm and 4nm features. The 5nm and 4nm features require the
checkout of the XL license and the QTS750 GXL option. This will enable 4 CPUs to perform
extraction. That is, you can run Quantus on 4 CPUs with an XL+QTS750 pair. For example,
you will need (two QTS300) + (two QTS750) for 8 CPUs.
The QTS750 GXL licensing option allows you to run the 32nm, 28nm, 22nm, 20nm, 16nm,
14nm, 12nm, 10nm, 7nm, 5nm, and 4nm designs. Quantus will use the same use model as
specified for the QTS600 license to check for the appropriate licenses first before checking out
QTS750 for the 32/28/22/20/16/14/12/10/7nm designs only.
Cadence Quantus 3nm Option (QTS753): The Cadence Quantus 3nm Option (QTS753)
covers the 3nm features. The 3nm features require the checkout of the XL license (QTS300)
and the QTS753 GXL option. This will enable 4 CPUs to perform extraction. That is, you can
run Quantus on 4 CPUs with an XL+QTS753 pair. For example, you will need (two QTS300)
+ (two QTS753) for 8 CPUs.
The QTS753 GXL licensing option allows you to run the 32nm, 28nm, 16nm, 14nm,
12nm,10nm, 7nm, 5nm, and 4nm designs. Quantus will use the same use model as specified
for the QTS600 license to check for the appropriate licenses first before checking out QTS753
for the 32/28/16/14/12/10/7/5/4nm designs only.
Cadence Quantus FS Megascale GXL Option (QTS315) - This license option allows to run
Quantus FS on 8 CPUs for every license. Quantus will use the 2(n+2) scaling rule for the
license option check out, where n is the number of QTS315 license options to be checked out.
For 5 to 8 CPU Quantus FS run, n = 1. That is, you need 1 x QTS315 license option. Similarly,
for 16 CPU Quantus FS run, n=2. That is, you need 2 x QTS315 license options. This option
allows you to run Quantus FS on a maximum of 1024 CPUs, as shown below:
1 x QTS315 allows from 5 CPUs upto 8 CPUs
2 x QTS315 allows upto 16CPUs
3 x QTS315 allows upto 32CPUs
4 x QTS315 allows upto 64CPUs
5 x QTS315 allows upto 128CPUs
6 x QTS315 allows upto 256CPUs
7 x QTS315 allows upto 512CPUs
8 x QTS315 allows upto 1024CPUs
The massively parallel Quantus FS mode can be invoked using one of the following use
models:
distributed_processing -multi_cpu <no. of CPUs>
With this distributed processing mode, the massively parallel license option (QTS315)
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will be checked out depending upon the availability of this license option on the license
server.
Note: To invoke the massively parallel license options, the number of CPUs specified
must be greater than or equal to 5.
distributed_processing -multi_cpu
<no. of CPUs> -field_solver_config
<filename>
When this option is used with the -multi_cpu option, Quantus will use the CPU
configuration specified with the -multi_cpu option whereas Quantus FS will use the
CPU configuration specified with the -field_solver_config option.
Note: To invoke the massively parallel license options, the number of processes
specified in the config file must be greater than or equal to 5.
Cadence Quantus FS Gigascale GXL Option (QTS317) - This license option allows to run
Quantus FS on more than 1024 CPUs. This option is added on top of 8 x QTS315.
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When the Quantus FS distributing processing mode is enabled, the following licenses
will be checked out:
base licenses + QTS310 + a number of QTS315 licenses [ + one QTS317 ]
"Base licenses" are the technology process node-specific base licenses that align
with the general licensing scheme for a 4-CPU run. Details of base licenses are
provided below. If there are other non-FS features being turned on by the CCL
command file, the licenses related to that non-FS feature will be added on top of this
"base licenses".
Base Licenses
Following are the examples of base licenses required for different process nodes:
40nm and above node = (2 x QTS300 + 1 x QTS310)
32/28nm node = (2 x QTS300 + 1 x QTS310 + 1 x QTS320)
22/20/16nm node = (2 x QTS300 + 1 x QTS310 + 1 x QTS320 + (1 x QTS520 or 1 x
QTS530) or QTS600)
10nm node = (2 x QTS300 + 1 x QTS310 + 1 x QTS320 + 1 x QTS530)
7nm node = (1 x QTS300 + 1 x QTS310 + 1 x QTS700)
5nm node = (1 x QTS300 + 1 x QTS310 + 1 x QTS750)
4nm node = (1 x QTS300 + 1 x QTS310 + 1 x QTS750)
3nm node = (1 x QTS300 + 1 x QTS310 + 1 x QTS753)
The following are examples of the licenses required for the massively parallel feature
for different process nodes:
Example 1: to use 64CPUs for 16nm process nodes, you need the following:
Base license + 4 x QTS315 licenses = (2 x QTS300 + 1 x QTS310 + 1 x QTS320 + 1
x QTS530 + 4 x QTS315)
Example 2: to use 128CPUs for 7nm process nodes, you need the following:
Base license + 5 x QTS315 licenses = (1 x QTS300 + 1 x QTS310 + 1 x QTS700 + 5
x QTS315)
Example 3: to use 2000CPUs for 16nm process nodes, you need the following:
Base license + 8 x QTS315 + 1 x QTS317 licenses = (2 x QTS300 + 1 x QTS310 + 1
x QTS320 + 1 x QTS530 + 8 x QTS315 + 1 x QTS317)
Example 4: to use 2000CPUs for 7nm process nodes, you need the following:
Base license + 8 x QTS315 + 1 x QTS317 licenses = (1 x QTS300 + 1 x QTS310 + 1
x QTS700 + 8 x QTS315 + 1 x QTS317)
If the QTS315/ QTS317 licenses are not available, Quantus will use the multi-CPU licensing
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scheme. The number of CPUs used for license computation would then be determined by the
larger number of CPUs specified among the two CCL options, that is, -multi_cpu and field_solver_config. The licensing scheme is based on the number of CPUs used in the
following scenarios:
the number of XL licenses checked out x 2 = number of CPUs allowed for
16/14/12/10nm or older process nodes.
the number of (XL + QTS700) licenses checked out x 4 = number of CPUs allowed for
7nm process node.
the number of (XL + QTS750) licenses checked out x 4 = number of CPUs allowed for
5nm and 4nm process nodes.
the number of (XL + QTS753) licenses checked out x 4 = number of CPUs allowed for
3nm process node.
Quantus does not support backward licensing. Specific to this release, Quantus 20.1 will not
honor Quantus 19.1 or older licenses, and will only work with Quantus 20.1 licenses. That is,
the latest version of the software does not work with the older version of licenses. However,
the older versions of the software can work with the newer version of the licenses.
Each of the following features available in the XL (QTS300) license scheme requires one XL
license:
Inductance
Field Solver
Substrate Extraction
Hierarchical extraction
For example, if you use XL and want to use inductance and Field Solver at the same time, you need
to use two XL licenses. In addition, if you have two XL licenses, one for inductance and one for
Field Solver, then you should be able to run both jobs together on four machines. The AM GXL
option requires one XL license and one AM GXL option to run a feature that requires the AM GXL
option, and any of the above-mentioned features that require an exclusive XL license.
The following are examples of feature interlocking:
Features
April 2020
Licensing Requirement
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OPC-WEE (AM feature)
1 XL + 1 AM option
Reason: A GXL option must be paired with an XL
license.
OPC-WEE (AM feature) +
Cf/Cco (normal XL feature)
1 XL + 1 AM option
OPC-WEE (AM feature) +
Hierarchical Extraction
(requires an exclusive XL
license)
1 XL + 1 AM option
OPC-WEE (AM feature) +
Hierarchical Extraction
(requires an exclusive XL
license) + Field Solver (requires
an exclusive XL license)
2 XL + 1 AM option
Reason: AM option can share XL license with any
feature that requires an XL license.
Reason: 1 XL + 1 AM option is used for OPC-WEE.
Hierarchical Extraction will leverage the XL license
already checked out by the OPC-WEE feature.
Reason: 1 XL + 1 AM option is used for OPC-WEE.
Hierarchical Extraction will leverage the XL license
already checked out by the OPC-WEE feature.
However, one more XL license will be required for
Field Solver.
The following information is related to Product Numbers, and licenses for the various product
configurations.
Quantus Product Configuration and Licensing
Product Name
Product
Numbers
Key
Cadence Quantus Extraction L
QTS100
Virtuoso_QRC_Extraction_L1
Cadence Quantus Extraction XL
QTS300
Virtuoso_QRC_Extraction_XL
Cadence Quantus Advanced Analysis
(AA) GXL Option
QTS310
QRC_Advanced_Analysis
Cadence Quantus Advanced Modeling
(AM) GXL Option
QTS320
QRC_Advanced_Modeling
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Cadence Quantus Display Technology
(DT) GXL Option
QTS330
QRCX_Display_Technology_Option
Cadence Quantus Advanced Modeling20
(AM20) GXL Option
QTS520
QRC_Advanced_Modeling_20
Cadence Quantus Advanced Node
Modeling (AN) GXL Option
QTS530
QRC_Advanced_Node_Modeling
Cadence Quantus 32/28nm to 10nm
Option
QTS600
32_28nm_to_10nm
Cadence Quantus 7nm Option
QTS700
Advanced_sub_10nm_modeling
Cadence Quantus 5nm and 4nm Option
QTS750
Advanced_sub_5nm_modeling
Cadence Quantus 3nm Option
QTS753
Advanced_sub_3nm_modeling
Cadence Quantus FS Megascale GXL
Option
QTS315
massively_parallel_FSmegascale
Cadence Quantus FS Gigascale GXL
Option
QTS317
massively_parallel_FSgigascale
1
Each of the license keys for these products is a single job execution license.
Note: In earlier Quantus releases, Quantus used an exchange mechanism to consume two L-level
licenses as equivalent to a single XL license. However, starting with the EXT 9.1 release, license
stacking is no longer allowed.
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Node Size Modeling Licensing Scheme
QTS-L(QTS100) is required for nodes > 65nm (90nm and above)
QTS-XL(QTS300) is required for nodes > 32/28nm (45/40nm and above) and/or any
QTS-XL process feature being used (see the table titled, "Features of Quantus Product
Configurations" for details)
QTS-XL(QTS300) + QTS-AM(QTS320) is required for 32nm/28nm. If QTS320 is not
present, then QTS600, QTS700, QTS750, or QTS753 can be used.
QTS-XL(QTS300) + QTS-AM(QTS320) + QTS-AM20(QTS520) is required for
22/20nm. If these licenses are not present as a whole or if one of the licenses is
missing, then QTS600, QTS700, QTS750, or QTS753 can be used.
QTS-XL(QTS300) + QTS-AM(QTS320) + QTS-AN(QTS530) is required for 16nm/14nm
and 12nm/10nm. If these licenses are not present as a whole or if one of the licenses is
missing, then QTS600, QTS700, QTS750, or QTS753 can be used.
QTS-XL(QTS300) + QTS700 is required for 7nm. If QTS700 is not present, then
QTS750 or QTS753 can be used.
QTS-XL(QTS300) + QTS750 is required for 5nm. If QTS750 is not present, then
QTS753 can be used.
QTS-XL(QTS300) + QTS753 is required for 3nm.
The following table outlines at a high level which features are available with each product
configuration.
Features of Quantus Product Configurations
List of Features
Unlimited Transistor
April 2020
QT
S1
00
QT
S3
00
QT
S3
00
+
QT
S3
10
QT
S3
00
+
QT
S3
20
QT
S3
00
+
QT
S3
30
QT
S3
00
+
QT
S3
20
+
QT
S5
20
QT
S3
00
+
QT
S3
20
+
QT
S5
30
QT
S3
00
+
QT
S7
00
QT
S3
00
+
QT
S7
50
QT
S3
00
+
QT
S7
53
X
X
X
X
X
X
X
X
X
X
26
QT
S3
15
QT
S3
17
Supported
Command(s)/
Options
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300K Cell Instance
Limit
X
Unlimited Cell
Instances
Distributed
Processing 1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Quantus FS
Massively Parallel
Multiple Process
Corners2
Calibre ® Input
Wire Edge
Enlargement
OD WEE
Separate bias for
Capacitance and
Resistance
April 2020
distributed_proc
essing
(in Quantus
command file)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
27
X
distributed_proc
essing
-multi_cpu | field_solver_con
fig
(in Quantus
command file, for FS
run)
process_technolo
gy
technology_libra
ry_file
file_name
-technology_name
techName
technology_corne
r corner1
corner2 corner3
(in Quantus
command file)
See
Running Quantus
with Pegasus and
Calibre Inputs.
wire_edge_enlarg
ement
wire_edge_enlarg
ement_r
wire_edge_enlarg
ement_c
(in ICT file)
wire_edge_enlarg
ement
wire_edge_enlarg
ement_r
wire_edge_enlarg
ement_c
(in ICT file)
wire_edge_enlarg
ement_r
wire_edge_enlarg
ement_c
(in ICT file)
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Virtual Metal Fill
metal_fill (in
ICT), and
metal_fill –type
VIRTUAL
(in Quantus
command file)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
temp_tc1 value1
temp_tc2 value2
(in ICT file)
X
X
X
X
X
X
X
X
X
X
wire_thickness_r
atio
(in ICT file)
Wire Bottom
Etching 3
X
X
X
X
X
X
X
X
X
X
wire_bottom_etch
ing
(in ICT file)
Mathematical RC
Reduction
X
X
X
X
X
X
X
X
X
X
Temp dependent
Resistance
Thickness f(density)
Frequency/Delaybased Mathematical
RC Reduction
X
parasitic_reduct
ion –
enable_reduction
true
(in Quantus
command file)
parasitic_reduct
ion –
enable_reduction
true
-selection_file
<file containing frequency/delay_rel/delay_abs options>
(in Quantus
command file)
M-Factor Reduction
Pegasus- Quantus
LVS Extracted View
Flow
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
device_reduction
-m_factor
(in Quantus
command file)
output_db –type
extracted_view
(in Quantus
command file)
Note: Quantus
supports both PVS
and Pegasus LVS.
M-Factor Keep R
April 2020
X
X
X
X
X
X
28
X
X
X
device_reduction
m_factor_keep_re
s
(in Quantus
command file)
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Explicit Via Effect
min_top_encl
value
min_bot_encl
value
min_width value
min_spacing
value
via_top_enlargem
ent value
via_bottom_enlar
gement value
(in ICT file)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
width_dependent_
tc
(in ICT file)
X
X
X
X
X
X
X
X
X
wire_thickness_r
atio
(in ICT file)
X
X
X
X
X
X
X
X
X
Gate Contact Cap
(Cco)
X
X
X
X
X
X
X
X
X
Gate Diffusion
Fringe Cap (Cf)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Resistivity f(w,s)
Temp f(w)
Thickness f(d,w)
Loading Effect
Gate Diffusion
Inverse Fringe Cap
(Cfi)
Hierarchical
Extraction
April 2020
29
resistivity
[value1 width1
value2
width2 ... ] |
rho_widths W1
... Wn
rho_spacings S1
... Sx
rho_values RW1S1
.... RWnS1
(in ICT file)
loading_effect
(in ICT file)
via_edge_enlarge
ment
(in ICT file)
extract
extract_gate_dif
fusion_fringing_
cap
and
gate_diffusion_f
ringing_cap
(in Quantus
command file)
gate_diffusion_f
ringing_inverse_
cap
(in ICT file)
hierarchical_ext
ract
hierarchical_cel
l_list_file
filename
(in Quantus
command file)
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Deterministic FS
X
Probabilistic FS 4
Transistor-level
Inductance
Topological Corner
TC1/TC2 Printing
CMP Extraction
Thermal Map
Resistance
Extraction
Litho Aware
Extraction
Mesh Resistance 5
April 2020
X
X
X
X
X
X
X
X
X
Cell-level
Inductance
Substrate Extraction
X
X
–
field_solver_typ
e probabilistic
option in the CCL
command file (for
transistor-level flow)
X
X
X
X
X
X
X
X
X
X
extract -type
rlc_*
extract -type
rlck_*
(in Quantus
command file)
extract -type [
rlc_decoupled |
rlc_coupled]
(in Quantus
command file)
X
X
X
X
X
X
X
substrate_extrac
t
(in Quantus
command file)
enable_corner_re
laxation
(in Quantus
command file)
X
output_db
include_parasiti
c_res_temp_coeff
(in Quantus
command file)
X
process_technolo
gy -erosion_file
(in Quantus
command file)
X
process_technolo
gy thermal_map_file
(in Quantus
command file)
X
Litho Configuration
File, Contour
Directory
X
X
extract selection use_field_solver
(in Quantus
command file)
extraction_setup
-resistance_mesh
(in Quantus
command file)
X
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Split Wide Mosfet6
X
device_reduction
-split_wide_mos
(in Quantus
command file)
Via Mesh
Resistance
X
extraction_setup
–
resistance_mesh_
via_layers
(in Quantus
command file)
Merge Vias by Layer
Advanced Coupling
X
X
X
X
X
X
X
X
X
X
capacitance –
coupling
advanced
(in Quantus
command file)
X
Sensitivity Extraction
sSPEF2SPEF
extraction_setup
max_via_array_si
ze_by_layer
“<layer>
[<size>|auto]”
[“<layer>
[<size|auto>]” …
]
extraction_setup
–
max_via_array_co
unt_by_layer
“<layer>
<count>”
[“<layer>
<count>”… ]
(in Quantus
command file)
X
X
X
X
X
X
X
X
X
X
X
X
extraction_setup
enable_sensitivi
ty_extraction
(in Quantus
command file)
sSPEF2SPEF [ -v
-V ]
-corner
cornerFile
cornerName
sSPEF_in
SPEF_out
See sSPEF2SPEF
Utility.
Substrate Contour
Map
April 2020
X
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RLCK Reduction
Turbo Reduction
RDL-GDS+DEF
Dual Poly
OPC-WEE
April 2020
input_db -type
def
input_db -type
gds
(in Quantus
command file)
X
3D transistor
devices
Copper contact
parasitic_reduct
ion
-reduction_level
(in Quantus
command file)
X
Via size-dependent
temperature
coefficients
3DIC extraction
extract -type
rlc_*
extract -type
rlck_*
parasitic_reduct
ion
enable_reduction
true
(in Quantus
command file)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
area_dependent_t
c
temp_areas
temp_tc1
TC11......TC1k
temp_tc2
TC21......TC2k
(in ICT file)
See Creating the
ICT File.
See 3DIC Extraction
and "Techgen
Interface Simulation
Command" in
Techgen
Commands.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32
M0,V0 stack. See
Creating the ICT
File.
See
Layer Setup File
Mapping for Dual
Poly Structures.
higher_order_wir
e_edge_enlargeme
nt order
higher_order_wir
e_edge_enlargeme
nt_[r|c] order
(in ICT file)
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Dual Bias
X
X
Slot via modeling for
short vias
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Slot via modeling for
long vias
Equation-based
Resistance
X
X
See section "Dual
Contact Biasing" in
Creating the ICT
File.
slot_via_short_e
dge
<short_side_in_u
m>
[<short_side_in_
um>]
slot_via_long_ed
ge
<long_side_in_um
>
[<long_side_in_u
m>]
slot_via_short_e
dge_enlargement
<bias_in_um>
[<bias_in_um>]
slot_via_long_ed
ge_enlargement
<bias_in_um>
[<bias_in_um>]
(in ICT file)
slot_via_short_e
dge
<short_side_in_u
m>
[<short_side_in_
um>]
slot_via_long_ed
ge
<long_side_in_um
>
[<long_side_in_u
m>]
slot_via_short_e
dge_enlargement
<bias_in_um>
[<bias_in_um>]
slot_via_long_ed
ge_enlargement
<bias_in_um>
[<bias_in_um>]
(in ICT file)
extraction_setup
enable_diffusion
_resistance_equa
tions (in Quantus
command file)
res_equation_thr
eshold_*,
res_tcl_equation
(in ICT file)
Standalone
Quantus UI
April 2020
X
X
X
X
X
X
X
33
X
X
X
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Thick Substrate
Techgen thick_substrate
(in Quantus
command file)
Note: The
thick_substrate
option will check out
1XL + DT license
only when it is used
along with Techgen
–si –non_planar
option.
Non-Planar Process
Non- Manhattan
resistance
Diffusion/OD
Coplanar Dielectric
Double Patterning
Technology (DPT)
extraction_setup
nonmanhattan_res
istance
(in Quantus
command file)
X
LithoBias
Raised
Techgen non_planar
(in Quantus
command file)
X
X
X
X
X
X
Techgen –
simulation –
retargeting
(in Quantus
command file)
raised_diffusion
(in ICT file)
X
X
X
X
X
X
X
X
X
X
X
dielectric name
(in ICT file)
max_shift
variable_dielect
ric_constants
(in ICT file)
custom_dpt_corne
r
corner_definitio
n_file_name
enable_dpt_color
_import[ true |
false]
(in Quantus
command file)
Via Resistance
Based
on Via Overhangs
April 2020
X
X
34
X
X
X
overhang_depende
nt_via {
...
via_resistance
res1 res2 res3
...
(in ICT file)
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Fracture Vias
X
fracture_vias
{true | false}
(in ICT file)
X
X
X
X
X
X
X
X
X
X
14/16nm advanced
process nodes
X
X
X
X
See FinFET
Technology.
10nm Color WEE
Table
X
X
X
X
wire_edge_enlarg
ement_by_color
(in ICT file)
Poly Liner
(height_over)
height_over
(in ICT file)
See Advanced Node
Modeling
10nm DPT
X
X
X
X
conductor_silico
n_spacing
(in ICT file)
See Advanced Node
Modeling
10nm Erosion Table
X
X
X
X
wtr_silicon_widt
h_ranges
wtr_density_clam
ping_width
wtr_density_clam
ping_max
wtr_density_clam
ping_min
wtr_max
wtr_min
(in ICT file)
See Advanced Node
Modeling
Poly over diffusion
edge rule
X
X
X
X
See FinFET
Technology.
Width/Length
dependent Liner
dielectric
X
X
X
X
See FinFET
Technology.
X
X
X
X
Integrated Virtual
Metal Fill13
X
L/W dependent
gate resistance
Signoff ECO
(Incremental
Quantus Extraction)
Macro Cell Graybox
Flow
April 2020
X
extraction_setup
-enable_eco_mode
(in Quantus
command file)
X
graybox –type
layout
(in Quantus
command file)
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7nm advanced
process nodes
X
X
X
5nm advanced
process nodes
X
X
4nm advanced
process nodes
X
X
3nm advanced
process nodes
X
Color-Dependent
Width Bias Modeling
for Many Colors
X
X
X
See Advanced Node
Modeling
Color-Dependent
Conductor
Thickness and
Erosion Table
X
X
X
See Advanced Node
Modeling
Voltus-Fi
Hierarchical EMIR
Analog on Top Flow
X
extraction_setup
macro_cells_type
white
input_db libgen_library_n
ame <file_name>
(in Quantus
command file)
Advanced Adaptive
Mesh Resistance
Extraction
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extraction_setup
-resistance_mesh
_automatic_size
(in Quantus
command file)
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Incremental
Techgen
X
process_technolo
gy
incremental_tech
nology_library_f
ile <filename>
incremental_tech
nology_name
<techname>
incremental_tech
nology_corner
<corner1>
<corner2>...
OR
process_technolo
gy
incremental_tech
nology_directory
<techpath>
(in Quantus
command file)
Point-to-Point
Resistance Analysis
X
Standalone
Reduction
X
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qreduce -type
dspf [options]
input.dspf
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1
For distributed processing, the number of licenses required = (X/2) rounded up to a whole
number, where X is the number of machines or processors required to run the application.
For example, 5 machines requires three licenses (5/2 rounded up). The Quantus GXL
options use the Quantus XL licenses (NOT L licenses) for distributed processing. For
example, for a feature that uses a Quantus GXL option, if you request 3 CPUs, then
Quantus will check out 2 XL licenses and 1 Quantus GXL option.
In Quantus, multi-CPU licensing is not considered as "feature" licensing. The overall
number of XL licenses is determined by:
max(Number of XL due to rounded up (Number of CPUs/2), Number of XL due to
features)
In 9.1.x releases prior to EXT 9.1.4 HF1, if you have 1 L license and 1 XL license you can
run one L feature on 2 machines and 1 XL feature on 2 machines. This means that even if
1 XL license is available, it will not be consumed together with the 1 L license to run the
feature on 4 machines. Starting with EXT 9.1.4 HF 1 release, if you have 1 L license and 1
XL license, you can run an L feature on 4 machines.
Prior to the 11.1 release, when the number of CPUs/processes requested in an IQuantus
run was more than what the existing number of licenses could accommodate, IQuantus
exited with an error message. Starting with the 11.1 release, IQuantus is enhanced to
continue the extraction run by scaling down the number of CPUs/processes for the
number of XL licenses available. If no XL license is available at that time, then IQuantus
errors out with a proper message.
Distributed Processing Examples:
Example 1: if you use QTS300, and want to use inductance and Field Solver at the same
time, you need to use two QTS300 licenses. In addition, if you have two XL licenses, one
for inductance and one for Field Solver, then you should be able to run both jobs together
on four machines.
Example 2: if you use QTS310, and want to use two XL features (such as, Integrated
Virtual Metal Fill and Reduction) in the distributed processing mode (4 CPUs), then no
extra license would be checked out. You can run Quantus on 4 CPUs with the same 2 XL
licenses.
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2
Multi-corner extraction is restricted to five corners and applies to both L and XL licenses. If
you want to run more than five corners, then a second L or XL license is required. In
addition, the five corner limit per license is applicable to both transistor and cell level
extraction and to L and XL licenses.
From a licensing perspective, multi-corner extraction is treated as a feature, and checks
out its own L or XL license. It does not mean that if you already have an XL license for
another feature, you can run five corner extraction. You need to have a separate XL
license for multi-corner extraction.
As an example, for 6 corners if a Quantus run invokes an Advanced Analysis/Modeling
GXL feature, Quantus will check out 2 XL licenses and 1 GXL option.
For running Quantus in the multi-corner and distributed processing mode together, the
license modeling is (QTS-L or QTS-XL):
max (Rounded up(no of corners / 5) , Rounded up(no of CPUs / 2) )
For example, for 12 RC corners running on 4 CPUs:
12 RC corners -> 3 licenses
4 CPUs -> 2 licenses
12 RC corners on 4 CPUs -> 3 licenses (max(3,2) )
The following example illustrates how Quantus determines the number of XL licenses
based on features and multiple CPUs:
Integrated Virtual Metal Fill (IVMF): ON -> AA + XL
Turbo Reduction: ON -> AA + XL
Corners: 6 -> Additional license = (no. of corners + 4)/5 -1 = (10/5)-1 = 1XL
Therefore, the licenses for these features are 3XL + 2AA
CPU: 4 -> 2XL (2 CPUs require 1 license)
Final XL count: max(Number of XL due to rounded up (Number of CPUs/2), Number of
XL due to features)= max(2XL, 3XL) = 3XL
So, the final license count is: 3XL + 2AA
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For 65nm and below process nodes, both wire_bottom_etching (drawn) and
wire_bottom_etching (silicon) features require an XL license. For higher nodes, the
features require an L license.
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4
For the LEF/DEF or OA flow (cell-level extraction) and the LVS flow (transistor-level
extraction), Probabilistic FS is the default field solver for all process nodes. This FS mode
offers better performance, accuracy, and capacity. Probabilistic FS requires the QTS310
Advanced Analysis license (XL + AA).
For 28nm and above process nodes, you can invoke Deterministic FS by setting the extract
-field_solver_type option to deterministic, which requires only an XL license.
Deterministic FS is not supported for 20nm and below process nodes.
5
6
7
8
9
10
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If a qrcTechfile is created using the -thick_substrate option, and you want to use meshR
(functionality of Quantus), then during runtime Quantus checks out 1XL + 1AA license only
(for meshR functionality), and DT GXL option is not checked out. However, if meshR
option is used on a techfile created with -thick_substrate and -non_planar simulation
options, then during runtime Quantus checks out 3XL + 2DT + 1AA licenses (1XL + 1DT
for -thick_substrate, 1XL + 1DT for -non_planar, and 1XL+1AA for meshR).
In common use model, split mos is always used together with meshR, in that case only 1
XL + AA license is needed. If only split-wide-MOS feature is turned on, without meshR,
then also the XL + AA license is checked-out.
If the turbo reduction feature is turned on (-reduction_level option is set to default), it
requires an XL license and an AA GXL option. However, if a license is not available (that
is, all licenses are already checked out), Quantus will exit with an error message. If the
turbo reduction is turned off, then the AA GXL option is not required at all. Also, if the AA
GXL option is not installed in the license server, then the licensing code toggles the value
of the reduction_level option to off and checks out the XL license only.
For technology nodes higher than 32nm, Quantus requires an L license for the dual poly
feature. However, for 32nm and lower technology nodes, Quantus checks out an XL
license and an AM GXL option.
OPC-WEE is disabled for Turbo-Quantus (and AM license is not checked). OPC WEE can
be enabled (and license checked) for IQuantus and standalone Quantus.
The Equation-based Resistance feature, by default, is turned on (if the ICT file contains
the diffusion resistance equations) and checks out an XL license and an AM GXL option.
When this feature is explicitly turned off (enable_diffusion_resistance_equations false),
then these licenses are not checked out.
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12
13
The standalone Quantus UI requires an L license. When a Quantus job is submitted, the
UI releases the license. During the Quantus run, Quantus checks out whatever license(s)
it needs for its run, depending on the use models and technology modeling features used.
The UI then checks-out the L license again immediately after the Quantus job has
completed.
The non-manhattan_resistance CCL option when set to high_accuracy, requires an XL
license and a DT GXL option. However, if the qrcTechFile is created using the Techgen non_planar simulation option then this feature is automatically enabled and an additional
DT GXL option is not required.
Quantus checks out XL + AA license, when IVMF feature is invoked with the following
CCL option.
metal_fill –type virtual -enable_advanced_virtual_fill true
For IQuantus, when Innovus IVMF is turned on, XL+AA license is needed. Similarly, for
TQuantus, when Innovus IVMF is turned on, and external VMF rule files are used, XL+AA
license is needed.
Note: The Quantus licensing scheme applies to IQuantus as well.
14
The 90nm (or above) process nodes require only the QTS-L (QTS100) license regardless
of features, with the following exceptions:
If the qrcTechFile is created using the Techgen -non_planar simulation option, Quantus
requires the QTS-XL (QTS300) and DT GXL (QTS330) licenses.
For the non-qrcTechFile features, such as advanced coupling capacitance, meshR,
Quantus FS, and turbo reduction, Quantus requires the appropriate combination of
QTS-XL (QTS300) and/or AA GXL (QTS310) licenses.
Note: If the meshR option is used on a techfile created with the -non_planar simulation
option, then during runtime Quantus will check out 2 QTS-XL, 1 DT GXL (for non_planar
techfile), and 1 AA GXL (for meshR).
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The filter_res -merge_parallel_via option requires an additional AA license with the
Advanced Adaptive Mesh feature. Therefore, when both the extraction_setup resistance_mesh_automatic_size and filter_res -merge_parallel_via options are
specified, XL and 2AA GXL licenses are checked out.
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Supported Operating Systems
For the most recent information about specific versions of supported operating system and required
patches, please see the "Platform Support" matrix in the What's New document for the current
release.
Software Installation
Quantus and Techgen software installation follows the standard Cadence software
installation procedure. Please refer to the Cadence Installation Guide.
Note: The $PATH specified for Quantus executables is different from the $PATH specified in the
Cadence Installation Guide.
You must add Quantus and Techgen executables to your $PATH as follows:
​set path = ($path <quantus_install_dir>/bin )
​Quantus also requires the installation of the OpenAccess (OA) shared libraries and binaries.
The installation of OA usually occurs immediately following the installation of the Quantus
release. An <install_dir>/share/oa link is created when you execute the Configuration step
in InstallScape.
Please refer to the OpenAccess Installation and Configuration Guide for complete instructions
on installing and configuring OA for use with Techgen and Quantus.
When Assura and Quantus installations both appear in the path, the Quantus release must
appear in the path before the Assura release, and $ASSURAHOME must be correctly set in order
for both Quantus and Assura to run correctly. See the Assura Installation Guide for details on
defining $ASSURAHOME.
An Assura installation is required when running Quantus under the following circumstances:
You are using an Assura database as input for extraction,
You are creating an extracted_view for output,
You want to use the Quantus User Interface to run Quantus extraction from the Assura
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UI.
You want to use the Quantus Substrate AC Analysis feature which is launched from the
Assura UI.
The Assura LVS database to be used by Quantus must be created with (or be
compatible with) the version of Assura found in your $PATH.
To run Quantus from the Quantus UI, you must set the following environment variable before
launching Virtuoso:
setenv QRC_HOME <ext_install_dir>
You can run Quantus GUI only in the Virtuoso 64-bit mode. Quantus does not support the 32-bit
mode (batch and GUI). Therefore, Quantus GUI will not be available in the Virtuoso 32-bit or icfb
modes. Refer to the Setting Up the Quantus User-Interface chapter for more information.
Quantus uses large data structures and arrays for performance. You can set the stack size to
unlimited to prevent software crash. To set the unlimited stack size, execute the following
command from the UNIX command line:
limit stacksize unlimited
Configuring the Quantus UI
In EXT8.1 the Quantus user-interface is delivered in a stand-alone context file that is included in the
Quantus release. This breaks the dependency between Quantus and Assura releases for users of
the GUI. In this case, users of Cadence Pegasus and Mentor Graphics Calibre LVS tools do not
need to have Assura installed in order to use the Quantus UI.
The Quantus UI has dependencies on the IC release to load the Quantus menu into Virtuoso, the
Assura release when Assura input is used, and the Pegasus release when Pegasus input is used.
For more information on the various release versions required to support the Quantus UI, refer to the
What's New document for the specific release you are using.
Quantus supports both PVS and Pegasus LVS.
Note: Starting with the EXT10.1 release, for Assura-Quantus flow, you need Assura 4.1 USR1 HF9
or a later release to load the Quantus menu in Virtuoso. If you have an Assura version earlier than
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Assura 4.1 USR1 HF9, you must first load the aux_qrcui.cxt context file in .cdsinit or in the CIW
window as follows:
loadContext("path_to_file_location/aux_qrcui.cxt")
The aux_qrcui.cxt context file is found at the following locations in the Quantus installation
directory:
install_dir/tools/extraction/bin/64bit/etc/context/5.1.0/64bit/
install_dir/tools/extraction/bin/64bit/etc/context/6.1.0/64bit/
If you are using the Pegasus-Quantus or Calibre-Quantus UI flows without Assura, then it is not
required to manually load the aux_qrcui.cxt file, even though loading the context file will not
interfere with the Quantus UI in these flows.
Virtuoso Quantus Menu
To setup the stand-alone Quantus menu, you must define the QRC_HOME environment variable:
setenv QRC_HOME <ext_install_dir>
Where <ext_install_dir> represents the directory in which you have installed the EXT8.1 or later
releases.
Note: Starting with the EXT 10.1 release, for Assura-Quantus flow, you need Assura 4.1 USR1 HF9
or a later release for the stand-alone Quantus menu to appear in Virtuoso.
When the QRC_HOME environment variable has been set, the Quantus context file is automatically
loaded after the Virtuoso Layout Editor is invoked. This adds the Quantus menu into the Virtuoso
Layout Editor toolbar menu (see figure above), and also automatically loads SKILL code required
by ADE that is responsible for instantiating the substrate subckt in the Spectre netlist.
If the Virtuoso Layout Editor has not been invoked, then the SKILL code required by ADE for
instantiating the substrate subckt is not automatically loaded. When performing substrate analysis
or simulation including substrate netlist (extracted by Quantus) without invoking Virtuoso Layout
Editor, the context file must be manually loaded in Virtuoso Schematic Editor to make this SKILL
code available for use by ADE.
For manual loading, load the qrc.ini file that can be found at the following locations in the Quantus
installation directory:
install_dir/tools/extraction/bin/64bit/etc/context/5.1.0/64bit
install_dir/tools/extraction/bin/64bit/etc/context/6.1.0/64bit
Use the 5.1.0 versions of qrc.ini when using IC 5.1.x versions and the 6.1.0 versions of qrc.ini
when using the IC 6.1.x versions.
The Quantus menu has the following commands:
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Setup Quantus - allows you to define template files that contain default selections and valid
options available when running Quantus. Refer to "Defining Quantus UI Templates" for more
information on setting up Quantus UI templates.
Run Assura- Quantus - invokes the Quantus (Assura) Parasitic Extraction Run Form for use
with Assura LVS input. Refer to "Quantus Graphical User Interface," for complete details of the
Quantus Parasitic Extraction Run Form.
Note: This command is the same as the Run Quantus command from the Assura menu.
Run Pegasus-Quantus - invokes the Quantus (Pegasus) Parasitic Extraction Run Form for
use with Pegasus input data. See "Quantus Graphical User Interface," for more information on
running the Quantus UI with Pegasus input.
Run Calibre-Quantus - invokes the Quantus Parasitic Extraction Run Form for use with
Calibre input data. See "Running Quantus with Pegasus and Calibre Inputs", for more
information on running the Quantus UI with Calibre input.
Quantus SND Analysis - Invokes the Surface Noise Distribution Analysis form. See "Quantus
Substrate AC Analysis" for more information.
Note: This command is the same as the Quantus SND Analysis command on the Assura
menu.
In case the OA_HOME environment variable is set, then it is recommended to unset it for
Quantus run from UI.
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Typographic and Syntax Conventions
This document uses the following typographic and syntax conventions:
Commands, parameters, keywords, and actual filenames are shown in Courier font:
command_name
Variables for which you are to substitute a value are shown in Courier italic font:
filename, cellname, layer_name
Vertical bars (|) in commands indicate choices of one OR another.
Square brackets indicate that you must select one of the choices:
[a|b|c]
Square brackets followed by a plus sign indicate that you can choose more than one of the
choices, but you must select at least one:
[a|b|c]+
Use white space (tabs or spaces) to separate a command and its arguments.
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2
Quantus Introduction
Quantus Overview Flow
Required Inputs
Parasitic Extraction
Outputs
Quantus in the Overall Design Flow
Timing Closure
Signal Integrity Analysis
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Quantus Overview Flow
This chapter discusses the Quantus tool and data flow, and where Quantus fits into the overall
design process.
Quantus Inputs and Outputs
As integrated circuit device geometries shrink and clock speeds increase, the extraction and
simulation of parasitic resistance, capacitance and inductance assumes an increasingly important
role in physical verification and the production of successful silicon.
Closer physical geometries, faster clock and signal net switching speeds, and longer, thinner
interconnect lines can lead to increased parasitic capacitance, resistance and inductance values.
These parasitics can significantly degrade logic levels, delay clock and signal speeds, and
otherwise prevent a circuit from performing as designed. Quantus is an accurate, high-capacity,
high-performance cell and transistor-level parasitic extractor that is fast enough to use after every
detailed routing session.
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Required Inputs
Three-Dimensional Process Modeling and Techgen
Quantus uses a technology file, created from the fabrication process information, along with the
actual design data for resistance and capacitance extraction. The fabrication process information is
entered into an ASCII-format process description file from which Techgen generates a technology
file for Quantus (see the red boxes in the figure, "Quantus Inputs and Outputs"). The compiled
technology file contains a suite of three-dimensional adaptive analytical models that are generated
for each process description. This file contains interconnect models used by Quantus to extract the
interconnect parasitic resistance and capacitance for the design. For resistance extraction, it
contains resistance information for each interconnect layer and via; for capacitance extraction, it
contains three-dimensional interconnect models. See Quantus Techgen Reference Manual for
more information on defining the process description and running Techgen.
Design and Library Files
Quantus supports a variety of input formats for both design and library files. Each of these is
described briefly below.
LEF/DEF
Quantus takes a DEF file describing the design to be extracted, or multiple DEF files as input
(see the blue boxes in the figure, "Quantus Inputs and Outputs"). The DEF 5.7 standard is
supported to provide 45 nm and 65 nm enhancements.
In previous releases, if multiple DEF files were provided as input to Quantus, these files had
to be merged by using the MergeDEF utility prior to running Quantus.
Starting with the EXT 9.1 release, Quantus (at cell-level) has been enhanced to read multiple
hierarchical DEF files and generate a flat DSPF/SPEF file. Therefore, you do not need to run
the MergeDEF utility to merge the DEF files into a single flat DEF file. You can specify the
multiple hierarchical DEF files using the input_db CCL command. See input_db.
Note: Starting with the EXT 9.1 release, the MergeDEF utility is no longer available with
Quantus.
LEF library files defining the contents of each standard cell and megacell are required. The
library data can be contained in one or more LEF files in support of the DEF design files. If
there are duplicate VIA definitions for a via in the LEF (including multiple LEF files) file,
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Quantus will only take the first VIA definition of the via, and all the other duplicate via
definitions will be ignored.
Cell libraries, created by LibGen, can be used in place of LEF library files. The use of LibGen
is not required with Quantus, which reads LEF library files directly. However, existing libraries
are supported.
GDS input data can also be used to specify metal fill shapes to be used in association with
the DEF design input.
Quantus supports net/instance name length up to 16k characters in the LEF/DEF flow.
Pegasus and Assura LVS
Quantus also supports an Assura LVS or a Pegasus database, created as output of the
DRC/LVS run (see the cyanboxes in the figure, "Quantus Inputs and Outputs"). Both Assura
LVS and Pegasus also require the addition of an lvsfile, which is a mapping of the LVS
extraction rules into a format that can be used by Quantus for device extraction. See Quantus
Techgen Reference Manual for more information on defining the lvsfile.
Quantus supports both PVS and Pegasus LVS.
OpenAccess
Quantus reads and writes an OpenAccess database. The DM4 data model for OA is
supported.
Mentor Graphics Calibre®
Quantus also accepts input data files from Mentor Graphics Calibre LVS product. The details
of setting up the environment to run Quantus with Calibre input data are described in Running
Quantus with Pegasus and Calibre Inputs.
Dracula LVS
For Dracula-Quantus (dracToQRC) flow, use the Dracula LVS as your verification tool and
then use Quantus to generate the output netlist.
Note: The dracToQRC flow is used in the same manner as the Dracula To RCX flow. For
more information, refer to "Chapter 4: Extracting RC Parasitics" of the Dracula User Guide.
Quantus Command File
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The Quantus command file contains commands and variables used to control the nature of parasitic
extraction, and the type of output generated (see the yellow box in the figure, "Quantus Inputs and
Outputs"). A complete listing of the commands available for use in Quantus is located at Quantus
Command Files.
Parasitic Extraction
Quantus performs capacitance, resistance, and inductance extraction for both cell-level and
transistor-level designs. It supports digital, analog, and RF designs. It performs hierarchical and flat
extraction for the whole design or selected nets, for block-level or top-down design extractions.
During parasitic extraction, Quantus geometrically analyzes each conductor in all three dimensions,
generates parameters based on specific three-dimensional regions, then passes the parameters to
the technology file models for capacitance calculation. The models use an influence region or halo
to account for all lateral and multi-level interconnect capacitive effects, including the impact of
crossover fringe, corners, and capacitive shielding. The 3D extraction maintains both lumped and
fully distributed net-to-net coupled capacitance.
Resistance and inductance extraction are performed on design interconnect and vias based on
layer resistance properties defined in the technology file, and on fracturing and frequency rules that
you establish in the Quantus command file. The combined extracted parasitic RCLK networks are
then added to the design netlist for output to the selected format.
Outputs
Quantus also provides a variety of output formats (see the green boxes in the figure, "Quantus
Inputs and Outputs") to support different downstream applications.
DSPF/SPEF
Quantus supports output of both DSPF and SPEF delay netlists for timing calculation. In
addition, Quantus supports extended version of these two formats, providing additional
information for timing analysis and debug. Please refer to Supported Output Formats for more
information on these output formats.
SPICE
Quantus also provides both SPICE netlist output for use in design simulation with parasitic
elements added to the netlist.
DFII Extracted View
Quantus supports output of the DFII Extracted View for use with most of Cadence's suite of
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design and simulation tools.
OpenAccess
Quantus also provides OpenAccess outputs in cases where the design input was also an OA
database.
Quantus in the Overall Design Flow
The role of Quantus in signal integrity analysis and delay calculation is shown below.
Quantus in a Design Flow
Timing Closure
At 0.13um and below, signal delay due to interconnect parasitics becomes much more significant
than the contribution to signal delay due to the inherent cell delays. Approximately 80% of the delay
for most paths is now due to interconnect delays. The figure below illustrates the need for
considering parasitics to ensure correct circuit simulation results (a simple inverter circuit is
depicted).
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Therefore accurate modeling of the parasitics on the interconnects is vital for high performance chip
designs. Signal integrity analysis also requires accurate coupling capacitance extraction. However,
accuracy of parasitic extraction comes at a cost - in terms of run time for performing the extraction. It
is a function of design size, process, desired results, and the number and configurations of systems
that are available to do the extraction. Quantus responds to the industry's verification needs for a
fast, accurate three-dimensional RC extractor early in the design cycle.
Circuit Simulation Waveform Results With and Without Parasitics
Meeting timing constraints and resolving all timing violations in designs below 0.13 microns can
often take several iterations in the synthesis, placement, and routing loop. Extraction tools using
older two-dimensional or 2.5-dimensional extraction techniques can introduce a 25- to 100-percent
error in this loop, making over-design and conservative timing necessary to offset this inaccuracy.
Over-design can be costly, resulting in problems such as excessive power consumption, IR drop,
electromigration risk, unnecessary timing closure iterations, increased noise, and coupling delay.
The current generation of field solvers using three-dimensional extraction techniques is not
practical for timing closure because of long run times.
Signal Integrity Analysis
To use a simulation tool such as CeltIC NDC to predict noise effects between neighboring nets, first
use Quantus to extract coupled capacitance in order to retain coupling interactions between nets. If
parasitic capacitors are decoupled, the total capacitance of the net is preserved, but signal integrity
analysis is not achievable. Decoupled capacitance is appropriate when the Quantus output netlist
is input to a timing analysis tool or when the user wants to reduce the number of parasitic
components in the output netlist.
Coupling capacitance extraction accuracy is required to perform effective signal integrity analysis.
Quantus accurately models coupling capacitance values for use in Cadence's downstream delay
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calculator and signal integrity analyzer, CeltIC NDC, as well as other SPEF and DSPF signal
integrity flows.
Signal integrity problems can significantly impact design timing and functionality in nanometer
designs. When delay calculators such as Cadence's CeltIC NDC calculate delay, they include the
impact of IR drop, ground bounce, and crosstalk, in their calculations.
Coupling capacitance is a major contributor to signal integrity problems. When coupled signals
switch voltage, the capacitive coupling causes a charge injection, known as crosstalk, to occur.
Crosstalk impacts delay when a strongly driven net is highly coupled to a weaker driven net, and
both nets transition in the same timing window. In this case, when the strong driver (aggressor) net
switches, it injects charge onto the weaker (victim) net, which can impact the timing of the victim net.
If the aggressor and victim nets transition in opposite directions, the victim net is slowed, with the
charge injection working against the victim's transition, as illustrated in the below figure. In this
case, the effective coupling capacitance can be upwards of two times the extracted value.
Victim and Aggressor Nets Transitioning in Opposite Directions
If the aggressor nets and the victim nets transition in the same direction, the effective coupling
capacitance is reduced, enabling the victim net to transition faster.
Another effect of crosstalk is noise injection. When an aggressor net and a victim net transition at
the same time, the crosstalk impacts timing. When only an aggressor net transitions, the charge
injection causes a noise spike to be injected onto the victim net, as illustrated below.
Noise Injection on Victim Net
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Since noise, by definition, does not impact timing, noise analysis determines whether a noise glitch
will cause any logic failures. Logic failure typically occurs when the noise glitch is greater than the
threshold voltage of the input pin or input pins driven by the net. Since each input pin may have its
own tolerance to noise injection, any noise analysis must enable you to specify these tolerances.
Quantus supports distributed, lumped, coupled or decoupled RC extraction. It can generate SPEF
or DSPF files for use by CeltIC NDC for crosstalk analysis, delay calculation, and signal integrity
analysis.
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3
Running Quantus
Setting up the Environment
Design Input Restrictions
Starting Quantus
Creating a Command File
Specifying Distributed Processing
Specifying a Temp Directory
Specifying the Log File Name
Specifying State File Locations
Specifying Techgen Compilation Restriction
Specifying Crash Report Directory
Specifying Inputs
DEF Input
OA Input
Assura Input
Pegasus Input
Calibre Input
Technology Files and Process Variation
Managing Process Corners
Sensitivity Extraction
Double Patterning Technology (DPT)
Parasitic Extraction
Selecting Nets to Extract
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Resistance Extraction
Capacitance Extraction
Transistor-Level Inductance Extraction
Cell-Level Inductance Extraction
Hierarchical Extraction
Substrate Extraction with Quantus AoT
Obtaining Output
Setting up the Output
Supported Output Formats
DSPF Output
SPEF Output
SPICE Output
Extracted View Output
Smart View Output
OA Output
Output Reports
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Quantus is a command line tool with many commands to control details of extraction such as using
distributed processing, specifying the name and type of input file for the design data, the types of
extraction to perform, and the type of outputs to produce. This chapter touches briefly on all aspects
of the Quantus extraction flow. It does not list all of the commands available for use in
Quantus . See Quantus Command Files for details of all Quantus commands, whether discussed in
this chapter or not.
Setting up the Environment
Before you actually run Quantus, you must set various parameters on the command line and in a
command file. These settings will then determine how Quantus runs in the current session.
Design Input Restrictions
The format of the input design determines which of Quantus's many features will be available
during the extraction run. For instance, the extract -selection def_special_nets command is
only available when the design input format is DEF (input_db -type def).
There are many similar restrictions to Quantus commands depending upon the input data format.
These restrictions are centered around the design formats of DEF and OA on the one hand, or
Assura LVS and Pegasus on the other. In the text that follows, restrictions of the features of Quantus
to a specific input format are noted as follows:
This feature of Quantus only applies to DEF or OA design input.
or
This feature of Quantus only applies to LVS input (Assura, Calibre, or Pegasus).
If a feature does not have a specific limitation noted, then it is available for use with any input
design data format. The Command Syntax defined in Quantus Command Files lists the specific
Input Restrictions for every command and its options.
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Starting Quantus
Quantus is invoked on a shell command line (see Quantus Command-Line):
% quantus [-v|-h|-u] -lsf_number # -cmd < command_file >
Where:
-lsf_number # specifies that the Quantus extraction should be run across multiple
machines using LSF to manage the distributed processes.
-cmd < command_file > are a required keyword, and the path and file name of the
Quantus command file to be used during extraction. The keyword -cmd must always
precede the command file name.
Creating a Command File
Command File Inputs to Quantus
The Quantus extraction process is controlled through the use of a command file provided as input at
the time of execution. This is a simple ASCII file specifying the Quantus commands to be executed.
For a complete listing of available commands, and syntax conventions, see Quantus Command
Files.
Specifying Distributed Processing
The multi-processing capabilities of Quantus can be specified both from the command-line, or from
a command file. Quantus supports distributed processing on a single machine with multiple CPUs,
or from multiple machines, or using the Load Sharing Facility. See distributed_processing for more
information on these commands.
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Specifying a Temp Directory
Quantus writes files to a temporary directory. This can result in large temporary files which can
overflow the disk where the working directory is located. To specify an alternate temporary directory
add the following command to the command file:
output_setup -temporary_directory_name directory
Specifying the Log File Name
​You can set the name of the log file, by specifying the following command in the command file:
log_file -file_name filename
​ he default log file name is qrc.log written to the working directory from which Quantus was
T
executed.
Specifying State File Locations
Quantus allows you to set multiple directory locations for saving and loading state files. To enable
this feature, you must set the following environment variable before launching Virtuoso:
setenv QUANTUS_UIFORMS_STATE_DIR dir1:dir2:dir3
To separate directory names in the variable value, use the colon symbol ‘:’.
Example:
setenv QUANTUS_UIFORMS_STATE_DIR state1:state2
Note: The multiple directory locations for saving and loading state files that can be set include,
all the directories specified using the QUANTUS_UIFORMS_STATE_DIR variable, the current directory,
and your home directory.
When this variable is specified, the following features are enabled in the GUI:
The Load State dialog box will display all states located in the directories specified by the
QUANTUS_UIFORMS_STATE_DIR environment variable.
When you specify a state name and click OK in the Save State dialog box, the Choose State
File dialog box appears that allows you to save the state in one of the listed directories, as
shown below:
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When you select Run Pegasus - Quantus/ Run Calibre - Quantus options from the Quantus
menu, the Choose State File dialog box appears that allows you to load a state from one of
the listed directories, as shown below:
The list of directories in the Choose State File dialog box comes from the
QUANTUS_UIFORMS_STATE_DIR environment variable.
Specifying Techgen Compilation Restriction
Quantus lets you exit if the extraction version you are using is older than the Techgen compilation
version. This is done by setting the following environment variable:
QUANTUS_STRICT_VERSION_CHECK
When this variable is set to 1 and the extraction version being used is older than the Techgen
compilation version, Quantus will exit and print an error message.
Example:
setenv QUANTUS_STRICT_VERSION_CHECK 1
Specifying Crash Report Directory
Quantus allows you to specify a directory in which the crash report for all the Quantus transistorlevel executables is to be saved. This directory can be specified using the QUANTUS_CRASH_LOG_DIR
environment variable.
The crash report is saved in the Quantus run directory by default in the following format:
crashReport_<MMDDYY>_<HMS>_quantus_<version>_<username>_<hostname>.log
This environment variable can be used to alter the directory where the crash report is to be
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generated, as shown in the following example:
setenv QUANTUS_CRASH_LOG_DIR
/my/crash/log/directory
The crash report will have the following sections:
Stack trace (back-trace of the executable that crashed)
CCL file associated with this Quantus run
All the environment variables used in this job
This feature is supported only in the transistor-level flow for the Assura, Pegasus, and Calibre LVS
front ends, and all output formats.
Specifying Inputs
​ ​As shown in the figure, Command File Inputs to Quantus, Quantus requires one of three different
database types as input. These are a DEF file, an Assura LVS database, or an OpenAccess (OA)
database, containing the device placement and interconnect routing information of your design.
Quantus also requires a cell library containing the contents of the cells in the design, and a
technology file created by Techgen, containing information concerning the foundry process being
used.
All of this information is defined in the Quantus command-file specified on the command-line when
Quantus is executed. The command to specify the input database type is:
input_db -type [ def | assura | oa | pegasus | calibre | metal_fill ]
Each design format is discussed in greater detail below.
DEF Input
DEF Input with LEF Library Files and GDS Metal Fill
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input_db -type def
-design_file <filename>
-def_file_list_file <filename>
-lef_file_list <filename+> | -lef_file_list_file <filename>
-gds_file_list <filename+> | -gds_file_list_file <filename>
-libgen_library_name <filename>
Where:
-design_file <filename> specifies a single DEF file for use as the input design database.
-def_file_list_file <filename> specifies a file that contains a list of lower-level DEF files,
one filename per line. These files are for the child cells instantiated in the parent DEF file. The
parent DEF file is specified using the -design_file <filename> option.
You can specify the lower-level DEF files in any order.
-lef_file_list <filename+> refers to one or more LEF files that contain the cell definitions
for the design.
A list of files may also be predefined in a separate file, and defined with the alternate lef_file_list_file <filename> argument.
-gds_file_list <filename+> specifies a list of GDS files that contain layout data for cells
specified in the DEF design file to be used as gray data for capacitance extraction. The use of
this command allows both LEF and GDS input data to be read directly by Quantus and
completely eliminates the need for LibGen from the flow.
A list of files may also be predefined in a separate file, and defined with the alternate gds_file_list_file <filename> argument.
-libgen_library_name <filename> can be optionally used to specify LibGen created cell
library files (.cl).
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libgen_library_name is mutually exclusive with lef_file_list, and lef_file_list_file.
If width is not defined for a layer in the non-default rule in the LEF/DEF file, then Quantus will
assume the default width for that layer.
Note: Starting with the PVE 11.1.2 release, Quantus has been enhanced to support comments in
the files provided as an input to the -design_file, - def_file_list_file, -lef_file_list_file,
and -gds_file_list_file options. The comment lines should start with a pound-sign character "#"
(tab or space before # is allowed). Anything after # is considered a comment. You cannot use # in
the middle of a line if a non-space character exists before it. You can also have multiple comment
lines in a file.
Reading Library Files
Quantus supports the ability to read LEF and GDS files directly, called the LEF-in flow, or to read
LibGen created cell libraries (.cl files) called the LibGen flow. The following offers details of these
two flows for reading library files, and setting the graybox level for evaluation of the library data by
Quantus during extraction.
LEF-in Flow
Quantus supports LEF files, version 5.8 down to 5.1, as input for the macro cell definitions used in
the design. Quantus loads the pin information and obstruction data for each cell defined in the DEF
design file from the LEF files specified in the lef_file_list commands. The LEF files will be read
in the order presented in the command, and cells are processed as encountered and duplicate
definitions are ignored with a warning. The LEF/DEF files can be in a compressed (.gz) format.
You can also read layout data from GDS files by using the gds_file_list command to list one or
more GDS files which contain layout information for cells in the design. In this case Quantus will
obtain the abstract view of a cell from the LEF file and the layout view from the GDS file. GDS files
must be used together with LEF files because Quantus reads ports information only from the LEF
files.
The GDS files can be in a compressed (.gz) format. Top-level cells are mapped from the FOREIGN
or MACRO statements in the input LEF file. If duplicate top-level cells are defined (either in a single
GDS file, or across multiple GDS files) Quantus will offer a warning, and will use the first definition
of the cell.
Quantus reads hierarchical GDS files and attempts to do a file-based flattening of the hierarchy
when creating the library data. File-based flattening means that all the required sub-cells of the
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hierarchy appear in the file in which they are used. If a sub-cell is defined in one GDS file, but
instantiated in a cell defined in another GDS file, then file-based flattening is not possible, and
Quantus reverts to standard flattening as provided by LibGen.
With file-based flattening of the GDS hierarchy, Quantus can read duplicate sub-cells defined in
different GDS files, provided they are used hierarchically in the file in which they are defined. In the
figure, "Handling Dupliacte Cells", for example, the two occurrences of sub_21 are acceptable
because they are used in the top-level cells in the files in which they are defined.
However, because sub_23 is defined in file 2, but also used in file 1, file-based flattening will not
work, and so Quantus will revert to standard flattening of the GDS hierarchy. In this case, duplicate
sub-level cells in separate files are not supported, and Quantus will report a warning and will use
the first definition of the cell. In the example, cells sub_21 in file 1 and file 2 are marked as
duplicates and only the first definition of sub_21 is used.
Handling Duplicate Cells
The origins of the any GDS Files used files should match the origins of the LEF input, or the
GDS data may not properly align with the LEF data when read by Quantus. In this case,
extraction results may not be accurate.
Quantus matches the cells defined in the LEF files with cells defined in the GDS file through the use
of the FOREIGN statement in the LEF macro. If the FOREIGN statement is missing from the LEF,
Quantus will assume the GDS cell name is the same as the MACRO name. If a LEF macro cell has
multiple FOREIGN statements, then geometries of multiple GDS structures will be merged for that
cell.
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If the GDS and LEF cell names do not match, or the GDS names do not match the LEF FOREIGN
statements, you can manually map the cells though the use of the following command (see
"graybox"):
graybox -foreign_name_map <LEF_cellname> <GDS_cellname>
This command (or -foreign_name_map_file) allows you to specify an association between the
FOREIGN name (or MACRO name) of the LEF file to the cell name in the GDS file. You can also
use this command to redirect the LEF cell to a different GDS cell rather than the default if that is
desired.
When a GDS cell is not found as a match for the LEF cell (either FOREIGN or MACRO name), the
graybox -halt_on_missing_foreign_data true command will cause Quantus to abort extraction
with a fatal error. The default behavior is for Quantus to continue extraction, and issue a warning
regarding the missing cell data.
Starting with PVE 12.1.1 release, LEF 5.8 version is supported in Quantus. Quantus
supports FILL shapes referenced in the FILL LEF Macro. It checks the following class property and
flattens the macro geometries as metal fills.
LEF MACRO, PROPERTY LEF58_CLASS "CLASS COVER FILL ;" ;
LibGen Flow
To read the LibGen library, you must first run LibGen on LEF and GDS files to create the binary cell
library (.cl) file. For details on creating this cell library please refer to the VoltageStorm Data
Preparation Manual from the same release that you have obtained LibGen.
The use of LibGen is no longer required since Quantus can read LEF library files directly. As
a result of this, Libgen is no longer provided in the Extraction product release. If you still
desire to use LibGen with Quantus, you must get it from the SEV4.1 or later release, or the
ANLS6.1 or later release.
When you have access to the needed LibGen cell library, you can specify the library using the libgen_library_name command to read the cell library into Quantus.
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Graybox Evaluation
The Quantus graybox command establishes the level of detail of the design that Quantus will
examine during the extraction run (see "graybox"). This determines both the level of parasitics
extracted from the design, as well as the run-time performance of the extraction. In graybox
extraction, the shapes in a cell are considered grounded and used for capacitance extraction only.
Since it is seen by Quantus as gray data, no resistance will be extracted from the shapes in the
cells. Resistance is extracted only from routing and shapes of the top cell of the design.
By default, Quantus examines the layout level of detail for the design (graybox -type layout). This
requires the addition of GDS data for the cells.
If graybox is set to layout and the GDS data is missing for a cell, then Quantus will use the
obstruction data from the LEF input, and will report a warning. If the LEF obstruction data is missing
for a cell, then Quantus will view the cell as a blackbox and report a warning.
However, when using only LEF library data, without GDS, the graybox command should be set to
the LEF obstruction level (graybox -type lef_obstruction) to avoid warnings regarding missing
layout data. Specifying -type lef_obstruction indicates that the imported LEF obstruction data is
the limit of detail for the purposes of capacitance extraction.
The copy_port_to_gray command should only be used in Libgen when GDSII data is
available for all macros in the library. Otherwise it should be disabled. Libgen will copy the
LEF port data as layout data in the library file when the copy_port_to_gray command is
specified. If there is no other GDS data for the cell in the library file, the copied port data will
prevent Quantus from using the lef_obstruction data for that cell, and the capacitance
extraction will be incorrect. For more information please refer to the VoltageStorm Data
Preparation Manual .
You can also specify graybox -type none indicating that the cells should be viewed as black box
data. In this case, since shapes in the black box cells are not visible to Quantus, no capacitance or
resistance is extracted from these cells. The use of graybox -type none applies to all cells in the
design. However, you can use the graybox -type lef_obstruction and the graybox blackbox_cells_file commands together to specify that all cells should be viewed as graybox with
the exception of the cells specified as blackbox.
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Layer Mapping GDS and LEF/DEF Layers using -gds_layer_map
Since GDS files do not use layer names, if library data for cells is input from GDS files, then the
layer names in the design must be mapped to the GDS layer numbers using the following command
(see "extraction_setup"):
extraction_setup -gds_layer_map designLayer1 gdsLayer1 gdsDatatype1 ...
Where:
designLayer1 is a layer name as specified in either the LEF or DEF files.
gdsLayer1 is the layer number from the GDS file that is associated with the specified
designLayer .
gdsDatatype1 is the datatype of the GDS layer. You must specify <designLayer>
<gdsLayer> <gdsDatatype> together for a layer map.
`...' indicates that additional <designLayer> <gdsLayer> <gdsDatatype> sets can be
specified in the command.
Quantus will issue a warning message if it finds a GDS layer that has not been mapped to a design
layer. Note that you only need to map those layers that will be used for extraction.
If the LEF or DEF files used in the DEF flow contain layer names that are different from those found
in the technology file (as specified in the process description file), then these names must be
mapped with the following command:
extraction_setup \
-technology_layer_map \
designLayer1 techLayer1 ...
Where:
designLayer1 is a layer name as specified in either the LEF or DEF files. These names
may be different, in which case both layers will need to map to the associated layer in
the technology file.
techLayer1 is the layer in the technology file that is associated with the specified
designLayer .
`... ' indicates that additional designLayer techLayer pairs can be specified in the
command.
For instance, Metal1 in the DEF file is named Met1 in the LEF file, and these layers map
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to m1 in the technology file:
extraction_setup \
-technology_layer_map \
Metal1 m1 \
Met1 m1
If a ROUTING, CUT, or MASTERSLICE layer is defined in the LEF file but not used in the DEF file
and not defined in the technology file, Quantus will only issue a warning and continue extraction.
However, if any layer is referenced or used directly by the DEF file but not defined in the technology
file, a fatal error will occur and Quantus will terminate execution.
When a MASTERSLICE layer is being used as a logical termination point in a bump, or as a
passivation layer after the top metal layer in I/O cells in a LEF macro's OBS or PORT geometries
and this layer is NOT used in the DEF file, you should map the MASTERSLICE layer to the
reserved ICT file layer none in the command file:
extraction_setup \
-technology_layer_map \
<MASTERSLICE Layer> none
If the MASTERSLICE layer as POLY is used in a via definition and this via is used in the DEF file,
you must map the layer to the proper layer in the techfile:
extraction_setup \
-technology_layer_map \
<MASTERSLICE Layer> <ICT file Poly Layer>
Mapping Colored GDS/OASIS and LEF/DEF Layers
In the Quantus (LEF/DEF) flow, there are GDSII/OASIS files, which are used for gray shapes (of the
macro cells), and metal fills. For some advanced process nodes where DPT is used, the
GDSII/OASIS imports would require color information. The gray shapes and metal fill shapes are
specified in a list of GDSII/OASIS file names (that is, -gds_file_list/-oasis_file_list) and the
layer mapping is specified by the options: -gds_layer_map/-oasis_layer_map. If there is metal fill
data in the specified GDSII/OASIS library files, use -gds_fill_layer_map/-oasis_fill_layer_map
for metal fill shapes in the library to distinguish with gray data.
To import the color information from GDSII/OASIS, use the following options of the
extraction_setup CCL command:
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-gds_layer_map_by_color -|1|2 designLayer1 gdsLayer1 gdsDataType1 designLayer2
gdsLayer2 gdsDataType2 …
-gds_fill_layer_map_by_color -|1|2 designLayer1 gdsLayer1 gdsDataType1
designLayer2 gdsLayer2 gdsDataType2 …
-oasis_layer_map_by_color -|1|2 designLayer1 oasisLayer1 oasisDataType1
designLayer2 oasisLayer2 oasisDataType2 …
-oasis_fill_layer_map_by_color -|1|2 designLayer1 oasisLayer1 oasisDataType1
designLayer2 oasisLayer2 oasisDataType2 …
Note that only some layers would be DPT enabled. For color-based layer map, use “1” or “2” if the
layer is colored, or use “-” or "0" if the layer is not colored. For instance, if M2 is colored, and M5 is
uncolored in the design, then use the following CCL option:
gds_layer_map_by_color \
1
M2
32
1
2
M2
32
2
M5
35
1
The color-based GDS/OASIS layermap (including -gds_layer_map_by_color, gds_fill_layer_map_by_color, -oasis_layer_map_by_color, and oasis_fill_layer_map_by_color) is mutually exclusive with the non-color based
GDS/OASIS layermap (including -gds_layer_map, -gds_fill_layer_map, -oasis_layer_map,
and -oasis_fill_layer_map).
Layer Mapping GDS and LEF/DEF Layers using -stream_layer_map
The Quantus (LEF/DEF) flow provides a simple use model for layer mapping the GDS/OASIS and
LEF/DEF layers. Instead of using separate CCLs (9 CCL options) for specifying the cell library and
metal fill data, and the layer map for colored designs, you can use a single CCL (extraction_setup
-stream_layer_map or -stream_layer_map_file) for GDS/OASIS layer mapping.
The following table illustrates the link between the two use models for layer mapping:
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Stream
Layer mapping with -gds_layer_map
Layer mapping with -stream_layer_map
GDS
-gds_layer_map
-gds_fill_layer_map
-gds_layer_map_by_color
-gds_fill_layer_map_by_color
-gds_active_fill_layer_map
-gds_actve_fill_layer_map_by_color
-stream_layer_map
OASIS
Or
-stream_layer_map_file
-oasis_layer_map
-oasis_fill_layer_map
-oasis_active_fill_layer_map
The use model of the -stream_layer_map CCL option is:
stream_layer_map “<LEF-layer-name> <stream-layer-ID> <DT> <use-type> <color-ID> ”
<LEF-layer-name> is the LEF layer name in the design.
<stream-layer-ID> is the layer ID in the GDS/OASIS file
<DT> is the datatype of the layer in the GDS/OASIS file
<use-type> is the keyword for identifying the use of the data. The valid values are:
gray: library data in the GDS/OASIS file
fill: regular metal fill data in the GDS/OASIS file
active: active metal fill data in the GDS/OASIS file
<color-ID> is the color ID. Use 1, 2, 3, 4, 5, or 6 if the layer is colored, or use hyphen “-” if the
layer is not colored
“” quotes for each layer map is optional
Note: This feature is applicable only for the cell-level flow.
The following are two examples of the stream_layer_map option:
Non-colored
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-stream_layer_map \
M1 31 0 gray - \ <- library data
M1 31 1 fill - \ <- metal fill data
M1 31 7 fill - \ <- metal fill data
M7 37 15 active - \ <- active metal
fill data
M7 37 17 active - \ <- active metal
fill data
-stream_layer_map \
M1 31 0 gray - \ <- use '-' for non-colored
layers
M1 31 1 fill 1 \
M1 31 7 fill 2 \
M7 37 15 active 1 \
M7 37 17 active 2 \
For better readability, layer map must be specified per line, as shown in these examples. If a layer
exists in GDS/OASIS file but is not mapped, Quantus will issue a warning and ignore the layer.
If a layer ID is unique to “use-type”, you can use hyphen “-” as DT for that layer ID. In the following
example, layer ID 31 indicates metal fill data:
M1 31 1 fill - \
M1 31 7 fill -
-> “M1 31 - fill - ”
You can also specify a layer map in a separate file using the -stream_layer_map_file option:
extraction_setup \
-stream_layer_map_file “layermap.txt” \
The layermap.txt file contains the content of stream_layer_map, as shown below:
M1 31 0 gray M1 31 1 fill M2 32 0 gray M2 32 1 fill -stream_layer_map and –stream_layer_map_file are mutually exclusive.
Note: “\” is not required at the end of line for the layer map content inside the file.
Use Model 1: Layer Map for Top-Level Metal Fill
Use the input_db -type metal_fill -gds_file (or -oasis_file) CCL option to specify the toplevel GDS/OASIS metal fill file. The data found from this file will be treated as metal fill. You can
specify either -stream_layer_map or -stream_layer_map_file for layer mapping of top-level metal
fill data. If there are multiple top cells in the GDS/OASIS metal fill files, you must use the input_db metal_fill_top_cell option to specify the right metal fill top cell. If you do not specify this option,
Quantus will error out to ensure that the right top metal fill cell is used.
Example:
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input_db –type metal_fill –gds_file “DM.gds”
extraction_setup \
-stream_layer_map \
M1 31 1 fill - \
M2 32 1 fill - \
M2 33 7 fill - \
……
If metal fill is of the type active fill, use “active” for use-type.
Use Model 2: Layer Map for Block-Level Metal Fill and Library
Use the following options under the input_db -type def CCL option to specify the GDS/OASIS
files:
-gds_file_list | -gds_file_list_file | -oasis_file_list | -oasis_file_list_file
Files from the above list could be library files or metal fill files from the design blocks. One file may
include both the library data and metal fill data. You can specify either -stream_layer_map or stream_layer_map_file for layer mapping of block-level library and metal fill data. For activating the
GDS/OASIS input, you must set “graybox –type layout”.
Using the -stream_layer_map option, the block-level metal fill files are invoked from the original LEF
macro of each design block. While flattening the block DEF, if a metal fill cell exists in the blocklevel GDS/OASIS metal fill files and the metal fill cell name is found from the LEF macro of the
block DEF (or through -foreign_name_map), Quantus will flatten the metal fill cell to the
corresponding block DEF. You must use the same metal fill cell name in LEF under the FOREIGN
statement, or use -foreign_name_map to map the metal fill cell name.
Example:
input_db –type def –gds_file_list lib.gds block-A.gds block-B.gds
extraction_setup \
-stream_layer_map \
M1 31 0 gray - \ -> for “lib.gds”
M1 31 1 fill - \ -> for metal fill in “block-A.gds” and “block-B.gds”
M2 32 0 gray - \
M2 32 1 fill - \
M2 33 7 fill - \
……
Metal fill could be active fill as well. In such a case, use “active” for use-type. Data could be
colored. Use “1” or “2” for colored layers and use “-” for layers without color.
Use Model 3: Same Layer ID and DT for Different Use-Types
When all the metal fill data is in a single GDS/OASIS file, and the input_db -type metal_fill -
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gds_file (or -oasis_file) is used to specify the top-level GDS/OASIS metal fill file, the same layer
ID and DT can be used for different use-types (fill and gray). In this case, the data in the
GDS/OASIS files set under input_db -def will be treated as the gray data.
Example:
input_db -type metal_fill -gds_file “DM.gds”
input_db -type def -gds_file_list “blockA.gds”
extraction_setup \
-stream_layer_map \
M1 31 0 fill - \ -> for metal fill data in the top-level metal fill file “DM.gds”
M1 31 0 gray - \ -> for gray data in the library “blockA.gds”
M2 32 0 fill - \
……
If top-level metal fill is not set using input_db -type metal_fill -gds_file, and different use-type
is set for the same layer ID and DT, Quantus gives an error message stating that it cannot
distinguish between the metal fill data and gray data.
DEF 5.7 Support
Quantus accepts DEF, versions 5.7 down to 5.1, as input for design data. DEF 5.6 and 5.7 contain
many new constructs for handling 45-degree interconnect and polygons. The table below lists
certain new constructs of the DEF specification, and how they are supported by Quantus.
DEF 5.7 features
DEF Feature
Quantus Support
FILL adds VIAs and OPC
type
Supported
Multi PORT PINs
Keep only one PORT in *P section and include
additional PORTs as internal nodes in SPEF/DSPF
output.
PINs adds Via
Supported
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45 degree shapes in
BLOCKAGES, FILLS, and
SLOTS sections
Rectilinear polygons are broken into rectangles for
extraction.
45 degree shapes in PINS
section
Bounding box of pin created with a warning.
45 degree shapes in VIAS
section
Rectilinear via is broken into rectangles for
extraction.
Polygons with oblique edges are ignored with a
warning. The number of shapes ignored per section
is reported.
VIAS with oblique edges are approximated with
bounding box and a warning.
Generated Via Parameters
Supported
Nondefault Rules
Supported
X routing
NOT supported
Styles
NOT supported
Multiple pins
Supported
Rectilinear die area
Supported
Rotated Vias in Nets Routing
Section
Supported
Special Nets Enhancements
RECT construct supported.
Limited support for POLYGON construct - nets will
only be extracted in c_only_coupled mode.
Unit Values
Support for 10,000 unit value only. 20,000 unit value
will not be supported.
DEF Statement Order
Supported
Geometric Shapes Outside of
the Die Area
Supported
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Default values for Bus Bit,
Characters and Divider
Character
Supported
NAMECASESENSITIVE
OFF
Supported
Single-Layer Turn Vias
Supported
Note: Starting 14.11 release, there is no restriction in defining DBU in DEF. You can define any
value greater than zero.
Scaling the DEF design data
Quantus can resize design input data by a specified scale factor as it is being read into the
extraction engine. You might need to do this for designs which are drawn at one scale, such as 0.18
microns, but being fabricated at another scale, such as 0.15 microns. You might also need to do this
to assign actual dimensions to a design drawn in "virtual" dimensions, or without an established
scale.
The scaling value by which to scale the drawn dimensions in the layout can be specified using the
layout_scale keyword in the ICT file.
Metal Fill Input
The input_db command is usually only specified one time in the Quantus command file. The
exception to this occurs when the input_db command is used to specify -type metal_fill in
addition to the DEF design data:
The input DEF file can have metal fill defined in the FILLS section, or in the SPECIALNETS section as
+SHAPE FILLWIRE statements. The metal fill in the DEF design, or imported in a GDS file, can also
be specified as either floating or grounded to define the capacitive effects of the fill metal (see
"metal_fill").
Note: Metal fill specified in the SPECIALNETS section of the DEF input data is always considered
grounded, and is not affected by the metal_fill command.
You can alternatively include metal fill defined in a separate GDS file if needed. To do this, use the
input_db command a second time to specify the GDS file providing the metal fill shapes:
input_db -type metal_fill -gds_file <filename>
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If you specify metal fill as coming from a GDS file, any fill shapes defined in the DEF file will be
ignored and not processed by Quantus as a default. However, you can retain the DEF metal fill, to
be considered along with the GDS metal fill, by specifying the following command:
input_db \
-type metal_fill \
-retain_def_metal_fill true
Where, -retain_def_metal_fill directs Quantus to use both the metal fill found in the original input
DEF file, and the additional metal fill specified in the GDS input. Refer to "input_db" for more
information.
The input GDS file can also be offset in both the X and Y direction using the -offset_x and offset_y options, and rotated or mirrored using the -orientation option. In this way the shapes in
the GDS file can be lined up properly with the shapes in the DEF file. Refer to the input_db
command for details of these options.
Note: You must be very careful when specifying any offset or orientation, or you may cause
unintentional shorts between the DEF and GDS data.
The GDS file specified for input_db -type metal_fill can be either a flat or hierarchical GDS file.
In the case of hierarchical GDS, Quantus will extract and flatten the top-level cell from the file. In 8.1,
you can specify the top level cell by name, using the input_db -metal_fill_top_cell < name >
option. If no top-level cell is specified, Quantus will automatically detect the top-level cell.
In the multiple GDS metal fill (MF) flow, the block-level GDS MF is treated as MACRO,
therefore the ORIGIN, SYMMETRY, SIZE, and FOREIGN statements between the LEF macro for the
block-GDS-MF and the LEF macro for the block-DEF must be the same for the same block.
If you specify a GDS file as input for metal fill, you must also perform layer mapping for the GDS
layer numbers to map them to a design layer name (see "Layer Mapping GDS and LEF/DEF
Layers"). If you do not do this, then a fatal error will occur.
Note: If you also use GDS files for library input (input_db -type def -gds_file_list) you must
make sure the GDS files do not have conflicting layers, where the same layer number in different
GDS files maps to two different design layers. The gds_layer_map command does not support this
condition.
You can view the layer-based metal fill statistics for the DEF and GDS (OASIS) inputs in the log file
for better usability and improved debugging. The following table gives information about the metal
fill statistics reported in the log file:
DEF metal fills
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Statistics
Displayed
Total number of DEF metal fill shapes
Fill type for each layer.
The fill type will always be passive because
active fill data in DEF is part of the NETS
section.
Total number of GDS/OASIS
metal fill shapes
Fill type for each layer
Total number of GDS/OASIS
metal fill for each layer
Total number of DEF metal fill shapes for
each layer
Number of DEF-based metal fill polygons.
This is displayed if:
GDS/OASIS metal fill is not used at the
same time when the metal fill data is
included in DEF.
GDS/OASIS metal fill is used and the
input_db -retain_def_metal_fill CCL
command option is set to true.
This is displayed if the input_db retain_def_metal_fill CCL command
option is set to true.
Note: If multiple-DEF files are specified as
input, all metal fills from all the DEF files are
reported in the log file.
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Log File
Snippet
INFO (EXTSNZ-168) : Total number of DEF
Metal FILL shapes: 199964
LEF Layer
m2
m3
m4
...
Fill Type
Passive
Passive
Passive
Fill Count
37486
42221
18940
INFO (EXTSNZ-169) : Total
number of GDS/OASIS Metal
FILL shapes: 39728
LEF Layer
Layer Id
Data Type
Fill Type
Fill Count
m6
117
0
Passive
10000
m6
117
1
Active
5000
m7
118
0
Passive
20000
...
If the DEF and GDS|OASIS fill are used together in the design through the input_db retain_def_metal_fill true CCL command option, the metal fill statistics will be printed for both
the DEF and GDS inputs. When retain_def_metal_fill is set to false, the metal fill statistics will
be printed only for the GDS input.
OA Input
Quantus also supports the OpenAccess (OA) database as an input file format for cell-level
extraction only. It supports both flat and hierarchical OA flat designs. You must specify the name of
the OA library definitions file, and the design cell and view name from that library. You can also
specify special handling of specific cells in terms of which library and view should be used for the
cell.
Note: Quantus provides support for the DM4 data model. Earlier releases of Quantus require the
DM3 data model.
In the OA flow, Quantus can read the abstract view or the layout view of cells from the OA database
libraries directly to populate the design. The abstract view of OA includes bounding box, I/O macro
pins, and obstructions (blockages). The corresponding layout view must include bounding box and
I/O macro pins.
For flat OA designs, the library_definitions_file should be provided to define the available OA
Libraries to search.
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The syntax for OA input is as follow:
OA Database
input_db -type oa
-design_cell_name <cellname> <viewname> <libname>
-library_definitions_file <string>
-library_cell_name <cellname1> <viewname1> <libname1>
[<cellname2> <viewname2> <libname2> ...]
-libgen_library_name <library_name>
Where:
-design_cell_name <cellname> <viewname> <libname>specifies the cell and view name for
the top-level design, as well as the library where the cell will be found.
-library_definitions_file <filename> specifies the library definitions file (usually called
lib.defs) which contains the names and paths to libraries used by the design. The lib.defs
file specifies where the OA database entry point information is located. The default filename is
"lib.defs".
Note: Starting with IC version 6.1.4, the use of lib.defs file has been discontinued in
Quantus. If you specify a lib.defs file using the - library_definitions_file option, Quantus
will return an error. Therefore, if you are using IC 6.1.4, specify the library definitions file as
cds.lib. However, if you are using an IC 6.1 version that is earlier than 6.1.4, you can still use
the lib.defs file by setting the environment variable DD_USE_LIBDEFS to YES. If you set the
environment variable DD_USE_LIBDEFS to NO (uppercase), then Quantus will honor only cds.lib
irrespective of the IC version you are using.
-library_cell_name <cellname1> <viewname1> <libname1> specifies which view and library
the specified cell data will be taken from when Quantus is invoked. The default view is
abstract.
-libgen_library_name <filename> can be optionally used to specify LibGen created cell
library files (.cl).
When reading LEF input files, both Quantus and LibGen process a macro cell definition as it
is encountered in the LEF input and ignores any duplicate entries encountered later.
However, the lef2oa utility for creating OA libraries overwrites a macro cell definition with
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each instance it encounters in the LEF input. This can cause discrepancies in the macro cell
definitions from a LEF input library (or a LibGen library) and an OA library, and may affect
extraction results.
Note: libgen_library_name is mutually exclusive with library_definitions_file and
library_cell_name.
For hierarchical OA flat designs, the -oa_cells_list should be provided to specify the OA block
cells. The syntax for OA input is as follow:
input_db -type oa \
-design_cellview
lib1
top_cell
asm6 \
-oa_cells_list
lib2 Cell1 layout \
lib3 Cell2 layout1 \
lib1 Cell3 quantus1
or
-oa_cells_list_file list.txt
The following is a snippet of the list.txt file:
lib2
lib3
lib1
Cell1
Cell2
Cell3
layout
layout1
quantus1
Here,
-design_cellview <library_name> <cell_name> <view_name> : Specifies the Open Access
top cell to be extracted. You need to specify the library name, top cell name in the library, and
the layout view name in the specified cell.
-oa_cells_list <library_name1> <cell_name1> <view_name1> .... <library_nameN>
<cell_nameN> <view_nameN> : Specifies one or more block cells for extraction. You need to
specify the library name, block cell name in the library, and the layout view name in the
specified cell for each block cell.
-oa_cells_list_file list.txt : Specifies a file containing the list of block cell names. This
file has the same syntax as the -oa_cells_list option.
You can specify either -oa_cells_list or -oa_cells_list_file to list the block cell names.
For these options, you must specify the OA cells, library, and cell view in the following order: library
name, cell name, and view name. The library and view names are optional for the Pcells, and you
can mark these fields with hyphen “-”.
To extract the remaining cells as graybox, the use model is:
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graybox –type layout | lef_obstruction | none
Here,
none indicates that the cells are viewed as blackbox data.
layout indicates that the cell view will be loaded based on the search order of the view name
(layout, abstract, <view in hierarchy binding>). Quantus will load the maskLayout viewtype of
OA cells (this is irrespective of the viewName being loaded). Quantus will link to the
GDS|OASIS cell through graybox -foreign_name_map/-foreign_name_map_file or the same
name of the OA cell.
lef_obstruction indicates that cell view will be loaded based on the search order of the view
name (abstract, <view in hierarchy binding>).
The following are not supported in the OA flow:
graybox -def_cells_file, -use_macro_density, and -density_cell_list_file options
extraction_setup -promote_bump_ports -ignore_unconnected_bump_cells options
display of the fill statistics in the log file
Creating an OA database
You can create an OpenAccess database for input into Quantus by using the OA data converters:
def2oa, lef2oa, and strm2oa. To generate the layout view, use the lef2oa utility with the "-view
layout" option, and then use the def2oa and strm2oa utilities. lef2oa generates the abstract view by
default. These utilities take the various data formats as inputs and create an OA database.
Please refer to the OpenAccess documentation for complete information on using these utilities.
Scaling the OA input
Quantus can resize the design input by a specified scale factor as it is being read into the extraction
engine. See Scaling the DEF design data for more information.
Assura Input
Quantus accepts the Assura LVS database as input for extraction. This requires different arguments
to the input_db command.
Assura LVS Database Input to Quantus
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input_db -type assura
-directory_name <dir>
-run_name <string>
-format DFII | GDS
-design_file <file>
-design_cell_name <cellName> <viewName> <libraryName>
-hierarchy_delimiter <char>
-library_definitions_file <filename>
Where:
-directory_name <dir> specifies the working directory of the Assura LVS run. This is where
the various output files of Assura LVS will be found. These files are the required input for
Quantus.
-run_name <string> specifies the Assura run which contains the LVS database to be used as
input to Quantus..
-format DFII | GDS specifies the original layout database input to Assura as either GDS
format, or DFII.
For GDS format, you must also specify the path to the actual GDS file:
-design_file <file>
For DFII format you must specify the cell and view name for the top-level design, as well
as the library the cell will be found:
-design_cell_name <cellName> <viewName> <libraryName>
Note: Starting with EXT10.1.1, Quantus has been enhanced to support numeric strings
for library names specified in the above CCL option.
-hierarchy_delimiter <char> specifies the character used as a delimiter to separate
instance names from different levels of hierarchy in the input database.
-library_definitions_file <filename> specifies the library definitions file (usually called
cds.lib) which contains the names and paths to libraries used by the layout and schematic
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designs.
Quantus supports the following outputs in the Assura-Quantus flow, irrespective of the input
provided to the LVS tool (GDS2 or DFII):
Spice
Transistor Level DSPF
(xDSPF)
Extracted View
Lvs Extracted
View
SPEF
Transistor Level SPEF
(xSPEF)
DSPF
Hierarchical xSPEF
Hierarchical Spice
Hiearchical
xDSPF
Hierarchical Extracted View
Changing Device Prefixes in the Netlist Output
Quantus also supports the prefixDevice option added to the Assura device extraction rules.
Quantus reads the device prefixes (specified using the prefixDevice option) from the Assura device
extraction rules and overrides the default name prefixes in the extraction output netlists with the
prefixes specified in the Assura device extraction rules.
The prefixDevice option is supported for all device types (defined in the extraction rule file). For
example, extractDevice, extractMOS, extractBJT, and so on.
Similar support exists in the QCI flow using the netlist element keyword in the Calibre LVS rule
file.
Note: The prefixDevice option works only if you have Assura AV4.1 or a later version.
Note: In the Assura-Quantus flow, the prefixDevice option can be used in conjunction with Techgen
-compilation. However, if specified in both, the device prefixes specified using Techgen compilation take precedence over the device prefixes specified in the device extraction rules of
Assura.
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Scaling the Assura design data
Quantus can resize the Assura input data by a specified scale factor. You might need to do this for
designs which are drawn at one scale, such as 0.18 microns, but being fabricated at another scale,
such as 0.15 microns. You might also need to do this to assign actual dimensions to a design
drawn in "virtual" dimensions, or without an established scale.
While DEF and OA input data can be scaled directly by Quantus with the use of the layout_scale
command, for Assura and Pegasus input the scaling factor is established by Techgen during
technology setup. Techgen establishes the scale factor for the design using the compilation -scale
option (see Quantus Techgen Reference Manual for more information).
The scaling value by which to scale the drawn dimensions in the layout can be specified using one
of the following approaches:
Scale is specified in the techfile using the layout_scale keyword in the ICT file,
Scale is specified during Techgen compilation using the -scale option:
Techgen -compilation -scale value
When the layout_scale is specified in the ICT file, it should not be specified with the Techgen scale command. If it is defined using both techniques the scale value must be the same or Quantus
will abort with an error.
Pegasus Input
Quantus supports both PVS and Pegasus LVS. The Quantus UI displays ‘PVS’ if you have
PVS installation in the PATH, and displays ‘Pegasus’ if you have Pegasus installation in the
PATH.
Quantus also accepts a Pegasus database as input for extraction in place of the Assura LVS
database.
Here are the high level steps for interfacing Pegasus into Quantus:
Pegasus Database Input to Quantus
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1. Run the Pegasus command pegasus -lvs -qrc_data to output all the files necessary for an
annotated GDS flow for use with Quantus. Refer to the Cadence ® Pegasus User Guide for
more information on this command.
Pegasus will automatically rename special layer names containing a `:' or `_' character
for compatibility with Quantus layer naming conventions. The `_' character will be
replaced with `_0' while the `:' character will be replaced with `_1'. This renaming
occurs when Pegasus creates the .xcn, .layermap, and .textmap files.
2. Setup the technology directory (see Quantus Techgen Reference Manual). Ensure that the
layer_setup file layer names map to the to the Pegasus layers names that appear in the .xcn
file created by Pegasus.
3. Create a Quantus command file with the following input_db commands (see "input_db"):
input_db -type pegasus
-directory_name < pegasus_run_dir >
-run_name < top_cell >
-library_cell_list < filename >
Where:
-directory_name < pegasus_run_dir > specifies the output directory of the Pegasus run.
The output of Pegasus is required as input for Quantus. This is required.
-run_name < top_cell > specifies the cell containing the top-level of the design. This is
required.
-library_cell_list < filename > optionally specifies a file containing a list of cells that
Quantus will output to the DSPF/SPEF netlist.
The Pegasus run name is also the filename prefix of all the files output by Pegasus for use by
Quantus. The Pegasus files have a predefined naming convention: top_cell .<SUFFIX>, where
<SUFFIX> is one of the following: angds, net, layermap, textmap, blkbox, xcn, gnx, gdx, and
matched.
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Quantus supports the following outputs in the Pegasus-Quantus flow, irrespective of the input
provided to the LVS tool (GDS2 or DFII):
Spice
Transistor Level DSPF
(xDSPF)
Extracted View
Lvs Extracted
View
SPEF
Transistor Level SPEF
(xSPEF)
DSPF
Hierarchical xSPEF
Hierarchical Spice
Hiearchical
xDSPF
Hierarchical Extracted View
Note: When Run Pegasus- Quantus is selected from the Quantus menu, the only available outputs
will be Spice, Extracted View, Lvs Extracted View, DSPF (cell level), SPEF (cell level), Power Grid
Database, Transistor DSPF, and Transistor SPEF.
Scaling the Pegasus design data
Quantus can resize the Pegasus input data by a specified scale factor. Please see the scaling
assura for more information.
Device Properties File
Quantus (Pegasus-Quantus flow) has been enhanced to read the LVS-measured device properties
from the device properties side file generated by Pegasus (see the device_properties_file option
of the command input_db). For details on the device properties file, refer to Device Properties File .
Calibre Input
Quantus also accepts a Calibre database as input for extraction in place of the Assura LVS or
Pegasus database.
Calibre Database Input to Quantus
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The following is the command syntax for Quantus to define the Calibre input database.
input_db -type calibre
-directory_name <dir>
-run_name <string>
-layer_map_file <filename>
-device_property_value <value>
-instance_property_value <value>
-net_property_value <value>
-library_cell_list_file <filename>
-hierarchy_delimiter <char>
-design_cell_name <cellName> <viewName> <libraryName>
For details of preparing the Calibre data, and the Quantus files necessary to support the QCI flow,
please refer to Running Quantus with Pegasus and Calibre Inputs.
Quantus supports the following outputs in the QCI flow:
Spice
Transistor Level DSPF
(xDSPF)
Extracted View
Lvs Extracted
View
SPEF
Transistor Level SPEF
(xSPEF)
DSPF
Hierarchical xSPEF
Hierarchical Spice
Hiearchical
xDSPF
Hierarchical Extracted View
Technology Files and Process Variation
Technology Directories and Files
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Quantus requires the use of a technology file that describes the fabrication process being used, and
contains capacitance models and resistance information that can be applied to the design data for
extraction. The technology directory and files are created separately by defining process description
files and simulating and compiling those files with Techgen. Refer to Quantus Techgen Reference
Manual for a complete description of this process.
When running Quantus, you must specify the technology directory. You will do this in the Quantus
command file through the use of the process_technology command:
​
process_technology \
-technology_library_file filename
-technology_name techname
Where:
technology_library_file specifies the path and file name of the technology library file. The
library file contains a list of techname aliases that can be used by Quantus, and the
technology directory path. A relative path can be specified, relative to the location of the
technology_library_file or an absolute path can be specified.
You must specify the -technology_library_file to direct Quantus to the specified technology
file.
Note: See process_technology for details on the format of the technology_library_file.
technology_name indicates a specific techname alias from the technology_library_file that
Quantus should use during extraction.
​Layer names used in the design that match layer names used in the technology file are mapped
automatically by Quantus. However, names that do not match must be mapped together using the
technology_layer_map argument of the extraction_setup command.
extraction_setup \
-technology_layer_map <design_layer_name1> <technology_layer_name1> \
[<design_layer_name2> <technology_layer_name2> ... ]
Design layers may also be excluded from Quantus extraction by mapping the layer name to a layer
in the technology file that is not a routing layer.
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Managing Process Corners
The fabrication process being used to manufacture the design will have some process variation
from wafer to wafer, or even from chip to chip. The range of variations can be modeled in process
corner techfiles stored in subdirectories of a specific technology directory. These process corners
allow you to evaluate a design under variations of the fabrication process. For instance, you could
define a process description and create a technology file that models the typical results of a specific
fabrication process. Then you could create two worst case process corners called min and max that
describe the results of the fabrication process at the opposite ranges of variation.
Process Corners and Corner Definition File
You can use any of the process corner technology files during extraction simply by specifying the
technology_name as the one for Quantus to use during the extraction run. However, you can also
specify multiple process corners for evaluation during a single extraction run, to allow Quantus to
perform extraction across the range of process variation as defined by the specified process corner
files. This requires the presence of a corner.defs file (or corner definitions file) in the technology
directory. The corner.defs file lists the available process corners for the specified technology_name
. An example corner.defs file for these process corners is given below:
DEFINE typ corner_typ
DEFINE cbest corner_cbest
DEFINE cworst corner_cworst
DEFINE rcbest corner_rbest
DEFINE rcworst corner_rworst
Refer to "process_technology" for more information on defining the corner.defs file. You can
specify the extraction of multiple process corners during a single Quantus run with the following
process_technology command:
process_technology \
-technology_library_file file_name \
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-technology_name techName \
-technology_corner corner1 corner2 corner3
Quantus looks for the corner.defs file in the technology directory specified with the technology_name command, and validates the definition of the corners specified in the technology_corner command. If the specified corners are not defined in the corner.defs file, or if
the technology directory for the process corner can not be found, then Quantus exits with an error.
For more information about the technology directory structure, refer to the “Creating the
Technology Library File” section in the Running Techgen chapter in Quantus Techgen Reference
Manual.
Quantus handles the output of parasitic networks from multiple process corners differently
depending upon the specified output format.
For DSPF/SPEF output, refer to dspf_mutiprocess.
For SPICE output, refer to spice_mutiprocess.
For OA output, refer to OA Output.
Sensitivity Extraction
This feature of Quantus only applies to DEF or OA design input.
The ability to cover multiple process corners in a single extraction run for both cell-level and
transistor-level designs makes Quantus a very efficient extraction tool. However, this requires the
existence of a process corner technology file for each process corner supported. The more
coverage you desire in the range of variation, the more process corner files that you must first set up
and model using Techgen.
Quantus also supports an even more powerful statistical extraction process called sensitivity
extraction. Sensitivity extraction is supported for cell-level extraction using DEF or OA input only,
and is enabled by the extraction_setup -enable_sensitivity_extraction command.
Note: Sensitivity extraction is not compatible with multiple process corners. Quantus will exit with
an error if both process_technology -technology_corner and extraction_setup
-enable_sensitivity_extraction are specified in the Quantus command file.
Sensitivity extraction allows Quantus to model a range of process variation automatically based
upon modeling the typical fabrication process, and specifying the range of variation possible within
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that process. The range of variation is stored in an added technology file called a sensitivity
technology file ( techfile .sens). The sensitivity techfile can only be created by using the Techgen
-cell -variation command. Refer to Quantus Techgen Reference Manual for details of the
variation command.
For enabling sensitivity extraction use the following Quantus command:
extraction_setup -enable_sensitivity_extraction true
With this command specified (see "extraction_setup"), Quantus will perform statistical extraction of
the fabrication process variation if the technology directory contains a sensitivity technology file. If
sensitivity extraction is selected, and there is no sensitivity techfile, Quantus will exit with an error.
Sensitivity SPEF Netlist​
Sensitivity extraction is only supported for the SPEF netlist output, and produces a new form of
SPEF called sensitivity SPEF, or sSPEF. sSPEF is specified with the output_db -type spef
command (see output_db) when sensitivity extraction is enabled. If SPEF output is not specified for
the extraction, Quantus will exit with an error.
Sensitivity SPEF format is a Cadence developed extension to the SPEF standard format. It is used
to describe the statistical variation of the output parasitic network from Quantus for use by Innovus.
The sSPEF netlist format provides a syntax for supporting the variation of key parasitic values
without hugely expanding the netlist size.
The extensions of sSPEF are stored as comments in the SPEF netlist, with the values for the typical
technology file defined in the actual SPEF netlist. As such, any tool supporting SPEF should be
able to read the typical values from the sSPEF netlist. However, it may be desirable to extract a
different set of parasitic values from the sSPEF netlist for analysis. You can extract a standard
SPEF netlist from any of the variations stored within the sSPEF netlist with the use of the
sSPEF2SPEF utility provided with Quantus. Please refer to the sSPEF2SPEF Utility chapter for
instructions on running the sSPEF2SPEF utility.
IEEE 1481 has finalized an official IEEE sSPEF format, which has become the industry standard.
Therefore, starting with the EXT 9.1 release, Quantus has been enhanced to produce a new sSPEF
netlist output that maps to the IEEE sSPEF format. Since the new sSPEF output complies to the
IEEE 1481 sSPEF format, it may not contain customer-specific setup information. Therefore,
Quantus also generates a side file to include such information.
To generate the new sSPEF format, a new argument -enable_ieee_sensititvity that takes true or
false (default) as values has been added to the output_setup command. See "output_setup".
The new sSPEF output along with the side file is used to describe the statistical variation of the
output parasitic network from Quantus for use by Innovus.
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Note: The Quantus sSPEF2SPEF utility does not support the IEEE sSPEF format and cannot be used
to generate standalone corners.
Double Patterning Technology (DPT)
For 20nm processes, one or more back-end layers (M1 and above) have dual masks. Each mask
has a unique color. Major foundries today utilize the colorless DPT corner concept to model the
impact of mask shift on capacitance for 20nm processes. The databases do not include mask
colors. The database models have built-in pessimism. This pessimism can be reduced by
considering mask colors during Quantus extraction.
Support for Triplet DPT Corners Flow
Starting with the PVE 11.1.2 HF1 release, DPT modeling (variable dielectric) is supported through
ICT file and can output triplet corners. This flow requires three corner qrcTechFiles:
process_technology \
-technology_library_file techlib.defs \
-technology_name t20nm \
-technology_corner
min typ max
Color-Aware Triplet DPT Corners Flow
For this flow, the input database does not need to be colorized. When you run Quantus, you get the
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following output:
Single output file with triplet RC value
In case of LEF/DEF, the output is a SPEF file
LVS-based outputs a Spice/extracted view
CCL Command to Enable Triplet Value Output
To obtain a triplet value output as SPEF, you use the following CCL command:
output_db
-type spef -output_triplet_rc true
For more information, see output_db.
Pessimism Reduction with Triplet DPT Corners Flow
The color information of input database can be used in the DPT corner mode to reduce pessimism.
Pessimism Reduction with Colors
To do this, each corner case (that is, min, max) uses a combination of coupling capacitance values.
The CC(typ) value is reported between the same mask color. The CC(min)/CC(max) value is
reported between different mask colors. Mask shift is applied after WEE biasing. This flow also
requires three corner qrcTechFiles:
process_technology \
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-technology library file techlib.defs \
-technology_name t20nm \
-technology corner
min typ max
Color-Aware Triplet DPT Corners Flow with Pessimism Reduction
The input database must be colorized. The output is similar with triplet DPT corners flow.
For triplet DPT corner, you need to set color_layer keyword in layer_setup file to define the mask
layers for a given LVS/ext_layer.
An example is as follows:
pro_layer=M1 ext_layer=M1 color_layer=M1_mask1,M1_mask2
pro_layer=M2 ext_layer=M2 color_layer=M2_mask1,M2_mask2
pro_layer=M3 ext_layer=M3 color_layer=M3_mask1,M3_mask2
Here, M1_mask1 and M1_mask2 are the two masks for M1 layer. Similarly, M2_mask1, and M2_mask2 are
the two masks for M2 layer. Whereas for custom/shift corner DPT feature, color_layer keyword is
optional in layer_setup file, because these mask layers are in any case defined in
corner_definition_file of the following CCL command:
extraction_setup -custom_dpt_corner file_name
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Support for Shift Corners
Quantus supports runtime specified mask shift amount using the CCL command option. For
supporting runtime mask shift, maximum shift range is required for capacitance model generation.
This requires a shift range definition in the ICT file for each layer. To define shift range, the ICT file
uses the max_shift syntax. max_shift defines the maximum mask shift (in um) for each DPT metal
layer, based on foundry specification. The value of max_shift must be a positive number. This is
valid only for conductor statements and for the metal layers that have multiple masks.
Shift Corner Extraction Flow
This flow requires only one corner qrcTechFile, colored input database and a customer defined shift
corner file. To define a shift corner, you can use the following CCL command:
extraction_setup -custom_dpt_corner corner_definition_file_name
Note: Shift corner functionality (for GDS-based flow) is supported by Field Solver.
Thickness Variation by the Color
Quantus supports thickness variation by color. This feature is supported only in the Quantus(GDSII)
flow when the following CCL command is activated:
extraction_setup -custom_dpt_corner corner_definition_file_name
In a corner definition file, an optional syntax (thickness_variation) is added to the end of each line,
to model the thickness variation of each colored conductor. When thickness_variation is
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specified, the R and C values of the respective colored wires are appropriately impacted.
The following example shows the thickness variation syntax in the Quantus(GDSII) flow. Note that
thickness_variation is an optional new keyword. The values are specified in micro meters (um).
A positive thickness_variation means wire thickness becomes large.
Metal1_A
Metal1_B
Metal2_A
Metal1
Metal1
Metal2
shift_x=0.002 shift_y=-0.002
shift_x=-0.002 shift_y=0.001
shift_x=-0.001 shift_y=0.003
thickness_variation=0.001
thickness_variation=-0.002
In the below figure, the R effect and thickness variation are depicted. Specifically, thickness
variation depends on wire color. It is applied after the opcWEE and erosion effect. Both opcWEE
and erosion effects do not depend on color, nor the shift amount.
Thickness Variation R Effect
In the below figure, the capacitive effect of thickness variation is illustrated. Similar to R effects, the
thickness_variation amount depends on the wire color. Both opcWEE and erosion do not depend
on color, nor the shift amount. However, the important spacing parameter for coupling capacitance
depends on the color and the shift amount.
Thickness Variation and Capacitive Effect
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For more details, refer to the "Double Patterning Technology (DPT)" section in Quantus Techgen
Reference Manual.
10nm DPT Extraction Flow with Colored DB
Quantus supports 10nm DPT modeling through ICT file, and outputs multiple SPEF files/ multivalued Spice/Extracted View.
This flow has the following input database colored requirements:
DEF version 5.8
DEF Self-Aligned Double Patterning (SADP) and GDS Metal Fill for SADP layers that must
be colorized
All other DB layers' color is optional, including DPT
You can specify multiple corner techfiles.
10nm DPT Extraction Flow
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When you run Quantus, you get the following output:
LEF/DEF outputs multiple SPEF files (one for every corner techfile)
LVS-based outputs multi-valued Spice/Extracted view
For information on 10nm DPT Modeling, refer to the Advanced Node Modeling chapter of Quantus
Techgen Reference Manual.
CCL Command to Enable Color Import
To import color information, you use the following CCL command:
extraction_setup -enable_dpt_color_import true (default)
Parasitic Extraction
Selecting Nets to Extract
Resistance Extraction
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Capacitance Extraction
Inductance Extraction
Hierarchical Extraction
Substrate Extraction with Quantus AoT
​Selecting Nets to Extract
The Quantus extract command allows you to define the set of nets you are interested in extracting
and the type of extraction to perform. You can run extraction on the whole design, or on selected
portions of the design. The following is the syntax of the extract -selection command option:
extract
-selection [ all | def_special_nets | def_regular_nets | def_mustjoin_nets | net
<regexpr> | nets_file <file> | selected_path_file <file> ]
You can define nets using regular expression wildcards, as defined in the Using Wildcards with
Quantus chapter. You can also define lists of nets in files that are read by Quantus to determine
which nets to include in the extraction.
Quantus only extracts nets in accordance with the extract command explicitly defined in the
Quantus command file. You must specify a selection of nets, and a type of extraction to be
performed in the command file.
Quantus excludes power and ground nets from extraction by default. Power and ground nets are
recognized by the use of the global_nets command in the command file (see global_nets), or the
definition of nets with the USE POWER or USE GROUND constructs in the input DEF file. Quantus
excludes these nets from extraction unless you specify their name or a matching pattern with the
extract -selection command.
There is no limit to the number of extract commands that you can define in a single command file,
so you can use them repeatedly to fully describe the nets to extract and completely control the type
of extraction desired.
Note: Later command specifications override earlier ones if they select the same nets, so you must
take care to specify the correct extraction type for a specific net.
Here are some examples:
extract -selection def_special_nets -type r_only
extract -selection nets_file c_nets -type rc_coupled
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extract -selection net VDD* -type rc_coupled
These lines would result in resistance-only extraction for all DEF SPECIAL nets, and coupled RC
extraction on all nets named in the c_nets file, and on all nets whose names begin with "VDD".
Full Chip, All Nets
To extract the full chip, all nets except global nets are included for resistance and capacitance
extraction.
Note: This requires the use of only the extract -selection all command, with no further extract
selections specified except to define the use of the field solver for a subset of nets with -type
c_only_xxx.
For LVS input, when inductance extraction is specified all nets are included, or a subset of nets are
extracted as specified by the extract -inductance_nets_file command (see Inductance
Extraction).
Only nets specified with the extract -substrate_nets_file command are included when substrate
extraction is specified with LVS input (see Substrate Extraction with Quantus AoT).
The Quantus field solver can also be specified for capacitance extraction of all nets, or a subset of
nets (see Capacitance Extraction).
An example Quantus command to support this mode is as follows:
extract \
-selection all \
-type rlc_coupled \
-inductance_nets_file < ind_nets > \
-substrate_nets_file < sub_nets >
extract \
-selection < nets_file > \
-type c_only_coupled \
-use_field_solver default_accuracy
Full Chip, Selected Nets
For full chip, selected nets, capacitance extraction is done for the whole design while resistance
and inductance extraction are only performed on a specific set of nets of interest.
All nets are included for capacitance extraction with extract -selection all and extract -type
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c_only_xxx.
Only specified nets are included for resistance extraction with extract -selection nets_file and
extract -type rc_xxx.
This mode does not support inductance extraction or substrate extraction.
The Quantus field solver can also be specified for capacitance extraction of all nets or a specified
subset of nets.
An example Quantus command to support this mode is as follows:
extract \
-selection all \
-type c_only_decoupled
extract \
-selection nets_file < filename > \
-type c_only_coupled \
-use_field_solver high_accuracy
You can also do a resistance only extraction (r_only) on selected nets, with no capacitance
extracted on any nets. An example of this is as follows:
extract \
-selection all \
-type none
extract \
-selection nets_file < filename > \
-type r_only
Selected Nets Proper
Quantus supports a selected nets proper (or selected nets only) mode of extraction. In this case only
the nets expressly specified are included for extraction. The rest of the design is excluded.
Nets can be specified with extract -selection nets_file or -selection net for all inputs, or can
be specified with the extract -selection def_xxx_nets arguments for DEF or OA input only.
Note: For selected nets proper extraction you can use multiple extract -selection options as long
as you do not specify extract -selection all.
For DEF or OA input, the r_only, c_only_xxx, rc_xxx, rlc_xxx or rlck_xxx extraction types are
supported.
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For LVS input, when inductance extraction is specified all nets are included, or a subset of nets are
extracted as specified by the extract -inductance_nets_file command (see Inductance
Extraction).
Only nets specified with the extract -substrate_nets_file command are included when substrate
extraction is specified (see Substrate Extraction with Quantus AoT).
The Quantus field solver can also be specified for capacitance extraction of all selected nets, or a
subset of nets (see Capacitance Extraction).
An example Quantus command to support this mode is as follows:
extract \
-selection nets_file < many_nets_file > \
-type rlc_coupled
-inductance_nets_file < fewest_nets_file >
Excluded Nets
For excluded nets extraction, all nets have resistance extracted except a limited group of nets which
are excluded. This is similar to the full chip, selected nets extraction except in this case so many
nets are included in resistance extraction that it is simpler to specify the nets that are excluded.
All nets are included for resistance and capacitance extraction with extract -selection all and
extract -type rc_xxx (or -type rlc_xxx or rlck_xxx).
Specified nets are excluded from resistance extraction with extract -selection nets_file and
extract -type c_only_xxx (or -type none). However, even if resistance extraction is not done, the
xDSPF and xSPEF output still has small value mwires added to establish connectivity.
When inductance extraction is specified all resistance nets also have inductance extracted, or a
subset of nets are extracted as specified by the extract -inductance_nets_file command (see
Inductance Extraction).
Note: Inductance nets specified must not be excluded from resistance extraction or an error will
occur.
Only nets specified with the extract -substrate_nets_file command are included when substrate
extraction is specified (see Substrate Extraction with Quantus AoT).
Note: Substrate nets specified must not be excluded from resistance extraction or an error will
occur.
The Quantus field solver can also be specified for capacitance extraction of all nets or a specified
subset of nets.
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An example Quantus command to support this mode is as follows:
extract \
-selection all \
-type rc_coupled
extract \
-selection nets_file < filename > \
-type c_only_decoupled \
-use_field_solver high_accuracy
Excluded Nets Proper
For excluded nets proper extraction, all nets have resistance and/or capacitance extracted except a
limited group of nets which are excluded from both R and C extraction. This is similar to the
selected nets proper extraction, except in this case so many nets are included in resistance and
capacitance extraction that it is simpler to specify the nets that are excluded.
All nets are included for resistance and capacitance extraction with extract -selection all and
extract -type rc_xxx (or -type rlc_xxx or rlck_xxx or r_only or c_only_xxx). Specified nets are
excluded from resistance and capacitance extraction with extract -selection nets_file and
extract -type none.
When inductance extraction is specified all resistance nets also have inductance extracted, or a
subset of nets are extracted as specified by the extract -inductance_nets_file command (see
Inductance Extraction).
Note: Inductance nets specified must not be excluded from resistance extraction or an error will
occur.
Only nets specified with the extract -substrate_nets_file command are included when substrate
extraction is specified (see Substrate Extraction with Quantus AoT).
Note: Substrate nets specified must not be excluded from resistance or capacitance extraction or
an error will occur.
The Quantus field solver can be used in all field solver extraction modes except for Selected Paths
extraction. In the field solver extraction modes Selected Nets or Excluded Nets, then the selected
nets for field solver cannot also be excluded from Quantus extraction.
An example Quantus command to support this mode is as follows:
extract \
-selection all\
-type rc_coupled \
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extract \
-selection -nets_file "./netsfile"\
-type none\
In the above example, the nets specified in the . /netsfile file are excluded from both R and C
extraction, while all the other nets are extracted. Any nets extracted that capacitively couple to
excluded nets, will be decoupled to the ground node.
Selected Paths
This feature of Quantus only applies to LVS input (Assura, Calibre, or Pegasus).
For selected path extraction Quantus uses a net expansion algorithm on the specified nets to define
the selected paths. The net expansion algorithm expands the listed nets through MOSFET diffusion
paths until they terminate at a MOSFET gate, or a Quantus global net (see "extract").
Specified nets are included for capacitance and resistance extraction with extract
-selection selected_path_file.
Note: For selected path extraction, you should have only a single extract command specified in
the command file.
This mode does not support inductance extraction or substrate extraction.
The Quantus field solver can also be used for capacitance extraction on the specified nets.
This extraction mode only outputs a partial list of designed devices and components on the
nets specified in the selected_path_file plus extracted parasitics rather than the complete
device output of other extraction modes.
An example Quantus command to support this mode is as follows:
extract \
-selection selected_path_file < filename > \
-type c_only_coupled \
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-use_field_solver default_accuracy
Net Name Space
This feature of Quantus only applies to LVS input (Assura, Calibre, or Pegasus).
Assura and Pegasus can provide both the schematic view and the layout view of a design as part of
the input when the input_db -format argument specifies DFII. Because of this, you must establish
the naming convention you will be following before specifying the nets to extract either in the
Quantus command file or in the files that define lists of net names and cell names from the design.
The naming convention you follow will be from either the schematic or the layout, and is specified
by the command:
extraction_setup -net_name_space [ schematic | layout ]
Incomplete Nets
The following feature of Quantus only applies to DEF or OA design input.
There are times early in the design phase when you may want preliminary extraction data. This
enables Quantus to perform a fast but less accurate extraction of a design that is in an early stage of
completion. Because the design is not yet finished, the routing is usually incomplete, and the
connectivity will often contain shorts or incomplete nets.
Quantus can detect incomplete and unrouted nets before extraction is done, and reports nets that
have one of the following conditions:
Disjoint segments (multiple partitions)
One pin nets.
Quantus allows you to ignore these issues and still extract the parasitics for the design by
specifying the following command:
output_db \
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-output_incomplete_nets true \
-output_unrouted_nets true
When set to true, incomplete and unrouted interconnect shapes will be extracted as normal nets
and the resistance and capacitance will appear in the output (DSPF or SPEF).
If set to false, which is the default value, all geometries for the incomplete nets will be treated as
gray data, and no resistance or capacitance will be extracted. They will appear as grounded shapes
when considering capacitance extraction on neighboring interconnect.
Ignoring Cells
You may not want Quantus to consider the effects of certain cells in your design if these cells have
RC parasitic values built into the cell simulation model, or if these cells are not relevant to the
extraction, especially if they are missing, undefined, or contain information such as a company logo.
There are two commands to use to exclude cells from extraction based on the input design format
(see "extraction_setup").
For Def or OA input
extraction_setup -ignore_cells_file filename
Where filename specifies a file containing a list of cells to ignore during extraction. During
resistance extraction, Quantus will not detect the specified cell's pins. During capacitance
extraction, it considers the cell a black box.
For Assura, Pegasus, or Calibre input
extraction_setup -parasitic_blocking_device_cells_file filename
Where filename specifies a file containing a list of cells to ignore during extraction. The
specified cell will be flattened into the output netlist after extraction. During capacitance
extraction, Quantus considers the contents of the cell as white data by default. To consider the
contents of the cell as gray data during capacitance extraction, use the following command:
extraction_setup -parasitic_blocking_device_cells_type gray
​Resistance Extraction
Choose any extraction mode that includes resistance (R) to extract parasitic resistors to your
specified output format:
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extract -type [ r_only | rc_decoupled | rc_coupled | rc_decoupled_to_substrate |
rlc_decoupled | rlc_coupled | rlc_decoupled_to_substrate | rlck_decoupled |
rlck_coupled | rlck_decoupled_to_substrate ]
Parasitic RC Network
Resistance Extraction for Interconnect
If resistance extraction is specified, an interconnect fracture length can be defined to control the
maximum length of interconnect for extracted parasitic resistors. Interconnect polygons in the layout
data are fractured at contacts, T-intersections, and at device pins. In addition, interconnect polygons
are fractured in accordance with the Quantus extraction_setup command:
extraction_setup -max_fracture_length value
If an interconnect segment exceeds the specified length value , Quantus fractures the segment at
that length, and forms a parasitic resistor between the fracture points.
If parasitic capacitance extraction is also specified for the Quantus run, the capacitance of the
fractured interconnect segments is calculated, and parasitic capacitors are placed at the resistor
segment terminals to form a parasitic RC network. The above figure illustrates an extracted RC
network produced for a Quantus run that specified both resistance and decoupled capacitance
extraction.
The default value of max_fracture_length for an LVS input is infinite (no limit on interconnect
length). For the DEF/OA input, the default value is 100 microns. These defaults provide sufficient
resolution for resistance extraction in the distributed RC networks, and also provide the least
number of extracted resistors in the Quantus output for fastest extraction and smaller output netlists.
For RLCK extraction, see “rlckextraction".
Note: The max_fracture_length value cannot be less than 5. If you specify a value less than 5um (or
5 squares, if the unit is specified as squares using max_fracture_length_unit), Quantus issues an
error.
Effect of Max Fracture Setting on Extracted RC Networks
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This feature of Quantus only applies to LVS input (Assura, Calibre, or Pegasus) and celllevel flows.
Resistance Extraction of Via Arrays
Vias and contacts are handled differently from interconnect in that the shapes on contact layers are
grouped by default into arrays to speed resistance extraction. Quantus groups vias and contacts
together according to the distance between them -- if the distance between contacts or vias does
not exceed a specified maximum distance, they are grouped within the same array. This distance
has an internal default value, but can also be defined in the layer_setup file with the use of the
array_vias_spacing command (see Quantus Techgen Reference Manual).
In some designs there will be a large number of vias or contacts clustered into a small area, with
very tight spacing. In this case the merged via array can become quite large. To prevent the merged
via arrays from becoming too large, and adversely affecting the calculation of contact or via
resistance, you can specify the maximum via array size with the Quantus extraction_setup
command:
extraction_setup -max_via_array_size value
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​ ​ ​Resistance Effects of Bias, Erosion, and Metal Fill
The technology file provides constructs to define the bias and width-dependent bias of conductor or
metal layers. In addition, there is also an extensive syntax for defining the effects of erosion on the
thickness of a layer. The erosion can be related to the density of the interconnect at a specific
location, or be related to both the surrounding density and the actual width and spacing of the
interconnect. Erosion can also be defined as a table of coefficients to a polynomial expression that
determines the thickness of the interconnect based on actual wire widths rather than the
interconnect density in areas of the chip. Refer to Quantus Techgen Reference Manual for more
information on bias and erosion.
Note: The use_silicon_density keyword in the qrcTechFile directs Quantus to calculate the
density based on the silicon dimensions of the interconnect. If the keyword is not defined then
Quantus uses the drawn dimensions by default. Refer to Quantus Techgen Reference Manual for
more information.
The process_technology -erosion_file command provides you with the ability of using the
Cadence CMP Predictor (or CCP) to simulate the effects of CMP on the actual design data. The
erosion_file will specify the output of the CCP erosion simulator, which will be used in place of
any erosion specification defined in the technology file. For more information, see
"process_technology".
Since wire bias affects the width of the interconnect, and erosion affects the thickness of the
interconnect, both of these characteristics of the technology file will have an effect on the extracted
resistance and capacitance for that layer. There is no command to enable or disable the effects of
either bias or erosion during the Quantus run 2, as these are attributes of the fabrication process.
In addition, since erosion is related to the metal density of a layer, the addition or exclusion of fill
metal can also have an effect on erosion and on the resistance extraction. To control the addition of
metal fill to the design, Quantus provides the metal_fill command. See "metal_fill" for more
information.
Resistance Extraction for Transistors
This feature of Quantus only applies to LVS input (Assura, Calibre, or Pegasus).
For a single connected gate, Quantus calculates gate resistance (R g ) by taking the sheet
resistance of the gate material (R sheet ) multiplying that with the width of the gate (W) divided by the
length of the gate (L) and then reduces that value in half:
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R g = (R sheet * (W/L))/2
This is done with the understanding that the parasitic resistance of the gate is at the middle of the
gate, and so the gate resistance should be reduced by a factor of 2 in this case. While that is true for
transistor gates with single connections, a different model needs to be applied for transistors with
double connected gates. Because the double connected gate has two sources of current flow, there
are essentially two parasitic resistors in parallel on the gate. In addition, the gate width is cut in half
to account for the current flow through the two terminals.
In the below figure, assume 80 ohms of total resistance due to the gate material. In the single
connected gate (Device A) this would equate to an actual gate resistance of 40 ohms. However, on
the double connected gate (Device B), the gate width is cut in half (0.5W) to account for the two
terminals and this is then applied to the gate resistance calculation:
Rg = (Rsheet * (0.5W/L))/2
Resistance of Gates
When the Techgen -res_gate_factor command is not set, this results in two parallel 40 ohm
resistors so the effective R is 20 ohms for the gate resistance. The gate resistance for a
double connected gate is one quarter (1/4) the sheet resistance of the gate material.
When Techgen -res_gate_default_factor 2.0 is set, this results in two parallel 20 ohm
resistors, so the effective R is 10 ohms for the gate resistance. The gate resistance for a
double connected gate is one eighth (1/8) the sheet resistance of the gate material.
Note: The calculation of the gate resistance can be modified when creating the technology file in
Techgen through the use of the res_gate_default_factor or the delta_gate_ckt commands. Refer
to Quantus Techgen Reference Manual for more information.
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​ ​Resistance as a Function of Temperature
Resistance values can be extracted based upon temperature using the Quantus
process_technology command:
process_technology -temperature temp
The temperature specifies the operating temperature of the device for the purposes of temperature
dependent resistance extraction. The change in temperature (deltaT) between the specified
operating temperature and the nominal temperature is used to determine the effect of temperature
on parasitic resistance (see "process_technology").
The nominal temperature for the device is specified in the technology file, either through the use of
the temp_reference argument in the ICT file or the temp_nominal command when running Techgen compilation. Temperature coefficients (TC1 and TC2) must also be added to the technology file. If
the -temperature command is used and no temperature coefficients have been defined, a warning is
issued, and the effect of temperature on resistance will be disregarded.
Note: If a p2lvsfile file exists in the technology directory, and it contains a width-dependent TC table
that is different than the table in the ICT file, then the p2lvsfile takes precedence over the TC table
specified in the ICT file. For getting the correct TC extraction result based on ICT table, you need to
remove TC-related contents from p2lvsfile before running Quantus.
See Quantus Techgen Reference Manual for more information on defining the nominal temperature
and temperature coefficients in the technology file.
Quantus also has the ability to read a thermal map file produced by Innovus. The
thermal_map_file provides layer and XY location specific operating temperatures for consideration
by Quantus during temperature dependent resistance extraction. Refer to "process_technology" for
more information on the -thermal_map_file option.
Reducing Resistors
In many cases you will want to reduce the number or type of parasitic resistors in the output netlist
to eliminate unnecessary details. This will result in smaller netlists, and improved simulation times
for downstream processes like timing analysis. There are two types of reduction provided in
Quantus: rule based, and mathematical reduction.
Rule-based reduction commands such as the filter_res command are offered by Quantus to filter
out very small resistors from the design, with the understanding that they will have limited impact on
the actual performance of the design. In addition you can eliminate dangling resistors that don't
attach to anything meaningful, and merge parallel resistors to reduce the actual number of parasitic
resistors without affecting the circuit (see filter_res).
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Mathematical reduction is also offered by Quantus in the parasitic_reduction command to allow
you to reduce the number of parasitic elements from the netlist as well, based on an internal
reduction algorithm (see parasitic_reduction).
Capacitance Extraction
For parasitic capacitance extraction choose any of the extraction types that include capacitance
(C):
extract -type [ c_only_decoupled | c_only_coupled | c_only_decoupled_to_substrate |
rc_decoupled | rc_coupled | rc_decoupled_to_substrate | rlc_decoupled | rlc_coupled |
rlc_decoupled_to_substrate | rlck_decoupled | rlck_coupled |
rlck_decoupled_to_substrate ]
Decoupled and Coupled Output from a Single Extraction
The following feature of Quantus only applies to DEF or OA design input.
Quantus supports the ability to output both a coupled extraction netlist and a decoupled extraction
netlist from a single coupled extraction run. This is specified with the use of the output_setup write_coupled_decoupled_files command option, which only supports cell-level DSPF or SPEF
output. Refer to "output_setup" for more information on this command.
Intralayer and Interlayer Parasitic Cap Components (Cross-sectional View)
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Parasitic Capacitance Extraction for Interconnect
Capacitance is a function of the surfaces and separation of two conductors and their intermediate
insulator's permittivity and thickness. Area capacitance is formed between different layers. Sidewall
capacitance is formed between the edge of a conductor and another conductor above or below it or
an edge coincident to it. Quantus will not extract capacitance between different shapes on the same
net or between shapes on different nets that are shielded by an intermediate differing net. The
above figure illustrates a cross-sectional view of different intralayer and inter-layer shapes above
the substrate in a layout design and the intralayer and inter-layer parasitic capacitance components
between these shapes.
The default Quantus capacitance extraction compares intralayer (same layer) layout shapes and
interlayer (different layer) layout shapes on the nets selected for extraction to capacitance models in
the Quantus technology file. Once the layout shapes are matched to corresponding models, the
models are used to calculate the parasitic capacitance between the intralayer and interlayer net
shapes.
​Field Solver
The Quantus field solver calculates parasitic capacitance directly from the interconnect shapes in
the design data without the use of capacitance model-matching. This results in a more accurate
extraction at the expense of additional run time. The field solver can be specified with the use of the
command:
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extract -use_field_solver [ default_accuracy | high_accuracy ]
You can combine the -use_field_solver option in multiple extract commands to use the field solver
on all but a few excluded nets. The following command sequence would be one way to achieve
this:
extract \
-selection all \
-type c_only_decoupled
-use_field_solver default_accuracy
extract \
-selection nets_file <file> \
-type none
-use_field_solver default_accuracy
Each line in the file specified with the -selection nets_file option must consist of a single net
name. If you specify multiple net names in a single line, you may get unexpected capacitance
values in the output netlist.
The default precision of xy coordinates for Quantus FS in the cell-level flow is 10000
DBUperUU.
​ ​Capacitance Effects of Bias, Erosion, and Metal Fill
Bias and erosions as defined in the technology file affect both the extracted resistance and
capacitance for a specific layer. For a complete explanation of these effects please refer to
"Resistance Effects of Bias, Erosion, and Metal Fill".
While metal fill only affects resistance extraction in as much as it affects the metal density of a layer,
it has a direct effect on the number and amount of capacitance extracted in the design. The metal
fill, whether it is floating or grounded will have capacitive coupling with other metal shapes in the
design.
In some cases metal fill may block capacitance interactions between shapes, thereby reducing the
coupling between those shapes, or it may introduce new coupling where none previously existed.
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Parasitic Capacitance Extraction for Transistors
This feature of Quantus only applies to LVS input (Assura, Calibre, or Pegasus).
By default, Quantus will extract gate capacitance for defined MOS devices between the gate and
the substrate (C gate2sub ), and between adjoining gates (C gate2gate ) as illustrated in the
below figure.
Extracting Gate Capacitance
Quantus will not extract fringe capacitance between the gate and diffusion layers as these are
traditionally modeled in the Spice model for the device. However, the device fringing capacitance
can be modeled in the ICT file and qrcTechFile, and you can enable Quantus to extract the fringing
cap by specifying the following command (refer to "extract"):
extract \
-selection all \
-type rc_coupled \
-extract_via_cap true
-extract_gate_diffusion_fringing_cap true
If the device simulation model includes the gate capacitance or resistance, you must eliminate them
from the Quantus extraction. Use the Techgen -compilation -p command option to block extraction
of the gate capacitance. Eliminate the gate resistance from Quantus extraction with the Techgen compilation -exclude_gate_res command. Refer to Quantus Techgen Reference Manual for more
information.
Quantus will also extract contact capacitance for the transistor device terminals (C contact2contact
and C contact2gate ). You can enable this contact capacitance extraction by using the
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extract_via_cap option:
extract \
-selection all \
-type rc_coupled \
-extract_via_cap true
The Quantus field solver extracts contact capacitance of MOS devices by default, so you can also
disable this in the field solver by setting this same command to false.
extract \
-selection nets_file <file> \
-type r_only_coupled \
-use_field_solver default_accuracy \
-extract_via_cap false
​How Quantus Forms Coupled and Decoupled Parasitic Caps
Capacitance extraction always requires the definition of the ground net, which is used for
decoupling capacitors to an ideal substrate.
For all capacitance extraction types, Quantus extracts coupling capacitance between selected nets
and neighboring nets, assuming the width and separation of net shapes fall within the ranges
modeled in the technology file. Quantus does not extract capacitance on unselected nets (but it
does extract capacitance between selected and unselected nets).
Global (power and ground) nets are treated the same as other nets, and can be treated as selected
or unselected nets according to the extract command -selection setting.
If coupled capacitance is selected, Quantus produces coupling caps on the selected nets, and then
decouples the capacitance between selected nets and unselected nets to the ground net.
Decoupling the capacitance extracted on the selected nets is performed as follows (see the below
figure):
1. Quantus removes the coupling capacitor between two nets (or net nodes), and produces two
decoupled caps, attaching one decoupled cap to each of the two nets (or nodes).
2. Quantus attaches the second terminal of each decoupled cap to the ground net specified, or to
the actual substrate ground occurring at the location of the parasitic capacitor (in the case of
Decoupled To Substrate ).
Quantus Decoupled Cap Extraction
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If decoupled capacitance extraction is selected, all extracted capacitance on selected nets is
decoupled to the ground net and multiplied by the decoupling factor.
decoupled_to_substrate supports Assura, Pegasus, or Calibre design input only.
If decoupled_to_substrate capacitance extraction is selected, all extracted capacitance on selected
nets is decoupled to the substrate ground that is local to the area that the parasitic capacitor occurs
in the design and multiplied by the decoupling factor. Quantus will simply decouple capacitors to
the ground net (like decoupled extraction) if it cannot determine another node for connecting to.
Note: The decoupled_to_substrate option is only available for the Spice, Extracted View, xDSPF,
and xSPEF output formats.
Extracted coupled and decoupled capacitors on selected nets are distributed across RC networks
on the selected nets according to the Max fracture setting specified in the resistance section on the
Run form (see "Resistance Extraction"). Parallel coupled and decoupled caps produced at one
node on a net are merged to form one capacitor (with a corresponding parallel capacitance value).
When you use excluded nets proper extraction type in coupled mode, any net coupled to an
excluded net should have a reference of the excluded nets replaced with the ground node. In
decoupled mode, any caps for the excluded net to the ground node will not be present in the netlist.
Reducing Capacitance
There are a number of ways to reduce the output netlist size, but reducing the number of parasitic
capacitors produced. The filter_coupling_cap command decouples the coupling caps on a net
when certain thresholds have been met (see "filter_coupling_cap"). This command allows you to
set levels of coupling between two nets that are of interest, below which the capacitance will be
decoupled to ground. This preserves the amount of capacitance on the net, but reduces the overall
number of capacitors in the netlist.
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​Transistor-Level Inductance Extraction
​Quantus also supports inductance extraction for interconnect parasitic self and mutual inductance.
Quantus includes inductance extraction algorithm known Partial Element Equivalent Circuit (PEEC)
which outputs partial inductance values. This method calculates inductance for 90 and 45 degree
interconnect. 3 An optional broadband interconnect model (ladder network) can capture high
frequency effects such as the skin and proximity effects..
In the extraction flow for inductance the input to Quantus is provided by Assura LVS. Quantus
extracts the parasitic resistance (R) and capacitance (C) values. The Quantus field solver can also
be used for capacitance extraction of highly sensitive nets as needed. Quantus then computes the
self (L) and mutual (K) inductance for selected nets or portions of the layout.
Inductance extraction is tied to resistance and capacitance extraction in Quantus. The extract
command for extracting inductances is specified as:
extract -type [ rlc_decoupled | rlc_coupled | rlc_decoupled_to_substrate |
rlck_decoupled | rlck_coupled | rlck_decoupled_to_substrate ]
Note that in all cases resistance and capacitance are included in the extraction. The figure
below illustrates the addition of the parasitic inductors into the standard RC network.
Because inductance extraction also requires resistance extraction, the Techgen
-res_blocking command has the effect of regionally blocking inductance
RLCK Network
Inductance extraction is performed in four stages. First, the wires of each selected inductance net is
fractured into wire segments according to runtime settings (i.e., max fracture length or frequency
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file). The DC resistance of each wire segment is computed. Second, the coupling capacitance and
the partial self and mutual inductances at DC are calculated. If the optional broadband model is
specified (see "Wide Band Interconnect Model"), then the high frequency effects for resistance and
inductance are computed. Finally, the complete network is output as a unified netlist.
High-resistivity layers should be excluded from inductance extraction with the use of the Techgen lexclude option (see Quantus Techgen Reference Manual). This will exclude highly resistive, short
interconnect length layers, such as poly, from inductance extraction since the resistive effects of
these layers dominate their inductance effects. If the -lexclude option is not used to set up the
technology file prior to an extraction run, a warning message is produced in the Quantus output log.
​PEEC Inductance Extraction
The PEEC extraction algorithm is applied only within user-defined interaction regions. Interaction
regions are defined as non-overlapping areas on the layout. Even though each region is defined by
the (x,y) coordinates on the layout plane, the interaction regions are three-dimensional volume
elements since the process cross-section (z-direction) is also considered. Partial inductance values
are extracted only for specified nets or portions of specified nets within the user-defined regions.
To activate PEEC-mode you must specify the command:
inductance -peec_model true
One or more (non-overlapping) interaction regions must also be specified when the PEEC model is
selected:
inductance -interaction_region filename
Where filename specifies a file defining one or more interaction regions. See "inductance" for
details of defining this file.
Within each user-defined region, partial self inductances are calculated on all specified inductance
nets. Partial mutual inductances are calculated between nets, or portions of the nets, that reside in
the same interaction region, but are not calculated between nets that reside in different regions. The
interaction regions do not affect the resistance or capacitance calculations. This approach is a
simple and effective way to manage data size and runtime by processing nets together where
magnetic interactions are critical, while isolating nets where the mutual inductance interactions are
not considered important. Quantus processes each interaction region once in the vertical direction
and once in the horizontal direction to create two distinct sets of values containing the verticallyoriented and horizontally-oriented wire segments, respectively. In both processing steps, the 45
degree wires segments are also included while avoiding double-counting. The PEEC method is
most appropriate for analog or RF designs where the size of the block or design, or the number of
inductance nets, are reasonable.
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​
​Wide Band Interconnect Model
At low frequencies, current flows uniformly throughout the wire cross section. As frequency
increases, the resistance of a wire increases while the inductance decreases. For a single wire in
free space, current tends to crowd toward the surface of the conductor (i.e., skin effect). The current
distribution can be further modified due to the proximity effect, which is dependent on nearby
conductors and the relative phases of the currents within the wires.
By default, each line segment is represented by a resistor in series with a self inductor. When highfrequency effects are considered, a ladder network (see the figure below) comprised of frequencyindependent elements is used to model the broadband frequency-dependent behavior of each line
segment. The wide band model is enabled through the use of the Quantus command:
inductance -wide_band_model
Wide Band model for a Single Interconnect Segment
A single parasitic netlist with ladder networks is valid from DC to greater than 20 GHz. The value R 1
and the sum (L1 + L2) are the resistance and partial inductance values at DC, respectively. As
frequency increases, the total resistance of the ladder network increases as the inductor L2 starts to
electrically open, and more of the current flows through the resistor R 2; conversely, the total
inductance tends to decrease. This simple ladder network models the skin effect of a single
conductor segment. Between segments, mutual inductances and active elements (not shown in the
above figure) model the proximity effect.
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Inductance Filtering
Reduction and filtering algorithms are often required to produce a manageable netlist size. At the
same time, the integrity of the parasitic simulation results must be maintained.
Quantus employs a filtering mechanism that applies to the PEEC algorithm. It removes small line
segments (rectangles) before the partial inductance matrices are calculated. The size of these
rectangles is defined with the command:
inductance -filter_size value
In Quantus 8.1, the parasitic_reduction command has been enhanced to support reduction when
either inductance and/or substrate extraction has been performed. While this will not reduce the
number of parasitic inductors extracted from the design, it will reduce the overall netlist size when
inductance has been extracted. Refer to parasitic_reduction for more information.
Inductance Extraction Dependencies
Inductance extraction automatically merges parallel parasitic resistors even if the filter_res
-merge_parallel_res command is not specified. (see filter_res ).
Inductance extraction requires a min_res value of at least 0.001. If you specify the filter_res
-min_res command with a value less than 0.001, Quantus will issue a warning message
during the run, and substitute a value of 0.001.
Inductance extraction is not supported for SPEF output.
It is recommended to use RLCK extraction over RLC extraction for better accuracy (even
though it presents challenges for the amount of data). With RLC extraction, only selfinductance of metal line fractures is accounted for, and mutual inductance between pieces of
a wire is completely ignored. For example, an extracted inductance of a straight piece of wire
would be about the same in the RLC extraction mode as for a loop made of this wire
fractures - irrespective of the loop area and shape. Therefore, the RLC mode should not be
used in cases where mutual inductive coupling between pieces of wire is important or not
known. The RLC mode should be used with care and only in situations where inductive
coupling is known to be small or unimportant. While Quantus allows you to use the RLC
extraction mode, it is not recommended to use this mode due to the risk of potential errors in
extraction and simulation results.
Refer to the “Recommended Settings for RLCK Extraction” section to see how netlist size
can be controlled.
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Recommended Settings for transistor-level RLCK Extraction
The RLCK extraction controls the netlist size in order to simulate it without affecting accuracy.
However, if resistance extraction is not controlled the size of the netlist may increase. To control the
netlist size, the following settings are recommended:
Ladder networks: Do not set the Ladder Network option to on by default. For more details,
refer to Ladder Networks.
Slotted metals: Quantus treats shapes as they are extracted by the LVS. Slotted metals may
generate small resistances, so you may need to fill the metal slots for RLCK extraction.
Add explicit vias - RLCK extraction requires output_db -add_explicit_vias to be enabled
(true). If -add_explicit_vias is set to false, resistance extraction could create a single
resistor traversing several layers making it difficult for the L engine to calculate matching selfinductance (L) and mutual inductance (K) values.
Maximum Fracture Length: Metals are by default fractured at junctions, terminals, and vias
(when max_fracture_length option is set to infinite). For Inductance nets, metals are
fractured at bends also. For long transmission lines, it is recommended to set a maximum
fracture value of 100u micron instead of the default infinite value. (The value should not be
less than 50u as it may affect accuracy.)
If max_fracture_length set to infinite does not give sufficient accuracy, then recommended
settings of 50um should be sufficient for most applications. For more details on max fracture
length, refer to section Max Fracture Length and Units.
Stacked metal and via arrays: Inductances are extracted on metals but not on vias. Also, via
resistance is not merged with metal resistance (even if add_explicit_vias is off). However, via
array merging is important because it controls the number of resistances being extracted. It is
recommended to set the maximum via array size to the same value as maximum fracture
length.
For example,
extraction_setup \
-array_vias_spacing auto \
-global_frequency 50000 \
-max_fracture_length 100 \
-max_fracture_length_unit "MICRONS" \
-max_via_array_size 100
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For more details, refer to section resistance.
The RLCK netlist size can also be controlled with inductance nets file and user region file:
Metal1 being thin and high resistive may be excluded from user region file. Also, metal1
may have many short small connections, which means many metal1 resistances and a
huge amount of L elements. So the user region file may have only metal layers starting
from metal2.
The user region file will include all the areas that have Inductance to be extracted and
mutual inductance between each pair of inductance elements. To reduce the number of
Ls, the user region should only include critical areas for inductance effect. To reduce
number of Ks, it is possible to have more than 1 single region (K elements are not
extracted between distinct regions).
For more details refer to to section User Region.
The Inductance nets file can be used to limit inductance extraction only on specific nets (by
default all the nets are considered). With Inductance nets file the fracture length can be
controlled on a per-net basis (if no value is provided in that file, then max_fracture_length is
used). For more details, refer to inductance.
Netlist reduction:
Parasitic Reduction, using parasitic_reduction -enable_reduction true, supports
RLCK extraction, but will only apply to elements that do not have any L (excluded from
Inductance Nets File and User Region File). Parasitic Reduction will also reduce the
number of K and CCVS elements when Ladder Network is enabled
(wide_band_model). Parasitic reduction is not sensitive to frequency. For more details,
refer to section Reduce Parasitics.
Cell-Level Inductance Extraction
In the cell-level extraction flow for inductance, the input to Quantus is provided by the LEF/DEF
input and the output is in the DSPF/SPEF format. To enable the cell inductance extraction with
decoupled or coupled capacitance extraction, use the following CCL command:
extract -type [ rlc_decoupled | rlc_coupled ]
Cell-level inductance extraction supports the following:
Wide band network to model frequency dependent resistance and inductance computation.
Specification of the layers to process for inductance extraction using the following CCL option:
inductance -extract_layer_list <layername+>
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Automatic detection of return path segments on power/ground nets, that is, all nets with the
“USE POWER | GROUND” keyword in DEF are considered for return paths
Selected nets (file) extraction (extract -selection -nets_file | -net)
Distributed processing modes
The cell-level extraction flow requires the QTS300 (XL) and QTS310 (Advanced Analysis) licenses.
The following is a snippet of the DSPF output of the RLC network:
*|NET clk 3.30654e-15
*|P (clk I 0.0 137.19 0.765)
*|I (clk_L0:D0 clk_L0 D0 I 0.0 124.84 9.69)
*|I (C5134:D0 C5134 D0 I 0.0 141.015 4.105)
C1 clk 0 3.15479e-16
C2 clk_L0:D0 0 8.3941e-17
C3 C5134:D0 0 1.30492e-16
.
.
R1 clk clk:14 0.813682
L1 clk:14 clk:3 1.88591e-12
R2 clk:3 clk:15 2.84739
L2 clk:3 clk:15 2.28239e-12
Recommended Settings for cell-level RLC Extraction
To achieve better accuracy, the following settings are recommended:
Add explicit vias - RLC extraction requires output_db -add_explicit_vias to be enabled
(true). If -add_explicit_vias is set to false, resistance extraction could create a single
resistor traversing several layers making it difficult for the L engine to calculate matching
inductance (L) values.
Maximum Fracture Length: It is recommended to set a maximum fracture value of 200
microns (extraction_setup -max_fracture_length) instead of the default value.
Global Frequency: The extraction_setup -global_frequency option is set to the frequency of
interest, or to the maximum frequency of operation. It is recommended to set 4200MHZ for
most of high speed digital designs.
Wide Band Model: It is recommended to always set this option to true (inductance wide_band_model true).
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​Hierarchical Extraction
This feature of Quantus only applies to LVS input (Assura, Calibre, or Pegasus).
​H ierarchical netlist generation is required to support certain design flows. Hierarchical netlists can
be significantly more compact than the equivalent flat netlists, and can therefore be key to enabling
simulation and analysis. Hierarchical netlists enable you to perform simulations hierarchically
and/or incrementally.
An increase in performance and capacity can be obtained in hierarchical extraction due to the fact
that cells or blocks are often reused many times in a design. In hierarchical extraction a cell or block
is extracted only once, and the extracted data is re-used for each recurring instance. Quantus
supports hierarchical extraction through the use of the command:
hiearchical_extract -hierarchical_cell_list_file filename
Where filename specifies a list of cells to use. Hierarchical extraction in Quantus requires that
each specified cell is fully contained with its own reference to power and ground to insure correct
results. Quantus also requires all layers that form a cell to be found on the same level of the design
hierarchy. An error condition occurs if layers forming a device exist in different levels of hierarchy.
Hierarchical Extraction
During hierarchical extraction, Quantus views the contents and extracts the parasitics of cells
according to the netlist= control statement specified in the hierarchical_cell_list_file. See
"hierarchical_extract" for more information on defining this file. Any results of the cell-level
extraction are stored hierarchically in the output. Cells that are not specified as hierarchical cells are
simply flattened to the top-level of the design during extraction.
Note: Setting the HRCX_GRAY_BOX_FILL environment variable will cause Quantus to fill any small
gaps in the shapes of hierarchical cells to create larger virtual shapes and reduce the extraction
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time for that cell:
setenv HRCX_GRAY_BOX_FILL Y
For capacitance extraction at the top-level of the design, each hierarchical cell is viewed according
to the capacitanceView= control statement in the hierarchical_cell_list_file. The hierarchical
cells are viewed as a graybox (capacitanceView=grayBox) in which the contents of the shape are
grounded. This is the default for hierarchical extraction. Or the cells are viewed as blackbox in
which the shapes inside the cell are not seen by the top-level of the design, and therefore have no
interaction with the shapes at the top-level (capacitanceView=blackBox).
Using the above figure, "Hierarchical Extraction", as an example, you can see that there are two
cells, Cell_A and Cell_B, as well as the top-level design. In the case of Cell_B there are two
instances of the cell, one instantiated inside Cell_A and one instantiated at the top-level of the
design. In this example, if Cell_A is specified in the hierarchical_cell_list_file with the control
statements netlist=none and capacitanceView=grayBox, then an empty subcircuit for Cell_A is
output to the netlist as no extraction is performed on the cell, but the shapes inside Cell_A are
viewed as grounded and interacting with the top-level interconnect for capacitance extraction of the
top-level of the design. If Cell_B is specified with netlist=extractedNetlist, and
capacitanceView=blackBox, then the contents of Cell_B are extracted and the full subcircuit of
Cell_B is output to the netlist, but the cell is viewed as a blackbox for capacitance extraction and
there is no interaction with the top-level of the design.
Note: Since Cell_B is a blackbox, all instances of it are viewed as a blackbox. If Cell_A is extracted
(netlist=extractedNetlist) then the contents of Cell_B would not be visible to, or have interaction
with Cell_A.
For design input coming from Assura LVS, the RSF for the LVS run should include the ?
preserveCells avParameter (see the Assura Command Reference manual for more information).
This ensures that specified hierarchical cells will not be flattened during the LVS run.
The list of cells specified by the ?preserveCells command should at least match the cells specified
in the hierarchical_cell_list_file. If this command is not used during the LVS run some of the
hierarchical cells might be incidentally flattened by LVS, preventing Quantus from evaluating the
flattened cells hierarchically.
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Substrate Extraction with Quantus AoT
This feature of Quantus only applies to LVS input (Assura, Calibre, or Pegasus).
With the increasing complexity of mixed signal and RF designs, and with the decreasing feature
size of device technologies, back annotation of parasitic coupling through the substrate has
become a key issue in eliminating problems and iterations from the design of new circuits.
Substrate extraction has been directly integrated into Quantus with the Quantus AoT flow. This is
intended to address the needs of the "Analog on Top" designer who works with medium to large
designs with significant analog content, and some digital content. Some key sign-off concerns of the
AoT designer are digital noise propagation and its impact on the analog content, and the
effectiveness of guard rings, separate power supplies, and other noise isolation techniques.
Quantus directly supports a simplified understanding of the substrate through the LVS geomStamp
command and the stamp=2 statement in the layer_setup file. However, Quantus AoT adds a highly
accurate substrate model to the extracted netlist.
Quantus AoT integrates substrate parasitic extraction into Quantus to develop a more thorough
model of the substrate. It uses physical layout and technology descriptions to generate a
macromodel of the substrate. The implemented model features resistive bulks and wells, linked by
junction capacitances (see the below figure). The intrinsic capacitance of highly resistive substrates
is also incorporated into the model when needed, according to the user-defined maximum
frequency of operation (see the Maximum Operating Frequency chapter). This model is
implemented in a netlist format that can be directly read by simulators such as UltraSim, Spectre
RF, and others.
Quantus AoT Substrate Model
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The Quantus AoT flow directly integrates the substrate extraction and substrate noise analysis tools
into Quantus. This eliminates the need to rely on the SKILL interface required by Assura RF which
provides for overall improvements to performance, and capacity. Substrate extraction and SND
capacity has increased to support medium-sized AoT design size.
The Quantus AoT flow supports existing Assura RF PDKs without modification. In this case, you
must rerun Assura LVS on the design using the Assura 3.1.7_USR1 or later release before doing
substrate extraction with Quantus AoT. This is required to update some internal files required by the
new flow. The following are the complete requirements for using the Assura RF PDK in the Quantus
AoT flow:
The "RF" switch is enabled in the LVS rule deck
The keyword "TIE" or "tie" is used in both the extract.rul rule deck and SCparameters.cds
file to identify extracted TIE devices.
Note: In the new Quantus AoT flow, the file SCparameters.cds is no longer used, and is
replaced by the substrateFile which is integrated into the Quantus technology directory. The
substrateFile provides a mapping between the design data and the substrate extraction
technology file. For more information, refer to the "Substrate Extraction Files" chapter of
Quantus Techgen Reference Manual.
The saveDerived() command with layer purpose "SNA" is used in the extract.rul file:
saveDerived( nwell_sna ("SNA" "nwell" ) ext_view)
Devices are extracted so that they include a back gate connection (or bulk connection) to the
substrate. For example, four terminals and not three for a MOS or LDD device, and three
terminals for a drawn Resistor or Capacitor. Refer to the Assura Physical Verification
Command Reference for more information on extracting devices.
All contact layers used to connect to the substrate network must be connected to an LVS layer
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that is mapped as a substrate layer in the procfile. For example, for the following contact layer
in the layer_setup file:
pro_cont=contact ext_cont=contact ...
which connects metal1 to diffusion in the lvsfile:
connect diffusion metal1 by contact
where the procfile contains the following step 1 layer definitions in the deposition section
(defining substrate layers):
step 1 substrate sub [...]
step 1 substrate diff [...]
then the layer_setup file must contain the following layer mapping:
pro_layer=diff ext_layer=diffusion
Or the contact layer will not be identified as a connection to the substrate network, and some
substrate connections may be missed as a result.
Rerun LVS using Assura 317_USR1 with the RF switch enabled
If you specify the RSF command ?rulesFile when running Assura LVS, then the full path to
the rules file must be specified. If you enter a relative path while running LVS, then Quantus
may not be able to find extract.rul file. Refer to the Assura Physical Verification Users
Guide or the Assura Physical Verification Command Reference for more information on
specifying the rules file.
Running Quantus AoT
The Quantus AoT flow is driven by the substrate technology file (SCtechnology) created with the
Quantus TCT program (see Quantus Substrate Technology Characterization Manual ). Quantus
AoT generates aSubstrate Abstract View (SAV) from the layout, the circuit netlist, and technology
information from the SCtechnology file.
Any one or more of the following Quantus commands activates substrate extraction in the Quantus
AoT flow:
substrate_extract -extract_under_contacts true
substrate_extract -extract_under_devices true
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extract -substrate_nets_file <filename>
Refer to substrate_extract or "extract" for more information on these commands. When running from
the Quantus command file, you must also specify the required substrate technology files with the
use of the new -substrate_technology_ xxx options of the process_technology command (see
"process_technology").
You can also enable substrate extraction and substrate noise analysis through the Quantus UserInterface and the Quantus Parasitic Extraction Run Form . See Quantus Graphical User Interface,
Substrate Extraction, and Quantus Substrate AC Analysis chapters for more information.
Quantus AoT offers some new substrate extraction features:
Increase the capacity of substrate extraction and surface noise distribution analysis.
Run substrate extraction in batch mode using the Quantus command language, or
interactively through the user-interface.
Support for both Spice netlist and extracted_view output.
Perform only substrate parasitic extraction, as well as the comprehensive device, interconnect
and substrate extraction.
Select which TIEs to connect to the substrate network by specifying an area or areas of the
design.
Define multiple well-to-substrate voltages.
Specify a new fast substrate reduction algorithm to improve reduction and simulation
runtimes, as well as the more exhaustive default reduction mode.
Define the bounding box of the Substrate Abstract View (SAV).
Generate a SAV for Substrate Noise Analysis without having to perform a complete substrate
extraction.
Terminate the Quantus AoT run at any point in the flow, including substrate extraction and
reduction.
New in EXT 10.1, multiple CPU support has been added for substrate extraction resulting in
an improved performance. In Quantus-AoT flow, the multiple CPU support is triggered by the
distributed_processing -multi_cpu CCL option (see distributed_processing).
When performing substrate extraction, the supported Quantus extraction modes are RC, RLC, and
RLCK type extraction only.
​ uring substrate extraction Quantus AoT generates the SAV which becomes the input to the
D
substrate extractor, which then creates a three-dimensional substrate model. Two dimensions of the
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substrate model are given by the X-Y plane of the layout objects, and the third dimension is given
by the technology description in the SCtechnology file. The substrate netlist, which contains the
electrical model of the substrate, including parasitic capacitors and resistors, is generated from this
three-dimensional model. The substrate netlist can be included in the design view as a subcircuit to
more accurately simulate the entire design.
The SAV is also used by the Surface Noise Distribution tool (see the Quantus Substrate AC Analysis
chapter).
The three-dimensional substrate model generated by Quantus AoT can be quite large. This
parasitic RC model includes a relatively small number of external nodes, which connect the
substrate parasitic network to the rest of the circuit (through optional connection points such as
critical interconnect nets, power supplies, and device backgates), and a much larger number of
internal nodes. Substrate RC Reduction can significantly reduce the number of internal nodes. The
reduced network retains the critical electrical response of the network, while reducing postextraction simulation time.
Note: Substrate RC Reduction can only be applied to circuits with less than about 5,000 external
nodes. For larger designs Substrate Reduction can be turned off to enable a successful substrate
extraction.
Extracted View Output:
The substrate.subckt file and SAV file (SCabstractview) will be placed in the extracted_view
directory:
<library>/<cellname>/<extracted_view_name>
An instance of the substrate in the extracted_view will point to the relative path of the
substrate.subckt file.
Spice Output:
substrate.subckt file and the SAV will be placed in the same location as the Spice output file. Files
will be named as follows:
<spice_file_name>.sp
<spice_file_name>.sp.substrate
<spice_file_name>.sp.sav
An .include statement inside the Spice output will indicate the relative path of substrate.subckt
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file:
.include "<spice_file_name>.sp.substrate"
An empty .subckt for TIE devices will be added to the Spice output if the LVS rule deck extracts TIE
devices as is the case with the Assura RF PDK.
Note: Differences may be seen between Spice and extracted_view simulation results.
Extracted_view may have some post-processing of device parameters, while the Spice output will
not.
Obtaining Output
Setting up the Output
Supported Output Formats
Setting up the Output
Quantus has many options to specify the type of output you want to create, any special formatting
requirements of the output, and the location and name of the output files. The following sections
discuss preparing to create output in Quantus and then the details of creating each supported
output format.
Specifying the Output File Name and Directory
​To specify the name of the output file created by Quantus, specify the following command.
output_setup -file_name filename
No extension is required for filename , as Quantus will append an extension specific to each
output format: .dspf, .spef, .sp. If you do not specify a filename with the output_setup command
the default will be the name of the design. Therefore, by default, the output DSPF netlist from
Quantus will be named design_name .dspf.
When running Quantus sensitivity extraction, or extraction for multiple process corners (see
"Managing Process Corners"), the output netlists are written with the specified filename (or the
default design_name ) followed by an underscore (`_'), and then the process corner name. An
extension is added to indicate the netlist format. An example follows:
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<design_name>_<corner1>.dspf
<design_name>_<corner2>.dspf
By default Quantus writes output files to the directory from which the tool was executed. To specify
a different directory for the output use the following command:
output_setup -directory_name directory
Compressed Output
By specifying the output_db -type < type > -compressed true command, you can compress the
output netlist with the gzip utility. The Spice, DSPF, and SPEF netlist formats can be compressed
with this command. For more information refer to output_db.
Supported Output Formats
​​​​​​​​​
You can generate Quantus netlist output in the form of standard or extended DSPF, a SPEF netlist
of a variety of formats to serve different purposes, and standard SPICE netlist. You can also write
extracted parasitic information back into the input OpenAccess database.
In general, Quantus supports the following outputs in the Assura-Quantus, Pegasus-Quantus, and
QCI flows:
Spice
Transistor Level DSPF
(xDSPF)
Extracted View
Lvs Extracted
View
SPEF
Transistor Level SPEF
(xSPEF)
DSPF
Hierarchical xSPEF
Hierarchical Spice
Hiearchical
xDSPF
Hierarchical Extracted View
Note: When Run Pegasus- Quantus is selected from the Quantus menu, the only available outputs
will be Spice, Extracted View, Lvs Extracted View, DSPF (cell level), SPEF (cell level), Power Grid
Database, Transistor DSPF, and Transistor SPEF.
Of course, Quantus also creates a log file of the extraction run as indicated with the log_file
command prior to extraction, or to the default qrc.log file in the working directory. You can also
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specify various reports that can be output from Quantus.
Available Outputs from Quantus
DSPF Output
output_db -type dspf
-subtype standard|extended
-parameter_name width <string> | length <string> | area <string> |
layer <string>
-cdl_out_map_directory <directory>
-sub_node_char <string>
-include_parasitic_cap_model true|false|comment
-include_parasitic_res_model true|false|comment
-include_parasitic_res_width true|false |
-include_parasitic_res_width_drawn true|false
-include_parasitic_res_parameters_unscaled true|false
-include_parasitic_res_length true|false
-include_cap_model true|false|comment
-include_res_model true|false|comment
-hierarchy_delimiter <string>
-pin_delimiter <string>
-busbit_delimiter <string>
-device_finger_delimiter <string>
-pin_order_file <file>
-pin_cap_file <file>
-units [ micron | angstrom ]
-disable_instances true|false
-disable_subnodes true|false
-header_file <file>
-output_xy canonical_cap | parasitic_cap | canonical_res | parasitic_res |
diode | mos | bipolar | generic
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-output_incomplete_nets true|false
-output_unrouted_nets true|false
-compressed true|false
-map_eeq_to_master true|false
-escape_special_character true|false
-match_res_cap true|false
-add_cap_prefix true|false
-add_explicit_vias true|false
-add_bulk_terminal true|false
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SPEF Output
output_db -type spef
-subtype standard|starN|extended
-parameter_name width <string> | length <string> | area <string> |
layer <string>
-cdl_out_map_dir <directory>
-sub_node_char <string>
-include_parasitic_cap_model true|false|comment
-include_parasitic_res_model true|false|comment
-include_parasitic_res_width true|false |
-include_parasitic_res_width_drawn true|false
-include_parasitic_res_parameters_unscaled true|false
-include_parasitic_res_length true|false
-pin_delimiter <string>
-busbit_delimiter <string>
-device_finger_delimiter <string>
-pin_cap_file <file>
-units [ micron | angstrom ]
-disable_instances true|false
-disable_subnodes true|false
-header_file <file>
-output_xy canonical_cap | parasitic_cap | canonical_res | parasitic_res |
diode | mos | bipolar | generic
-output_incomplete_nets true|false
-output_unrouted_nets true|false
-compressed true|false
-map_eeq_to_master true|false
-escape_special_character true|false
-match_res_cap true|false
-add_explicit_vias true|false
-add_bulk_terminal true|false
-predefined_spef_cells_file <file>
-use_name_map true|false
-name_map_start_index <value>
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By default, Quantus 14.10 always outputs unscaled coordinates for pins and nodes for
SPEF and DSPF in Quantus cell level extraction. The coordinates in the short report file ( a
file with a .shorts extension, if the option write_incomplete_shorts_nets_file true is set)
are also changed to unscaled coordinates. It does not change the length, width, area of
resistors.
Creating Cell-level DSPF/SPEF or Transistor-level DSPF/SPEF
Quantus can output both cell-level (DSPF/SPEF) and transistor-level (XDSPF/XSPEF) netlists.
The Detailed Standard Parasitic Format (DSPF) contains interconnect parasitic elements that can
be converted to delays for timing analysis tools. DSPF can be used with any delay calculator to
produce a standard delay format (SDF) file used for simulation.
SPEF netlist provides the same information as the DSPF netlist but in a compressed format that
reduces output file size by as much as five times. The DSPF netlist is crafted to be Spice equivalent
so a DSPF file can be read by a Spice simulator. However, the SPEF netlist format is not required
to be Spice compatible.
Starting from EXT 13.1 HF1 release:
Quantus writes out all pins with zero capacitance in the SPEF file, provided the net has
zero total capacitance and still features a R-network.
Quantus with Turbo reduction removes driving cell information (*D) from the CONN
section of the SPEF file. This will have no impact on the timing flows.
To support DSPF (or SPEF) output, following steps must be performed:
1. Cell Selection:
a. defined in the DEF or OA input
OR
2. specified with the ?dspfCells command in Assura LVS
The LVS command ?dspfCells ensures that the listed cells are preserved hierarchically and
are consistent for the DSPF flow. The Assura LVS exports the cells to the runName.dcl file
for use by Quantus.
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OR
3. specified with the library_cell_list_file option in the Quantus command file for Calibre
and Pegasus inputs as shown below:
input_db -type pegasus | calibre -library_cell_list_file <filename>
Corresponding to option DSPF Cell File option in GUI, Quantus creates the runName.dcl file for the
Calibre and Pegasus input flows.
Calibre and Pegasus have the following possible setups to ensure that the cells are preserved:
The -hcell option that takes a file list of cells, layout_name, schematic_name or using hcell
or hcell_file in the rules file
The rule file also contains rules that preserve hierarchy
In Pegasus format :
preserve_cell_list
In Calibre format :
LVS PRESERVE CELL LIST plist
LAYOUT CELL LIST plist "nm$$*" "pm$$*"
Parasitic extraction
With LVS input (Assura, Calibre, or Pegasus) Quantus views DSPF cells as black boxes by
default. This means that no shapes are seen within the DSPF cells for parasitic extraction.
However, for DEF or OA input, the view of the cell is determined by the input library data. Use
the grayBox command to change the view of cells that Quantus uses during extraction. See
"graybox"for more information.
DSPF/SPEF netlist generation.
Transistor level DSPF and SPEF (XDSPF or XSPEF) output is also a feature of Quantus.
This output is only available with LVS input, and is not supported for DEF or OA input.
Devices such as MOS/LDDs, BJTs, Diodes, drawn Resistors and Capacitors are treated
similar to cells in the regular DSPF output format. The number of parasitic capacitance
records is the same as SPICE output. The number of parasitic resistors may increase slightly
to account for abutment resistors.
During extraction, Quantus automatically determines whether to output cell-level or transistorlevel DSPF or SPEF output by testing for the presence of a DSPF cells file (run_name.dcl) in
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the input directory name. If a .dcl file is found then Quantus will output a cell-level DSPF
netlist. However, if there is no .dcl file, then Quantus outputs a transistor-level DSPF netlist.
Note: In the case of either Pegasus or Calibre input data, the .dcl file is created when the
input_db -type pegasus (or calibre) -library_cell_list_file is specified in the Quantus command
file.
Making Connections for Cell-level DSPF/SPEF Output
In Cell-level DSPF output mode, with 2 levels of hierarchy, the connectivity information must be
complete by routing layer for each level of the hierarchy. There is no connection by vias through
different levels of hierarchy. The DSPF cells must have IO pins on metal layers. For example,
consider the two similar cases (see the below figure) where there is a metal1 wire in a cell and
metal2 wire in the top cell, with a via (m1_2via) connecting metal2 to metal1.
Hierarchical Connections for DSPF Extraction
In Case A, inside the cell instance there is a metal1 wire. In the top cell there is a metal2 wire and
m1_2via connecting metal2 to metal1. However, since there is no metal1 in the top cell (or
conversely, no metal2 in the child cell), the metal2 to metal1 connection is not maintained through
the hierarchy of the cell by the m1_2via. The connection is lost through the hierarchy resulting in an
open condition.
In Case B, the same situation exists with the addition of something new. The m1_2via is also
enclosed by a metal1 wire in the top cell. Since the metal1 in the top cell that overlaps (or abuts) the
metal1 wire in the cell, the metal1 port is created by Quantus and the metal2 connection to the cell
is correct. Note that the connection through the m1_2via is on a single level of the hierarchy (the top
cell in this case), and the connection through the hierarchy is carried through the metal1 connection.
For Hierarchical Extraction a correct netlist will be generated for either of the connectivity
cases discussed above.
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Connection of cells by abutment is also supported. In GDSII/DFII/OASIS input to DSPF/SPEF
output flow, cells whose instance pins that are connected by instance abutments without any toplevel wire routing are connected by Quantus through artificial 0.001 ohm resistors having very large
width values (1000000000) and zero length values (L=0).
Cells connected through abutment have the following restrictions:
The connection by cell abutments must be made through the same LVS layer.
The connection between two cell instances through a via is not supported.
Note: In earlier Quantus releases,for a proper connection in Quantus, all instance pin shapes had
to overlap/abut wire routing in the top cell (on the same layer). For instance, two cells (X2.out and
X3.out) whose shapes overlapped each other with no top cell routing to join them were not
connected in Quantus (although they were considered connected in an LVS tool).
Connection of Cells by Abutment
In the above figure, cells X1.in and X2.out are connected with a small wire. In addition, cell X2.out
abuts cell X3.out. Earlier, Quantus did not connect cells X2.out and X3.out since there was no top
cell routing to join them. However, now, connection between these cells is made through a small
abutment resistor (.001 ohm).
You must also be careful when using resistance blocking (see Techgen -res_blocking command in
Quantus Techgen Reference Manual). Blocking resistance on a layer makes shapes conductive
(non-resistive). However, DSPF requires resistive materials for extracting netlist connectivity
between cells (this is also true for hierarchical extraction). The res_blocking shapes can block
interconnect shapes in a cell causing connection errors. Shapes in a cell making connection with
other cells in the hierarchy should not be blocked.
Standard or Extended DSPF/SPEF
Quantus can output a standard format DSPF netlist, on an extended format. The extended DSPF
format provides additional information to the standard DSPF netlist:
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Adds the layer name to the Sub-node, Instance, Pin and Port sections of the DSPF netlist.
Adds the length, width, and layer name to the Resistor description.
Adds the area and layer name to the Via Resistor description.
Starting with the 8.1.5 release, Quantus also provides the layer information for transistor-level
XDSPF/XSPEF output including the hierarchical mode. However, the length, width, area, and
layer strings do not have an impact on the transistor-level XDSPF/XSPEF netlists.
Defining Pin Order for DSPF Output
Simulation requires that the order of pins in the output DSPF netlist match the order of pins
specified in the Spice simulation models. This can be specified through the use of the output_db type dspf -pin_order_file command.
The file format and the number of files specified for the pin_order_file argument vary
depending on DEF/OA input or Assura/Pegasus/Calibre input.
Reduced Netlist Output
By specifying the output_db -disable_instances true or the -disable_subnodes true arguments,
you can reduce the size of the output DSPF or SPEF netlist. These commands eliminate a level of
detail from the output netlist while preserving the integrity of the netlist. For more information refer to
output_db.
Predefined SPEF cells
Predefined SPEF cells only applies to DEF or OA design input.
Quantus allows you to specify a file that contains the names of blocks or cells pre-characterized in
SPEF format to be incorporated into the design. Quantus will exclude the listed cells from
extraction, and merge the SPEF netlist of the specified cells into the output SPEF netlist of the
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extraction run. This is done with the use of the command:
output_db -type spef -predefined_spef_cells_file_name filename
DSPF/SPEF Output for Multiple Process Corners
Running Quantus on multiple process corners will result in multiple DSPF or SPEF netlists output
from a single Quantus extraction run. The corner name will be appended to the output file name as
shown in below example.
Note: DSPF and SPEF output for multiple process corner extraction are only supported for DEF or
OA inputs (input_db -type def or input_db –type oa).
Example1:
The following command file example specifies three process corners and defines the output to be
an extended DSPF netlist in compressed form:
process_technology -technology_corner typical corner1 corner2
output_setup -file_name dma_mac
output_db -type dspf -subtype extended -compressed true
The output files created by the preceding command file will be:
dma_mac_typical.dspf.gz
dma_mac_corner1.dspf.gz
dma_mac_corner2.dspf.gz
Note: If a single process corner is specified, the corner name is not appended to the DSPF/SPEF
output. For example:
process_technology -technology_corner corner1
output_setup -file_name dma_mac
output_db -type dspf -subtype extended -compressed true
The output file created by the preceding command file will be:
dma_mac.dspf.gz
Example 2:
The following is an example of temperature dependent multiple process corners.
The corner.defs file will be:
DEFINE nominal nom_tech
DEFINE RCmin rcmin_tech
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DEFINE RCmax rnmax_tech
The Quantus command file will be:
input_db -type def\
process_technology -technology_library_file ./techlib.defs -technology_name tech \
-technology_corner nominal nominal RCmin RCmax -temperature 25 125 -40 125
output_setup -file_name my_test
The output SPEF file names from above setup will be:
my_test_nominal_25.spef
my_test_nominal_125.spef
my_test_RCmin_-40.spef
my_test_RCmax_125.spef
xDSPF Output for Multiple Process Corners
Running Quantus on multiple process corners will result in single xDSPF netlist with multiple-value
format from a single Quantus extraction run.
Note: xDSPF output for multiple process corner extraction is only supported for LVS input (Assura,
Calibre, or Pegasus).
The parasitic capacitance and resistance values for multiple process corners will use vector format
in the xDSPF output. The vector format that will be used in place of RC values is shown below. The
C1, C2, and C3 are the process corner names. This format is used in the existing SPICE and
extracted view flows.
*|NET net1 ‘Ctot_c1*C1+Ctot_c2*C2+Ctot_c3*C3'
R1 net1#1 net1#2 ’R_c1*C1+R_c2*C2+R_c3*C3’
C1 net1#1 net2#1 ’Cc_c1*C1+Cc_c2*C2+Cc_c3*C3'
For the xDSPF, the default process corner names will be changed to “C1”, “C2”, “C3”, … for both R
and C elements and if the process_corner_names file is used, same corner name should be
specified for both R and C elements.
To implement the default process corner names, the sample file shown below will suffice. The
variable “i” would assume the value 1, 2, 3, … for the first, second, and third technology directory,
respectively.
C C=Ci
R R=Ri
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The output file name is specified using the below CCL. If this CCL is not specified, the output file
name will use the design name by default.
output_setup -file_name <outfile>
Note: You can give any name to the output file. However, the recommended naming convention for
the <outfile> parameter in the CCL, output_setup -file_name is “_mv”. For example, you can
name the output file, <design>_mv.dspf.
Example
The following command file example specifies three process corners C1, C2, C3 with temperature
values t1, t2, and t3, respectively:
process_technology \
-technology_library_file "./ techlib.defs"
-technology_name tech \
-technology_corner C1 C2 C3
-temperature t1 t2 t3
output_setup -file_name design_mv.dspf
Sample MPC xDSPF Output File
Header section
--------------------------------------------------------*|OPERATING_TEMPERATURE 25 25 25 << operating temperature
** CORNER_NAME C1 C2 C3 << corner names
Parasitic section
---------------------------------------------------Total cap format
*|NET A2 'C1*4.57697e-16+C2*4.57697e-16+C3*4.57697e-16'
Coupling cap format
C1 A2#9 VSS 'C1*1.32158e-17+C2*1.32158e-17+C3*1.32158e-17'
Resistance format
Rm_2_11 XM14#g A2#6 'C1*378.702454+C2*378.702454+C3*378.702454'
The multiple process corner support in xDSPF is illustrated in the below figure.
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xDSPF Output for Multiple Process Corners
Note: For the xSPEF format, the multi-value format used in the Quantus(DEF/OA) will be used.
Single Value Multiple-File MPC Output
Starting with the 20.11 release, for the Quantus transistor-level flow, you can generate single-value,
multiple output files in a single Quantus run for multiple process corners. Each file is specific to a
process corner.
This feature is supported for all LVS input formats (Calibre, Pegasus, and Assura), and for the
xDSPF/xSPEF output formats. The feature is not supported in the SPICE and Extracted View and
Smart View formats. Cell level DSPF/SPEF format from LVS is not supported.
To enable this feature, the following CCL is required to be set to false.
output_db -output_multi_value_rc
Depending on whether this option is used in the cell-level or the transistor-level flow, the default
value of -output_multi_value_rc is different.
For DEF/OA cell-level flow: output_db -output_multi_value_rc true | false
For transistor-level flow: output_db -output_multi_value_rc true | false
For the transistor-level flow, the default value of this option is true. In this flow, when
output_multi_value_rc is set to false, Quantus generates single-value multiple xDSPF/xSPEF
files in a single Quantus run for multiple process corner extraction.
The multiple output file naming convention will follow that for Quantus(DEF/OA).
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The output files are named as follows:
<outfile>_<corner>_<temp>.dspf[.gz]
<outfile>_<corner>_<temp>.spef[.gz]
[<outfile>_<corner>_<temp>.dpf[.gz]]
<= First corner only
Key Considerations for this Support
If the netlist post processing is specified, it will be applied to each output file separately. The
following CCL is used:
output_db -postprocess_output_netlist true | false
When the connectivity checker is applied, it will only be applied to the first output file. The
connectivity checker support for the multi-file MPC support will be for the following CCL
settings:
output_setup -enable_connectivity_checker flat | hierarchical | false \
-connectivity_checker_bypass_postprocessing
true | false
In the MPC mode, reduction is not supported. The following CCL will not work:
parasitic_reduction -enable_reduction true
The performance of the multiple-file output format is not as good compared to that of the
single-file output format. This is because the former’s output is N times larger than that of the
latter, where N is the number of process corners.
Temperature corner support is not yet provided.
In the SPEF format, there is an optional device file (.dpf file), which will not vary across
multiple process corners. Therefore, only the first corner device files will be provided, if
requested.
Hierarchical extraction enabled using the hierarchical_extract hierarchical_cell_list_file CCL command is supported in the MPC mode - both the multivalue, single-file MPC, and the single-value, multi-file MPC.
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SPICE Output
Spice output from Quantus only applies to LVS input (Assura, Calibre, or Pegasus).
output_db -type spice
-hierarchy_delimiter <string>
-device_finger_delimiter <string>
-header_file <file>
-output_xy canonical_cap | parasitic_cap | canonical_res | parasitic_res |
diode | mos | bipolar | generic
-postprocess_output_netlist <string>
-output_self_looped_diodes true|false
-include_parasitic_cap_model true|false|comment
-include_parasitic_res_model true|false|comment
-include_cap_model true|false|comment
-include_res_model true|false|comment
-include_parasitic_res_width true|false |
-include_parasitic_res_width_drawn true|false
-include_parasitic_res_parameters_unscaled true|false
-include_parasitic_res_length true|false
-sub_node_char <string>
-add_explicit_vias true|false
simulator lang=spice insensitive=no
Spice as Input to Spectre Simulator
For Spectre to read in the Quantus-generated SPICE netlist as input, ensure that you add the
following to the SPICE netlist before inputting the netlist to the Spectre simulator:
simulator lang=spice insensitive=no
SPICE Output of Multiple Process Corners
Note: Spice output is only available for LVS input.
The parasitic capacitance and resistance values for multiple process corners will take the form of a
numerical expression in the SPICE output. The numerical expression is enclosed in single quotes,
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with no blank characters inside.The numerical expression is in the form:
`P1*val_1+P2*val_2+...'
Where P1 and P2 are the process corner property names. The default values are c1, c2, c3... for
parasitic capacitors (corresponding to corner1, corner2, corner3), and r1, r2, r3...for parasitic
resistors.
The property name for each process corner is user-definable, and is stored in a file named
process_corner_names located in each technology directory. An example of the
process_corner_names file follows:
C C=cap1
R R=res1
Where each line starts with the SPICE character for the parasitic element (C for caps, R for
resistors). The same character is used for the parasitic devices primary value (C = capacitance for
instance).
CDL Output from SPICE
If the -cdl argument was specified during Techgen compilation, the output_db -type spice
command will create a CDL format netlist. See Quantus Techgen Reference Manual for more
information.
-- In case of the transistor flow (SPICE output), the parasitic RCs in the multiple process
corner mode are not written as multiple SPICE files with scalar RC values, but a single
output file with vector RC values
-- The file name “process_corner_names” is fixed, and no other name can be used for this
purpose.
-- In case of the extracted view output, the same expression format as for the SPICE output is
used in the Quantus internal file “extview.tmp” (which is the input to construct the extracted
view).
The multiple process corner support is illustrated in the following diagram:
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Here, a single Quantus run is made with multiple process corners (that is, multiple Quantus
technology directories), and the output is a single SPICE file, or a single extracted view. The default
process corner names are R1/C1, R2/C2, … , Rk/Ck for technology directory 1, 2, …, K,
respectively. The process corner names allow you to select a single corner RC value.
Example:
The following command file example specifies three process corners and defines the output to be
SPICE:
input_db -type pegasus
output_db -type spice
process_technology -technology_library_file "./assura_tech.lib"
\
-technology_corner C1 C2 C3 -temperature 25 125 -25
-technology_name Tech
In above example, C1, C2, and C3 are pointing to the same process corner (typical), so the
capacitance value in the final netlist will be the same in each case but the resistance value will be
different because temperature values are different for each corner.
The syntax of the corner.defs file present in the technology directory “Tech” is:
DEFINE C1
DEFINE C2
DEFINE C3
./Tech_def1
./Tech_def2
./Tech_def3
The side directory “Tech” has the following three technology directories as per the three corners
defined in the corner.defs file.
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Tech_def1
Tech_def2
Tech_def3
Inside each directory, there is a file named as "process_corner_names" as shown below:
"process_corner_names" in Tech_def1
C C=cap1
R R=res1
"process_corner_names" in Tech_def2
C C=cap2
R R=res2
"process_corner_names" in Tech_def3
C C=cap3
R R=res3
With the above setup, the multiple corner Quantus run generates the following SPICE output:
Rh1
Rh2
B2#8
B2#10
B2#10
B2#11
'res1*0.34771+res2*0.40751+res3*0.31694'
'res1*0.60755+res2*0.71204+res3*0.55377'
C1
C2
VSS
VDD
B2
VSS
cmodel
cmodel
$M1
$M1
'cap1*1.00272E-17+cap2*1.00272E-17+cap3*1.00272E-17
'cap1*2.17743E-16+cap2*2.17743E-16+cap3*2.17743E-16'
Note: In case there is no “process_corner_names” file, the default values are c1, c2, c3 for parasitic
capacitors (corresponding to corner1, corner2, corner3), and r1, r2, r3 for parasitic resistors.
Therefore, the output in the SPICE file will be:
Rh1
Rh2
B2#8
B2#10
B2#10
B2#11
'R1*0.34771+R2*0.40751+R3*0.31694'
'R1*0.60755+R2*0.71204+R3*0.55377'
C1
C2
VSS
VDD
B2
VSS
cmodel
cmodel
$M1
$M1
'C1*1.00272E-17+C2*1.00272E-17+C3*1.00272E-17
'C1*2.17743E-16+C2*2.17743E-16+C3*2.17743E-16'
Note: In case you run Quantus for a single corner individually, you will get the following output:
SPICE output file for “C1 ; 25deg”
Rh1
Rh2
B2#8 B2#10
B2#10 B2#11
C1
C2
B2
VDD
0.3477
0.6076
VSS
cmodel
VSS
cmodel
$M1
$M1
1.00272E-17
2.17743E-16
SPICE output file for “C1 ; 125deg”
Rh1
B2#8
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Rh2
B2#10
C1
C2
B2
VDD
B2#11
VSS
VSS
0.7120
cmodel
cmodel
$M1
1.00272E-17
2.17743E-16
SPICE output file for “C1 ; -25deg”
Rh1
Rh2
B2#8
B2#10
B2#10
B2#11
C1
C2
B2
VDD
VSS
VSS
0.3169
0.5538
cmodel
cmodel
$M1
1.00272E-17
2.17743E-16
Extracted View Output
The Extracted View output can be generated for Assura, Pegasus, and Calibre flows.
For Assura-Quantus flow, extracted view is generated from Assura installation using
rcxToDfII.
For Pegasus-Quantus flow, extracted view is generated using qrcToDfII from IC6.1.X or
5.1.41.
For QCI flow, extracted view is generated using qrcToDfII from IC6.1.X or 5.1.41.
Note: Quantus does not support generation of the DFII extracted view output for the flat
Calibre LVS flow. In the flat LVS flow, back annotation of instance names to the schematic
names is not complete. The DFII extracted view output is only supported in the hierarchical
mode (calibre -hier).
The maximum file size of the extracted_view output for 32-bit processors is 2 GBytes, and for 64-bit
processors is 2,000 GBytes.
The physical layout always has scalar pins (for example a<0>, a<1>, a<2>, a<3>.. pins).
Therefore, the connection to the view of an instantiated device must also have scalar pins,
and not vector pins (like bus terminals a<0:3>). There is no mechanism in the qrcToDfII
utility to bundle nets in the correct order and make the connections to the bus pin.
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Redirecting the Extracted View Output
To have Quantus redirect the output extracted_view from the current library directory to a different
location, for the purposes of disk management for instance, you can create a link to the desired
location in the library directory:
For example, if the AND directory has the layout, schematic, and the av_extracted views, execute
the following command from within the AND directory:
ln /usr1/nsm/av_extracted av_extracted
In this case Quantus will write the extracted_view output to AND/av_extracted and it will actually
reside at /usr1/nsm/av_extracted.
Creating CCLFile in Extracted View
When the Quantus software is run, a text file named CCLFile is automatically created in the
extracted_view directory. The file contains the CCL commands used for the Quantus Run. This file
is not created for any other output format.
Note: You cannot change the CCLFile name or location, since this file is used in downstream flows
(e.g., SND GUI).
Note: The Virtuoso Library Manager will not copy the CCLFile, but other functions such as Rename
and Delete will work properly.
Multiple Process Corners in the Extracted View
The results of two separate Quantus extractions on two different process corners could yield a
single capacitor with a common name, but different values:
C1 n1 n2 cmodel value1 (from first Quantus run, first rule set)
C1 n1 n2 cmodel value2 (from second Quantus run, second rule set)
While a single Quantus run using multiple process corners, would yield a single capacitor with an
expression parameter:
C1 n1 n2 cmodel `c1*value1+c2*value2'
The parasitic capacitance and resistance values for multiple process corners will take the form of a
numerical expression in both the Spice and Extracted View output. The numerical expression is
enclosed in single quotes, with no blank characters inside. The value is in the form:
`P1*val_1+P2*val_2+...'
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Where P1 and P2 are the process corner property names. The default values are c1, c2, c3... for
parasitic capacitors (corresponding to corner1, corner2, corner3), and r1, r2, r3... for parasitic
resistors.
The property name for each process corner is user-definable, and is stored in a file named
"process_corner_names" located in each rule set or technology directory. An example of the
process_corner_names file follows:
C C=cap1
R R=res1 L=len1 W=width1 A=area1
Where each line starts with the SPICE character for the parasitic element (C for caps, R for
resistors). The same character is used for the parasitic devices primary value (C = capacitance for
instance). Additional parameters of L, W, and A describe the Length, Width, and Area parameters of
the parasitic resistor.
You can create a process_corner_names file in one rule set, and use the default values for the other
rule sets if that is desired.
In the extracted_view output, the rcxParameters ?capPropName and ?resPropName will be ignored,
and the property name will be defined for each process corner as defined by the
process_corner_names file, or by the default value for each process corner.
Simulating the Multi-Corner Extracted View
To simulate the extracted view output with multiple process corner expression values requires
changes to the CDF of the parasitic devices being used in the extracted view. The CDF
customization is usually performed by the CAD group.
The steps required to do this are:
1. In CIW, Click Tools->CDF->Edit . The CDF Edit window pops up.
2. Browse to the library and cell for the pcapacitor (for example).
3. In the Component Parameters section, in the field for "c", type in
C1*iPar("slow")+C2*iPar("fast")
Here "slow" and "fast" correspond to the corners defined in the "process_corner_names" file. If you
had another corner "nom" you would add "+C3*iPar("nom")" to the above.
You will run Assura as usual to create an extracted view, selecting multiple process corners. On the
Assura extracted view, you will see parasitic capacitors with the value
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"C1*iPar("slow")+C2*iPar("fast")"
Now you can netlist the extracted view in ADE. The netlist will contain pcapacitors of the form
C10 (p90 _net0) capacitor c=C1*(4.16e-15)+C2*(5.0e-15)
By setting C1, C2 in the simulation environment, it will be possible to simulate the netlist.
Smart View Output
Smart View, the next-generation of Quantus™ Extracted View output, has a comprehensive
architecture that:
leverages massively parallel technology to significantly improve performance
is based on Cadence® internal DB format, and is tightly integrated with Virtuoso® ADE
addresses memory, netlist size, and ADE netlisting experience and runtimes
Some of the advantages of Smart View when compared to Extracted View are:
Better usability, improved functionality, and the same integration with Virtuoso® and
Virtuoso® ADE platforms.
Netlisting is based on the DSPF file format as opposed to the Spectre® (SPICE) format. This
allows direct support for Fast SPICE tools like Spectre XPS.
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Smart View requires the same input files as Extracted View. However, there are some
additional setup items required when moving from Extracted View to Smart View. These are
listed below.
1. For Extracted View, it is not required for the LVS to DFII layer mapping to be present
inside either the extview.trp file or the icellmap.yaml for viewing parasitic R,C. In this
case, the layer mapping is absent so the layout interconnect shapes are not seen and it
reduces the size of the extracted view. However, parasitic R,C analogLib components
are still visible in Extracted View. On the other hand, for Smart View it is required that
LVS to DFII layer mapping is present inside the extview.trp (version#2), or the
icellmap.yaml file or the extview.rul file (when extview.trp version#1 is used) for
viewing the parasitic R,C associated with the nets through Smart-Parasitics -> Display
Parasitics menu in Virtuoso Layout Suite XL/GXL. This is because Smart View is
based on OA architecture, which requires both layer and location information to be
present for the formation of oaNodes in the parasitic network. If either the LVS to DFII
mapping is missing, Smart View is not able to form oaNodes and, therefore, does not
display parasitic R,C information inside the view.
2. The Extracted View parasitic R, C can be viewed in Layout L, XL, GXL or EXL.
However, the Smart Parasitics window for parasitic display, layout overlay is only
available through Layout XL, Layout GXL or Layout EXL. If Smart View is opened in
Layout L, Smart Parasitics plugin is not available.
Specifying Device Recognition Layer (DRL) Names in extview.trp and
icellmap.yaml
Device Recognition Layer (DRL) name specification is supported in the extview.trp(version#2) and
icellmap.yaml files. It is supported in the single process corner and multiple process corner
modes. The DRL name is placed after the model/device line as follows:
extview.trp:
model: g45rm3
device: g45rm3
drl: _resm3
dfiiCell: lib=gpdk45 cell=resm3 view=ivpcell
pinMap: PLUS=PLUS MINUS=MINUS
pmExclude m=4
This means that model: g45rm3, with library gpdk45, lies on recognition layer with drl name : _resm3
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icellmap.yaml
model: crtmom
drl: _mom4
cellview: { lib: gpdk45, cell: crtmom, view: ivpcell }
pin: { PLUS: PLUS, MINUS: MINUS, BULK: BULK }
pmExclude: { model= "vwxyz", m: "1", sp: s }
Applicable Scenarios:
For duplicate model, device, and drl combination, only the first definition is considered, and
the rest are ignored.
model: g45rm3
device: g45rm3
drl: _resm3
dfiiCell: lib=gpdk45 cell=resm3 view=ivpcell
pinMap: PLUS=PLUS MINUS=MINUS
pmExclude m=4
model: g45rm3
device: g45rm3
drl: _resm3
dfiiCell: lib=gpdk45 cell=resm3 view=ivpcell
pinMap: PLUS=PLUS MINUS=MINUS
pmExclude m=3
Note: In above example, since there are two models on the same device for same drl, the
second definition will be ignored.
If an incorrect drl name is specified, it will not be read.
If the drl name is not specified immediately after the model/device names, it will be ignored. In
the example below, the drl line will be ignored becasue it is not immediately after
model/device name.
model: g45rm3
device: g45rm3
dfiiCell: lib=gpdk45 cell=resm3 view=ivpcell
pinMap:
PLUS=PLUS MINUS=MINUS
drl: _resm4
For one model name, if drl is mentioned, the transfer properties are picked up on basis of DRL
name and not the library name.
Quantus Smart View output format is activated by the following CCL option combination:
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input_db -type [calibre|pegasus|assura]
output_db -type smart_view
The Smart View output can be enabled through the GUI by selecting the Smart View option from the
Output drop-down list in the Setup tab of Quantus Parasitic Extraction Run Form.
This format is available for the Assura, Calibre, and Pegasus LVS inputs. To generate the Smart
View output format, the following CCL is required:
output_setup –net_name_space schematic
The following Extracted View CCL options are not supported in the Smart View flow:
output_setup \
-net_name_space layout
output_db \
-cap_component <string>
-cap_property_name <string>
-res_property_name <string>
-include_parasitic_cap_model true
-include_parasitic_res_model true
-enable_cellview_check
The Smart View flow does not support the following flows, and the support will be provided
in future depending upon ADE readiness:
Multi Corner Extraction (process_technology -technology_directory <techpath1 >
<techpath2> ...)
HRCX Flow (hierarchical_extract)
Inductance Extraction (extract -type rlc|rlck)
Substrate Extraction (substrate_extract)
Smart View for EMIR Flow
Smart View provides key post-layout simulation verification functionality, such as in-context crossprobing, back annotation, and parasitic reporting, in the Virtuoso environment. For efficiency, Smart
View has no layout shapes. In-context cross-probing and visualization is enabled via layout overlay
on the Smart View. To perform visualization, access the Smart-Parasitics menu that is displayed by
default (from the Smart View window) when you are working with Virtuoso ADE XL or GXL., as
shown below:
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To use the Smart View feature, you must have the Virtuoso IC 6.1.8 and the ICADVM18.1 release
versions and above. For more information on post-layout visualization, refer to the Virtuoso
documentation.
OA Output
output_db -type oa
-output_name <name>
Note: In order for Quantus to output extraction results to an OA database, the design input must be
from an OA database. In addition, Quantus can only output to a flat OA database. If the input OA
database is hierarchical, Quantus will output a flattened SPEF netlist instead.
OA output of Multiple Process Corners
In the case of multiple process corners, each process corner specified for extraction using the
process_technology -technology_corner command will be created as a separate oaOpPoint in the
OA database. This allows the single OA database to store multiple parasitic networks.
Output Reports
output_db -type coupling_cap_reports
output_db -type promoted_feedthru
output_db -type unconnected_pins
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1
Global nets are excluded from resistance extraction in Quantus by default (see global_nets).
2
In prior releases, QXC offered a variety of commands to enable or disable manufacturing
effects in the extraction run. These commands are no longer available.
3
Quantus will not correctly extract a designed inductor or interconnect that is composed of
circular shapes.
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4
Quantus Graphical User Interface
Accessing the Quantus GUI
Quantus UI and Assura LVS Input
Quantus UI and Pegasus/PVS Input
Quantus UI and Calibre LVS Input
Quantus Resistance Analysis
The Quantus Run Form
Setup Tab
Technology Selector and Rule Sets
Output Format
Spice Output
Spice Options
Extracted View Output
LVS Extracted View Output
Smart View Output
Cell-level DSPF Output
DSPF Netlist Output
Cell-level SPEF Output
DSPF and SPEF Command Options
Transistor-level DSPF Output
Transistor-level SPEF Output
XDSPF and XSPEF Command Options
Extraction Tab
Extraction Type
Name Space
Resistance Commands
Non-Manhattan Resistance
Layer Setup Customization
Capacitance Commands
Inductance Commands
NET Selection Mode
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How to Input Net Names
Quantus Field Solver Capacitance Extraction
Hierarchical Extraction
Filtering Tab
Netlisting Tab
Run Details Tab
Quantus Run Mode
Substrate Tab
The Command File
Standalone Quantus UI
Launching the Standalone Quantus UI
Running Standalone Quantus UI in Replay Mode
Standalone Quantus UI Restrictions
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The user interface described in this chapter can be used to define and launch a Quantus extraction run when the input data is
from a supported LVS application (Assura LVS, Calibre, or Pegasus). It does not support cell-level extraction with DEF or OA
input.
Accessing the Quantus GUI
This section explains the steps you should follow to run Quantus from the Quantus menu that appears in Cadence Design
Framework II GUI environment. It assumes that you have already correctly installed the software releases needed to support this
flow.
The Quantus UI has dependencies on the IC release to load the Quantus menu into Virtuoso, the Assura release when Assura
input is used, and the Pegasus release when Pegasus input is used. For more information on the various release versions
required to support the Quantus UI, refer to the What's New document for the specific release you are using. For specific
instructions on configuring the Quantus UI, refer to the Configuring the Quantus UI section of the “ Preface " chapter.
Note: Starting with PVE 12.1 release, AIX Quantus GUI can only be run using Virtuoso 64-bit.
To access the Quantus menu, do the following:
1. Launch the Cadence DFII executable (such as icfb, layoutPlus or layout for CDBA and virtuoso for OA)
Launch the DFII executable from a directory that contains a cds.lib or lib.defs file which references the libraries used in
the design, and an assura_tech.lib file which references the Assura technology directory that contains the Assura LVS
rules and Quantus technology files. Typically, the DFII executable will be launched from the directory previously used as
the LVS run directory so that the Quantus run automatically uses the same cds.lib and assura_tech.lib files as Assura
LVS.
Note: You can also launch the DFII executable if the directory contains the Cadence setup search file (setup.loc) that
defines the search mechanism for the cds.lib file. Starting with EXT 10.1.1, the Quantus UI has been enhanced to read
the setup.loc file, if present.
2. ​ ​Select File->Open... from the DFII CIW (Command Interpreter Window)
3. Select the library, and top cell name of the design, then select layout view, then click OK to open the layout view in the
Cadence Virtuoso® Layout Editor.
4. Once the layout view opens in the Virtuoso layout editor, the Quantus menu is loaded into the Virtuoso menu banner as
shown below.
Virtuoso Menu
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The Quantus menu has the following commands:
Setup Quantus - Allows you to define template files that contain default selections and valid options available when
running Quantus (see the Setting Up the Quantus User-Interface chapter).
Run Assura - Quantus - Invokes the Quantus (Assura) Parasitic Extraction Run Form for use with Assura LVS input data.
See Quantus UI and Assura LVS Input for more information on running the Quantus UI with Assura LVS input.
Note: This is the same as the Assura > Run Quantus command.
Run Pegasus - Quantus - Invokes the Quantus (Pegasus) Parasitic Extraction Run Form for use with Pegasus input data.
See Quantus UI and Pegasus Input for more information on running the Quantus UI with Pegasus input.
Quantus supports both PVS and Pegasus LVS. The Quantus UI displays ‘PVS’ if you have PVS installation in the
PATH, and displays ‘Pegasus’ if you have Pegasus installation in the PATH.
Run Calibre - Quantus - Invokes the Quantus (Calibre) Parasitic Extraction Run Form for use with Calibre input data. See
Quantus UI and Calibre LVS Input for more information on running the Quantus UI with Calibre input.
Run Quantus for VoltusFi - Invokes the extraction UI used for generating DSPF for VoltusFi EMIR flow. For details of the
flow, see "xDSPF Generation using Quantus" chapter in the Voltus-Fi Custom Power Integrity Solution XL User Guide.
Quantus SND Analysis - Invokes the Surface Noise Distribution Analysis form. See the Quantus Substrate AC
Analysis chapter for more information.
Note: This command is the same as the Quantus SND Analysis command on the Assura menu.
Quantus Reduction - Invokes the Standalone Reduction form. This form is used for mathematical reduction of the input
parasitic netlist files. See Standalone Reduction chapter for more information on running the flow.
Quantus R-analysis - Invokes the Quantus p2p R Analysis and Quantus Term to Term R Analysis forms. See Point-to-Point
Resistance Analysis and Term-to-Term Resistance Analysis for more information.
Quantus UI and Assura LVS Input
Assura LVS must be run on a design before Quantus extraction is run on the LVS database. At a minimum, an LVS database
with devices and connectivity extracted from the layout data must exist prior to the Quantus run. A complete LVS run extracts
devices and connectivity from the layout, then compares the schematic netlist to the extracted layout netlist and reports any
mismatches or errors. If the layout does not match the original schematic design, the mismatches should be resolved, then
Quantus should be run to extract parasitics from the clean LVS layout data.
In earlier Quantus releases, it was mandatory to open an Assura LVS run in the GUI to enable the Assura - Quantus GUI menu
option. To do this, an Assura_UI license was mandatory. However, now, you can run the Assura GUI flow without opening an
Assura LVS run (using the Open Run option from the Assura menu) in the GUI. Now, Quantus checks for the existence of the
DFM_core_tecnhology license instead of the Assura_UI license.
To run Quantus with Assura LVS input, perform any of the following:
If you have an Assura_UI license, select Open Run...from the Assura menu.
Note: If you do not have an Assura_UI license, this option is disabled.
If you do not have an Assura_UI license, select Assura -> Run Quantus. A form to select an LVS run is displayed in which
you need to specify the run directory and select the run name. Then, the Assura LVS run is opened implicitly.
The Quantus (Assura) Parasitic Extraction Run Form will be opened at this time, and can be used to specify the details of the
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extraction run. Refer to The Quantus Run Form for a complete description of the form and its many options.
Quantus UI and Pegasus/PVS Input
Quantus supports both PVS and Pegasus LVS. The Quantus UI displays ‘PVS’ if you have PVS installation in the PATH,
and displays ‘Pegasus’ if you have Pegasus installation in the PATH.
When running Quantus with Pegasus input data, you would execute the Run Pegasus- Quantus command from the Quantus
menu. This will open the Quantus Pegasus Interface form to allow you to specify the name of the Pegasus run to load. this form
is shown below.
If a Pegasus LVS run is already opened through the use of the Pegasus GUI, then the Quantus Pegasus Interface form is
populated with the information for the currently opened Pegasus run. Refer to the Pegasus Users Guide for more information on
running Pegasus.
If no Pegasus LVS run is opened, the Quantus Pegasus Interface form displays the last known state for the Design Cell Name
and Pegasus/Quantus Data Directory.
The first time you invoke Quantus Pegasus Interface form, the Quantus Tech Lib and Technology fields are set to default values.
Subsequent invocation displays the last known state.
Pegasus Data Input Form
The fields on the Quantus Pegasus Interface form are as follows:
Design Cell Name
Specifies the cell containing the top-level of the design.
Related Commands Quantus: input_db -type pegasus -run_name
Pegasus Query Data Directory
Specifies the output directory of the Pegasus run. The output of Pegasus is required as input for Quantus. On clicking the file
browser button (...), the Pegasus Quantus-DB form appears. This form allows you to select the directory containing the data
created by Pegasus.
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When you run Quantus after a Pegasus LVS run, Quantus automatically picks up the data directory information from the latest
Pegasus LVS run. However, if Pegasus LVS has not been run previously to create Quantus data in a given IC session, you must
enter the path to the Pegasus data directory in the Pegasus Query Data Directory field. In either case, the rest of the pre-form is
populated automatically with information from the specified Pegasus LVS run.
This field is related to the input_db -type pegasus -directory_name command.
Related Commands Quantus: input_db -type pegasus -directory_name
Note: If the path to the Pegasus query data directory is incorrect, the following pop-up window opens:
Quantus Tech Lib
Specifies the technology library file to load. This field defaults to ./assura_tech.lib when the form is first opened. On clicking
the Change button, the Quantus Technology Lib Select form appears. Click the file browser button (...) to access the Quantus
File Selector form. This form allows you to select another technology library file if your Quantus technology data is defined in
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another file such as the pvtech.lib file.
In the Calibre-Quantus flow, the standalone Quantus UI automatically loads the pvtech.lib technology library file if the
assura_tech.lib (default) is not available.
If both assura_tech.lib and pvtech.lib technology library files are not available, the Quantus Tech Lib field is left blank.
Quantus automatically loads the pvtech.lib technology library file in the Pegasus-Quantus flow. However, if Pegasus does not
use a technology setup and instead uses a rule file to run LVS, this field reverts to its default value.
Related Command Quantus: process_technology -technology_library_file
Technology
Defines the technology name to use during the Quantus extraction run. When you run Quantus after a Pegasus LVS run, this
field is automatically populated with the technology name from the Pegasus LVS run.
Related Command Quantus: process_technology -technology_name
When an existing extraction run is already open, Quantus will first notify you that the open run will be closed and a new run
started with the Pegasus input data. In this case you will see the following prompt:
Running Pegasus - Quantus with an Assura LVS Run Open
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Quantus UI and Calibre LVS Input
When running Quantus with Calibre input data, you would execute the Run Calibre - Quantus command from the Quantus menu.
This will open the Quantus Calibre Interface form to allow you to specify the information required to support Calibre LVS input as
shown below.
Calibre Data Input Form
Refer to Quantus UI and Calibre Input in Running Quantus with Pegasus and Calibre Inputs for more information on the
requirements of the various fields of the form.
When an existing extraction run is already open, Quantus will first notify you that the open run will be closed and a new run
started with the Calibre input data. In this case you will see the following prompt:
Running Calibre- Quantus with an Assura LVS Run Open
Quantus Resistance Analysis
Quantus UI supports point-to-point and term-to-term resistance calculation in the Extracted View and Smart View output formats.
The two analysis types are accessed from the Quantus R-analysis submenu in the Quantus menu.
You can enable this feature only if the Extracted View/Smart View is open in Virtuoso Layout Editor. Smart View must be
launched in the read-only mode in either the Layout XL or Layout GXL application level from the Launch menu in Virtuoso.
This feature requires an XL license and an Advanced Analysis (AA) GXL option.
Quantus R-analysis Submenu
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Quantus R-analysis Submenu
Note: The option is disabled if the Extracted View/Smart View is not open, or if the Extracted View/Smart View is multiplecorner/hierarchical/C-only.
Point-to-Point Resistance Analysis
Point-to-point effective resistance analysis lets you calculate the resistance between two nodes of the same net. To perform
point-to-point effective resistance probing:
1. Select the Quantus P2P R Analysis option from the Quantus R-analysis submenu in the Quantus menu. The Quantus p2p
R Analysis form opens.
Quantus p2p R Analysis Form
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Note: The option is disabled if the Extracted View/Smart View is not open, or if the Extracted View/Smart View is multiplecorner/hierarchical/C-only.
2. Click the Select button in the Point 1 section, and click on a shape from the view. The form will move to the background,
and Virtuoso view will come to the foreground. The Net, Node 1#, x, y, Layer, and Full Node Name of the first node shape
in the view will be identified and displayed in the Quantus p2p R Analysis form. If the selected object is not a net, Quantus
displays an error message.
Note: The Net field in the Quantus p2p R Analysis form displays all nets in the current cell view. You can either select a net
name from the drop-down list, or enter a net name in the Net field. When this form is opened for the first time, the Net field
will not show any nets in the drop-down list. This field will display the list of nets only after first node selection using the
Select button in the Point 1 or Point 2 section.
3. By default, when you select a net from the Net drop-down list, or select a node using the Select button, the node’s net (or
selected net) is highlighted with a blinking (“unbound device”) pattern, as shown below. To remove the highlighting,
uncheck the Highlight checkbox.
4. Click the Select button in the Point 2 section, and click on a shape from the cell view.
The Net, Node 2#, x, y, Layer, and Full Node Name of the second node shape in the Extracted View/Smart View will be
identified and displayed in the Quantus p2p R Analysis form.
If the two nodes are in different nets, a warning message like the following will be displayed in the Net field:
Nodes '237:AVDD' AND '43:outm' are in different nets!
The layers for Point 1 and Point 2 can be the same. You must select the points and layers on the form from the layout. That
is, manual entry of points is not allowed.
5. When selecting a node in Smart View, you may need to choose a node from the list of layers, as shown below:
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This window appears if the cell view may have nodes from multiple metal layers at the same point.
6. Click the Calculate button to extract the whole net information internally from the Extracted View and to calculate
resistance.
The calculated value is displayed in the R Value (in Ohms) field. You can click the Reset button to reset all the parameters
in the form.
7. Click the Close button.
Term-to-Term Resistance Analysis
You can calculate resistance between device terminals associated with a selected net in the Extracted View and Smart View
output formats. This feature provides an easy way to pick nodes that are directly connected to device terminals.
To perform term-to-term effective resistance probing:
1. Select Term to Term option from the Quantus R-analysis submenu. The Quantus Term To Term R Analysis form opens.
Quantus Term To Term R Analysis Form
Note: When the form opens for the first time, all fields are grayed out.
2. Click Choose to select the Current Cell View. You can choose a different view if there are multiple extracted or smart
views. When multiple views are available, either in the extracted view or smart view or both, and you click Choose.
The Choose Cell View pop-up window opens. Select the view and click OK.
3. In the Term To Term R Analysis form, select the Net from the list of nets in the drop-down list. All the device terminals
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belonging to the selected net are populated in the Terminal 1: and Terminal 2: drop-down lists. By default, the name of the
first terminal in the drop-down list is displayed.
Note: The terminals 1 and 2 for the selected net must be different. If the two terminals are the same, the resistance value
displayed is 0.
4. By default, when you select a net from the Net drop-down list, the selected net is highlighted with a blinking (“unbound
device”) pattern. To remove the highlighting, uncheck the Highlight checkbox.
5. Click the Calculate button to extract the resistance between the two terminals for the selected net for both Extracted View
and smart view. The calculated value is displayed in the R Value (in Ohms) field.
6. Click the Close button.
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The Quantus Run Form
Quantus Parasitic Extraction Run Form
Note: The Quantus Run form provides user controls for all Quantus options, but only those options for which you have a current
license are enabled during runtime.
The features of the Quantus Parasitic Extraction Run Form are:
Button Bar - provides commands to execute or cancel the execution of the extraction run, as well as loading and saving
command settings from extraction runs.
Setup Tab - used to define the technology directory containing the Quantus process file, as well as the desired output of the
Quantus run. Various options specific to each output format are displayed as a result of output selection.
Extraction Tab - defines the specific objectives of the extraction run, having to do with resistance, capacitance, and
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inductance, as well as specifying which nets in the design to perform extraction on, and whether the extraction should be
hierarchical or flat.
Filtering Tab - specify various options to filter unnecessary parasitic devices from the extraction process. These options
usually result in improved extraction speed and smaller netlists for improved simulation.
Netlisting Tab - defines the options for specific netlist outputs, including models to use, and character delimiters to apply to
the netlist output.
Run Details Tab - defines the various details of the Quantus run, including temp directories, and log file, and enables multiprocessing and load sharing options.
Substrate Tab - provides the User Interface for the new Quantus AoT option to Quantus. This option requires the addition of
the Virtuoso_QTS_Extraction_XL license and the Advanced Analysis (AA) GXL option. You will use Quantus AoT to
perform parasitic extraction on RF or AoT designs, or RF blocks of a larger design.
Form Bottom - provides access to quick help display and page up and down buttons for navigating the various tabs of the
Quantus Parasitic Extraction Run Form.
Button Bar
Quantus Run Form Button Bar Menu
OK
Closes the Quantus Run form then starts the Quantus extraction run using the current settings, which are captured in the
Quantus command file.
Note: Starting with the EXT 9.1 release Quantus uses a CCL file instead of the legacy RCX RSF command language when
started from the Quantus UI (see The Command File).
Cancel
Closes the Quantus Run form and discards any changes made to the settings during the current session.
Apply
Runs Quantus using the current settings. The Run form remains opened.
Defaults
Loads and uses the template file (.rcx_setup.tpl) for setting the default values. The behavior of the Defaults button will be in the
following order of priority:
Read the template file from the directory specified using the environment variable QRC_UIFORMS_TEMPLATE_DIR.
Read the default template file (.rcx_setup.tpl).
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Restore the default Quantus settings.
Load State
Click this button to display the Load State dialog that lists the names of saved states--that is, saved settings--from previous
Quantus sessions. During the first Quantus session, this dialog box is empty. During subsequent sessions, the list includes Last,
which is the name of the saved settings used in the last Quantus run. It also lists any previous states you have saved. You can
use the ( ) toggle button to sort the names of the saved states in an alphabetical order. Choose a saved-state name from the list,
then click OK to load the settings saved under the chosen saved-state name into the Quantus Run form.
Alternatively, you can load the *.state files from a user-specified directory instead of loading all the previously saved states. To
enable this feature, you must set the following environment variable before launching Virtuoso:
setenv QUANTUS_UIFORMS_STATE_DIR dir1:dir2:dir3
When this variable is specified, the Load State dialog box will display all states located in the directories specified with the
QUANTUS_UIFORMS_STATE_DIR environment variable.
The file manager points to the default directory if the environment variable ASSURA_UIFORMS_STATE_DIR or
QUANTUS_UIFORMS_STATE_DIR is not set, or to the user-specified directory if the variable is set.
Note: The multiple directory locations for saving and loading state files that can be set include, all the directories specified using
the QUANTUS_UIFORMS_STATE_DIR variable, the current directory, and your home directory.
Save State
Saves the current Run and Option form settings. Click this button to display the Save State dialog with a list of saved states
(including LastState). Choose the name of a saved-state from the list or insert a new name in the name field. You can use the (
/ ) toggle buttons to sort the names of the saved states in an alphabetical order. Click OK to save the current Quantus settings
under the specified saved-state name. If you choose the name of an existing saved state from the dialog box, then click OK, the
settings from the current Quantus session replace the settings previously saved under the chosen saved-state name.
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By default, the *.state and .QRC.run files are saved into the directory where Virtuoso is started. Alternatively, you can save the
*.state files into a user-specified directory instead of the default directory. To enable this feature, you must set the following
environment variable before launching Virtuoso:
setenv QUANTUS_UIFORMS_STATE_DIR dir1:dir2:dir3
When you specify a state name and click OK in the Save State dialog box, the Choose State File dialog box appears that allows
you to save the state in one of the listed directories, as shown below:
In the Assura-LVS flow, you can save the *.state files into a user-specified directory using both or one of the following variables:
setenv ASSURA_UIFORMS_STATE_DIR <directory>
setenv QUANTUS_UIFORMS_STATE_DIR dir1:dir2:dir3
View Command File
Opens the GUI-produced command file for the current Quantus run in your default text editor. Starting with the EXT 9.1 release
Quantus Parasitic Extraction Run Form produces a CCL file instead of the command file in RCX compatible RSF format using
rcxParameters. See The Command File for a sample Quantus CCL file.
Help
Invokes Cadence Help system to review the product manuals.
You can also manually launch Cadence Help from a terminal window to view the Quantus release documents:
< inst_dir >/bin/cdnshelp
Help Text Window
At the bottom of the Quantus Run Form is context sensitive help for each of the five tabs. As you navigate through the different
tabs, the text displayed in the window will change to reflect the Quantus settings defined in that tab.
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There is a caret (^) and an `X' above the help text that controls the display of the help text.
Use the `^' to hide the help text window on the Quantus Run form. This causes the `^' to change to a `v'. Select the `v' to display
the help text window again. This causes the `v' to become a `^' once again.
The `X' allows the help text to be displayed in a separate window to view more text at one time. Close the separate help text
window at any time.
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Setup Tab
Quantus Run Form Setup Tab
The Setup tab has two primary panels: the Technology Selector, and the Output Format. The Technology Selector is consistent
across all outputs. The content of the Output Format panel varies significantly based on the currently selected output format.
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Technology Selector and Rule Sets
Technology and Rule Set Selectors
Technology
This cyclic control specifies the technology name that will be used for the current Quantus run. The technology name is passed
from the opened Assura LVS run into Quantus, and is displayed in this field when the Quantus Run form opens. The
assura_tech.lib file maps each technology name to a directory that contains the technology files for the Quantus run (see the
Assura Developer Guide for a listing of the Assura LVS technology files). Additional technology names (if any) that are passed
from LVS to Quantus can be selected from the cyclic list.
Related Command Quantus: process_technology -technology_name
RuleSet
RuleSet Options
This cyclic control contains the name of any rule sets defined for the technology name specified in the technology field. The
Quantus rule set name selected for the currently open Assura LVS run is passed from Assura LVS into Quantus, and is selected
when the Quantus Run form opens. If no rule set was passed, Quantus searches the techRuleSets file for the "default" rule set. If
the default rule set is found in the techRuleSets file default is displayed for the Rule Set. However, if the techRuleSets file does
not contain the default rule set, then the Rule Set cyclic control displays NONE. Additional rule sets (if any) that are defined for
the currently selected technology can be selected from the cyclic list.
Note: The RuleSet field displays only those rulesets that have the RcxSetupDir keyword.
See "Setting Up Technology Data" in the Assura Physical Verification Developer Guide for more information on Technology
Rule Sets.
In the Pegasus-Quantus flow, Quantus automatically obtains the name of the rule set if that information is specified during the
Pegasus LVS run. In addition, if a list of valid Quantus Rule Sets is specified during the Pegasus LVS run, the available Rule
Sets displayed in the Quantus UI are limited accordingly.
In earlier release, if corner.defs was present in technology directory but there was no TechRuleSet file, GUI did not pick up any
corner. Starting with PVE 12.1 release, Quantus GUI can pick up the corners from corner.defs file which is present in technology
directory even if TechRuleSets file is not present. You can also use corner.defs if there any specific corner is undefined. In the
Quantus UI mode, if both the TechRuleSets and corner.defs files are present in the technology directory, the TechRuleSets file
takes precedence.
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Note: The rule set names in Quantus should not contain any spaces.
See "Handling Technology Data in Pegasus" in the Physical Verification User Guide for more information on Technology Rule
Sets.
Related Command Quantus: process_technology -technology_corner
p2lvsSet
This cyclic control contains the name of any p2lvs sets (an lvsfile/p2lvsfile pair) defined for the technology name specified
in the technology field.
An example of the use of p2lvsSet could be performing a C-only extraction, with the addition of gate resistance. To accomplish
this, you would create a p2lvs_set (called polyOnly for instance) below the primary technology directory, and create a duplicate
of the p2lvsfile in which all the metal layers have sheet_res=0 to specify no resistance for those layers. The poly layer (or gate
layer) would have a specified sheet_res value so that resistance would be extracted for the gate layer. During Quantus
extraction, specify p2lvsSet "polyOnly" and perform extraction for both R & C. In this case, only the poly layer (or gate layer)
would have resistance extracted, while all other resistances would be zero.
Related Command Quantus: process_technology -technology_set_up
Setup Directory
This text entry field is initially inactive, and displays the directory path associated with the currently selected Quantus technology
name or rule set. The displayed directory path must contain the Quantus technology files for the current Quantus run (see the
Assura Developer Guide for instructions on creating the Quantus technology files). If a selected rule set contains a Quantus
setup directory definition, the setup directory path takes precedence over the technology name directory path. You can click the
check box to override the displayed path name, then type a different directory path or use the browser button (...) to select the
name of a directory path.
When you click the browser button (...), the following form opens:
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Select the file and click OK.
Starting with the 11.1 release, the Setup Dir field has been enhanced to support the process_technology technology_directory CCL command.
Related Command Quantus: process_technology -technology_directory
Template
This drop-down list specifies all the *.tpl files that are applicable for the current Technology and Rule Set values. You can select
a .tpl file and click Load to load the selected file to the Run form.
Template
The .tpl file that is automatically applied to this field is based on the availability of the following files in the given sequence:
.rcx_setup.tpl
default_setup.tpl
Include Command File
The Include Command File field allows you to specify an additional CCL file to be included into the top-level CCL being created
by the Quantus User Interface.
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Include Command File
Some features of Quantus are not supported through the Quantus UI (for example the process_technology -erosion_file
command). In order to use these features you can use the Include Command File file and command.
Note: If you specify the process_technology, input_db, and output_db commands in the include file, you must also specify the
following arguments with the commands, otherwise, Quantus will display an error:
Command Name
Required Arguments
process_technology
-technology_library_file
-technology_name
input_db
-type
output_db
-type
Note: You can also edit the CCL created by the Quantus Run form and then manually launch Quantus (see The Command File).
When the specified Technology Rule Set (process_technology -technology_name) specifies an include file, this file is
automatically loaded into the Include Command File field, and the radio button is enabled to include the file. You can disable the
radio button to prevent the specified file from being included in the Quantus run.
Note: When the Include Command File radio button is disabled, the file will not be included in the CCL file created by the GUI,
even though the filename is still displayed in the form.
If the specified Technology Rule Set does not contain an Include file, then you can specify one by enabling the Include
Command File radio button, and manually defining the path to the file to be included.
The included CCL commands are added to the beginning of the CCL output by the user interface.
Since the included commands are inserted at the beginning of the top-level CCL, any Quantus commands you modify in the user
interface will override the value from the included CCL.
When the include command file is placed in the technology directory (specified by the process_technology
technology_directory CCL command), the file is automatically loaded by Quantus. The include command file is referenced by
the keyword RcxInclude in the techRuleSets file. Following is a snippet of the techRuleSets file:
ruleSet( "typical"
(RcxTemplateFile "./rcx_setup.tpl" )
(RcxInclude "./include.ccl" )
)
If a .tpl file exists in the root technology directory for multiple corners, the Quantus UI loads the .tpl file by default. If .tpl
does not exist in the root technology directory, Quantus looks into the corner directory to find .tpl and loads it accordingly.
If the .tpl file is same in each corner, then changing the corner names in the Quantus run form will not change the previous
run form settings. However, if there is a different .tpl file in each corner technology directory, then it will change the
previous run form as per the corner name selected in the Quantus UI.
The path to the techRuleSets file is < technology_path >/techRuleSets. Then, Quantus loads the < technology_path
>/include.ccl file (for the corner typical) before loading the CCL command file. This action is equivalent to specifying the
include command at the beginning of the CCL command file. For example:
#####
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# OPTION COMMAND FILE created by Cadence Extraction Quantus
######
include <technology_path>/include.ccl
Since the keyword RcxInclude is associated with a corner, the feature is only applicable to single corner mode.
No syntax or error checking is provided for the included CCL. You must be sure that any included commands are correct
and applicable to the design.
Note: In previous Quantus releases, this field was named RSF Include and enabled you to include an RSF file into the top-level
CCL file. Though the RSF Include functionality has been replaced in this release with CCL Include, it is still supported in
backward compatibility mode. This means that you can still specify the RSF include file in the Include Command File field. The
specified RSF include file is translated to a CCL include file, and the CCL include file is then included in the main CCL file
produced by the GUI. It is recommended that you use a CCL Include file instead of an RSF Include file because 100%
conversion correctness of the RSF Include file is not guaranteed.
Rule Command File Include
The Rule Command File Include field is the Include Command File definition from the techRuleSets file in the technology
directory. If the rule set has the RcxInclude key, then the Rule Command File Include field will take the specified file.
ruleSet( "rule1"
…
(RcxInclude "rule.include.ccl")
)
Tech Cmd File
Technology Command File
Techgen provides the ability to specify options previously defined on the command line from within a command file. These
runtime options can then be specified and modified as needed during Quantus extraction through the use of the Tech Cmd File.
Enable the Tech Cmd File radio button to specify a technology command file for use during extraction. You can then specify
either Default or User in the cyclic menu.
If you specify Default, Quantus will search the technology directory for a technology.cmd file. In this way a default technology
command file can be provided along with the qrcTechFile for use at extraction run time.
Note: If the technology.cmd file does not exist in the technology directory, the Default option is disabled.
If you specify User, then the text entry field can be used to enter a path and file name for the technology command file.
Quantus will exit with an error if Tech Cmd File is set to User and the specified technology command file can not be found in the
specified path.
See the -technology_command_file option of the process_technology command for a complete description of this command and
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the format of the technology command file, process_technology.
Related Command Quantus: process_technology -technology_command_file
Layer Setup File
Defines layer mapping between the ICT file and Assura LVS data (lvsfile). This file enables metal layer and contact layer
mapping, and supports changing some parameters such as layer resistance at Quantus runtime. The layer_setup file can be
used to manipulate basic metal and via properties during extraction and allows Quantus runtime flexibility for shorting layers.
This allows some level of what-if analysis to be done on the design without changing the technology file.
Related Command Quantus: process_technology - technology_layer_setup_file
< filename >
LPE Config File
Specifies the location of the lpe_confile control file that contains the definitions of the device parameters. This option overrides
the lpe_confile file located in the technology directory with the specified file. The filename may be specified in either the
absolute path name, or the relative path name per the UNIX file naming convention. It is not mandatory to name this control file
as “lpe_confile”, whereas the control file located in the technology directory must be named as “lpe_confile”.
Related Command Quantus: process_technology -technology_lpe_confile < filename >
Library Cell Mapping File
Specifies the foundry provided iCellmap file that contains simulation model to DFII cell view mappings and transfer property
information.
Related Command Quantus:
input_db -technology_library_cell_map_file < file_name >
Black Box Cell View
Specifies to replace the default macro cell view name with the user-specified view name. It replaces the macro/blackbox cell
view from layout to another view, such as “symbol”. By default, this field is empty. You can type the name of the view. The
specified black box cell view name must be meaningful in the Virtuoso environment. This field is supported by Pegasus and
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Calibre inputs but not by Assura.
Related Commands Quantus:
output_db -black_box_cell_view
<view_name>
Probe Text File
Adds to the existing probe or pin texts imported from LVS file. The probe text file format contains the following fields separated by
blank characters:
<probe_text> <x_coordinate_in_um> <y_coordinate_in_um> <lvs_layer_name>
The X/Y coordinates should be specified with respect to the top cell.
For example, if INVD1 is the top cell, then probe text file may contain the following:
AAA 0.025 0.5760 M1 <= x y in um and in INVD1 coordinates
BBB 0.055 0.5760 M1 INVD1
Related Commands Quantus: input_db - probe_text_file
Library Definition File
The library definitions file contains the names and paths to libraries used by the design. This field is supported by Calibre and
Assura inputs but not with Pegasus.
Related Command Quantus: input_db - library_definitions_file
Use Multiple Rule Sets
You can run Quantus on multiple process corners in a single extraction run, to evaluate a design with different manufacturing
tolerances for instance.
This feature can significantly reduce the time it takes to extract different process corners, since much of the extraction run is only
performed once and used repeatedly for each process corner. The layout data preparation and capacitance parameter
measurements are done only once, and this information is applied to multiple capacitance models to generate the cap values for
each process corner.
Multiple Rule Sets Selection Form
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Select the Use Multiple Rule Sets radio button to enable support for multiple process corners. This will enable the filebrowser(...) button which opens the Multiple Rule Set Selection form enabling you to specify the various rule sets to be used.
To select a rule set, highlight it on the right side of the form (Available Rule Sets), and click the <- Add button to add it to the left
side of the form (Selected Rule Sets). The available rule sets are defined by the selected technology. Rule sets may also be
removed from the selected list by highlighting the rule set on the left side of the form, and clicking the Remove -> button. In the
above figure, the Max and Min rule sets have been selected from the tech_018 technology directory.
The order that rule sets are selected on the GUI (or, the order specified in the ?techRuleSets command) is critical to the
extraction process. The Techgen script initialization options used by Quantus are determined by the first process corner specified
(see Quantus Techgen Reference Manual). In addition, since only a single RC network is extracted, the first process corner will
determine the output R/C topology for all process corners (through RC reduction for example).
Overwrite Multiple Rule Sets
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Overwrite Multiple Rule Sets
If you do not currently have technology directories established with multiple rule sets, but rather have individual technology
directories that you would like to use, you can use the Overwrite Rule Sets radio button as shown in above figure. This command
allows you to specify technology directories in addition to the LVS technology directory, or in place of it. Use the "..." (file
browser) button to select a technology directory to use, then click the Add to Selected Directories button. You can add multiple
technology directories for use as process corners. The order the technology directories are added is important, since the first
specified technology directory will be determine the extracted RC network. You can use the Remove from Selected Directories
button to remove directories from the run.
The ?rcxSetupDir command used when overriding the LVS technology directory, and any rule sets it may have defined.
The use of multiple process corners consumes one additional Quantus License for every two additional process corners
specified.
Restrictions in Quantus for Multiple Process Corner Extraction
Only "flat" Quantus runs are supported. Hierarchical extraction and LVS macrocells (?blackBoxCells) are not supported.
The Quantus extraction modes that are supported are limited to RC, C-Only, and R-Only. Inductance extraction is not supported.
Also, since multiple process corners rely on the capacitance models extracted by Techgen, the Field Solver is not supported.
Finally, decoupled_to_substrate extraction is not supported, only coupled and decoupled capacitance extraction are allowed.
When specifying multiple process corners, the first technology directory will be used to establish the Techgen initialization run
options used, and the behavior of the Quantus application. For example, if Techgen -cdl is specified in the first technology
directory, it will apply for all rule sets whether -cdl is specified or not in the other rule sets.
In addition, the RC network must not be changed in such a way as to modify the output netlist or extracted view, so many of the
reduction commands are not compatible with multiple process corners. ReduceRC, and Exclude Floating Nets are not
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supported.
The rule-based RC reduction commands (?minR, ?minC, ?mFactorR, ?mFactorW) are handled in such a way as to preserve the RC
topology for all corners. In the case of the filtering/reduction commands, only the first process corner is evaluated against the
command criteria. For example, if ?minR is specified at 1 ohm, and the value of a parasitic resistor is 0.9 ohm in Corner 1, and 1.1
ohm in Corner 2, the resistor will be filtered out of the netlist based on the results of Corner 1. The ?minC, ?mFactorR and ?
mFactorW commands are also determined from the results of the first process corner.
Output Format
Output Formats Menu
This section specifies the Quantus output format and content. The available output formats can be broken into the following
categories:
Spice format netlists include both Spice and Spectre netlists which can be used for simulation (see Spice Output).
Note: Quantus does not support Spectre netlist. This option is available in the UI for compatibility with prior versions of
Quantus.
Extracted Views includes a standard DFII extracted view, which has parasitic properties back annotated onto a layout
design (see Extracted View Output). The LVS Extracted View is a variation of the standard extracted view in which no
parasitics are extracted, but the LVS netlist is back annotated onto the layout for simulation without the added
parasitics. The Smart View format is the next generation of the Extracted View output with similar functionality, and much
reduced netlisting time. Smart View is a Cadence® internal DB format, and is tightly integrated with Virtuoso® ADE that
does the netlisting in the DSPF file format. For efficiency, Smart View has no layout shapes, and in-context probing and
visualization of shapes/parasitics is enabled via layout overlay on the Smart View using the Smart-Parasitics menu
accessed from the Virtuoso environment.
Note: When Run Pegasus- Quantus is selected from the Quantus menu, the only available outputs will be Spice, Extracted
View, Lvs Extracted View, Smart View, DSPF (cell level), SPEF (cell level), Power Grid Database, Transistor DSPF, and
Transistor SPEF.
Standard Parasitic Extraction netlists include Detailed Standard Parasitic Format (DSPF) and Standard Parasitic
Extraction Format (SPEF) which is a compressed equivalent of DSPF (see Cell-level DSPF Output). This also includes the
Transistor-level DSPF netlist. These netlists can be used for timing analysis (see Transistor-Level DSPF Output).
Note: New in the 11.1.1 release, Quantus has been enhanced to support Full Chip Selected Nets and Selected Nets
Proper extraction modes in the Cell-level DSPF and the Cell-level SPEF output flows. This support was earlier available in
batch mode only.
By default, Quantus keeps track of the size of the output netlist file and creates continuation files if the file size exceeds 2
gigabytes. Quantus adds an .include <next_file> statement as the last line of the file to be continued. The <next_file> is
generated has the specified output filename with a .0, .1, .2, etc. appended to the original filename.
Note: Quantus does not split Extracted View output.
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Spice Output​
Spice Netlist Output
Output netlist contains parasitic elements and designed devices for SPICE circuit-level simulation.
Starting with the EXT 10.1.1 HF1 release, you can generate a SPICE netlist without the parasitic elements by selecting the
NONE option from Extraction Type list located under the Extraction tab. Like the LVS extracted view, the generated netlist is also
flat. With the NONE option, the Quantus options NRD/NRS device parameters (available for all MOS/LDD devices and also for
devices specified using the Techgen -genericMos command), LPE parameters, and netlist post processing are enabled.
New in EXT 10.1.2, if the mosPinOrder argument is specified with the Techgen -genericMos command, Quantus (PegasusQuantus and QCI flows) outputs the pin order of 5-terminal/6-terminal MOS, LDD, and generic MOS devices as D,G,S, B to
follow the SPICE convention.
Related Command Quantus: output_db -type spice
Spice Options
When SPICE is selected as the output format on the Quantus Run form, the Name option is available.
The default filename for the SPICE output is the LVS runname.You can specify a different file name in the Name field or by
clicking "..." to invoke a file browser to choose an existing filename. The Quantus output will overwrite the contents of the
selected file.
Related Command Quantus: output_setup -file_name
Substrate Extract
The Substrate Extract command is only available when the output format is Spice or Extracted View.
The Substrate Extract command activates Quantus AoT, which extracts both interconnect parasitics and substrate parasitics.
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The Quantus AoT substrate commands are primarily located on the Substrate tab (see the Substrate Extraction chapter), but also
affects various features of the Extraction, Filtering and Netlisting tabs as will be noted in this documentation.
When you enable the Substrate Extract button, the following commands are set to these required values:
Substrate Profile is disabled as these are mutually exclusive commands.
Substrate tab is enabled on the Quantus Run form (see "Substrate Tab" ).
Substrate Nets option is available on the Extraction tab.
Exclude Self Capacitance is turned off so that self capacitance will be included in the output (see "Exclude Self
Capacitance" ).
Filter Size is set to 0.5 to insure the highest level of Inductance extraction (see Filter Size).
Reduce Parasitics is enabled.
Add Explicit Vias is enabled (see "Add Explicit Vias" ).
Capacitance Extraction Mode is limited to Coupled (see Cap Coupling Mode).
During substrate extraction two types of parasitic capacitor models will be generated by Quantus. The first is the standard
"cmodel" capacitor which is the usual parasitic capacitor extracted by Quantus. The name of the "cmodel" capacitor can be
controlled by the Techgen -M model_name command. The second capacitor is the "snacapacitor" which is only used to model
parasitic capacitance to the substrate; the name is hard-coded and cannot be changed.
Related Command Quantus: substrate_extract -extract_under_contacts [ true | false ]
Extract MOS Diffusion AP
This command is no longer recommended and should not be specified.
Extract MOS Diffusion Res
Check this box to extract parasitic resistors on MOSFET source and drain regions. These parasitic resistors are listed in the
SPICE netlist as NRS and NRD properties, which contain the number of squares of parasitic resistance for MOSFET source and
drain regions, respectively.
Enabling this command disables the Extract MOS Diffusion High command as they are mutually exclusive.
Related Command Quantus: mos_diffusion_parameter_extraction -res [ fast | moderate | accurate ]
Add LVS MOS Diffusion Res
Check this box to add the NRD/NRS values (calculated by Quantus) to the corresponding values passed on by Assura LVS to
Quantus.
Note: This option can be selected only when the Extract MOS Diffusion Res option is selected.
Related Command Quantus: mos_diffusion_parameter_extraction -add_lvs_extracted_res {true | false}
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You can also enable this option in the Setup tab of the Quantus Parasitic Extraction Setup Form before opening the
Quantus Parasitic Extraction Run Form.
Output DPF
Specifies to run Quantus twice with the -restart option. The first time, it runs with the selected extraction type to generate DSPF,
and the second time with the extraction type none to generate the .dpf file. The first run can be any of the supported extraction
modes, while the second run can only be DPF. The log file will have the '_dpf’ suffix for the second run.
Related Commands Quantus: extract -selection all -type none
Extract MOS Diffusion High
This command provides the NRD/NRS extraction using the 2D Laplace solver with the ability to specify the desired level of
accuracy. Zero is the default accuracy and is recommended in most cases; 3 offers the greatest accuracy, but results in very long
run times. Specifying "None" turns off the 2D Laplace solver.
If Extract Mos Diffusion Res is enabled this command is disabled.
Related Command Quantus: mos_diffusion_parameter_extraction -res [ fast | moderate | accurate ]
Auto Accuracy Downgrade
This command automatically downgrades the resistance field solver accuracy modes, specified with the
mos_diffusion_parameter_extraction -res option, to compute diffusion resistance. When this field is selected, Quantus
internally estimates the memory usage and downgrades accuracy from “accurate” to “moderate”, or from “moderate” to “fast” on
a case by case basis. It is possible that no accuracy downgrade is needed if all the diffusion regions are small.
Related Command Quantus: mos_diffusion_parameter_extraction -auto_accuracy_downgrade [true|false]
Substrate Profile
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In heavily-doped substrates, magnetic fields generated by interconnect penetrate into the substrate and generate eddy currents,
altering the effective values of inductance and resistance of the interconnect. When using this option, the impact of the eddy
current losses on interconnect inductance and resistance is considered
Selecting Substrate Extract allows for explicit parasitic RC extraction for lightly-doped substrates, and is therefore
complementary to the Substrate Profile command which considers eddy current losses in heavily-doped substrates. These two
methods of substrate loss calculation are mutually exclusive, and the appropriate option should be chosen based on the
substrate doping in the process of interest.
For instructions on creating the Substrate Profile, please refer to "Run Subgen for Substrate Profile" in Quantus Techgen
Reference Manual.
Related Command Quantus: substrate_extract -substrate_profile
Compressed Output File
Check this box to generate a a gzip compressed output file for all LVS front ends (Assura, Pegasus, Calibre) and the following
output formats (both flat and hierarchical mode):
Spice
Transistor Dspf
Dspf
Transistor Spef
Spef
The output file names are appended with the .gz extension.
Related Command Quantus: output_setup -compressed [true | false]
Enable Import Color
Turns on or off the color information of the input database. For more information, see "Double Patterning Technology" section in
Running Quantus chapter.
Related Command Quantus: extraction_setup -enable_dpt_color_import [true | false]
DPT Corner Triplet RC Format
Obtaining Triplet Value Output
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This GUI option works for SPICE and EV output formats only. For more information, see "Double Patterning Technology" section
in Running Quantus chapter.
Related Command Quantus: output_db -output_triplet_rc [true | false]
Custom DPT Corner File
Corner Definition File Search
Lets you search for a custom DPT corner definition file, view it, or edit existing corner definition files. For more information, see
"Double Patterning Technology" section in Running Quantus chapter.
Related Command Quantus: extraction_setup -custom_dpt_corner
Device Properties File
Note: This option is visible only in the Calibre- Quantus UI.
Specify the location of the device properties file dumped by Calibre in this field. You can also click (...) and browse to the location
containing the file. For details on the device properties file, refer to Device Properties File .
Related Command Quantus: input_db -device_properties_file
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Extracted View Output​
Cadence Design Framework II Extracted View Output
Extracted View and Lib Cell View
The Lib and Cell are determined by the selections you made when opening the design in Cadence Virtuoso Layout Editor.
These fields cannot be modified here.
The default View name is av_extracted but can be changed by typing in the text entry field.
Starting with PVE 12.1.1 release, you can generate a Extracted View without the parasitic elements by selecting the NONE
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option from Extraction Type list.
Related Command Quantus: output_db -type extracted_view
Enable CellView Check
Turning on the Enable CellView Check command causes Quantus to abort if any of the cellViews defined by the extractXXX
statements in the LVS rule deck are not found. This occurs regardless of whether the cellViews are actually required in the
design. See the Assura Command Reference for more information on the device extraction commands (extractXXX).
With this command disabled, as a default, Quantus will continue to execute unless a cellView that is actually required by the
design is not found.
Related Command Quantus: output_db -enable_cellview_check [true | false]
Replace Square Busbit Delimiter
Turning on the Replace Square Busbit Delimiter command replaces square busbit delimiters with angular busbit delimiters. The
angular busbit delimiter treatment is required to align the extracted view with the DFII namespace in the schematic so that
netlisting and cross-probing work properly. The input database should be Calibre or Pegasus. Assura input database is not
supported.
The feature is only supported in the extracted view and LVS extracted view output formats. By default, the option is not selected.
Related Commands Quantus: output_db –replace_square_busbit_delimiter [true | false]
Parasitic Resistor Component and Property
Specify the parasitic resistor component in the DFII library and parasitic resistor property name (Id) for Quantus to use in the
extracted view output. The default parasitic resistor component and property name are presistor and r, respectively.
Related Commands Quantus: output_db -res_component and -res_property_name
Parasitic Cap Component and Prop Name
Parasitic Capacitor Component and Property
Specify the parasitic capacitor component in the DFII library and parasitic capacitor property name (Id) for Quantus to use in the
extracted view output. The default parasitic capacitor component and property name are pcapacitor and c, respectively.
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Note: If a property name is specified, an optional view name followed by an optional library name also can be specified (the
default view is symbol view). Each of these additional names must be separated from the previous name by a space (see the
illustration below).
Related Commands Quantus: output_db -cap_component and -cap_property_name
Specify a Larger View to See Parasitics. If you have a view in your library for parasitic components, such as an ivpcell
view that scales parasitic component symbols to sizes larger than the default symbol view for these components, specify
the view name after the parasitic component name in the property name field--for example, insert pcapacitor ivpcell in
the property name field (see above figure). If applicable, use this technique for all parasitic component property name
fields in the extracted view options section (see the additional parasitic property name fields below) to view larger
depictions of each component in the extracted view.
Parasitic Inductor Component and Property Name
Specify the parasitic self-inductance (inductor) component in the DFII library and parasitic self-inductance property name (prop
Id) for Quantus to use in the extracted view output. The default parasitic self-inductance component and property name are
pinductor and l (lower case L), respectively.
Related Commands Quantus: output_db -ind_component and -ind_property_name
Parasitic Mutual Inductor Component and Coupling Coefficient Property Name
Specify the parasitic mutual inductor component in the DFII library and parasitic mutual-inductance coupling coefficient property
name (Id) for Quantus to use in the extracted view output. The default parasitic mutual inductance component and coupling
coefficient property name are pmind and k, respectively.
Related Commands Quantus: output_db -mutual_ind_component and -mutual_ind_property_name
Mutual Inductance L1 and L2 Property Names
Property Names of Mutual Inductances
Specify the first mutual inductance (L1) and second mutual inductance property names to use in the Quantus extracted view
output. The default first inductance (L1) property name is ind1 and the default second inductance (L2) property name is ind2.
Related Commands Quantus: output_db -ind1_property_name and -ind2_property_name
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Parasitic CCVS Component
Specify the parasitic CCVS component in the DFII library and parasitic Hgain and Vref property names (Id) for Quantus to use in
the extracted view output.
Related Commands Quantus: output_db -type extracted_view -ccvs_hgain_property_name <string> and -ccvs_vref_property_name <string>
Parasitic VS Component
Specify the parasitic VS component in the DFII library and parasitic property name (Id) for Quantus to use in the extracted view
output.
Related Commands Quantus: output_db -type extracted_view -vs_property_name <string>
Call Procedure
Specifies a SKILL file (including the path if the file is located outside the current working directory) that contains an
avExtractedCellViewCallProc procedure to modify the extracted view output. The use of this field is optional. It allows you to
customize the Quantus extracted view output to meet the requirements of your design flow and environment (by adding or
changing properties, manipulating DFII data, and such).
You can select the Call Procedure checkbox to write the Call Procedure option (output_db -postprocess_extracted_view) to
the CCL file that is to be run. This checkbox is selected by default. If you do not want to output this CCL command option, then
clear this checkbox.
The SKILL procedure is declared as follows:
procedure( avExtractedCellViewCallProc( cvId )
...operations on the extracted view data
)
Quantus will create the extracted view, then load the Call Procedure file and call the procedure, passing it the database ID of the
extracted view.
Note: You can also place the avExtractedCellViewCallProc code into a file named `callProc.il', and place that file in the
technology directory. Quantus automatically loads and executes the callproc.il file if it is found in the technology directory.
This is applicable in all three flows: Assura, Calibre, and Calibre-Quantus flows.
Related Command Quantus: output_db -postprocess_extracted_view
Substrate Extract
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The Substrate Extract command is only available when the output format is Spice or Extracted View. See "Substrate Extract" for
the details of this command.
Related Command Quantus: substrate_extract -extract_under_contacts [true | false]
Extract MOS Diffusion AP
This command is no longer recommended and should not be specified.
Extract MOS Diffusion Res
Check this box to extract parasitic resistors on MOSFET source and drain regions. These parasitic resistors are listed in the
SPICE netlist as NRS and NRD properties, which contain the number of squares of parasitic resistance for MOSFET source and
drain regions, respectively.
Enabling this command disables the Extract MOS Diffusion High command as they are mutually exclusive.
Related Command Quantus: mos_diffusion_parameter_extraction -res [ fast | moderate | accurate ]
Add LVS MOS Diffusion Res
Check this box to add the NRD/NRS values (calculated by Quantus) to the corresponding values passed on by Assura LVS to
Quantus.
Note: This option can be selected only when the Extract MOS Diffusion Res option is selected.
Related Command Quantus: mos_diffusion_parameter_extraction -add_lvs_extracted_res {true | false}
Extract MOS Diffusion High
This command provides the NRD/NRS extraction using the 2D Laplace solver with the ability to specify the desired level of
accuracy. Zero is the default accuracy and is recommended in most cases; 3 offers the greatest accuracy, but results in very long
run times. Specifying "None" turns off the 2D Laplace solver.
If Extract Mos Diffusion Res is enabled this command is disabled.
Related Command Quantus: mos_diffusion_parameter_extraction -res [ fast | moderate | accurate ]
Substrate Profile
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In heavily-doped substrates, magnetic fields generated by interconnect penetrate into the substrate and generate eddy currents,
altering the effective values of inductance and resistance of the interconnect. When using this option, the impact of the eddy
current losses on interconnect inductance and resistance is considered
Selecting Substrate Extract allows for explicit parasitic RC extraction for lightly-doped substrates, and is therefore
complementary to the Substrate Profilecommand which considers eddy current losses in heavily-doped substrates. These two
methods of substrate loss calculation are mutually exclusive, and the appropriate option should be chosen based on the
substrate doping in the process of interest.
For instructions on creating the Substrate Profile, please refer to "Run Subgen for Substrate Profile" in Quantus Techgen
Reference Manual.
Related Command Quantus: substrate_extract -substrate_profile
Library Prefix and Library Directory
Note: These commands are only active when the Enable HRCX command has been turned on (see "Hierarchical Extraction" ).
Define a Library Prefix for the extracted output created during hierarchical extraction of an extracted view. For example it could
be "ext_". The tool will automatically create new libraries using this prefix. For example if a cell comes from a library named
ra01x, Quantus will create a new library named ext_ra01x. All extracted cell views which are derived from library ra01x will be
placed in library ext_ra01x.
Specify a Library Directory for storing the new libraries created for an extracted view during hierarchical extraction.
If the new library defined by the Library Prefix and Library Directory already exists Quantus will use the existing library and
there is a possibility of overwriting a design library. Write permissions may prevent that from happening but you should be
aware of the possibility.
Related Commands Quantus: output_db -hierarchical_extracted_views_directory \
-hierarchical_extracted_views_prefix
CDL Out Run Directories
Note: In the case of Pegasus or Calibre input, the CDL Out Run Dirs command also applies to the Extracted View outputs.
In CDL netlists, the names of cells or devices may be modified with the addition of an "X" prefix for cell instances, or "M","Q", or
other device specific character prefix for device instances by the CDLOUT utility that creates the netlist. When this netlist is used
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as an input to an LVS tool and subsequently to Quantus, the output from Quantus will include the instance and net names from
the CDL and not from the original DFII names. The "X" prefix added to cell instances will also affect a hierarchical net name. For
example the net I5/I6/net1 will be seen in the netlist as XI5/XI6/net1.
However, DSPF/SPEF output requires the original instance names, and not the modified names of the CDL netlist. Parasitic
probing of the extracted view also requires the original instance and net names.
The mapping created by the CDLOUT utility remains in mapping files in the CDLOUT run directory. This is the specified run
directory when the CDL netlist was created. The CDL Out Run Dirs option indicates the location of the CDLOUT run directories
that should be searched for mapping files to associate the modified CDL instance name with the original device instance name
to be used in the output netlist. You can use the browse button to browse and select the CDLOUT run directory.
The CDL Out Run Dirs option is necessary whenever the schematic input file for LVS is one or more CDL netlists created by
CDLOUT from DFII schematics. In Quantus, this option is used for cell level DSPF/SPEF creation and extracted view creation for
Pegasus or Calibre input.
The CDL Out Run Dirs must be specified for proper back annotation to the extracted view from the Calibre or Pegasus input
netlist name space back to the schematic view name space. Quantus establishes proper mapping using the CDL Out Run Dirs if
the input netlist was originally from CDLOUT.
If Pegasus LVS is started from Virtuoso and a DFII schematic is specified as an input, and if the CDL netlisting is done as part of
the LVS run, then the run directory where CDLOut is run is passed to the Quantus UI, which is populated automatically.
Related Command Quantus: output_db -cdl_out_map_directory
LVS Extracted View Output
If LVS Extracted View is the selected output format, the Quantus run will produce a Cadence DFII extracted view without
parasitics extracted. An extracted view is created containing all of the designed devices and connectivity extracted from the
layout by LVS without executing the Quantus parasitic extraction. The default LVS Extracted View filename is av_extracted but
can be changed by typing in the text entry field.
Quantus supports generation of an LVS Extracted View for the Pegasus-Quantus flow. For the Pegasus-Quantus flow, the LVS
Extracted View is flat. Quantus flattens the hierarchy provided by Pegasus.
The Pegasus LVS extracted view supports the Transfer Property Control File if there is a schematic view and the output_db cdl_out_map_directory (see output_db ) is set appropriately. For details, see "The Transfer Property Control File
(extview.trp)" section in the Running Quantus with Pegasus and Calibre Inputs chapter.
Lvs Extracted View - Pegasus-Quantus Flow
Quantus supports generation of an LVS Extracted View for the QCI flow. Like the Pegasus-Quantus flow, the QCI LVS Extracted
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View is also flat.
Lvs Extracted View - QCI Flow
The QCI LVS extracted view supports the Device Properties File from Calibre LVS, and the Transfer Property Control file with
the same requirements as mentioned for the Pegasus-Quantus LVS Extracted View flow.
When you select the Lvs Extracted View option, in the QCI and Pegasus-Quantus flows, the following Quantus options that
provide NRD/NRS device parameters are made available for all MOS/LDD devices and also for devices specified using the
Techgen -genericMos command:
Extract MOS Diffusion Res
Add LVS MOS Diffusion Res
Extract MOS Diffusion High
Selecting LVS Extracted View disables the Extraction, Filtering, and Netlisting tabs on the Quantus Run form as these
options will not be necessary since parasitics will not be extracted.
Related Command Quantus: output_db -type lvs_extracted_view
LVS Extracted View Command Options
See the following commands under Extracted View:
Enable CellView Check
Replace Square Busbit Delimiter
Call Procedure
Library Prefix and Library Directory
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Smart View Output
Smart View and Lib Cell View
The Lib and Cell are determined by the selections you made when opening the design in Cadence Virtuoso Layout Editor. The
default View name is oa_extracted but can be changed by typing in the text entry field. Quantus supports generation of the
Smart View format for the QCI, Assura, and Pegasus LVS-Quantus flows.
Related Commands Quantus: output_db -type smart_view
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Cell-level DSPF Output​
Provides for the output of Detailed Standard Parasitic Format (DSPF) for use in timing analysis.
DSPF Netlist Output
Related Command Quantus: output_db -type dspf
Cell-level SPEF Output
Provides for the output of Standard Parasitic Extraction Format (SPEF) netlist for use in timing analysis.
SPEF Netlist Output
SPEF netlist provides the same information as the DSPF netlist but in a compressed format that reduces output file size
by as much as five times. The DSPF netlist is crafted to be Spice equivalent so a DSPF file can be read by a Spice
simulator. However, the SPEF netlist format is not compatible with Spice.
Related Command Quantus: output_db -type spef
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DSPF and SPEF Command Options
Name
Filename for DSPF or SPEF Output
The default filename for DSPF or SPEF output is the LVS runname followed by a .dspf or .spef extension, respectively.
You can specify a different name by typing in the filename field or by clicking "..."to invoke a file browser to choose an existing
filename. The Quantus output will overwrite the contents of the selected file.
Related Command Quantus: output_setup -file_name
Sub Nodes
If set to true (t), this parameter indicates that subnodes are to be included in the DSPF output netlist. The subnodes are the
"*|S"lines where the XY coordinates of net's internal nodes are printed. Including subnodes in the output can help with
debugging, but adds to processing time and output quantity.
Related Command Quantus: output_db -disable_subnodes [true | false]
Header File
Header, Pin Cap, DSPF Cells File, and Gray Box
Specifies a file that contains header text to be included in the DSPF output file as comments. This file can be used to contain a
date/time stamp, or a version number, or a logo or disclaimer information.
Related Command Quantus: output_db -header_file
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Pin Cap File
The direction of primary ports and instance pins in DSPF/SPEF output is automatically obtained from the schematic when
the Netlist with Names From: command is set to "schematic" (see Netlist Names). Therefore, the ?pinCapFile command is
no longer required. However, if the ?pinCapFile command is specified it takes precedence over the schematic
information.
Specifies a file that contains pin capacitance and pin direction information to be applied to the DSPF/SPEF output file. The Pin
Cap File and Pin Order File can be the same file containing both pin orders and pin capacitances, however both the Pin Order
File and Pin Cap File commands must be used to perform their respective functions.
Related Command Quantus: output_db -pin_cap_file
Pin Order File
Specifies a file that contains the pin orders for the listed cells to be applied to the netlist output. Pin names in the file must
correspond to the schematic pin names, and require the Name Space to be set to Schematic.
Related Command Quantus: output_db -pin_order_file
Force Subcircuit Pin Order
Specifies to align the hierarchical output netlist’s subcircuit IO pins with the schematic subcircuit IO pins as specified in the Pin
Order File field.
Related Command Quantus: output_db -force_subcell_pin_orders
DSPF Cell File
Used with Calibre or Pegasus input, the DSPF Cell file provides the list of cells that will be exported to the DSPF netlist. This
command replaces the ?dspfCells command supported in the Assura LVS flow. Since Assura LVS will not be generating the
runName.dcl file for RCX, one must be provided directly using this command.
The format of the DSPF Cells File is to specify one cell name per line. The DSPF Cells File may include cells that are not found
in the design. Cells that are not found in the design will simply be ignored by Quantus when parsing the file.
Related Command Quantus: input_db -type pegasus | calibre
-library_cell_list_file
Gray Box
By default Quantus views DSPF cells as black boxes, which it cannot see the contents of during extraction. This option specifies
that DSPF cells should be viewed as gray box cells, the contents of which are grounded for the purpose of capacitance
extraction.
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Related Command Quantus: graybox -type [ layout | lef_obstruction | none ]
Substrate Profile
In heavily-doped substrates, magnetic fields generated by interconnect penetrate into the substrate and generate eddy currents,
altering the effective values of inductance and resistance of the interconnect. When using this option, the impact of the eddy
current losses on interconnect inductance and resistance is considered
Selecting Substrate Extract allows for explicit parasitic RC extraction for lightly-doped substrates, and is therefore mutually
exclusive with the Substrate Profilecommand which considers eddy current losses in heavily-doped substrates. These two
methods of substrate loss calculation are complementary, and the appropriate option should be chosen based on the substrate
doping in the process of interest.
For instructions on creating the Substrate Profile, please refer to "Run Subgen for Substrate Profile" in Quantus Techgen
Reference Manual.
Related Command Quantus: substrate_extract -substrate_profile
Delete X-prefix
In the Quantus Pegasus/QCI flows with GDSII input, cell-level DSPF/SPEF output, and transistor-level xDSPF/xSPEF output,
the "X" prefix before hierarchical sub-circuit names can be removed with this option.
Related Command Quantus: output_db -delete_x [true | false]
CDL Out Run Directories
Note: This command does not apply to SPEF output.
CDL is sometimes used as an input to LVS and Quantus to generate a DSPF netlist. Instance names of devices may be modified
with the addition of an X prefix by the CDLOUT utility. However, the DSPF output requires the original DFII instance names
which remain in a mapping file in the CDLOUT run directory. Specify the names of the CDLOUT run directories to be searched
for instance name mapping files to be used when creating the DSPF netlist.
Related Command Quantus: output_db -cdl_out_map_directory
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Some DSPF and SPEF commands do not appear in the GUI. Refer to Assura RCX to Quantus Migration Guide for more
information on any of these commands:
?grayBox changes the default view of the DSPF cells from black box (in which case Quantus does not look into the cell) to
gray box.
?spefUnits the units to output to SPEF format netlist.
DSPF and SPEF output are not compatible with a variety of Quantus command options. The GUI will usually
disable the options when you select DSPF or SPEF output. Quantus might also provide a warning in the
command interpreter window (CIW) if you attempt to use DSPF with any of the following options:
Decoupled_To_Substrate (see Cap Coupling Mode)
Via Effect Off (see Via Effect Off)
Transistor-level DSPF Output​
The Transistor level DSPF (XDSPF) feature is available in Quantus to generate a transistor level DSPF netlist. Devices such as
MOS/LDDs, BJTs, Diodes, drawn Resistors and Capacitors are treated similar to cells in the regular DSPF output format. The
number of parasitic capacitance records is the same as SPICE output. The number of parasitic resistors may increase slightly to
account for abutment resistors.
Starting with the EXT 10.1.1 HF1 release, you can generate a transistor-level DSPF netlist without the parasitic elements by
selecting the NONE option from Extraction Type list located under the Extraction tab. Like the LVS extracted view, the generated
netlist is also flat. With the NONE option, the Quantus options NRD/NRS device parameters (available for all MOS/LDD devices
and also for devices specified using the Techgen -genericMos command), LPE parameters, and netlist post processing are
enabled.
Starting with the EXT 10.1 release, Quantus has been enhanced to output the actual pin names from the LVS rule file for
standard device instances (canonical resistors, capacitors, and diodes) in xDSPF and xSPEF outputs. Pegasus-Quantus,
Assura-Quantus, and QCI flows are supported. As in earlier releases, generic devices also have actual pin names, while MOS
and BJT are output as (d,g,s,b) and (c,b,e,s) respectively.
New in EXT 10.1.2, if the mosPinOrder argument is specified with the Techgen -genericMos command, Quantus (PegasusQuantus and QCI flows)) outputs the pin order of 5-terminal/6-terminal MOS, LDD, and generic MOS devices as D,G,S, B to
follow the SPICE convention.
Note: The direction of primary ports and instance pins in XDSPF/XSPEF output is automatically obtained from the schematic
when the Netlist with Names From: command is set to "schematic" (see Netlist Names). However, the pin directions for
canonical devices will not be generated. Either "B" (for XSPEF) or "X" (for XDSPF) is output to the netlist for these devices.
Transistor-level DSPF Netlist Output
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Transistor-level DSPF Netlist Output
For a complete understanding of the XDSPF/XSPEF netlist format, please refer to the ?xdspf command in Assura RCX to
Quantus Migration Guide.
Related Command Quantus: output_db -type dspf
Transistor-level SPEF Output
Transistor-level SPEF Output, or XSPEF netlists support better integration to the UltraSim simulator. However, unlike XDSPF
which is one file, with an optional Instance section, XSPEF output is two files with an optional Instance file. In addition, both
XDSPF and XSPEF were extended to support hierarchical as well as flat extraction modes. For a complete understanding of the
XDSPF/XSPEF netlist format, please refer to the ?xdspf and ?spef commands in Assura RCX to Quantus Migration Guide.
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Starting with the EXT 10.1.1 HF1 release, you can generate a transistor-level SPEF netlist without the parasitic elements by
selecting the NONE option from Extraction Type list. Like the LVS extracted view, the generated netlist is also flat. With the
NONE option, the Quantus options NRD/NRS device parameters (available for all MOS/LDD devices and also for devices
specified using the Techgen -genericMos command), LPE parameters, and netlist post processing are enabled.
New in EXT 10.1.2, if the mosPinOrder argument is specified with the Techgen -genericMos command, Quantus (PegasusQuantus and QCI flows)) outputs the pin order of
5-terminal/6-terminal MOS, LDD, and generic MOS devices as D,G,S, B to follow the SPICE convention.
Transistor-level SPEF Netlist Output
Related Command Quantus: output_db -type spef
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XDSPF and XSPEF Command Options
Name
The default filename for XDSPF output is the LVS runname followed by a .dspf extension.
You can specify a different name by typing in the filename field or by clicking "..."to invoke a file browser to choose an existing
filename (the Quantus output will overwrite the contents of the selected file).
However, because Transistor Spef (XSPEF) outputs multiple files during an extraction run, the Namefield is used to specify the
directory name to write the output into, and the actual file names are determined by the design name ( <DESIGN_name> ), where
<DESIGN_name> is either the name of the top-level cell, or any child cells in hierarchical extraction.
Related Command Quantus: output_setup -file_name
Extract MOS Diffusion AP
This command is no longer recommended and should not be specified.
Extract MOS Diffusion Res
Check this box to extract parasitic resistors on MOSFET source and drain regions. These parasitic resistors are listed in the
SPICE netlist as NRS and NRD properties, which contain the number of squares of parasitic resistance for MOSFET source and
drain regions, respectively.
Enabling this command disables the Extract MOS Diffusion High command as they are mutually exclusive.
Related Command Quantus: mos_diffusion_parameter_extraction -res [ fast | moderate | accurate ]
Add LVS MOS Diffusion Res
Check this box to add the NRD/NRS values (calculated by Quantus) to the corresponding values passed on by Assura LVS to
Quantus.
Note: This option can be selected only when the Extract MOS Diffusion Res option is selected.
Related Command Quantus: mos_diffusion_parameter_extraction -add_lvs_extracted_res {true | false}
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Extract MOS Diffusion High
This command provides the NRD/NRS extraction using the 2D Laplace solver with the ability to specify the desired level of
accuracy. Zero is the default accuracy and is recommended in most cases; 3 offers the greatest accuracy, but results in very long
run times. Specifying "None" turns off the 2D Laplace solver.
If Extract Mos Diffusion Res is enabled this command is disabled.
Related Command Quantus: mos_diffusion_parameter_extraction -res [ fast | moderate | accurate ]
SPEF Units
This option allows you to specify the units and the positive, real-valued multiplier for Resistance and Capacitance SPEF unit
variables: *C_UNIT (capacitance), and *R_UNIT (resistance).
You can enable SPEF Units by selecting the toggle button. You can also specify values for the SPEF Units by selecting the Edit
command. In this case the SPEF Units Editor opens to allow you to enter the SPEF multiplier for Capacitance and Resistance.
SPEF Units Editor
Note: The SPEF Units for time and impedance are not available through this form. You must use the command language to
modify those units. See output_db for more information.
Related Command Quantus: output_db -type spef -units [ micron | angstrom | < string > ]
Substrate Profile
In heavily-doped substrates, magnetic fields generated by interconnect penetrate into the substrate and generate eddy currents,
altering the effective values of inductance and resistance of the interconnect. When using this option, the impact of the eddy
current losses on interconnect inductance and resistance is considered
Selecting Substrate Extract allows for explicit parasitic RC extraction for lightly-doped substrates, and is therefore mutually
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exclusive with the Substrate Profilecommand which considers eddy current losses in heavily-doped substrates. These two
methods of substrate loss calculation are complementary, and the appropriate option should be chosen based on the substrate
doping in the process of interest.
For instructions on creating the Substrate Profile, please refer to "Run Subgen for Substrate Profile" in Quantus Techgen
Reference Manual.
Related Command Quantus: substrate_extract -substrate_profile
Add Bulk Terminal
By default, Quantus does not create the instance:terminal names for backgates of standard devices in the xDSPF/xSPEF netlist.
The addBulkTerminal option specifies that the instance:terminal names should be created for backgate terminals that have an
explicit connection to the R network. See the RCX to EXT Migration Guide for details of this command.
Related Command Quantus: output_db -add_bulk_terminal [true | false]
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Extraction Tab
Quantus Run Form Extraction Tab
Note: You need to scroll down to see the complete set of options.
The Extraction tab provides commands for specifying the type of extraction to perform, and the selection of nets from the design
to perform extraction on. In addition, there are commands to control various aspects of Resistance, Capacitance, and Inductance,
and Hierarchical Extraction. The following sections discuss the various commands in greater detail. For more information on the
details of extraction refer to "Parasitic Extraction" .
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Extraction Type​
This command allows you to choose the parasitic components to extract from the design during the Quantus run. The extraction
of resistance (R), capacitance (C) and inductance (L and K) can be individually selected or disabled, as explained below.
Decoupled capacitance extraction (C Only) is selected as the default Quantus extraction setting. You can select one or more
types of parasitic component extraction for the run--that is, capacitance, resistance and/or inductance extraction.
Starting with EXT 10.1.1 HF1, the extraction type NONE enables you to generate SPICE, xDSPF and xSPEF netlists without
any parasitics. Like the LVS extracted view, the generated netlists are also flat.
Starting with PVE 12.1.1 release, Quantus UI supports the extracted view output mode with Extraction Type set to NONE.
If the Substrate Extract command on the Setup tab is turned on, then the available extraction modes are R-only, RC, RLC,
and RLCK.
Related Commands Quantus: extract -type [ none | substrate_only | r_only | c_only_decoupled |
c_only_coupled |c_only_decoupled_to_substrate |
rc_decoupled | rc_coupled | rc_decoupled_to_substrate |
rlc_decoupled | rlc_coupled |rlc_decoupled_to_substrate |
rlck_decoupled | rlck_coupled | rlck_decoupled_to_substrate ]
Name Space​
This selection specifies the source of input net names for both Quantus and Field Solver extraction processing. Specifically, if
Quantus parasitic extraction or Field Solver capacitance extraction is performed on selected nets, excluded nets or selected
paths (specified later on the Run and Field Solver popup forms), this selection indicates whether the net names listed in the
selected or excluded net list box or in the designated selected or excluded net list files are Layout Names or Schematic
Names. The default net name space is layout names.
Related Command Quantus: extraction_setup -net_name_space [ schematic | layout ]
​ ​Resistance Commands
The following commands can be used in any extraction type that includes resistance (R) to control the extraction of parasitic
resistors to your specified output format. See "Resistance Extraction" for the details of this feature of Quantus.
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Max Fracture Length and Units
If resistance is selected, a Max Fracture (maximum fracture length) setting must be specified. This setting controls the maximum
length of extracted parasitic resistors as well as the distribution of parasitic capacitors in the extracted RC networks (assuming
capacitance extraction is also specified for the current Quantus run). To specify a maximum fracture length, you need to type a
numeric value, which can be an integer or a floating point number that is 5 or greater.
The Max fracture length units setting (which applies to the numeric value specified in the Max Fracture field) can be selected as
microns or squares. The default units setting is microns.
Effect of Max Fracture Setting on Extracted RC Networks
The default Max Fracture setting of infinite defines no limit on extracted resistor size. This provides sufficient resolution for
resistance fractures in the distributed parasitic RC networks, and also provides the least number of extracted resistors in the
extracted output for faster extraction and downstream simulation runtimes.
Note: The Max Fracture setting cannot be less than 5 microns. If you specify a value less than 5 microns (or 5 squares), Quantus
issues an error.
For very high speed nets (RF, optical networks, etc.) the resistance fracturing is specified along with the net name in the
Inductance nets file (see Enter Inductance Nets).
Related Command Quantus: extraction_setup -max_fracture_length \
-max_fracture_length_unit [ microns | squares ]
Max Fracture Length By Layer
Specifies to fracture wires on a layer basis for resistance extraction. You can define the specific LVS Layers and fracture length
value using the following two methods:
Using the Edit button - The Edit button opens the Max Fracture Length By Layer form, as shown below:
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You can then use the Add, Edit, or Delete button to define or change layers and fracture length.
Using the From File field - You can select the From File checkbox, and click the browse button to browse and select a text
file containing LVS Layers and fracture length value . The format of the text file is two columns with <layer name>
<fracture value> pair per line. When this file is selected, you can modify the text file values by clicking the Edit button.
Temperature
Specifies the operating temperature of the device for the purposes of temperature dependent resistance extraction. The change
in temperature (deltaT) between the specified operating temperature and the reference temperature is used to determine the
effect of temperature on parasitic resistance.
In order for temperature dependent resistance extraction to work, temperature coefficients (TC1 and TC2) must be added to the
ICT file (see Quantus Techgen Reference Manual). If temperature is specified and no temperature coefficients have been
defined a warning is returned to the log file, and the resistance extraction will not consider the effect of temperature.
In EXT8.1, enabling the Parasitic Resistance Temperature Coefficient switch will disable the Temperature field. This is due to
the fact that the TC1/TC2 coefficients are output directly, for temperature calculation by the downstream simulation or analysis
tool, and the resistance extracted by Quantus is not directly affected by temperature. See "Netlisting Tab" for more information on
this command.
Related Command Quantus: process_technology -temperature
Resistance Mesh
This command improves resistance extraction under specific situations. For irregular wide metal regions, traditional resistance
extraction techniques such as square counting no longer provide accurate estimates for resistance values between vias since
current flow is not straight. The width and length of a parasitic resistor are difficult to clearly define in this case. To improve
accuracy a field solver may be employed to compute resistances between contacts, but this approach can considerably increase
extraction runtimes.
With the use of the Resistance Mesh command, Quantus overlays a mesh resistance network on top of a metal region, and
eliminates the mesh points (or nodes) which fall outside the region. See "extraction_setup" for more information on the
Resistance Mesh command (resistance_mesh).
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When Resistance Mesh is specified, inductance will not be extracted in the areas of the mesh. In addition, metal bias,
resistivity as a function of width, and rho as a function of width and spacing are not supported with this option. If any of
these options are specified, then the Resistance Mesh option will be honored, but the resistivity values used for the
shapes on which mesh is applied might not reflect the actual widths and/or spacings of those shapes.
When enabling the switch, you must also define the specific LVS Layers and Mesh Sizes to be used by Quantus during
extraction using the Edit button. The LVS layers are the extraction layers read from layer_setup file.
The Edit button opens the LVS Layers and Meshes form shown in the below figure.
If a meshR.defs file is found in the specified technology directory, or technology corner, Quantus will read the meshR.defs file
and populate the LVS Layers and Meshes form with the information it contains. You can then use Add, Edit, or Delete commands
to define or change layers and mesh sizes.
LVS Layerspecifies an LVS layer name as specified in the extract.rul file or the ext_layer name from the layer_setup file. The
layer must be defined as a resistive layer in the layer_setup file. An LVS Layer may only be specified once in the Resistance
Mesh command.
Mesh Size is an optional argument that allows you to override the default mesh size calculated for the layer by Quantus. If you
specify the mesh size, the value should be a number that is smaller than the "SMALLEST SHAPE" which is used as an input to
mesh resistance calculation. Shapes smaller than the specified value will continue to use the regular field solver for resistance
computation.
Define LVS Layers and Mesh Sizes for the Resistance Mesh
Predefined Resistance Mesh Files
A predefined resistance mesh file called meshR.defs can be added to the technology directory with the following information:
< layer1 > < meshSize1 >
< layer2 > < meshSize2 >
...
< layerX > < meshSizeX >
Where:
< layerX > specifies an ext_layer in the layer_setup file to be used as the LVS Layer.
< meshSizeX > specifies the desired Mesh Size for the layer, and is optional in the meshR.defs file. Quantus will
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determine the default mesh size at runtime if none is specified in the meshR.defs file.
The meshR.defs file is located in the technology directory, or in each technology corner directory for a technology
directory with multiple process corners.
Related Command Quantus: extraction_setup -resistance_mesh
Adaptive
This option allows the use of parasitic resistor mesh for higher accuracy. When you select default (square adaptive meshing), the
software enhances the Quantus output by reducing the output size without causing accuracy degradations.
The default option is false. By default, the Adaptive option is disabled. This is enabled once you select the Resistance Mesh
check box.
Related Command Quantus: extraction_setup –resistance_mesh_adaptive [ default | false ]
Mesh Via Layer
This button enables you to specify layers for mesh resistance extraction. By default, the Mesh Via Layers button is disabled. This
is enabled once you select the Resistance Mesh check box.
Clicking Mesh Via Layers opens the Mesh Via form as shown below:
The LVS layers are the extraction layers read from layer_setup file.
Click Add to add the LVS via layers to be considered for mesh resistance extraction. The LVS Layers form opens.
Click Edit to edit the layers listed in the Mesh Via form.
Click Delete to delete a particular layer and Delete All to remove all the layers from the list.
Click Find to search a particular layer from the list of layers added.
LVS Layers Form​
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Once you have added the required LVS via layers, click OK. The selected layers will be considered in the mesh resistance
calculation.
Related Command Quantus: extraction_setup –resistance_mesh_via_layers
Automatic Mesh Size
This option specifies to automatically determine the mesh size for the specified layers. If you select the Automatic Mesh Size
checkbox, the following UI fields will be enabled:
Edit button
Adaptive drop-down list (set to "default")
R Mesh Accuracy drop-down list
Options button
By default, this checkbox is cleared. The Automatic Mesh Size field is mutually exclusive with the Resistance Mesh and R Mesh
User Region fields.
The Edit button opens the LVS Layers and Meshes form, as shown below:
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If a meshR.defs file is found in the specified technology directory, or technology corner, Quantus will read the meshR.defs file and
populate the LVS Layers and Meshes form with the information it contains. You can then use Add, Edit, or Delete commands to
define or change layers and mesh sizes.
Click Add to add the LVS layers to be considered for automatic mesh resistance extraction.
Click Edit to edit the layers listed in the LVS Layers and Meshes form.
Click Delete to delete a particular layer and Delete All to remove all the layers from the list.
Click Find to search a particular layer from the list of layers added.
If you select the non-custom accuracy level (Liberal, Moderate, Conservative, or V. Conservative) from the R Mesh
Accuracy drop-down list, the LVS Layers and Meshes form displays only the LVS Layer column, and if you select Custom
from the R Mesh Accuracy drop-down list, then the form has the LVS Layer and Mesh columns.
Once you have added the required LVS layers, click OK. The selected layers will be considered in the automatic mesh
resistance calculation.
Related Command Quantus: extraction_setup –resistance_mesh_automatic_size <layer1> <layer2> …
R Mesh Accuracy
The R Mesh Accuracy field allows you to control the accuracy level for automatic mesh sizing. The drop-down list has the
following values:
Custom
Liberal
Moderate
Conservative
V. Conservative
The default value is ‘Moderate’.
If you select the Resistance Mesh check box and select default from the Adaptive drop-down list, the R Mesh Accuracy
drop-down list displays the Custom and default options. When you select default, all the fields related to the R Mesh
Accuracy custom mode are disabled (that is, the Options button is disabled).
The following table specifies the default values of the Advanced Adpative Mesh Accuracy options based on the different
accuracy levels:
Auto
Mesh
Size
Scale
Factor
Error
Tolerance
Adaptive
Mesh
Square
Counting
Square
End
Offset
Enable
Corner
Square
Counting
Merge
Parallel
R
(Filtering
tab)
Merge
Parallel
Via
(Filtering
tab)
Advanced
Via
Merging
(Filtering
tab)
Merge
via
by mesh
size
(Filtering
tab)
Liberal
1.0
10.0
true
0.0
true
true
NA
true
true
Moderate
1.0
5.0
true
0.5
true
true
NA
true
true
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Conservative
1.0
1.0
true
1.0
false
NA
true
true
true
V.
Conservative
1.0
1.0
false
NA
false
NA
true
true
true
For example, each accuracy level, namely, the “Liberal”, the “Moderate” and the “Conservative” levels will set the
extraction_setup -max_resistance_mesh_size_error CCL option/Error Tolerance UI option to 10%, 5%, and 1% respectively.
The “conservative” levels have the highest accuracy in the automatic mesh size. If you select the Liberal, Moderate,
Conservative, or V. Conservative accuracy levels, the following UI options are grayed out:
Auto Mesh Size Scale Factor
Error Tolerance
Merge via by mesh size
Adaptive Mesh Square Counting
Square End Offset
Enable Corner Square Counting
Advanced Via Merging
You can modify these UI options only when the R Mesh Accuracy field is set to Custom.
Options
The Options button opens the Custom Settings form, as shown below:
The Custom Settings form contains the following fields:
Adaptive Mesh Square Counting - Enables additional square counting, which includes long and wide wires and nonManhattan (slant lines) wires. By default, this checkbox is cleared. The equivalent CCL option is extraction_setup resistance_mesh_more_square_counting.
Square End Offset - Specifies the interface depth of the mesh region to the square counting region, that is, how far a mesh
region extends into a non-meshed region. The width_ratio should be between 0 and 1. The equivalent CCL option is
extraction_setup -resistance_mesh_square_counting_buffer.
Enable Corner Square Counting - Specifies to include the bends (corners) or junctions in the long wide wire regions into
square counting. By default, this checkbox is cleared. The equivalent CCL option is extraction_setup resistance_mesh_corner_square_counting.
You can modify these UI options only when the R Mesh Accuracy field is set to Custom.
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Auto Mesh Size Scale Factor
final_mesh_size = <automatic_mesh_size>/<k_factor_value>
For example, if lower accuracy is tolerable, a <k_factor_value> of 0.5 will multiply the automatically generated mesh size by 2x.
Conversely, if higher accuracy is of essence, the <k_factor_value> of 2.0 would halve the automatically generated mesh size.
Related Commands Quantus: extraction_setup
-resistance_mesh_size_k_factor <value>
Error Tolerance
value
> is specified in percentage. This parameter is used in situations where the layout needs the most conservative mesh size to
achieve the highest possible accuracy.
Related Commands Quantus: extraction_setup -max_resistance_mesh_size_error <value>
R Mesh User Region
This option enables you to specify regions for mesh resistance extraction. You can specify the name of the region file in the text
box. Alternatively, you can click .... and browse to the location that contains the file.
The region file is a text file that contains the co-ordinates to specify a rectangular region defined by the lower-left corner and
upper-right corner (xlow ylow xhigh yhigh), the process layer name in the ICT file, and the mesh size in the following format:
(xlow,ylow) (xhigh,yhigh) layername mesh_size
To view the region text file, click View. You can also click Edit, and modify the region text file.
You can also select the co-ordinates from the layout, select a layer name, specify the mesh size, and create a new region file as
follows:
1. Click Select.
If a region file does not exist, the following dialog appears.
2. Click OK.
The Mesh R Select User Region window appears as follows:
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3. Click Draw BBox and select the co-ordinates from the layout.
The text box (highlighted) is automatically populated with the co-ordinates selected by you.
4. Select the layer name from the Layer Namedrop-down list.
Note: Only condutor names (and not sub_conductor layer names) are listed in the Layer Name drop-down list. In addition,
Techgen -lexclude or gate_forming_layer true keywords have no impact on the process layer names displayed in the
Layer Name drop-down list. That is, conductor layers (specified with gate_forming_layer true keyword in the ICT file), will
be listed in the Layer Name drop-down list.
5. Specify the mesh size in the Mesh Size text box.
6. Click Add.
The co-ordinates, layer name, and mesh size are displayed in the text field (highlighted) as follows:
7. Click OK and specify the location where you want to save the region file.
The co-ordinates are specified with respect to the top cell. You can define more than one user region in the region file. Each
region may have a different mesh size. In addition, the specified regions are allowed to overlap. If the overlapping regions on the
same metal layer have different mesh sizes, the smallest mesh size is used for mesh resistance calculation.
If non-overlapping regions on the same metal layer have different mesh sizes, then each region is meshed with its respective
mesh size.
The regions specified in user region file use the mesh resistance calculation, while the rest of the regions (not defined in the user
region file) use the standard resistance calculation. If one region is split into two types, equi-potential butting vias are created
between the regions in order to connect the resistor networks.
Related Command Quantus: extraction_setup -resistance_mesh_region
Starting with PVE 12.1 release, in a single corner mode, if there is a meshR.defs in the parent directory as well as in the corner
directory, the meshR.defs in the corner directory is used by Quantus. In a single corner mode, the meshR.defs file in parent
directory is searched if it is not present in a given corner. In a multi-corner mode, meshR.defs (if present in the parent directory), is
used for all corners.
Note: Starting with PVE 12.1 release, Quantus supports MeshR regions based on user-specified layers. For more information,
refer to Quantus Techgen Reference Manual.
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Non-Manhattan Resistance
LCD/MEMS designs may feature near orthogonal routing features, angled from 0 to 10 degrees away from manhattan, as
opposed to perfect Manhattan or 45 degree lines. Set the Non-Manhattan Resistance Accuracy option to handle such routing
features with better accuracy.
When this option is set to high, Quantus checks out an XL license and a Display Technology (DT) GXL option. However, if the
qrcTechFile is created using the Techgen -non_planar simulation option then this feature is automatically enabled and an
additional DT GXL option is not required.
Related Command Quantus: extraction_setup -nonmanhattan_resistance [default_accuracy | high_accuracy]
Layer Setup Customization
This option opens the Layer Setup Editor form.
Select the Layer Setup Customization option and click the Edit button to open the Layer Setup Editor form.
The below figure shows an example of the Layer Setup Editor form.
Layer Setup Editor
The Layer Setup Editor provides a GUI-based interface, where you can load an existing layer_setup file and modify it. After the
updates are complete, the output layer_setup file is named layerSetupFile and added to the Quantus run directory. The layer
setup GUI provides you the flexibility to change qrcTechFile layer settings (metal and via) at Quantus run time.
The layer_setup file that you want to modify must be located in the technology directory and should be named layerSetupFile.
If not, the Layer Setup Editor form will not be populated automatically.
Note: Starting with EXT 10.1.1, Quantus has been enhanced to read the template files from the directory specified using the
environment variable QRC_UIFORMS_TEMPLATE_DIR. Now, the Layer Setup Customization option is not disabled if a template file is
specified using QRC_UIFORMS_TEMPLATE_DIR environment variable.
Note: The Layer Setup Customization option works with Quantus unified tech file only and not with the RCX tech directory.
The Layer Setup Editor form contains the following fields:
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Layer Setup File: Allows you to select an existing layer_setup file that you want to modify.
Layer Name: Specifies the layer name.
Res: Specifies the type of resistance value. This field allows you to selectively change the layer resistance at Quantus run
time. The resistance type can be one of the following:
Default: Specifies that the default resistance value will be used.
Short: Sets the resistance value to 0.
Value: Allows you to specify a different resistance value.
Value: Allows you to specify the resistance value. This field is editable only when you select the Value option of the Res
field.
Add Explicit Via: Provides the capability of selectively adding the vias and contacts of your choice to the netlist explicitly.
This option is available for the CONT and VIAlayers only.
Note: If both Add Explicit Via and Layer Setup File options are used together, and the Layer Setup file has specific
contacts and vias selected, then the ?addExplicitVias t will not be output to the Quantus UI.
Example of Modifying a layer_setup File Using the Layer Setup Editor
Consider the following example of a layer_setup file, which will be used as input to the Layer Setup Editor:
# process_layers
pro_layer=FOX ext_layer=nxwell
pro_layer=FOX ext_layer=psub
pro_layer=active ext_layer=tdiff,ndiff
pro_layer=poly ext_layer=npoly
pro_layer=metal1 ext_layer=M1A,M1B
pro_layer=metal2 ext_layer=M2A sheet_res=2.0
pro_layer=metal3 ext_layer=M3
pro_cont=CONT ext_cont=PCONT top_layer=metal1 bottom_layer=pdiff res=5.0 model=A
pro_cont=CONT ext_cont=NCONT top_layer=metal1 bottom_layer=ndiff res=5.5 model=A
pro_cont=VIA1 ext_cont=v1 res=1.0
After making the changes as shown in the above figure, the layer_setup file will be changed to:
# process_layers
pro_layer=FOX ext_layer=nxwell
pro_layer=FOX ext_layer=psub
pro_layer=active ext_layer=tdiff,ndiff
pro_layer=poly ext_layer=npoly
pro_layer=metal1 ext_layer=M1A,M1B sheet_res=0
pro_layer=metal2 ext_layer=M2A sheet_res=1.0
pro_layer=metal3 ext_layer=M3
pro_cont=CONT ext_cont=PCONT top_layer=metal1 bottom_layer=pdiff res=5.0 model=A add_cont_res
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pro_cont=CONT ext_cont=NCONT top_layer=metal1 bottom_layer=ndiff res=5.5 model=A add_cont_res
pro_cont=VIA1 ext_cont=v1 res=0
Capacitance Commands
For parasitic capacitance extraction, select C Only, RC, RCL, or RCLK from the Extraction Type cyclic field. This enables
various capacitance extraction options, such as Cap Coupling Mode, Ref Node for grounding caps, and Mult Factor to provide a
capacitance multiplier. See "Capacitance Extraction" for the details of this feature of Quantus.
Cap Coupling Mode​
If capacitance extraction is checked, choose whether parasitic capacitors will be Coupled or Decoupled, or Decoupled To
Substrate.
Related Commands Quantus: extract -type [ none | substrate_only | r_only | c_only_decoupled |
c_only_coupled |c_only_decoupled_to_substrate |
rc_decoupled | rc_coupled | rc_decoupled_to_substrate |
rlc_decoupled | rlc_coupled |rlc_decoupled_to_substrate |
rlck_decoupled | rlck_coupled | rlck_decoupled_to_substrate ]
Reference Node
Specify the reference node (net) that Quantus will use for decoupling capacitors during a run. Typically VSS or a ground net is
specified. If you specify avS* or avC* in the Reference Node field, you must select Layout Names from the Name Space dropdown list.
If a reference net is not specified in the command file with the ?capGround command, then Quantus will use the first net
specified in the ?groundNets (or ?groundNetsFile) command as the reference net, or use the net defined by:
Techgen -cap_ground_layer
Related Command Quantus: capacitance -ground_net
Note: Sometimes, the substrate is not fully covered by all LVS substrate layer shapes
(holes exist in the layer). Under this situation, Quantus uses the last substrate layer (order determined by the ext_layer mapping
order in layer_setup file or p2lvsfile) to fill the hole shape and randomly picks a neighboring substrate shape net ID (connected
or floating) to assign to the added shape.
Note: A hole in the substrate layer means undefined electrical behavior in that area. It is recommended to review the LVS set up
and resolve this.
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Multiplication Factor
The value of each parasitic decoupled capacitor is multiplied by the Mult Factor (an integer or floating point value greater than
zero). This multiplication factor is used to adjust values for decoupled capacitors. Typically, it is used to introduce more
conservative values for simulation. The default Mult Factor is 1 (no additional capacitance added to decoupled caps).
Related Command Quantus: capacitance -decoupling_factor (Default Value: 1)
Extend Checking Distance
For designs having wider wires for routing, and requires larger checking distance for accurate capacitance extraction, EXT14.1
Quantus offers a new capacitance –max_checking_distance extended option to meet this requirement. The default option in the
drop-down list results in the existing Quantus behavior of checking the maximum spacing for capacitance computation, and the
extended option allows even larger checking distance for capacitance extraction.
It is not recommended to use manually added simulation points (such as, manual_simulation_points, or extra_simulation_points)
in the ICT file/qrcTechFile. If manually added simulation points exist in the ICT file/qrcTechFile then it will take precedence over
the Extend Checking Distance option. This feature does not require any new license.
Note: The field is disabled if GUI detects a techfile version earlier than 14.1.
For this feature, use the latest version of the Techgen (EXT14.1 and onwards).
Diffusion Resistance Equation
If the ICT file contains the diffusion resistance equations, then this button is automatically enabled, and Quantus, during run time,
enables the explicit netlisting of S/D contacts and also does not merge them with one another. If the diffusion resistance
equations are missing in the ICT file, then this button is disabled and greyed out.
Uncheck this option to disable the use of TCL equations from the ICT file for diffusion resistance calculation.
Related Command Quantus: extraction_setup -enable_diffusion_resistance_equations false
Inductance Commands
Quantus supports extraction of on-chip interconnect parasitic self and mutual inductance, targeted for use in block or chip level
extraction in mixed-signal, analog, and RF applications. See "Inductance Extraction" for the details of this feature of Quantus.
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Inductance Extraction Dependencies and Limitations
Inductance extraction is supported in Quantus Extraction Modes Full Chip All Nets, Selected Nets Proper, Excluded Nets
Proper, and Excluded Nets (see NET Selection Mode).
Inductance extraction is not supported for SPEF output.
Inductance Extraction automatically merges parallel parasitic resistances produced in the Quantus output even if Merge
Parallel R is not set for the current run (see Merge Parallel R).
Reduce Parasitics is enabled for Inductance extraction (see "Reduce Parasitics" ).
Inductance extraction requires a minR value of at least 0.001 (0.001 is the minR default value--see "Min R" ). If you specify
a minR value less than 0.001 for parasitic inductance extraction, the Quantus engine will issue a warning message during
the run, and substitute a minR value of 0.001, which will be used for the inductance extraction run.
Ladder Networks
Instructs Quantus to output frequency-based ladder networks (see "Wide Band Interconnect Model" ) instead of simple L and K
elements in order to model the frequency dependence of resistance and inductance. This feature is supported in transistor-level
extraction output modes when the output modes are extracted view, Spice and xDSPF. The use of this option will significantly
increase netlist size and extraction time.
Related Command Quantus: inductance -wide_band_model [true | false]
User Region
The User Region command can reduce the extraction time and output of inductance commands which might take considerable
time for the whole design. In this mode, inductances are extracted for any portion of a net that falls within the User Region.
The "..." (Browse) button allows you to navigate the file system and select a file containing the definition of user regions. Refer to
the interaction region of "inductance" for specific information regarding the syntax of the file.
The "View..." button allows you to open the specified user region file in a separate text viewer window.
The "Edit..." button allows you to open the specified user region file in a text editor to make modifications as needed.
The "Select..." button opens a form allowing you to graphically define bounding box regions from within the Layout editor, save
the regions in a file for use as user regions, and interactively edit user region files to modify them as needed. Pressing "Select..."
opens the Select User Region form as shown in below figure.
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The Select User Region form allows you to interactively create user regions in the Layout editor window. If the file specified in
the User Region field does not exist, then the list of defined regions will be empty when the form is opened (see above figure). In
this case, you will need to create regions in the design.
Begin by specifying a region number identifier in the Region Number entry box (see above figure). Each line in the user region
file requires a region number identifier, which is a positive integer. If you are creating a new user region file, you should begin
with the number 1.
Two different non-overlapping regions can have the same Region Number in which case they are treated as equivalent
from mutual inductance standpoint (i.e., K values are extracted between the disjointed regions).
Then specify the layers the region applies to by changing the layer selectors (see above figure). Each region in the file is
specified for a range of layers that the region applies to inclusively. Inductance will be extracted within the region on the layers
specified and all layers in between.
Note: In EXT8.1 the layers are no longer required in the user region file. When no layers are specified for a give region, Quantus
assumes all layers for that region.
The layer selectors are populated by reading the process file. If the procfile is unavailable then layer entry boxes will be
displayed instead of list boxes, and you will need to manually specify the layer names.
Note: The layer selectors do not display the names of the conductor layers that have the gate_forming_layer true keyword
specified in the ICT file. The sub conductor layer names are also not listed.
Then press the "Draw bBox" button on the Select User Region form, and select a region of the design in the Layout editor by
dragging the mouse with the left button held down. When you release the mouse button, the coordinates are displayed in the
bBox entry field (see above figure). The coordinates of the region may also be entered manually by editing the coordinates
directly in the bBox entry field. Manually editing the coordinates of the region causes the display of the region in the Layout editor
to be updated unless the specified coordinates are invalid.
When the region has been created, you must press the "Add" button to add the region to the list of defined regions.
You cannot save the user region file with overlapping regions. Automatic checking for overlap occurs when a user region
file is opened in the Select User Region form, or when you press "Add" or "Update" or "OK". Overlapping regions are
highlighted in the list of defined regions for you to repair.
Selecting a previously defined region from the displayed list of regions, allows you to modify the region as needed. You can
change the coordinates of the region, change the layers that the region applies to, or change the region number. Then press the
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"Update" button to apply any changes made to the region adding it back into the list of defined regions.
You can also delete regions from the list of defined regions by highlighting the region or regions you want to remove and
pressing the "Del" button.
When multiple regions are selected, the details of the first region are displayed in the top half of the form for editing, and
any changes are applied to the first region when "Update" is executed. However, the "Del" command removes all
selected regions.
Press "OK" to save any changes to the user region file specified. If no file was specified to begin with, the File Save form is
opened, with the default file name of userRegion.txt specified in the current working directory.
Press "Cancel" to close the Select User Region form without saving any changes to the user region file.
Related Command Quantus: inductance -interaction_region
Enter Inductance Nets​
This option is only available when either RLC or RLCK type extractions are selected, and enables you to specify a list of nets for
which inductance extraction should occur. Nets specified as Inductance Nets must also be specified for Resistance extraction as
a subgroup of the Selected Nets or All Nets depending on the Quantus extraction mode.
If nets specified as Inductance Nets are not also specified for resistance extraction, Quantus will exit with an error.
Inductance extraction for specified nets is supported in Quantus Extraction Modes Full Chip All Nets, Excluded Nets, Excluded
Nets Proper, and Selected Nets Proper. In the case of the Excluded Nets extraction, nets specified as Inductance Nets must not
be specified as Excluded Nets (i.e., excluded from resistance extraction).
If no Inductance Nets are specified (or no nets file is specified), then inductance is extracted for all nets according to the Quantus
extraction mode (All Nets or Selected Nets). When no Inductance Nets are specified all extracted nets are fractured at the bends
and also in accordance with the Max Fracture Length setting (see Max Fracture Length and Units).
In EXT8.1 the file format of the inductance_nets_file has been enhanced to include an optional fracture length specification (
signal_fracture_length ) for the net. In this case, you may enter one net name (in either the schematic or layout name space)
and a fracture length specified in units of microns or squares in accordance with the Max Fracture option. The net name and
fracture length are separated by a space or tab.
When Inductance Nets are specified, the nets are fractured as follows, based on the specification of the signal_fracture_length
:
<net> : Net only specified without fracture length, the net is fractured at the bends and then in accordance with the
Max Fracture Length
<net> 0 : Net specified with a fracture length of zero, fractured at the bends and then in accordance with the Max
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Fracture Length
<net> a : Net specified with a value of <a>, the net is fractured at the bends, and then at the minimum of either the
max fracture length or the specified value <a>
Note: The value of <a> must be specified as greater than or equal to 5 microns (or squares). If <a> is less than 5, then
Quantus uses a signal_fracture_length of 5. The exception to this rule is <a> with a value of zero (see above).
Nets may be entered directly, or you may also select nets from the schematic through the SelFromSch button. See How to Input
Net Names for more information.
Net names may be specified with wildcards. For more information refer to the Using Wildcards with Quantus chapter.
Related Command Quantus: extract -inductance_nets_file
Enter Substrate Nets​
Quantus AoT can optionally tie both interconnect and devices to the substrate. Enter Substrate Nets is used to specify which
nets should be capacitively coupled to the substrate network. Any net where resistance is extracted can be entered as a
Substrate Net.
Unlike Inductance Nets, the Substrate Nets must be explicitly defined, or no nets will be extracted as connected to the
substrate.
Related Command Quantus: extract -substrate_nets_file
NET Selection Mode​
You will need to specify the scope of the extraction to be performed by Quantus. What nets in the design do you want to include
or exclude from the extraction. Which nets would you like to use the Field Solver on? To specify nets for extraction (or exclusion
from extraction) you will use the Net Selection Mode cyclic menu. To specify the scope of the Field Solver extraction you will use
the FS Net Selection Mode cyclic menu.
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There are permitted combinations of the Net Selection Mode with the FS Net Selection Mode. For more information on these
permitted combinations, and their effect on extraction, refer to Quantus and Quantus Field Solver Extraction Combinations.
The following section describes the choices for specifying the Net Selection Mode, together with the extraction results of each
selection. The described results assume that you have selected both capacitance and resistance extraction on the Quantus Run
form and that no filtering or reduction of the R or C output has been selected on the GUI forms (MinR, MinC, and such).
Note: Capacitance extraction on nets specified under each choice follows the capacitance extraction mode setting--that is,
Coupled, Decoupled, or Decoupled To Substrate capacitance extraction on the specified nets as explained in Cap Coupling
Mode. Also notice that Quantus does not extract parasitic resistance on global (power and ground) nets (see Import Globals ).
Related Commands Quantus: extract -selection [ all | def_special_nets |
def_regular_nets | def_mustjoin_nets |
net <regexpr> | nets_file <filename> |
selected_path_file <filename> ]
Full Chip All Nets
Scope of R extraction: All nets except global nets are selected for R extraction.
Scope of C Extraction: All nets are selected for C extraction (netlisted caps are either all coupled or all decoupled
according to the capacitance extract mode).
Scope of Inductance Extraction: All nets are selected for L and/or K extraction. However, if Inductance Nets are
specified, then only named nets will have inductance extracted.
Scope of Substrate Nets Extraction:Nets specified with the Substrate Nets File command will be capacitively coupled
directly to the substrate parasitic network. If no Substrate Nets File are specified, then no nets will be capacitively coupled
directly to the substrate parasitic network. Only nets specified for Resistance and Capacitance extraction can be specified
as Substrate nets.
Quantus Output: All designed devices and components plus extracted parasitics.
Typical Use: For full-chip timing and SPICE analysis.
Coupled Example −
Assume a layout design that contains the following top-level global and primary I/O nets: vdd! vss! gnd! vinput iref1 in1 in2
plus numerous internal cell nets. The following is a portion of a SPICE netlist for an Quantus Coupled cap extraction of the cell
(vdd! was specified in the GUI Power Nets field, vss! and vdd! were specified as Ground Nets).
This partial listing is a small sample of the extracted coupling caps produced on the global and I/O nets (coupling caps are also
produced on each internal cell net).
.GLOBAL vdd! vss! gnd!
.SUBCKT test_cell vinput iref1 in1 in2
* CAPACITOR CARDS
C4 gnd! vss! cmodel 3.421E-14
C127 in2#3 in1#3 cmodel 5.018E-16
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C239 gnd! in2#3 cmodel 1.470E-15
C341 vdd! vinput#6 cmodel 8.843E-16
C538 vinput#4 iref1#10 cmodel 1.548E-17
Global nets in the above sample are not fractured into RC nodes (signified by a # symbol followed by a node number) since
Quantus does not extract resistance on the declared global nets (vdd!, vss! and gnd!).
Decoupled Example
The following is a portion of the SPICE output when Decoupled full-chip all nets extraction is performed (the decoupled
capacitance reference net is vss!). Again, only a small number of the extracted caps on global and primary I/O nets are included
in the sample (decoupled caps on internal cell nets are not shown).
.GLOBAL vdd! vss! gnd!
.SUBCKT test_cell vinput iref1 in1 in2
* CAPACITOR CARDS
C3 gnd! vss! cmodel 6.419E-14
C7 vdd! vss! cmodel 1.060E-13
C25 in2#4 vss! cmodel 3.989E-15
C26 in1#4 vss! cmodel 4.594E-15
C42 in2#5 vss! cmodel 5.735E-15
C43 in1#5 vss! cmodel 5.775E-15
C44 vinput#5 vss! cmodel 6.117E-14
C45 vinput#6 vss! cmodel 4.457E-14
C65 iref1#10 vss! cmodel 2.119E-15
C66 iref1#8 vss! cmodel 2.836E-15
C67 iref1#3 vss! cmodel 1.985E-15
C68 in1#1 vss! cmodel 4.147E-15
C69 iref1#1 vss! cmodel 2.557E-15
C124 in2#2 vss! cmodel 9.633E-15
Again, the global nets are not fractured (R extraction is not performed on global nets). Decoupled caps on the I/O nets are
distributed across the fractured parasitic RC networks, while nonfractured nets--that is the global nets--receive only one
decoupled cap. The number of caps produced in the output decreases compared to the previous coupled cap extraction since
one decoupled cap replaces multiple coupling caps attached to each node or net in the coupled cap extraction. The example,
below, illustrates this point:
Coupled Cap Extraction results for Node iref#1:
C134 iref1#1 vss! cmodel 1.750E-15
C411 vdd! iref1#1 cmodel 1.482E-16
C433 net34#4 iref1#1 cmodel 1.629E-16
C565 net34#8 iref1#1 cmodel 4.959E-16
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Decoupled Cap Extraction Results for Node iref#1:
C69 iref1#1 vss! cmodel 2.557E-15
Notice that one decoupled cap has replaced the four coupling caps at this node, and that its value equals the lumped value of
the four coupling caps (1.750E-15 + 0.1482E-15 + 0.1629E-15 + 0.4959E-15 = 2.557E-15).
Full Chip Selected Nets
Scope of R extraction: Listed nets only are selected for R extraction.
Scope of C Extraction: Same as full-chip all nets: all nets are selected for C extraction (netlisted caps are either all
coupled or all decoupled according to the capacitance extract mode).
Scope of Inductance Extraction: This mode does not support Inductance extraction.
Scope of Substrate Nets Extraction:This mode does not support Substrate extraction.
Quantus Output: All designed devices and components plus extracted parasitics. Output has fewer Rs than full-chip all
nets since R extraction is on selected nets only. Output also has fewer Cs than full-chip all nets since nonselected nets are
not fractured into separate RC nodes (fewer RC networks, hence fewer caps produced on nonselected nets.)
Typical Use: RC nodal analysis of specified selected nets with capacitance-only extraction on all other nets for faster
timing and SPICE simulation.
Coupled Example
This example is a sampling of the Quantus extraction results on the top-level global and I/O nets of a cell (vdd! vss! gnd!
vinput iref1 in1 in2). In this case, Full-Chip Selected Nets and Coupled cap extraction are specified on the Quantus run form,
and in1 and in2 are specified as the selected nets.
The resistor cards in the SPICE netlist show that parasitic resistors are extracted only on selected nets in1 and in2.
* PARASITIC RESISTOR AND CAP/DIODE CARDS
Rp_1 in1#3 in1#4 79.6425 $poly1
Rp_2 in1#4 in1#5 102.0000 $poly1
Rp_3 in2#3 in2#4 66.8925 $poly1
Rp_4 in2#4 in2#5 102.0000 $poly1
Rm1_1 in1#3 in1#1 4.7496 $metal1
Rm1_2 in2#3 in2#1 2.1435 $metal1
Rm2_1 in1#1 in1#2 0.4980 $metal2
Rm2_2 in1#2 in1 1.750E-02 $metal2
Rm2_3 in2#1 in2#2 0.5308 $metal2
Rm2_4 in2#2 in2 1.750E-02 $metal2
As in a full-chip all nets extraction, coupling caps are extracted for all node to node interactions (again, only a small number of
the extracted caps are shown below), but notice that nonselected nets as well as global nets are not fractured into multiple
smaller nodes. This means fewer nonselected net coupling caps are produced in the output compared to a full-chip all nets
extraction.
.GLOBAL vdd! vss! gnd!
.SUBCKT test_cell vinput iref1 in1 in2
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* CAPACITOR CARDS
C3
gnd! vss! cmodel 3.423E-14 ;nonselected net coupling
C74
in2#3 in1#3 cmodel 5.018E-16 ;selected node coupling
C96
gnd! in2#3 cmodel 1.469E-15 ;nonselected-to-selected node coupling
C33
vdd! vinput cmodel 3.835E-15 ;nonselected net coupling
C39
vinput iref1 cmodel 1.548E-17 ;nonselected net coupling
Decoupled Example
Below is a portion of Quantus extraction results with the same settings as above except Decoupled extraction is chosen. All nets
receive C extraction, but fewer caps are produced in the netlist compared to the previous coupled cap extraction since each
selected net node and each nonselected net has one lumped decoupled cap attached that represents the total capacitance on
the node or net to all other nodes and nets.
.GLOBAL vdd! vss! gnd!
.SUBCKT test_cell vinput iref1 in1 in2
* CAPACITOR CARDS
C3 gnd! vss! cmodel 6.417E-14
C5 vinput vss! cmodel 2.038E-13
C7 vdd! vss! cmodel 1.060E-13
C8 iref1 vss! cmodel 2.852E-14
C9 in1 vss! cmodel 1.123E-14
C10 in2 vss! cmodel 1.067E-15
C26 in2#4 vss! cmodel 3.990E-15
C27 in1#4 vss! cmodel 4.594E-15
C28 in2#5 vss! cmodel 5.735E-15
C29 in1#5 vss! cmodel 5.775E-15
C30 in2#1 vss! cmodel 2.761E-15
C31 in1#1 vss! cmodel 4.147E-15
C32 in2#3 vss! cmodel 5.743E-15
C33 in1#3 vss! cmodel 7.491E-15
C34 in2#2 vss! cmodel 9.634E-15
Again, the global and nonselected nets are not fractured, and decoupled caps on selected nets are distributed across the
parasitic RC networks on these nets.
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Selected Nets Proper
The Selected Nets Proper can only be specified on designs which contain devices, or Quantus will terminate with an
error.
Scope of R extraction: Listed nets only are selected for R extraction.
Scope of C Extraction:Listed nets only are selected for C extraction. Capacitance is extracted on selected nets to both
selected and nonselected nets. In coupled capacitance extraction, coupling caps are produced between selected nets;
coupling capacitance extracted on selected nets to nonselected nets is lumped and decoupled to the specified decoupled
capacitance reference net. In decoupled capacitance extraction, all coupling caps on selected nets are decoupled to the
specified decoupled capacitance reference net.
Note: In Selected Nets Proper mode the unselected nets are grounded for the purpose of extracting capacitance and will
be shown in the extracted view as grounded. However, the output netlist will be correct for simulation purposes.
Scope of Inductance Extraction: Selected nets will have L and K extraction. Mutual inductors between selected nets will
be preserved. Mutual inductors between selected nets and non-selected nets will be discarded. If Inductance Nets are
specified, then only named nets will have inductance extracted.
Scope of Substrate Nets Extraction:Nets specified with the Substrate Nets File command will be capacitively coupled
directly to the substrate parasitic network. If no Substrate Nets File are specified, then no nets will be capacitively coupled
directly to the substrate parasitic network. Only nets specified for Resistance and Capacitance extraction can be specified
as Substrate nets.
Quantus Output: All designed devices and components plus extracted parasitics. The parasitic output has fewer Rs than
full-chip all nets since (as in full-chip selected nets) R extraction is on selected nets only. The parasitic output has fewer
extracted Cs than full-chip all nets and full-chip selected nets since nonselected nets do not receive C extraction
(nonselected nets receive C extraction in both full-chip all nets and full-chip selected nets extractions).
Typical Use: For analysis of critical nets only.
Coupled Example
This example shows the Quantus extraction results on the same cell used in the previous examples. As in the previous full-chip
selected nets example, in1 and in2 are listed as selected nets. In this case, Quantus Selected Nets Proper extraction mode and
Coupled cap extraction are specified on the Quantus run form.
As in the full-chip selected nets example above, the resistor cards in the SPICE netlist show that parasitic resistors are extracted
only on selected nets in1 and in2.
* PARASITIC RESISTOR AND CAP/DIODE CARDS
*
Rp_1 in1#3 in1#4 79.6425 $poly1
Rp_2 in1#4 in1#5 102.0000 $poly1
Rp_3 in2#3 in2#4 66.8925 $poly1
Rp_4 in2#4 in2#5 102.0000 $poly1
Rm1_1 in1#3 in1#1 4.7496 $metal1
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Rm1_2 in2#3 in2#1 2.1435 $metal1
Rm2_1 in1#1 in1#2 0.4980 $metal2
Rm2_2 in1#2 in1 1.750E-02 $metal2
Rm2_3 in2#1 in2#2 0.5308 $metal2
Rm2_4 in2#2 in2 1.750E-02 $metal2
The complete parasitic C output is shown below. Notice that caps are extracted only on selected nets. Further, coupling caps
from a selected net node to another selected net node are produced, but coupling capacitance from a selected net node to all
nonselected nets has been lumped at each node and decoupled to the specified reference net (vss!). The total coupling
capacitance from each selected net node is the sum of the lumped decoupled cap to all nonselected nets plus any coupling caps
from the node to other selected net nodes (for example, total parasitic C at in2#3 is C11 + C12).
C3 in1 vss! cmodel 1.122E-14 ;total coupling to nonselected nets
C4 in2 vss! cmodel 1.067E-15 ;total coupling to nonselected nets
C5 in2#4 vss! cmodel 3.990E-15 ;total coupling to nonselected nets
C6 in1#4 vss! cmodel 4.594E-15 ;total coupling to nonselected nets
C7 in2#5 vss! cmodel 5.735E-15 ;total coupling to nonselected nets
C8 in1#5 vss! cmodel 5.775E-15 ;total coupling to nonselected nets
C9 in2#1 vss! cmodel 2.406E-15 ;total coupling to nonselected nets
C10 in1#1 vss! cmodel 4.171E-15 ;total coupling to nonselected nets
C11 in2#3 vss! cmodel 5.262E-15 ;total coupling to nonselected nets
C12 in2#3 in1#3 cmodel 5.107E-16 ;coupling between selected net nodes
C13 in1#3 vss! cmodel 6.602E-15 ;total coupling to nonselected nets
C14 in2#2 vss! cmodel 9.634E-15 ;total coupling to nonselected nets
C15 in1#3 in2#1 cmodel 3.861E-16 ;coupling between selected net nodes
Decoupled Example
Below is an excerpt of the Quantus extraction results with the same settings as above except Decoupled extraction is chosen.
The complete parasitic C output is shown below. Notice that the decoupled cap at each selected net node represents the total
capacitance at that node to both selected and nonselected nets (for example, C11 at selected net node in2#3, below, is the sum
of the separately produced C11 + C12 caps in the previous example: 5.262E-15 + 5.107E-16 = 5.7727E-15 = 5.773E-15) .
.GLOBAL vdd! vss! gnd!
.SUBCKT test_cell vinput iref1 in1 in2
C3 in1 vss! cmodel 1.122E-14
C4 in2 vss! cmodel 1.067E-15
C5 in2#4 vss! cmodel 3.990E-15
C6 in1#4 vss! cmodel 4.594E-15
C7 in2#5 vss! cmodel 5.735E-15
C8 in1#5 vss! cmodel 5.775E-15
C9 in2#1 vss! cmodel 2.792E-15
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C10 in1#1 vss! cmodel 4.171E-15
C11 in2#3 vss! cmodel 5.773E-15
C12 in1#3 vss! cmodel 7.499E-15
C13 in2#2 vss! cmodel 9.634E-15
Selected Paths
Quantus Selected Paths is not supported for Hierarchical Extraction, and LVS ?blackBoxCell.
Quantus uses the nets listed on the Quantus Parasitic Extraction Run Form together with a net expansion algorithm to define the
selected paths. The net expansion algorithm expands the listed nets through MOSFET diffusion paths until they terminate at a
MOSFET gate, or a Quantus global net (a declared or imported power or ground net).
Scope of R extraction: Paths derived from listed nets are selected for R extraction.
Scope of C Extraction: Paths derived from listed nets are selected for C extraction (see the note below on how Quantus
derives the selected paths). Capacitance is extracted on selected paths to both selected and nonselected nets. In coupled
capacitance extraction, coupling caps are produced between selected paths; coupling capacitance extracted on selected
paths to nonselected nets is lumped and decoupled to the specified decoupled capacitance reference net. In decoupled
capacitance extraction, all coupling caps on selected paths are decoupled to the specified decoupled capacitance
reference net.
Scope of Inductance Extraction: This mode does not support Inductance extraction.
Scope of Substrate Nets Extraction:This mode does not support Substrate extraction.
Quantus Output: Only designed devices and components on the selected paths plus extracted parasitic devices. Note the
partial list of designed devices is different from the complete device output of other Quantus extraction modes. The parasitic
output is netlisted as shown above in the Selected Nets Proper coupled and decoupled extraction examples, respectively.
Typical Use: For analysis of critical nets with designed device and component output limited to devices on the selected
path.
The Techgen -selected_paths_proper Option Affects This Mode. If Techgen was invoked with the selected_paths_proper option, the default net expansion algorithm described above is disabled (the Quantus output
contains devices and extracted parasitics on listed nets without net expansion). See the RCX to EXT Migration Guide for
additional information.
Coupled Example
These examples use the Quantus extraction settings used in the previous selected nets proper example (including vdd!, vss!
and gnd! declared as global nets, and in1 and in2 specified as the selected input nets) except that selected paths is specified as
the Quantus extraction mode. The parasitic R and C output is the same as the selected nets proper output in the previous
examples (R and Coupled cap extraction results shown below):
* RESISTOR AND CAP/DIODE CARDS [in1 and in2 only receive R extraction]
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Rp_1 in1#3 in1#4 79.6425 $poly1
Rp_2 in1#4 in1#5 102.0000 $poly1
Rp_3 in2#3 in2#4 66.8925 $poly1
Rp_4 in2#4 in2#5 102.0000 $poly1
Rm1_1 in1#3 in1#1 4.7496 $metal1
Rm1_2 in2#3 in2#1 2.1435 $metal1
Rm2_1 in1#1 in1#2 0.4980 $metal2
Rm2_2 in1#2 in1 1.750E-02 $metal2
Rm2_3 in2#1 in2#2 0.5308 $metal2
Rm2_4 in2#2 in2 1.750E-02 $metal2
* CAPACITOR CARDS [in1 and in2 only receive C extraction]
C1 in1 vss! cmodel 1.122E-14
C2 in2 vss! cmodel 1.067E-15
C3 in2#4 vss! cmodel 3.990E-15
C4 in1#4 vss! cmodel 4.594E-15
C5 in2#5 vss! cmodel 5.735E-15
C6 in1#5 vss! cmodel 5.775E-15
C7 in2#1 vss! cmodel 2.406E-15
C8 in1#1 vss! cmodel 4.171E-15
C9 in2#3 vss! cmodel 5.262E-15
C10 in2#3 in1#3 cmodel 5.107E-16
C11 in1#3 vss! cmodel 6.602E-15
C12 in2#2 vss! cmodel 9.634E-15
C13 in1#3 in2#1 cmodel 3.861E-16
Note, however, that only MOSFETs on the selected paths (in1 and in2) are included in the SPICE output:
..GLOBAL vdd! vss! gnd!
.SUBCKT test_cell vinput iref1 in1 in2
* TRANSISTOR CARDS
MI47/I8/M0 vdd! in2#5 vdd! vdd! pmos L=2U W=12U
MI47/I6/M0 vdd! in1#5 vdd! vdd! pmos L=2U W=12U
MI47/I8/M1 gnd! in2#4 vss! vss! nmos L=2U W=6U
MI47/I6/M1 gnd! in1#4 vss! vss! nmos L=2U W=6U
Rs and Cs are extracted only on the specified input nets because Quantus did not expand MOSFET diffusion paths--each in1
and in2 MOSFET diffusion path terminated at a declared global net (vdd! and vss!). Typically, this is the goal of a selected paths
extraction--to extract Rs and Cs only on the specified input nets (not to expand the selected input nets), while netlisting only the
designed devices and components on the selected nets (instead of extracting all designed devices and components as occurs in
the other Quantus extraction modes).
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In the following extraction, the preceding Quantus setup settings are used except that no globals (power or ground nets) are
declared on the Quantus Run form. Here is an excerpt from the R extraction results:
[Notice that there is no .GLOBAL card; vdd!, vss! and gnd! are listed as I/Os below]
.SUBCKT test_cell vss! gnd! vinput vdd! iref1 in1 in2
*
* RESISTOR AND CAP/DIODE CARDS
Rp_1 in1#3 in1#4 79.0925 $poly1
Rp_2 in1#4 in1#5 102.0000 $poly1
Rp_3 in2#3 in2#4 66.3425 $poly1
Rp_4 in2#4 in2#5 102.0000 $poly1
Rm1_1 in1#3 in1#1 5.2996 $metal1
Rm1_2 in2#3 in2#1 2.6935 $metal1
Rm1_3 vdd!#3 vdd!#5 0.3299 $metal1 [Rs extracted on vdd!]
Rm1_4 vdd!#5 vdd!#6 0.1435 $metal1
Rm1_5 vdd!#6 vdd!#7 0.2712 $metal1
Rm1_32 vss!#1 vss!#2 0.1253 $metal1 [Rs extracted on vss!]
Rm1_33 vss!#2 vss!#4 0.6466 $metal1
Rm1_34 vss!#4 vss!#5 0.1253 $metal1
Rm2_1 in1#1 in1#2 0.4980 $metal2
Rm2_2 in1#2 in1 1.750E-02 $metal2
Rm2_3 in2#1 in2#2 0.5308 $metal2
Rm2_4 in2#2 in2 1.750E-02 $metal2
Rm2_5 vdd!#1 vdd!#2 1.5252 $metal2
Rm2_6 vdd!#14 vdd! 0.4625 $metal2
Rm2_7 vdd! vdd!#15 1.750E-02 $metal2
Rm2_8 vss!#1 vss!#27 6.538E-02 $metal2
Rm2_9 vss!#27 vss! 1.763E-02 $metal2
The above results show the Quantus has expanded the input nets through MOSFET diffusion paths to include the vdd! and vss!
nets on the selected paths. The following partial sampling of the C extraction results shows that Cs also are extracted on vdd!
and vss! (partial coupled cap extraction results are shown):
C2 vss!#23 in1#1 cmodel 1.498E-16
C3 vdd!#12 vss!#3 cmodel 1.106E-15
C4 in2#5 vss!#3 cmodel 4.404E-15
C6 vss! in1#4 cmodel 1.030E-15
C9 vdd!#1 in2#1 cmodel 4.840E-16
C45 in2#5 vdd!#12 cmodel 6.405E-16
C46 vdd!#14 vss!#3 cmodel 5.878E-15
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As noted above, one way to ensure that Quantus does not expand the selected nets (even if global nets are not declared or
imported through Import Globals on the Quantus Run form) is to use the Techgen -selected_paths_proper option (see the RCX
to EXT Migration Guide).
Excluded Nets
Scope of R extraction: All nets except specified excluded nets are selected for R extraction.
Scope of C Extraction: All nets (including excluded nets) are selected for C extraction (netlisted caps are either all
coupled or all decoupled according to the capacitance extract mode).
Scope of Inductance Extraction: All nets except the specified excluded nets are selected for L and/or K extraction. If
Inductance Nets are specified, then only named nets will have inductance extracted. The Inductance nets specified must
not be excluded from resistance extraction or an error will occur.
Scope of Substrate Nets Extraction:Nets specified with the Substrate Nets File command will be capacitively coupled
directly to the substrate parasitic network. If no Substrate Nets File are specified, then no nets will be capacitively coupled
directly to the substrate parasitic network. The Substrate nets specified must not be excluded from resistance extraction or
an error will occur.
Quantus Output: All designed devices and components plus extracted parasitics.
Typical Use: For convenience when you wish to perform a selected nets extraction (Rs on selected nets and Cs on all
nets) but it is easier to exclude a small number of nets from R extraction using the excluded nets extraction mode rather
than listing a large number of nets for a selected nets extraction.
Use Excluded Nets to Avoid R Extraction: If the layout methodology does not declare global nets, excluded nets can
be used to prevent parasitic resistance extraction on the undeclared global nets. For other strategies to avoid extracting
parasitic Rs on global nets, see Import Globals.
Coupled Example
The examples below show the Quantus extraction results on the same cell used in the previous examples (with vdd!, vss! and
gnd! declared as globals), but with in1 and in2 listed as excluded nets in an excluded nets extraction. The first set of results are
from a Coupled cap extraction. Below is a small sampling of the parasitic R SPICE output. Notice that globals and in1 and in2
are excluded from R extraction, and that coupling caps are produced on all nets, including in1 and in2. Also global nets and
in1, and in2 in the coupled cap listing are not fractured by R extraction:
.GLOBAL vdd! vss! gnd!
.SUBCKT test_cell vinput iref1 in1 in2
PARASITIC RESISTOR AND CAP/DIODE CARDS
*
Rp_17 vinput#1
vinput#2 91.2128 $poly1
Rp_18 vinput#2
vinput#3 105.1746 $poly1
Rm1_1 iref1#3
iref1#5 1.0967 $metal1
Rm1_2 iref1#5
iref1#7 0.1393 $metal1
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Rm1_3 iref1#7
iref1#1 0.2259 $metal1
* CAPACITOR CARDS
C5 gnd! vss! cmodel 3.421E-14
C11 vdd! vss! cmodel 7.583E-14
C14 in1 vss! cmodel 2.928E-14 ; in1 coupling cap
C15 in2 vss! cmodel 2.341E-14 ; in2 coupling cap
C16 gnd! vdd! cmodel 2.081E-15 ;
C20 gnd! in1 cmodel 8.089E-16 ; in1 coupling cap
C21 gnd! in2 cmodel 1.781E-15 ; in2 coupling cap
C31 vdd! in1 cmodel 1.133E-15 ;in1 coupling cap
C41 vdd! in2 cmodel 1.223E-15 ;in2 coupling cap
C60 in2 in1 cmodel 8.791E-16 ; in1 to in2 coupling cap
C85 vinput#5 vss! cmodel 5.398E-14
C86 vinput#6 vss! cmodel 3.897E-14
C88 vinput#4 vss! cmodel 4.076E-14
C94 iref2#6 vss! cmodel 1.533E-15
C95 iref2#5 vss! cmodel 1.320E-15
C96 iref2#4 vss! cmodel 1.640E-15
C106 vinput#7 vss! cmodel 1.454E-15
C113 iref1#10 vss! cmodel 1.485E-15
C115 iref1#8 vss! cmodel 1.652E-15
C116 iref1#3 vss! cmodel 1.305E-15
C125 gnd! vinput#5 cmodel 5.719E-16
C277 vinput#3 vss! cmodel 2.642E-14
Decoupled Example
Below is an excerpt of the Quantus extraction results with the same settings as above except Decoupled extraction is chosen. A
sampling of the extracted caps is listed below. Notice that lumped decoupled caps to the reference net (vss!) are extracted on
each net, including in1 and in2:
C3 gnd! vss! cmodel 6.423E-14
C5 vinput vss! cmodel 1.049E-15
C7 vdd! vss! cmodel 1.060E-13
C8 iref1 vss! cmodel 2.216E-15
C9 in1 vss! cmodel 3.321E-14 ; in1 lumped decoupling cap
C10 in2 vss! cmodel 2.903E-14 ; in2 lumped decoupling cap
C40 vinput#5 vss! cmodel 6.117E-14
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C41 vinput#6 vss! cmodel 4.457E-14
C42 vinput#4 vss! cmodel 4.549E-14
C56 vinput#7 vss! cmodel 4.260E-15
C60 iref1#10 vss! cmodel 2.134E-15
C61 iref1#8 vss! cmodel 2.851E-15
C62 iref1#3 vss! cmodel 1.985E-15
C63 iref1#1 vss! cmodel 2.576E-15
C116 vinput#8 vss! cmodel 1.378E-14
C117 iref1#2 vss! cmodel 1.033E-14
C118 iref2#7 vss! cmodel 1.194E-15
C119 iref2#3 vss! cmodel 1.520E-15
C135 iref1#11 vss! cmodel 1.752E-15
Excluded Nets Proper
Scope of R extraction: All nets except specified excluded nets are selected for R extraction.
Scope of C Extraction: All nets except specified excluded nets are selected for C extraction.
Scope of Inductance Extraction: All nets except the specified excluded nets are selected for L and/or K extraction. If
Inductance Nets are specified, then only the named nets will have inductance extracted. The Inductance nets specified
must not be excluded from resistance extraction or an error will occur.
Scope of Substrate Nets Extraction: Nets specified with the Substrate Nets File command will be capacitively coupled
directly to the substrate parasitic network. If no Substrate Nets Fileis specified, then no nets will be capacitively coupled
directly to the substrate parasitic network.
Note: The Substrate nets specified must not be excluded from resistance or capacitance extraction or an error will occur.
Quantus Output: All designed devices and components plus extracted parasitics.
Typical Use: It is easier to exclude a large number of nets from RC extraction using the excluded nets proper mode.
Coupled Example
The examples below show the Quantus extraction results on the same cell used in the previous examples (with vdd!, vss! and
gnd! declared as globals). in1 and in2 are listed as excluded nets in an excluded nets proper extraction. For Coupled cap
extraction a sample RC output is shown below. Notice that globals and in1 and in2 are excluded from R extraction, and that
coupling caps are also excluded for in1 and in2 (whereas these couplings are present in case of excluded nets extraction type):
.GLOBAL vdd! vss! gnd!
.SUBCKT test_cell vinput iref1 in1 in2
PARASITIC RESISTOR AND CAP/DIODE CARDS
*
Rp_17 vinput#1
vinput#2 91.2128 $poly1
Rp_18 vinput#2
vinput#3 105.1746 $poly1
Rm1_1 iref1#3
iref1#5 1.0967 $metal1
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Rm1_2 iref1#5
iref1#7 0.1393 $metal1
Rm1_3 iref1#7
iref1#1 0.2259 $metal1
* CAPACITOR CARDS
C5 gnd! vss! cmodel 3.421E-14
C11 vdd! vss! cmodel 7.583E-14
C16 gnd! vdd! cmodel 2.081E-15 ;
C85 vinput#5 vss! cmodel 5.398E-14
C86 vinput#6 vss! cmodel 3.897E-14
C88 vinput#4 vss! cmodel 4.076E-14
C94 iref2#6 vss! cmodel 1.533E-15
C95 iref2#5 vss! cmodel 1.320E-15
C96 iref2#4 vss! cmodel 1.640E-15
C106 vinput#7 vss! cmodel 1.454E-15
C113 iref1#10 vss! cmodel 1.485E-15
C115 iref1#8 vss! cmodel 1.652E-15
C116 iref1#3 vss! cmodel 1.305E-15
C125 gnd! vinput#5 cmodel 5.719E-16
C277 vinput#3 vss! cmodel 2.642E-14
Decoupled Example
Below is an excerpt of the Quantus extraction results with the same settings as above except Decoupled extraction is chosen. A
sampling of the extracted caps is listed below. Notice that lumped decoupled caps to the reference net (vss!) are extracted on
each non excluded net. That is no decoupled cap for in1 and in2:
C3 gnd! vss! cmodel 6.423E-14
C5 vinput vss! cmodel 1.049E-15
C7 vdd! vss! cmodel 1.060E-13
C8 iref1 vss! cmodel 2.216E-15
C40 vinput#5 vss! cmodel 6.117E-14
C41 vinput#6 vss! cmodel 4.457E-14
C42 vinput#4 vss! cmodel 4.549E-14
C56 vinput#7 vss! cmodel 4.260E-15
C60 iref1#10 vss! cmodel 2.134E-15
C61 iref1#8 vss! cmodel 2.851E-15
C62 iref1#3 vss! cmodel 1.985E-15
C63 iref1#1 vss! cmodel 2.576E-15
C116 vinput#8 vss! cmodel 1.378E-14
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C117 iref1#2 vss! cmodel 1.033E-14
C118 iref2#7 vss! cmodel 1.194E-15
C119 iref2#3 vss! cmodel 1.520E-15
C135 iref1#11 vss! cmodel 1.752E-15
How to Input Net Names​
Net names may be specified with wildcards. For more information refer to the Using Wildcards with Quantus chapter.
If the Quantus Full Chip Selected Nets, Selected Nets Proper, Selected Paths, Excluded Nets Proper, or Excluded Nets net
selection mode is chosen, the extraction mode panel provides space to specify the Quantus Nets or Fixed Nets either directly in
a text entry box, by entering a filename with a list of nets, or selecting nets from the schematic or from the layout. The following
describes these four approaches to input net names:
List the selected/excluded net names in the nets box. Multiple net names should be listed one on each line. For
example, to enter Net1 and Net2 in the list box, enter Net1 then Net2 on the second line without any surrounding quotes or
parentheses and without any intervening commas (see the illustration below).
Select a predefined nets file. Click From File to specify the name of a file that contains a list of the selected/excluded nets.
Nets should be listed one net name per line in the file.
Selecting nets from the schematic (or layout). Click the SelFromSch or SelFromLay button to open a new window
displaying the top-level of the schematic hierarchy and begin selecting nets from the schematic. SelFromSch is available in
any Quantus extraction modes which take a list of nets as input.
Note: SelFromLay works in a similar fashion to the SelFromSch command.
Select Nets from Schematic
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Note: When you execute the SelFromSch command, the name space is automatically changed to Schematic Names (see Name
Space ).
As you select nets on the schematic, the list of nets is updated in Quantus Run form. To remove a net that has been selected
from the list of nets, simply select it a second time in the schematic window. The list of nets may also be hand edited to add or
remove any nets after the schematic window has been closed.
You can descend into the hierarchy of the schematic and select nets from within blocks of the design. If a schematic window is
already open, then that schematic window is used for net selection. However, if the schematic is not opened to the cell name of
the design specified in the Quantus run, the open schematic is replaced by the correct schematic.
The Pegasus-Quantus flow allows you to select the nets from the schematic or layout. However, for the layout selection to work,
the Pegasus run must contain an ECDB file (<topcell_name>.ecdb). Quantus searches for this file in the Pegasus run directory
and displays an error message if the ECDB file does not exist.
The QCI flow has also been enhanced to enable you to select the nets from the schematic. However, in the QCI flow, the
SelFromLay button is disabled.
Note: In earlier releases, this selection was available only for the Assura-Quantus flow.
Quantus Field Solver Capacitance Extraction
Field Solver uses a high-accuracy 3-D field solver to extract parasitic capacitance directly from the design data rather than
through the capacitance coefficient models created by Techgen. The results of the Field Solver capacitance extraction are
merged with the results of the standard Quantus flow to produce the Quantus extraction output (see Quantus and Quantus Field
Solver Extraction Combinations).
Parasitic caps extracted by Field Solver replace corresponding caps extracted by Quantus. Field Solver parasitic capacitance
extraction is more accurate, but slower than standard Quantus capacitance extraction. It is suitable for use on moderate size
blocks or specific nets in a large chip. Field Solver handles conformal dielectrics, air gaps, non-rectangular geometries, and
multiple substrate layers.
Note: Here, Field Solver implies Deterministic and Probabilistic field solver solutions. For more information on Field Solver
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extraction, refer to Quantus Capacitance Extraction Field Solver.
Quantus does not extract poly to diffusion capacitance, but Field Solver does. Therefore, to compare Quantus and Field
Solver results, you must specify Techgen -p to block this capacitance in the Field Solver in order to establish consistency
of results between the two tools. This is also true in the case of via capacitance (see "Exclude Via Capacitance" for more
information),
Quantus Field Solver Section
The Field Solver extraction options are displayed in the Field Solver section. This section is disabled if the Extraction Type is set
as R Only or None.
Field Solver
Enable Field Solver
The Enable Field Solver check box specifies to enable/disable Field Solver extraction.
Field Solver Type
Allows to select the type of field solver cap extraction. This field has the following options: Quantus FS and QRCFS.
For 28nm and above process nodes, you can set the field solver to Probabilistic FS by selecting the Quantus FS option, or set
the field solver to Deterministic FS by selecting the QRCFS option. However, for 20nm and below designs, the QRCFS option is
always grayed out. That is, you cannot set the field solver to Deterministic FS because this mode does not support 20nm and
below designs.
When launching Quantus FS jobs on a single (LSF) machine, use the distributed_processing -multi_cpu CCL option
for the single machine in order to achieve maximum parallelism.
Related Command -
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Quantus: extract -field_solver_type [deterministic | probabilistic]
FS Net Selection Mode
pecifies which nets in the design will use Field Solver processing for the extraction of parasitic capacitance. The Field Solver
extraction choices are listed below.
pecifies which nets in the design will use Field Solver processing for the extraction of parasitic capacitance. The Field Solver
extraction choices are listed below.
The choices available to you in the FS Net Selection Mode menu may be limited by the Quantus Net Selection Mode you
have previously selected. The following table gives a mapping between the Quantus net selection modes and the
corresponding Field Solver net selection modes:
Quantus Net
Selection Mode
Field Solver Net
Selection Mode
Full Chip All
Nets
Full Chip All Nets
Full Chip
Selected Nets
Excluded Nets
Selected Nets
Excluded Nets
Excluded Nets
Proper
Selected Nets
Proper
Selected Paths
Selected Paths
See "Quantus and Quantus Field Solver Extraction Combinations" for legal combinations of these commands.
Full Chip All Nets
Field Solver capacitance extraction on all nets except global nets will override standard Quantus capacitance extraction.
Full Chip All Nets is valid with standard Quantus modes Full Chips All Nets, Full Chips Selected Nets, and Excluded Nets.
Selected Nets
Field Solver capacitance extraction on selected nets, standard Quantus capacitance extraction on all remaining nets.
Selected Nets is valid with standard Quantus modes Full Chips All Nets, Full Chips Selected Nets, and Excluded Nets.
When using Selected Nets you will need to provide a list of nets for Field Solver extraction. See How to Input Net Names for
instructions on entering nets. The listed nets are written into a file named rcx.RCXFS.nets in the Quantus working directory,
this file is referenced in the ?rcxfsNetsFile command. There is only a single rcx.RCXFS.nets file in the working directory,
and it is overwritten for each new run of Quantus.
Selected Paths
Field Solver capacitance extraction on selected paths. Selected Paths is only valid in combination with standard Quantus
Selected Paths extraction. The selected nets list for both Quantus (?netsFile) and Field Solver (?rcxfsNetsFile) must be
identical.
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If the Quantus and Field Solver list of nets are not the same, Quantus will extract caps on the Quantus selected nets and no
Field Solver caps will be extracted. Use the same nets file for both ?netsFile and ?rcxfsNetsFile to prevent this problem.
Excluded Nets
Performs Field Solver capacitance extraction on all nets except those specified as excluded nets or those specified as
global nets as defined by the Ground Nets, Power Nets, or Import Globals commands. See Power Nets, Ground Nets, or
"Import Globals" for more information defining global nets.
Excluded Nets is valid for use with standard Quantus Full Chips All Nets, Full Chips Selected Nets, and Excluded Nets.
Unlike Field Solver Selected Nets, in which nets that are not specified will have capacitance extracted by Quantus pattern
matching instead of Field Solver, Excluded Nets only performs Field Solver extraction on the unspecified nets, and nets
specified as "excluded nets" or global nets will not have capacitance extracted.
Excluded nets, and global nets, may still have parasitic capacitance extracted as a result of coupling capacitance
from nearby nets, in either Coupled or Decoupled cap extract mode.
Note: Here, Field Solver implies Deterministic and Probabilistic field solver solutions.
Related Commands Quantus: extract -selection \
-use_field_solver [ default_accuracy | high_accuracy ]
Related Commands Quantus: extract -use_field_solver [ default_accuracy | high_accuracy ]\
-extract_via_cap
Field Solver Accuracy
Determines the use of the Quantus 3D capacitance field solver. This field has the following options: High and Default. If set
to High, indicates that the field solver should be run with the highest available accuracy that consumes additional processor
time. The Default setting provides sufficient accuracy in most cases and reduces extraction run time.
Related Command Quantus: extract -use_field_solver [ default_accuracy | high_accuracy ]
FS DP Configuration File
Specifies the path to the configuration file of Field Solver distributed processing. This field enables the Quantus FS
massively parallel feature. It can be used for large designs to run all nets or a large selection of nets with maximum
accuracy. The field allows you to use 100’s of CPUs for Quantus FS.
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The specified field solver config filename can have the following commands:
local -processes <value> -threads <value>
network -processes <value> -threads <value> -command_line "rsh machine_name“
lsf -processes <value> -threads <value> -command_line "bsub command with LSF resource string”
Multiple commands of each type and combination of commands are allowed. The recommended number of threads per
process is 32 because this results in the lowest memory consumption. If 32 CPUs are not available, then you can modify the
file depending on the number of available CPUs. To use more than 32 CPUs on a single machine, it is recommended to
increase the number of processes to get optimal scaling. If the -processes option is not specified in the config file, then by
default its value is assumed to be 1. The FS DP Configuration File field is enabled only if Quantus FS is selected from the
Field Solver Type drop-down list.
For more information on the FS DP Configuration File field, refer to the description of distributed_processing field_solver_config in the Quantus Command Files chapter.
Related Command Quantus: distributed_processing -field_solver_config <filename>
Custom Convergence
This section can be used for defining finer accuracy specification (convergence):
Total Cap Convergence - refers to the total capacitance accuracy.
Coupling Cap Convergence - refers to the coupling capacitance accuracy.
Total Cap Convergence Thresold - specifies the explicit absolute threshold for total capacitance.
Coupling Cap Convergence - specifies the explicit absolute threshold for coupling capacitance.
The Custom Convergence section is enabled only if Quantus FS is selected from the Field Solver Type drop-down list. For
more information on convergence setting, refer to Quantus Capacitance Extraction Field Solver.
Related Commands Quantus: extract -total_cap_convergence <value> \
-coupling_cap_convergence <value>\
-total_cap_threshold <value>\
-coupling_cap_threshold <value>
Change Wire Direction
Select the Change LithoBias Direction button to enable Quantus to apply horizontal direction bias on the vertical edges and
vice versa.
Change LithoBias Direction
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Note: This field is enabled only if the qrcTechFile has been built using the lithoBias file during Techgen simulation. In
addition, this field is enabled only for Dspf, Spef, Transistor Dspf Transistor Spef, Spice, and Extracted View output formats.
Related Command Quantus: extraction_setup -change_lithobias_direction [true | false]
Note: This feature is related to advanced process modeling and requires Advanced Modeling 20nm license. For more
details on licensing, refer to the Preface chapter of this manual.
For Litho Bias flow details, refer to the "Litho Bias Flow" chapter of Quantus Techgen Reference Manual .
Litho Config File
Specify the name of the LEA configuration file in this field.
Contour Directory
Specify the directory path/name of the delta D database location in this field.
Gate Resistance Factor
This section includes the following three fields:
Default Factor - Apply the specified factor when calculating the gate resistance. This field is mutually-exclusive to the
Enable Delta Gate Ckt checkbox. The specified value should be greater than or equal to 0.1.
Related Command - Quantus: extraction_setup -res_gate_default_factor <value>
Device Layer Names - Change the factor applied by Quantus when calculating the gate resistance for the specified
devices. This field is mutually-exclusive to the Enable Delta Gate Ckt checkbox. The Device Layer Names button
opens the Gate Resistance Factor form, as shown below:
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You can then use Add, Edit, or Delete commands to define or change layers and their values.
Click Add to add the device recognition layers for the specific transistor devices. Layer names must come from the LVS
rule deck (lvsfile).
Click Edit to edit the layers listed in the Gate Resistance Factor form.
Click Delete to delete a particular layer and Delete All to remove all the layers from the list.
Once you have added the required LVS layers, click OK. The selected layers will be considered for gate resistance
factor calculation.
Related Command - Quantus: extraction_setup -res_gate_factor “<value1> <devLayer1>” “<value2>
<devLayer2>” …
No Double Gate Conn - This field affects the way in which the Default Factor (res_gate_default_factor) field is
applied by Quantus. When you expressly define the Default Factor or Device Layer Names field, Quantus will handle
double connected gates differently from single connected gates. To change the Default Factor while still treating all
devices as single connected gates or to disable the Enable Delta Gate Ckt checkbox at Quantus run time, you must
select the No Double Gate Conn checkbox. This field is grayed out when the Enable Delta Gate Ckt checkbox is
selected.
Related Command - Quantus: extraction_setup -double_gate_conn [true | false]
Delta Gate Ckt
This section includes the following three fields:
Enable Delta Gate Ckt - Specifies to produce an equivalent circuit to model gate resistance. The equivalent circuit is
the same for either a single connected gate or a double connected gate, and the equivalent gate resistance will be
adjusted automatically based on the interconnect connection outside the gate. This field is mutually exclusive with all
the fields in the Gate Resistance Factor section, and with Device Names.
Related Command - Quantus: extraction_setup -delta_gate_ckt [true | false]
Device Names - This option specifies a list of MOS/LDD devices as taken from the LVS rule file. It allows the -
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delta_gate_ckt option to be applied to a subset of these devices. This field is mutually exclusive with all the fields in
the Gate Resistance Factor section, and with Enable Delta Gate Ckt. The Device Names button opens the Delta Gate
Ckt by Device form, as shown below:
You can then use Add, Edit, or Delete commands to define or change devices to be considered.
Click Add to add the MOS/LDD devices to be considered for the -delta_gate_ckt option.
Click Edit to edit the devices listed in the Delta Gate Ckt by Device form.
Click Delete to delete a particular layer and Delete All to remove all the devices from the list.
Once you have added the required devices, click OK. The selected devices will be applied by the delta_gate_ckt_by_device CCL option.
Related Command - Quantus: extraction_setup -delta_gate_ckt_by_device “<devLayer1>” “<devLayer2>” …
​
Gate Names - This option allows the -delta_gate_ckt CCL option to be applied to a subset of devices. This field is
similar to the Device Names field, except that the Gate Names field will also automatically set Techgen -genericMos
commands for the device layers of the devices that have the specified gate layers.
This field is mutually exclusive with all the fields in the Gate Resistance Factor section. The Gate Names button opens
the Delta Gate Ckt by Gate form, as shown below:
You can then use Add, Edit, or Delete commands to define or change devices to be considered.
Click Add to add the devices to be considered for the -delta_gate_ckt option.
Click Edit to edit the devices listed in the Delta Gate Ckt by Gate form.
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Click Delete to delete a particular layer and Delete All to remove all the devices from the list.
Once you have added the required devices, click OK. The selected devices will be applied by the delta_gate_ckt_by_gate CCL option.
Related Command - Quantus: extraction_setup -delta_gate_ckt_by_gate “<gate1>” “<gate2>” …
Hierarchical Extraction
Quantus AoT does not support Hierarchical Extraction and the command will be disabled if Substrate Extraction is
turned on.
Select the Enable HRCX button to turn on hierarchical extraction.
Hierarchical Extraction cannot be used with the following Quantus Net Selection Mode: Selected Nets, Selected Nets
Proper, or Selected Paths. In this case, when you enable Hierarchical Extraction, the Quantus Net Selection Mode is reset
to Full Chip All Nets.
Hierarchical extraction requires a list of hierarchical cells that can be manually entered into the text entry box, or can be
specified in a file entry field (?hrcxCellsFile). If the cells are entered manually, an rcx.HRCX.cells file is written to the
current directory, or the run directory.
Note: There is only a single rcx.HRCX.cells file in the working directory, and it is overwritten for each new run of Quantus.
Hierarchical extraction requires that each specified cell is fully contained with its own reference to power and ground to
insure correct results. Hierarchical extraction also requires all layers that form a cell to be found on the same level of the
design hierarchy. An error condition occurs if layers forming a device exist in different levels of hierarchy.
Related Command Quantus: hierarchical_extract -hierarchical_cell_list_file
Split Pins
A net in a cell might make connection at several places with the parent or neighbor. The Split Pins command enables
hierarchical extraction to identify these connection points and label them as unique pins in cases where there is at least a
minimum distance between them (the Split Pin Distance).
The Split Pins command can also be enabled when the selected output is the transistor-level DSPF flow (XDSPF).
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By default for XDSPF output, Quantus randomly picks one pin from a group of pins on the same net (multiple pins within the
same polygon) and discards the rest. The use Split Pins will cause Quantus to preserve all pins with different names (nonshorting) labeling them as unique pins. Note: Split Pin Distance does not apply in this case.
Related Command Quantus: hierarchical_extract -split_feedthrough_pins [true | false]
Split Pin Distance
The Split Pin Distance value specifies the minimum separation between pins before Quantus will split them according to the
Split Pins command. The default value is 5 microns.
Related Command Quantus: hierarchical_extract -split_feedthrough_pins_distance (Default Value: 5 microns)
Macro Cells Type
This option specifies whether the net parasitics (resistances and capacitances) between the top-level nets and the nets
within the macro cells should be considered during RC extraction. The possible values are:
default - specifies that the macro cells are treated as black boxes, and the net parasitics between the top-level nets
and the nets within the blocked cells will not be considered during RC extraction. For Macro Cells Type “default”, the
Delete Layers button is disabled.
white - specifies that the parasitic resistance network penetrates into the macro cells. The white mode macro cell
extraction is not supported for the Pegasus and Calibre LVS inputs. The Delete Layers button is enabled only when
Macro Cells Type is set to white.
​You can click the Delete Layers button to specify the LVS layer names that need not be promoted to the top cell in the
white mode macro cell RC extraction. The Delete Layers form appears as follows:
You can use this form to manage the list of deleted layers. For more information on macro_cells_type and
delete_layers options, refer to Quantus Command Files.
Use the Delete Layers File field to specify a user-defined file that contains the LVS layer names that are not to be
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promoted to the top cell in the white mode macro cell RC extraction. You can select the Delete Layers File checkbox,
and click the browse button to browse and select a user-defined delete layers file. If the checkbox is not selected,
Quantus will use the deleteLayers.defs file from the technology directory.
This field is enabled only when Macro Cell Type "white" is selected.
Related Commands Quantus: extraction_setup -macro_cells_type [ default | white ]
Quantus: extraction_setup -delete_layers <lvs_layer1> <lvs_layer2> …
Enter Cells for Parasitic Blocking
This command is used to block parasitic resistance and capacitance extraction for specific macrocells in the design. Use this
command to specify cells that already include parasitic RC values in their device models to avoid double counting.
Similar to specifying the ?hrcxCellsFile with the "+ netlist=lvsNetlist" control statements, the cell is included in the
netlist without parasitic effect. However, in this case, the cell will be flattened in the output netlist.
Cell names may be specified with wildcards. For more information refer to the Using Wildcards with Quantus chapter.
Note: This command is not supported when the Output is specified on the Setup Tab as DSPF or SPEF. Do not specify a
Parasitic Cell Blocking file in this case, or an error will occur during extraction.
Related Command Quantus: extraction_setup -parasitic_blocking_device_cells_file
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Filtering Tab
Quantus Run Form Filtering Tab
The Filtering tab enables the reduction of extracted parasitics based on a variety of command options discussed below.
These options allow filtering of parasitic resistors and capacitors based on minimum values, based on eliminating nonessential nets, based on specific operating frequencies, and based on merging parallel circuit structures.
The order of execution of the reduction options is:
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M Factor Reduction
Exclude Floating Nets
Min R
Merge Parallel R
Dangling R
Exclude Self Capacitance
Min C and Min C By Percentage
Reduce Parasitics
​
Reduce Parasitics
Reduce Parasitics offers a method to reduce the number of parasitic resistors and capacitors extracted from the layout in a
net-by-net fashion. This command supports R-only, RC, RLC, and RLCK type extraction. It does not support C-only
extraction. The Reduce Parasitics drop-down list has the following options: true and false.
Consider a net that is a resistor network connecting device terminals and primary I/O ports. There are also internal
nodes that do not connect to either the I/O port or the device terminals. If you select true from the drop-down list,
Quantus reduces the RC network on each net by attempting to eliminate internal nodes that are not connected to any
of the devices in the device files, or I/O nets. The capacitance is decoupled to the specified Ref Node (see "Reference
Node" ). Reduce Parasitics automatically runs with ?minR set at the default value of 0.001 (unless you specify a
different value) and also with ?mergeParallelR.
The false option specifies to disable mathematical RC reduction. The default is false.
The use of Reduce Parasitics is incompatible with the use of Parasitic Resistance Temperature Coefficient .
Although the GUI currently allows these two switches to be enabled at the same time, this will result in Quantus
aborting with an error.
Nets can be excluded from this reduction process by specifying nets with the Exclude Reduce Parasitics Nets option (see
Exclude Reduce Parasitics Nets).
Related Command Quantus: parasitic_reduction -enable_reduction [ true | false]
Reduction Selection File
Specifies the name of the selection file that can be used to set the reduction parameters. The Reduction Selection File field
is enabled only when the Reduce Parasitics option is set to true.
The format of the reduction selection file is a list of pairs:
-<option name> <value>
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Here, you can:
Click .... button and browse to the location that contains the file.
Click the View button to view an already existing reduction selection file that is specified in the Reduction Selection
File field.
Click the Edit button to create a new reduction selection file or modify an existing file. You can create a new file by
typing a file name directly in the Reduction Selection File field, and then clicking Edit.
To create a reduction selection file:
1. Specify the name of the selection file in the text box, and click the Edit button.
The following dialog box appears.
2. Click Yes to create a new selection file. ​
The Quantus Reduction Selection File form appears:
1. Click + to add a new netlist.
Note: You can click – to remove an existing netlist from the table, and click '^' and 'v' to change the order of netlists in
the table.
The Reduction Selection File Net Group Settings form appears.
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2. Type the list of nets, and select whether to include or exclude the nets in/from reduction by choosing the Reduce or
Exclude options from the Nets to drop-down list.
You can select all nets by giving the asterisk symbol (*) in the text field.
3. Type the list of layers, and select whether to include or exclude the layers in/from reduction by choosing the Reduce or
Exclude options from the Layers to drop-down list.
You can select all layers by giving the asterisk symbol (*) in the text field.
When some layers are selected to be excluded from reduction, the resulting file will have the following two
options:
-reduce_layers *
-exclude_layers <list of layers to exclude from reductionreduction>
4. Select the Enable checkbox to enable the Delay and Frequency Options section, and specify values for the following
license-dependent options:
Delay Error Relative
Delay Error Absolute
Reduction Frequency
5. (Optional) Enter the required value in the Reduction Control field.
Reduction Control enables you to control the reduction of interconnect parasitic devices extracted from the layout
versus accuracy in the Quantus transistor-level flow. This command supports R-only, RC, RLC, and RLCK type
extraction. It does not support C-only extraction. You can enter any positive floating point number in the range from 0
up to 1. A value of 0 will result in a reduced netlist with an accuracy close to the unreduced netlist accuracy. A value of
1 will be most aggressive, and may introduce >10% accuracy error.
6. (Optional) Select the Reduce Negative Resistor checkbox to reduce the negative resistors. By default, the checkbox is
cleared.
7. Click OK to confirm the changes made in the Reduction Selection File Net Group Settings form.
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The corresponding line will appear in the Quantus Reduction Selection File form:
The lines in the table have shortened abbreviated form.
8. Click OK to confirm the netlist settings and save the reduction selection file.
To modify an existing reduction selection file:
1. Click .... button next to the Reduction Selection File field, and browse to the location that contains the file.
2. Select the file, and click OK.
The file path appears in the Reduction Selection File field. You can click View to view the selection text file, as shown
below:
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3. Click the Edit button next to the Reduction Selection File field. The Quantus Reduction Selection File form appears.
4. Double click on an existing row to edit the reduction settings. The Reduction Selection File Net Group Settings form
appears.
5. Modify the required fields, and click OK to return to the Quantus Reduction Selection File form.
6. Click OK to confirm the netlist settings and save the reduction selection file.
Related Command Quantus: parasitic_reduction -selection_file <filename>
Merge Parallel R​
If enabled, this command specifies that parallel parasitic resistors should be merged in simple parallel fashion before
netlisting.
For the merged parasitic resistors, the L/W parameters are merged as follows:
L - is the length taken from one of the merged resistors (L1 | L2)
W - is the sum of the widths of the merged resistors (W1+W2)
The resulting merged parasitic resistor value is calculated according to Ohms law.
Related Command Quantus: filter_res -merge_parallel_res [true | false]
Dangling R
Quantus attempts to minimize the number of extracted Rs and Cs and will ignore metal that is not connected to anything and
has no current flow. Quantus automatically recognizes floating metal shapes and single layer dangling interconnect (a metal
line that has one end dangling), and will not extract parasitic resistance on these shapes.
However, Quantus will extract resistance for more complex dangling interconnect crossing multiple layers, thereby creating
one or more dangling parasitic resistors on the interconnect. A dangling resistor is defined as one that has a terminal which
does not connect to an I/O pin, a device terminal, or another parasitic resistor.
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The use of Techgen -danglingR_proper extends the definition of a dangling resistor to mean a parasitic resistor that
has a terminal which does not connect to an I/O pin, a device terminal, another parasitic resistor, or a parasitic
capacitor.
If Dangling R is enabled, Quantus will short out and remove dangling parasitic resistors. The shorting and removal of
dangling parasitic resistors does not affect parasitic capacitors attached to removed resistors--these parasitic capacitors are
retained in the output. Further, if the removal of a dangling resistor results in the parallel placement of two parasitic
capacitors, the resulting parallel parasitic capacitor pair is merged into one parasitic capacitor (with a value equal to
combined parasitic capacitor pair).
Note: As inductance extraction occurs after RC extraction, the elimination of dangling resistors will also eliminate parasitic
inductors which would be connected to those resistors.
Related Command Quantus: filter_res -remove_dangling_res [true | false]
Merge Parallel Via
Specifies that parallel via resistors should be merged in a simple parallel fashion before netlisting. The resulting merged via
resistor value is calculated according to the Ohms law. This option also affects the behavior of the Merge via by mesh size
option, which will not merge small vias, but will cut the long via to the mesh size. This option can only be used for the one
pair via resistance model. The other via resistance models are not supported.
The Merge Parallel Via check box is automatically enabled if you select the Conservative or V. Conservative options from
the R Mesh Accuracy drop-down list. This option is not enabled for the Liberal or Moderate options, and is optionally
enabled for the Custom option. The Merge Parallel Via option is mutually exclusive with the Merge ParallelR option, and
only has application when used along with the Merge Via by Mesh Size option.
Related Command Quantus: filter_res -merge_parallel_via [true | false]
Exclude Self Capacitance
Self-capacitance is the parasitic capacitance between distributed RC subnodes on the same layout net. To exclude selfcapacitance during Quantus and/or Field Solver cap extraction, click this cyclic field.
The following options are available in the drop-down:
No: Do not exclude self-capacitance.
Yes: Exclude self-capacitance from the extraction output during decoupled parasitic capacitance extraction.
Extended: Remove coupling capacitors between the two LVS nets across resistor devices.
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Note:
Exclude Self Capacitance is active only for RC, RLC, or RLCK extraction if Coupled capacitance extraction is selected
on the Extraction tab. It is disabled for other modes like R-only, C-only, or Decoupled extraction.
Use Reduce Parasitics to reduce parasitic Rs and Cs for Decoupled cap extraction.
Interaction with Min C Setting. If the Exclude Self Capacitance is not enabled, and Min C is specified (see Min C
and Min C By Percentage) Quantus will eliminate rather than decouple self-capacitance on a net if the total parasitic
self-capacitance on the net is equal to or less than the Min C setting.
Related Command Quantus: filter_cap -exclude_self_cap [extended | true | false]
Extended Self Capacitance Recursive
When the Ext. Self Cap Recursive option is checked, all capacitances between the nets connected through resistor devices
(or a series of them) will be treated as self-capacitance. This option is only enabled when the Exclude Self Capacitance
option is set to Extended. When this option is not set, which is the default value, Quantus will remove coupling capacitors
between the two nets/sub-nodes across each resistor device.
Related Command Quantus: filter_cap -extended_self_cap_recursive [true | false]
Exclude Floating Nets
This command removes floating nets from the design. Floating nets are typically introduced by area fill patterns for which
there are no conducting paths to power or ground. Sometimes these are introduced by spare parts not used in the circuit.
Floating nodes are fully isolated from the rest of the circuit except by capacitive coupling.
Related Command Quantus: filter_cap -exclude_floating_nets [true | false]
Exclude Float Limit
This command is used in conjunction with the Exclude Floating Nets command to specify a variable capacity limit that
applies an approximation algorithm to speed reduction. You specify the capacity limit as a non-negative integer where 0 is
the fastest and least accurate (that is, all nets are approximated), but the higher values offer greater accuracy.
Exclude Floating Nets has a default value of 2000 for process nodes at 28nm and above, and a default value of 50,000 for
nodes at 16nm and below.
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A warning is reported when Quantus switches to the approximation algorithm due to reaching the specified limit of ?
excludeFloatLimit.
Related Command Quantus: filter_cap -exclude_floating_nets_limit
Max Fracture Via Count
Specifies how many fractures are created when modelling vertical resistors for vias that have zero thickness and are defined
using the ictfile via{} definition keyword fracture_vias true. If the R network is large, the via fracturing limit by count can
be controlled. The default value is "auto" which means Quantus automatically sets the value to 100. To reduce data volume,
an alternative recommended value of 5 or 10 can be used.
Related Command Quantus: extraction_setup -max_fracture_via_count (Default Value: 100)
Min R
If resistance extraction is checked, you can use MinR to specify the minimum resistance value for parasitic resistors that will
be included in the Quantus output. Any extracted parasitic resistors with values smaller than or equal to the specified value
are discarded (the extracted resistor terminals are shorted together) and are not included in the Quantus output.
MinR is Applied After Max Fracture. Notice that MinR is applied to the discrete resistor segments produced by the max
fracture setting --specifically, any parasitic resistor segments whose resistance is equal to or less than the current MinR
setting will be shorted by Quantus.
The value is specified in Ohms, and can be specified as an integer or floating point value greater than 0. Since Quantus
uses 0.001 Ohm resistors for internal connections this is the default used by Quantus unless a different value is specified.
MinR will not remove resistors which would result in the loss of device ports or named nets even if they are smaller
than the specified value.
If RLC or RLCK type extraction is selected, MinR should be set to a value equal to or greater than 0.001. If you specify a
MinR value less than 0.001 for inductance extraction, Quantus will issue a warning message during the run, and substitute a
value of 0.001, which will be used for the inductance extraction run.
Note: When parasitic inductance is extracted, changing the minR value does not have any effect on the inductance nets in
the Quantus output. In other words, minR values do not apply to the inductance nets. However, other nets for which
inductance is not extracted still have minR reduction.
Related Command Quantus: filter_res -min_res (Default Value: 0.001 ohm)
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MinR for Selected Layers
Specifies the minimum resistance value for the extracted parasitic resistors on a layer basis. The Edit Layers button opens
the MinR for Selected Layers form, as shown below:
Click Add to add the LVS layer for which the MinR value needs to be specified.
Click Edit to edit the layers listed in the MinR for Selected Layers form.
Click Delete to delete a particular layer and Delete All to remove all the layers from the list.
Click Find to search a particular layer from the list of layers added.
A value of “0” disables the minimum resistance filter for that layer. When this option is specified for a specific layer, Quantus
overwrites the minimum resistance value specified by the MinR option, which is the setting for all the LVS layers.
Related Command Quantus: filter_res - min_res_by_layer “<lvs_layer1> <minRval_1>” “<lvs_layer2> <minRval_2>” …
​Min C and Min C By Percentage​
Min C can be used to reduce the number of parasitic capacitors extracted to the output. Min C reduces the number of
coupled capacitors by decoupling nets which have a total coupled capacitance value less than or equal to the specified
value of Min C. Min C By Percentage (fF on the GUI) decouples small coupling capacitors on nets that are not affected by
Min C, to help reduce the number of caps in the output netlist.
Min C has no effect for Decoupled or Decoupled_to_Substrate capacitance extractions.
This setting takes a positive floating point or integer femtoFarad value--for example, to specify a 3 e-15 (femtoFarad) Min C
value, type 3 in the Min C field (the GUI writes ?minC 3e-15 in the command file). If a minC value is specified, Quantus uses
it to limit the production of parasitic capacitance components in the Quantus output on a net-by-net basis. Min C behavior
differs for coupled and decoupled capacitance extraction, as explained in the RCX to EXT Migration Guide.
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Related Commands Quantus: filter_coupling_cap -coupling_cap_threshold_absolute \
-coupling_cap_threshold_relative
Decoupled to Substrate
Controls decoupling when the extraction type is: C, RC, RLC, and RLCK.
Note: This feature is applicable only for the transistor-level Quantus with LVS input.
​Filter Size​
This setting, which is specified as a positive integer or floating point number in microns, is used to set the minimum
resolution of Quantus Inductance extraction. Quantus disregard rectangles that are smaller than the specified micron size.
The valid range for filter size is 0.25 micron to 6.0 microns.
The default value of 2.0 microns should work fine in most cases and large deviations from the default setting are not
recommended.
Related Command Quantus: inductance -filter_size (Default Value: 2.0 microns)
Split Wide MOS
This setting enables the device splitting feature for the device types specified using Techgen -compilation -split_wide_mos
and -split_hv_mos.
​Split Wide MOS Options
The split_wide_mos option is supported only in the transistor-level flow with all LVS front ends. To edit Split Wide MOS
options, click Split Wide MOS Options. The Split Wide MOS Options form appears as shown below. The GUI reads Techgen
–compilation options –split_wide_mos from Quantus technology directory (or RCXspiceINIT file), and displays all
split_wide_mos options recorded in Techgen –compilation.
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You can edit the Techgen –split_wide_mos option values and the changes are accumulated as a single CCL command (split_wide_mos_options).
To edit the existing device layer details, click Edit. The Edit Split Option form appears as follows:
You can edit Width Threshold and Min Width options. Make the required edits and click Ok or Apply. The device layer
parameters are updated.
Note: When CCL process_technology –technology_command_file <file> is specified, then, the Techgen –split_wide_mos
editing feature is disabled because CCL: –technology_command_file edits all the Techgen –compilation options.
Related Commands Quantus: device_reduction -split_wide_mos [true | false]
Quantus: device_reduction -split_wide_mos_options
​Split HV MOS Options
The split_hv_mos option is supported only in the transistor-level flow with all LVS front ends. To edit split HV MOS options,
click Split HV MOS Options.
The Split HV MOS Options form appears, as shown below:
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The GUI reads Techgen - compilation option -split_hv_mos from the Quantus technology directory (or RCXspiceINIT file),
and displays all split_hv_mos options recorded in Techgen –compilation. You can edit the Techgen -split_hv_mos option
values and the changes are accumulated as a single CCL command (-split_hv_mos_options).
To edit the existing device layer details, click Edit. The Edit Split Option form appears, as shown below:
You can edit the Width Threshold and Min Width fields, and click OK or Apply.
The device layer parameters are updated.
Note: When CCL process_technology -technology_command_file <file> is specified, then, the Techgen -split_hv_mos
editing feature is disabled because CCL: -technology_command_file edits all the Techgen -compilation options.
Related Commands Quantus: device_reduction -split_wide_mos [true | false]
Quantus: device_reduction -split_hv_mos_options
​M Factor Reduction
The Quantus M-Factor reduction feature offers a method to reduce the number of MOS and LDD transistors in the output
netlist by merging parallel transistors in the layout. This feature compliments M-Factor in LVS. The M-Factor is annotated to
a transistor in schematic capture and the resultant layout should contain "m" transistors laid out in parallel. These parallel
transistors are designed such that the parasitics from gate to gate, source to source, drain to drain are minimal.
Note: To use M-Factor reduction with generic MOS devices, in addition to standard MOS and LDD devices, you must
specify the use of Techgen -genericMos (see Quantus Techgen Reference Manual for more information).
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When the Length and Width parameters of transistors are equal, the netlist output is modified to contain a merged transistor
with an M-Factor parameter equal to the count of merged transistors (m=n). M Factor R specifies a resistance value to use for
merging all transistors in which the shortest path resistance between the source/drain/gate of adjacent devices is less than
the value specified. When M Factor R is set to "infinite", the transistors are merged regardless of resistance between
source/drain/gate of devices.
For C-only extraction you can disable M Factor reduction by specifying no value, or a value of zero (`0') in the M
Factor R field. If you specify a value greater than zero with C-only extraction, M Factor R will default to "infinite" in the
RSF.
When L1 = L2 and W1 = W2, the merged transistors in the output will have an M-Factor (m=n) parameter, and W=W1.
When W1 != W2, the M-Factor Reduction will not merge the transistors unless M-Factor W is turned on.
Related Command Quantus: device_reduction -m_factor
M Factor Keep R
This command preserves the shortest path source, drain, and gate resistances between devices merged using the M Factor
R command resulting in accurate parasitic results. You must use the M Factor Keep R command in conjunction with the M
Factor R command.
Related Command Quantus: device_reduction -m_factor_keep_res
[true | false]
M Factor W
This command changes the default behavior of M-Factor R described above. If M-Factor W is specified, the Width values are
always summed, regardless of their equivalence, and no M-Factor (m=n) parameter is output to the netlist.
In this case W = ΣW (the sum of the width of the devices) if W1 = W2 or if W1 != W2.
Related Command Quantus: device_reduction -m_factor_summed_widths [true | false]
Advanced Via Merging
If the checkbox is cleared, via merging does not consider the top and bottom layer shapes, that is, vias are merged
from left to right.
If the checkbox is selected, via merging considers the top and bottom layer shapes, that is, merging is based on the
different wire width regions.
You can modify this option only when the R Mesh Accuracy field is set to Custom.
Related Command Quantus: extraction_setup -resistance_mesh_advanced_via_merging [true|false]
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Merge Via by Mesh Size
This command allows you to automate via layer merging or meshing. The Resistance Mesh option in the Extraction tab must
be selected to use this option as the automation is based on the specified conductor meshing layers.
Related Command Quantus: extraction_setup –resistance_mesh_automatic_via_layers [true | false]
Merge Via for all layers
Allows you to specify a value to control the Size of a merged via array or the Count (number of vias per side) allowed in an
array, for all LVS via layers.
Specify the Size in microns, reflecting the drawn dimensions of the shapes. The default value of "auto" simply retains
the internal setting used by Quantus.
Specify a positive integer value for the Count field. The smaller the value, the higher is the accuracy of the R network.
However, specifying a smaller value results in a large output resistor network.
Related Commands Quantus: extraction_setup –max_via_array_size [ <size> | "auto" ] and –max_via_array_count
Merge via for Selected layers
​This option controls the max via array size or count for selected layers. Selecting the Size check box and clicking Edit opens
the Merge Via Size limit by layer form as shown below:
​Selecting the Count check box and clicking Edit opens the Merge Via Count limit by layer form.
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Related Commands Quantus: extraction_setup –max_via_array_size_by_layer <layer> [ <size> | "auto" ] and –
max_via_array_count_by_layer
Array Vias Spacing
This command is intended to provide you control over the value of the array_vias_spacing parameter at Quantus run time.
The value specified will override any array_vias_spacing values specified in the layer_setup file. Refer to Quantus
Techgen Reference Manual for more information.
The default setting of "auto" uses the values provided in the layer_setup file.
Related Command Quantus: extraction_setup -array_vias_spacing [ <value > | "auto " ]
M-Factor Exclude File
Specify an ASCII file containing a list of transistor devices which should be excluded from the M-Factor reduction process.
The transistor devices are specified by their model name as defined in the cell view of a dfII cell, or in the SPICE model
name or the device name of the extractMOS, extractLDD, or extractDevice commands. See the Assura Physical Verification
Command Reference for more information on these Assura LVS commands.
Related Command Quantus: device_reduction -m_factor_exclude_file
​Exclude Reduce Parasitics Nets​
Net names may be specified with wildcards. For more information refer to the Using Wildcards with Quantus chapter.
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This option is enabled only if the Reduce Parasitics command has been selected (see "Reduce Parasitics" ).
Specify one or more net names in the text field (separate multiple net names with a space--for example, net44 net34) or click
From File, then use the file browser to choose the file (specify one net name per line in this text file). The names in the file
must correspond to the designated Name Space, which can be either layout or schematic (see "Name Space" ). When the
nets are entered into the form directly, they are written to a file rcx.reduceRCNets.nets in the current Quantus run directory.
Note: There is only a single rcx.reduceRCNets.nets file in the working directory, and it is overwritten for each new run of
Quantus.
Use the SelFromSch button to select nets from the schematic sheets to define the list of Nets to exclude from RC reduction.
See How to Input Net Names for details on the Select from Schematic command.
Related Command Quantus: parasitic_reduction -exclude_nets_file
​Power Nets​
Net names may be specified with wildcards. For more information refer to the Using Wildcards with Quantus chapter.
Note: Power Nets and Ground Nets entry is disabled in Quantus AoT. The Power and Ground Nets entries will be disabled
when the Substrate Extract command is turned on
Use this setting to inhibit parasitic resistance or capacitance extraction on specified power nets to reduce extraction run
times. Specify the set of nets to be treated as power nets. Quantus does not extract parasitic resistance or capacitance on
declared global (power and ground) nets.
By default, the power and ground nets are excluded from extraction in the cell-level flow (except if you enable power
or ground net extraction). However, the impact from the power and ground nets to the neighboring signal nets are still
included in the total capacitance of each neighbor's signal nets.
In the case of capacitance extraction, the global net is excluded from acting as an aggressor net, but not as a victim net. That
is coupling is not extracted from the global net to a signal net, but it may be extracted from a signal net to the global net.
Specify one or more power net names in the text field (separate multiple net names with a space--for example: vdd1 vdd2) or
click From File, then use the file browser to choose the file (specify one power net name per line in this text file). When the
power nets are entered into the form directly, they are written to a file rcx.pwrNets.nets in the current Quantus run directory.
Note: There is only a single rcx.pwrNets.nets file in the working directory, and it is overwritten for each new run of Quantus.
Use the SelFromSch button to select nets from the schematic sheets to define the list of Power Nets. See How to Input Net
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Names for details on the Select from Schematic command.
If the Import Globals option is checked on the Netlisting tab, global power and ground nets declared in the LVS input data
(for example, power:P, ground:G) are also treated by Quantus as global nets (see Import Globals). They do not need to be
explicitly listed as power or ground nets, and will be merged with any nets that are specified on the Power Nets or Ground
Nets list box.
Related Commands Quantus: global_nets -nets or -nets_file
​Ground Nets​
Net names may be specified with wildcards. For more information refer to the Using Wildcards with Quantus chapter.
Power Nets and Ground Nets entry is disabled in Quantus AoT. The Power and Ground Nets entries will
be disabled when the Substrate Extract command is turned on.
Use this setting to inhibit parasitic resistance or capacitance extraction on specified ground nets to reduce extraction run
times. Specify the set of nets to be treated as ground nets. Quantus does not extract parasitic resistance or capacitance on
declared global (power and ground) nets.
In the case of capacitance extraction, the global net is excluded from acting as an aggressor net, but not as a victim net. That
is coupling is not extracted from the global net to a signal net, but it may be extracted from a signal net to the global net.
Specify one or more ground net names in the text field (separate multiple net names with a space--for example: vss! gnd!)
or click From File, then use the file browser to choose the file (specify one ground net name per line in this text file). When
the ground nets are entered into the form directly, they are written to a file rcx.gndNets.nets in the current Quantus run
directory.
Note: There is only a single rcx.gndNets.nets file in the working directory, and it is overwritten for each new run of Quantus.
Use the SelFromSch button to select nets from the schematic sheets to define the list of Ground Nets. See How to Input Net
Names for details on the Select from Schematic command.
If the Import Globals option is checked on the Netlisting tab, global power and ground nets declared in the LVS input data
(for example, power:P, ground:G) also are treated by Quantus as global nets (see Import Globals). They do not need to be
explicitly listed as power or ground nets, and will be merged with any nets that are specified on the Power Nets or Ground
Nets list box.
Related Command Quantus: global_nets -nets or -nets_file
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​Netlisting Tab
Quantus Run Form Netlisting Tab
The commands on the Netlisting tab apply to SPICE, DSPF and SPEF, and to the XDSPF and XSPEF netlist formats. Some
of the commands apply to a specific netlist format, while other commands apply uniformly to all outputs. In addition, some of
these commands apply to the handling of input data as well as, or instead of, output data.
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Design Capacitor Models
Specify whether to Include design capacitor models, Do Not Include design capacitor models, or Include As Comments
in the Quantus netlist output.
The default setting is Do Not Include design capacitor models in the netlist output.
The design capacitor model name is optionally specified in the LVS extract.rul file as part of the extractCAP rule as
follows (marked in bold in brackets, below)--for the full extractCAP rule syntax, see the Assura Command Reference:
extractCAP( " deviceName " cap RecLayer termLayer ( " Term1Name " " Term2Name ")
[tubTermLayer("tubTermName")] [spiceModel(" modelName ")] )
If you specify Include Model for the design capacitor on the Quantus GUI and the optional spiceModel(" modelName ")
argument is not supplied to the extractCAP command, the deviceName supplied to extractCAP is written as the model name
in the output.
Usage Examples
SPICE netlist output with Do Not Include selected:
C<cap_name> <top_net> <bot_net> [<tub_net>] <value> ...
SPICE netlist output with Include Model selected:
C<cap_name> <top_net> <bot_net> [<tub_net>] <model_name> <value> ...
SPICE netlist output with Include As Comments selected (in-line SPICE comments begin with a $):
C<cap_name> <top_net> <bot_net> [<tub_net>] <value> ... $<model_name>
Related Command Quantus: output_db -include_cap_model [ true | false | comment ]
Parasitic Capacitor Models
Specify whether to Include parasitic capacitor models, Do Not Include parasitic capacitor models, or Include As
Comments in the Quantus netlist output.
The default setting is Do not Include design parasitic capacitor models in the netlist output.
The parasitic capacitor models should always be included when running Substrate Extract.
Related Command Quantus: output_db -include_parasitic_cap_model [ true | false | comment ]
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Design Resistor Models
Specify whether to Include design resistor models, Do Not Include design resistor models, or Include As Comments in
the Quantus netlist output file.
The default setting is Do Not Include design resistor models in the netlist output.
The design resistor model name is optionally specified in the LVS extract.rul file as part of the extractRES rule as follows
(marked in bold in brackets, below)--for the full extractRES rule syntax, see the Assura Command Reference:
extractRES( " deviceName " res RecLayer termLayer ( " Term1Name " " Term2Name ")
[tubTermLayer("tubTermName")] [spiceModel(" modelName ")] )
If you specify Include Model for design resistor and the optional spiceModel(" modelName ") argument is not specified, the
deviceName supplied to the extractRES is written as the model name in the netlist output.
Usage Examples
SPICE netlist output with Do Not Include selected:
R<r_name> <top_net> <bot_net> [<tub_net>] <value> ...
SPICE netlist output with Include Model selected:
R<r_name> <top_net> <bot_net> [<tub_net>] <model_name> <value> L=<value>
+ W=<value>
Note: As shown in the preceding line, resistor length and width parameter values also are output when Include Model
is selected.
SPICE netlist output with Include As Comments selected (in-line SPICE comments begin with a $):
R<r_name> <top_net> <bot_net> [<tub_net>] <value> ... $<model_name>
Related Command Quantus: output_db -include_res_model [ true | false | comment ]
Parasitic Resistor Models
Specify whether to Include parasitic resistor Models, Do Not Include parasitic resistor models, or Include As Comments in
the Quantus netlist output file.
The default setting is Include As Comments in the netlist output.
The parasitic resistor models should always be included when running Substrate Extract.
Related Command Quantus: output_db -include_parasitic_res_model [ true | false | comment ]
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Netlist Names​
This is the output net name space setting. It specifies whether Quantus writes device and net names from the schematic or
layout to the output netlist. The default setting is Schematic.
Note: LVS extract-only data has no schematic reference files (.ixf, .nxf) available for back-annotation. If you select the net
name space as Schematic and specify the output format as SPICE, xDSPF, or xSPEF for Pegasus-Quantus or QCI extract-only
data, Quantus will issue an error.
This option is not available for use with Extracted View output.
Related Command Quantus: output_setup -net_name_space [ schematic | layout ]
Enable Metal Fill
This command option is used to specify how Quantus should account for the impact of fill metal on the parasitic capacitance
extraction. This option has a cyclic list with the following values: grounded and virtual
grounded - specifies to model the metal fill shapes as grounded. Grounded metal fill act as gray data, this allows
Quantus to evaluate the metal fill objects without the need of any special models.
virtual - specifies to add virtual metal fill in a design where actual metal fill patterns are only added late in the design
process (after timing closures are achieved for instance). In other words, actual metal fill patterns are not present in the
layout at the time of RC extraction, so virtual metal fills are used to simulate the parasitic effects of the actual metal fill
on the circuit. The use of virtual metal fill requires the addition of rules to define the metal fill within the ICT file. For
more information on metal fill rules in the ICT file, see Quantus Techgen Reference Manual.
Related Command Quantus: metal_fill -type [ floating | grounded | virtual | none ]
EM Analysis
The EM Analysis option is used to activate the extraction options specific to EMIR analysis during a Quantus run.
To run the EMIR flow with the extracted view (Voltus-Fi Custom Power Integrity Solution-L) or the xDPSF output
(Voltus-Fi Custom Power Integrity Solution-XL), you must select the EM Analysis check box. Contact your foundry
partner for the additional settings required for advanced nodes.
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Related Command Quantus: output_db -em_extract [true | false ]
Save Fill Shapes
This command instructs Quantus to write the virtual metal fill shapes injected by the Virtual Metal Fill command into the
extracted view output. The default behavior is to discard the injected shapes prior to creating the extracted view output.
This command only works when used with the Extracted View output.
Related Command Quantus: output_db -save_fill_shapes [true | false ]
Sub Node Character
Specify a netlist subnode character. When Quantus fractures parasitic resistors, it enumerates each resistor segment in the
netlist by listing the original net name, followed by a subnode character, followed by an enumerated subnode number. The
default subnode character is "#" for Quantus transistor-level output. For cell-level output, the default subnode character is " :".
This command is not compatible with the Extracted View output.
`#' cannot be used for Sub Node Character and must be changed for SPEF output.
As an example, if a net is named "CLK" and if the sub-node character is #, subnet descriptors with the following format are
generated in the netlist output:
CLK#1
CLK#2
CLK#3
The underscore character (`_') should not be used as the subnode character because Assura uses underscore to
distinguish duplicate reference names within blocks of a design. The `_' characters are stripped off for back
annotation, and this can result in errors in the output netlist.
Related Command Quantus: output_db -sub_node_char ( Default Subnode Character: #)
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Bus Bit
Allows you to specify the busbit character for output to the DSPF/XDSPF/SPEF/XSPEF netlist. The default busbit character
is []. For flows from LVS input, both the cell level and transistor level, you must specify the actual characters used in the
LVS input database so that the *|BUSBIT line in the netlist is properly set. For DEF/OA, use Bus Bit to change the default
character output to the netlist, in cases where a different character is required.
Note: In the DEF/OA cell-level flow, the bus notation specified by setting the BUSBITCHARS statement in the DEF file overrides
the bus notation specified by busbit_delimiter in the Quantus command file.
Related Command Quantus: output_db -busbit_delimiter
Hierarchy Delimiter
Specify the hierarchy delimiter character that Quantus uses to separate instance names from different levels of hierarchy in
the input database. The default netlist hierarchy delimiter is a forward slash ("/"). Apply this command if the input data uses
a different hierarchy delimiter from the default.
This command is not compatible with the Extracted View output.
Related Command Quantus: output_db -hierarchy_delimiter (Default Delimiter: /)
Device Finger Delimiter
The Device Finger Delimiter enables UltraSim to recognize devices merged through M Factor reduction. This command
works for SPICE, XDSPF, and XSPEF netlists. This command is useful when several device or net names in layout are
mapped to the same schematic name through M Factor reduction. The unique names are created by appending this
character followed by a number.
Requires the ?outputNameSpace to be set to "schematic" for back annotation.
Related Command Quantus: output_db -device_finger_delimiter (Default Delimiter: @)
Import Globals​
If Import Globals is enabled, Quantus will import LVS global nets. Power and ground nets in the LVS input data defined as
"power:P" and "gnd:G" will be treated as global nets during extraction. Quantus will not extract parasitic resistance or
capacitance on global nets. The Field Solver will also exclude global nets from capacitance extraction.
Quantus and the Field Solver also treat any nets specified in the Enter Power Nets and Enter Ground Nets command on the
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Filtering tab as global nets (parasitic extraction is not performed on these nets).
Note:
Import Globals is ignored when Extracted View output is selected.
In the case of capacitance extraction, the global net is excluded from acting as an aggressor net, but not as a victim
net. This means that coupling is not extracted from the global net to a signal net, but it may be extracted from a signal
net to the global net.
By default, global power and ground nets declared in the LVS input data are not imported as global nets into Quantus.
Related Command Quantus: global_nets -import_from_lvs [true | false]
Force Globals
When a cell has a local net that is declared as global, and different instances of the cell have the same net connected
through a pin to different external nets, Quantus will not recognize the internal net as a valid global net. You must enable
Force Globals to allow Quantus to evaluate the net inside the cell as a global net.
This command is only compatible with DSPF or SPEF output.
Related Command Quantus: global_nets -force_global_nets [true | false]
Parasitic Resistance Width
This command is used to include the resistance width into the output netlist. The following options are used to specify this
command:
Silicon - specifies that the silicon resistor width should be specified in the output. This is the width of the resistor after
the interconnect has been subjected to scale and bias.
Drawn - specifies that the scaled drawn width of the resistor should be output. This is the width of the interconnect as it
was input.
Unscaled Drawn - specifies that the unscaled drawn width of the resistor should be output. This is the original width of
the interconnect without any scaling.
Example - The following example shows the SPICE output for a resistor with the silicon width of the parasitic resistor
included:
Rm1_1 net34#1 net34#2 6.4055 $metal1 W=0.8
Related Commands Quantus: output_db -include_parasitic_res_width [true | false] \
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-include_parasitic_res_width_drawn [true | false]
Parasitic Resistance Length
This option specifies that the length parameter (L=n) and width parameter (W=n) should be output for parasitic resistors on
resistive metal interconnect that undergoes significant width changes. The default width change that causes the parasitic
resistance to be fractured with this command is a change of 10%.
Note: With ?parasiticResWidthChangePercentage you can specify a new value to determine when wires should be fractured
due to width changes. There is no access to ?parasiticResWidthChangePercentage from the Quantus Run form. Please refer
to Assura RCX to Quantus Migration Guide for more information.
Enabling the Parasitic Resistor Length command causes the resistor width to be output to the netlist in the silicon dimension,
unless Parasitic Resistor Width is specifically set to Drawn. Even if Parasitic Resistor Width is set to None, the silicon width
will still be output.
Related Command Quantus: output_db -include_parasitic_res_length [true | false]
Parasitic Resistance Model By Sub Conductor
When the Parasitic Resistance Model By Sub Conductor option is enabled, prints sub_conductor layer names of parasitic
resistors. By default, parasitic resistors' layer names are defaulted to its corresponding conductor name in the ICT file, or if
specified, the model name (model=<name>) in the layer_setup file.
When this option is enabled, the model name in the layer_setup is ignored, and if used in conjunction with either of the EM
mode CCL commands (extraction_setup –analysis em or output_db –em_extract true), the poly layer R network
optimization that merges the field and gate poly layers will be turned off and the sub_conductor names will be printed for
each parasitic resistor.
Related Command Quantus: output_db - include_parasitic_res_model_by_sub_conductor [true | false]
Parasitic Resistance Temperature Coefficient​
Specifies that the temperature coefficients which are used to determine the effect of temperature on resistance are included
in the output netlist. The cyclic field has the following values:
Include - the temperature coefficients (TC1 and TC2), which are used to determine the effect of temperature on
resistance, are included in the output netlist.
Do Not Include - TC1 and TC2 are not included in the output netlist.
Include As Comment - TC1 and TC2 are printed as comments ( $TC1=, $TC2=).
The default value of this option is Do Not Include.
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If the Parasitic Resistance Temperature Coefficient option is set to either Include or Include As Comment, then:
Temperature and Reduce Parasitics options will be disabled
Add Explicit Vias option will be enabled
If the Parasitic Resistance Temperature Coefficient option is set to Do Not Include, then:
Temperature and Reduce Parasitics options will be enabled
Add Explicit Vias option will be disabled
You can manually enable/disable the Add Explicit Vias option. However, if the EM Analysis option is also enabled,
then the Add Explicit Vias option is disabled and grayed out irrespective of whether the Parasitic Resistance
Temperature Coefficient option is set to either Include or Include As Comment.
The temperature coefficients (TC1 and TC2) are defined in the ICT file when creating the technology file (see Quantus
Techgen Reference Manual ).
The multiple process corner mode supports temperature coefficient (TC1/TC2) printing in both the cell-level and
transistor-level flows.
In the transistor-level flow, the process corner property information (P1,P2,P3) and temperature coefficients
(TC1/TC2) are stored in the vector format for the parasitic R/C element values. During simulation, you can set the
values of P1, P2, P3 to retrieve the RC value of each process corner. For example, P1=1, P2=0, P3=0 would retrieve
the P1 corner’s RC values. P1/P2/P3 should sum up to 1.0. For example, P1=0.5, P2=0.5, P3=0 would retrieve an
imaginary process corner in between P1 and P2. By default, the process corner property names (P1,P2,P3…) for
resistance are R1,R2,R3 and for capacitance are C1,C2,C3. The following is an example of the temperature
coefficient print format in the vector format:
Rxx n1 n2 ‘R1*<Rval1>+R2*<Rval2>+R3*<Rval3>’
+ TC1=’R1*<tc1_a>+R2*<tc1_b>+R3*<tc1_c>’
+ TC2=’R1*<tc2_a>+R2*<tc2_b>+R3*<tc2_c>’
+ $M01 $L=0.246 $W=0.072 $X=241.442 $Y=229.979
Cxx n3 n4 ‘C1*<Cval1>+C2*<Cval2>+C3*<Cval3>’
...
In the transistor-level flow, multi-corner temperature coefficient printing is supported only in the SPICE and extracted
view output formats, and requires two XL licenses.
If the Parasitic Resistor Width is disabled (Off) or is set to Silicon, the temperature coefficient values will be printed based on
the silicon widths.
If the Parasitic Resistor Width is set to Drawn the temperature coefficient values will be printed based on the drawn widths. If
layout_scale is specified in the ICT file, then the TC1 and TC2 values will reflect the scaled drawn width.
The presence of the TC1/TC2 temperature coefficients in the output netlist (Spice, XDSPF, or Extracted View) allows the
downstream simulation to directly consider the effects of temperature on the circuit. When outputting TC1/TC2 into the output
netlist, the expected use model is to define the operating temperature or temperature range during the simulation step (for
example, during Spectre simulation).
In this case, you do not want Quantus to consider the effect of temperature on resistance extraction or you may be double
counting the effect. When Parasitic Resistance Temperature Coefficient is enabled, the Temperature option will be disabled
(see "Temperature" ).
Related Command Quantus: output_db -include_parasitic_res_temp_coeff [true|false|comment]
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XY Coordinates in Netlist
Specify designed device and parasitic component types for which Quantus will supply XY coordinate information in the
output netlist. Designed device selections are specified with upper case characters; parasitic component selections are
specified with lower case characters.Supported device type and parasitic component selections are R, C, r, c, D, M, Q, X
(design resistors, design capacitors, parasitic resistors, parasitic capacitors, design diodes, MOSFETs and BJTs, generic
devices respectively).
Starting with PVE 12.1.1 release, a new check box "X" has been added to this option. If the check box is enabled, then
Quantus outputs XY coordinates for generic devices. When disabled, then XY coordinates are not reported in the output
netlist.
This option is available for all outputs except when output is extracted view or LVS extracted view.
The selection designator for parasitic resistors (r) also determines whether XY coordinates for extracted inductance
components (parasitic Ls and Ks) are inserted in the netlist.
Related Commands Quantus: output_db -output_xy [ canonical_cap | parasitic_cap |
canonical_res | parasitic_res | diode | mos | bipolar | generic ]
Parasitic Resistance Conductor Bounding Box
Prints the bounding box for the conductor parasitic resistor. It prints the bounding boxes of all the resistive LVS connect
layers (LVS connect layers do not include the LVS via layers). The possible values of this option are:
False (default) - conductor bounding boxes are not written to the output file.
Edge - the edge style of conductor bounding box is written to the output file. The edge style extends the bounding box
to the edge of the resistor body polygon.
Center - the center style of conductor bounding box is written to the output file. The center style restricts the bounding
box to the center of the via.
Multiple - this is the same as the edge style, with the exception that multiple bounding boxes may be printed depending
on the resistor configuration.
The Parasitic Resistance Conductor Bounding Box and Parasitic Resistance Via Bounding Box By Layer fields are
enabled only if:
Transistor Dspf is selected from the Output drop-down list in the Setup tab.
r checkbox of the XY Coordinates field is selected in the Netlisting tab.
EM Analysis checkbox is selected, or Stacked Via Metal Width is set to EM in the Netlisting tab.
Quantus: output_db -include_parasitic_res_conductor_bounding_box [ edge | center | multiple | false ]
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Parasitic Resistance Via Bounding Box By Layer
Prints the bounding boxes for the specified vias in the output file. The possible values of this option are:
Off (default) - via bounding boxes are not written to the output file.
All - prints all the LVS vias (front-end via layers, back-end via layers, special via layers). The special via layers are
abutment, bridge, md_tap, and fracture vias.
Selected Via Layers - prints the required LVS via layer names. You can select this option and click Edit to open the
Parasitic Resistance Via Bounding Box By Layer form as shown below:
Related Command Quantus: output_db include_parasitic_res_via_bounding_box_by_layer “all”|”<via1>” … “<viaN>”
Ignore Vias
This command specifies that all vias belonging to the specified comma-separated list of layers, that occur on any of the
comma-separated list of nets, should be eliminated from resistance extraction.
This command is intended to suppress vias connecting to the substrate to prevent the substrate from shorting parasitic
resistors on nets connecting to the substrate (vss! for instance). This has the advantage of reducing the extracted parasitics
by eliminating many possible via resistors from the power or ground net, and reducing the RC networks as a result. Specify
the via layers and the substrate nets to achieve this result.
Quantus: substrate_connection -remove_contact
Note: If the layer_setup file does not contain the stamp command, then specifying stamp=1 will restore the old (that is, pre8.1 release) behavior. If the layer_setup file contains the stamp command, then minor changes in behavior maybe observed.
If stamp=0 is specified, the software will not restore the old behavior (pre-8.1 release).
Auto Substrate Stamping Off
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This command can be used to disable substrate stamping for designs that have stamp= statements specified in the
layer_setup file. This can be used to enable the Ignore Vias (?ignoreVias) command which is not compatible with substrate
stamping.
Quantus: substrate_connection -substrate_stamping_off [true | false]
​Add Explicit Vias
If this parameter is set to true (t), Quantus will netlist separate parasitic resistors for contacts and vias on all metal layers
mapped in the layer_setup file.
Note: Enabling the Parasitic Resistance Temperature Coefficient option automatically enables the Add Explicit Vias option
and disabling it disables the Add Explicit Vias option. In both the cases, you can manually turn ON/OFF the Add Explicit
Vias option. However, if the EM Analysis option is also enabled, then the Add Explicit Vias option is disabled and grayed out
irrespective of whether the Parasitic Resistance Temperature Coefficient option is enabled or disabled.
​Via Effect Off​
As a default, Quantus does not include the effect of vias or contacts on capacitance extraction results unless the via effect is
explicitly modeled in the techfile.Quantus provides three distinct methods for defining the via effect (see Quantus Techgen
Reference Manual):
Explicit definition of the via effect on the Via layer in the ICT file.
Use of the min_contact_poly_spacing keyword in the ICT file.
Use of the Techgen -add_via_effect command. 6
Via Effect Off allows you to disable the via capacitance effects specified in the techfile during Quantus capacitance
extraction. In this case, the via effect is ignored. This option can be used to exclude via capacitance extraction for both
Quantus and Quantus FS.
Related Command Quantus: extract -extract_via_cap [true | false]
Gate Diffusion Fringing Cap Off
This command enables Quantus to extract the transistor device gate-to-diffusion fringing cap (C f) when the
gate_diffusion_fringing_cap table is defined in the qrcTechFile. Refer to Quantus Techgen Reference Manual for more
information on defining the gate_diffusion_fringing_cap table.
The fringing cap is intended to be used in conjunction with metal diffusion contacts. The spacing parameters of the
gate_diffusion_fringing_cap table originate from the metal diffusion contacts.
Note: When the qrcTechfile includes the gate_diffusion_fringing_cap table the Virtuoso_QTS_Extraction_XL license is
required by Quantus.
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It is not recommended to activate the Gate Diffusion Fringing Cap Off button since the Cf values, if defined in
the qrcTechFile, are necessary for accurate device extraction results.
Related Command Quantus: extract -extract_gate_diffusion_fringing_cap [true | false]
Instance Off
The Instance section is optional in both the cell-level and the transistor-level DSPF and SPEF output. The Instance section
contains the list of device instances and their associated parameters. This command disables output of the Instances section
of the output netlist.
Related Command Quantus: output_db -disable_instances [true | false]
Netlist Coupling Values
By default, a single parasitic coupling capacitor is produced between two nets in the DSPF or transistor-level DSPF output
netlist.
If you set the value of the Netlist Coupling Values command to double, Quantus adds the values of coupling capacitors
between two nets with full value to both nets for cell-level and transistor-level DSPF netlists. However, this duplicate
coupling cap will cause errors if the netlist is passed to a SPICE or SPECTRE simulator.
Related Command Quantus: output_db -netlist_coupling_values [ single| double | separate ]
Reduce I-Cards
This option specifies to suppress the printing of the *|I cards for C only nets in the xDSPF netlists of RC extractions.
Related Command Quantus: output_db -reduce_i_cards
Layer Name Printing
This option enables Quantus to print the layer information in the transistor-level xDSPF/xSPEF output including the
hierarchical mode. By default, the option is turned off and is grayed out. It is enabled only when you select Transistor Dspf or
Transistor Spef as the output format from the Setup tab (see "Output Format" ).
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If you select the EM Analysis checkbox for the xDSPF, xSPEF, and Smart View output formats, the Layer Name Printing
checkbox will be automatically selected and grayed out. Alternatively, if you clear the EM Analysis checkbox, then the Layer
Name Printing checkbox is automatically cleared and enabled.
Related Command Quantus:
output_db -subtype extended
Empty Subcircuit Off
This option specifies to suppress the printing of empty subcircuit definitions for macro cells.
Related Command Quantus: output_db -suppress_empty_subckts
Disable Stacked Via
If a wire segment is very short between the inner layers of adjacent stacked vias, the current flowing in the short horizontal
segment is expected to be mostly vertical, whereas the horizontal currents may be non-real. Thus, by default, the W
parameter is set to 1,000,000 microns to prevent false EM violations.
The Disable Stacked Via option allows you to modify this default behavior and print the actual width values. The actual
width values are supported in certain foundry-provided EM rules for advanced nodes, therefore, contact your foundry
provider before changing the default behavior.
The use model of the parameter is:
when the checkbox is selected, reports the W parameter as 1,000,000 microns
when the checkbox is cleared, reports the actual wire width for the short horizontal metal segment.
The Disable Stacked Via field is applicable for all LVS inputs and for all extraction types, except none (extract -type none),
and for all output formats, except “LVS Extracted View”.
Related Command Quantus: extraction_setup -stacked_via_effect
Stacked Via Metal Width
This option determines whether or not stacked via checking needs to be performed.The Stacked Via Metal Width option can
be set to the following values:
Timing: (Default) When the value is set to Timing, stacked via metal width checking is not performed and the
extraction_setup -analysis CCL command is not added to the CCL output file.
EM: When the value is set to EM, stacked via metal width checking is turned on and the extraction_setup -analysis em
CCL command is added to the CCL output file. Using this option will result in the activation of 20nm EM features. For
more information, see "20nm EM features" section in the Quantus Command Files chapter.
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Note: The Stacked Via Metal Width option is enabled only when you select Spice, Transistor Dspf, Extracted View, or
Transistor Spef as the output format from the Setup tab (see "Output Format" ).
Related Command Quantus: extraction_setup -analysis [ em | timing ]
Output Postprocessing File
This option indicates that Quantus should postprocess the output using the specified scripts before writing the output file.
You can also click the (...) button and specify the file from the File Selector window.
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File Selector Window
Note: The Output Postprocessing File option is enabled only when you select Transistor Dspf or Spice as the output formats
in the Setup tab.
Related Command Quantus: output_db -postprocess_output_netlist
Output Multi-file
This option, when enabled, generates single-value, multiple xDSPF files in a single Quantus run for multiple process
corners. Each file is specific to a process corner. This option is supported for all LVS input formats (Calibre, Pegasus, and
Assura). This option is supported only for xDSPF/xSPEF output formats when the UseMultipleRuleSets option is enabled.
Related Command Quantus: output_db -output_multi_value_rc
Transfer of Net Expression
When set to false, this option specifies not to transfer the inherited net expression from the layout to the Extracted View. The
default setting is true, which means that the inherited net expression is transferred from the layout to the Extracted View.
Related Command Quantus: output_db -type extracted view -transfer_net_expression
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Run Details Tab
Quantus Run Form Run Details Tab
When you select Multi Processing from the Quantus Run Mode drop-down list, and queue from the Run Location
drop-down list, and specify the number of CPUs in the Number of Processors field, the tool will add this information in
the bsub command line of the run file (.QRC.run)
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Run Name
The default run name is the runName passed to Quantus from the open Assura LVS run (see "Quantus UI and Assura LVS
Input" ).
This command allows you to specify a different run name if you wish. Quantus creates a directory in the current working
directory with the specified run name (or uses an existing directory with this name) to store the files that are produced during
the Quantus run.
Related Command Quantus: output_setup -temporary_directory_name
​Run Directory
The Quantus run (working) directory name and path. This is the directory from which the Assura DFII executable (such as
icfb or layoutPlus for CDBA and virtuoso for OA), was launched. Output files and directories produced by the current
Quantus run are placed in this run directory.
Related Command Quantus: input_db -directory_name
Note: Starting with the 11.1 release, the Quantus UI behavior (for Pegasus-Quantus and QCI flows) has been enhanced for
the Run Directory option to make it consistent with Quantus batch mode behavior. That is, in Quantus GUI run form, you can
provide a different Run Directory name, which corresponds to the output_setup -directory_name CCL option.
Log File
Specify a log file path and name where Quantus will place a log file of the extraction run. Insert the directory path and name
in the text box or click Browse... to select an existing directory. As a default, Quantus names the log file rcx.< runName> .log,
as determined by the default or user-specified run name. You can click View to view the log file after the Quantus run.
Related Command Quantus: log_file -file_name
Keep Temporary Files
Specifies to preserve the temporary files in the directory specified by the output_setup -temporary_directory_name
command.
When this checkbox is not selected in the cell-level flow, Quantus removes the temporary files when extraction has
completed. Starting with EXT15.1, this option is honored in the Quantus transistor-level flow. If this checkbox is not selected
(default value), the previous default behavior of the transistor-level flow is preserved. That is, Quantus does not keep the
temporary files if it is the hierarchical, macro cell, or cell blocking flow. However, if the output format is extracted view, or if it
is a flat Quantus run, then all temporary files are automatically preserved as per the user specified
temporary_directory_name.
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Related Command Quantus: output_setup -keep_temporary_files
Print Command File In Output Log
Specifies to save the current Quantus CCL file contents in the log file. It also prints the file contents to the standard output.
The option works for both the cell-level and transistor-level flows.
Related Command Quantus: log_file -dump_options
Specifies to print the peak memory consumed. In addition to the peak memory consumption, the option also prints
information related to the host machine. This option is supported in both the single processing and distributed processing
(DP) modes. In the DP mode, the option is supported in the multi-CPU mode, but not supported in the multi-machine and
LSF modes.
Related Command Quantus: log_file - debug_log
Quantus Run Mode
When you specify a run mode (Multi Processing/ Multi Machine/ LSF Queue) in the Quantus Parasitic Extraction
Setup Form, the remaining run modes will not be available in the Quantus Parasitic Extraction Run Form. For
example, if you select the Enable Multi Processing checkbox in the setup form, then Multi Processing will be the only
option available for Quantus Run Mode drop-down list in the Run Details tab of the run form.
MultiProcessing
If the current Quantus run is to be performed on a single machine with multiple processors, click the Multiprocessing button
to have Quantus divide the extraction run into concurrent extraction processes to quicken extraction runtimes.
Number of Processors
If the Enable Multiprocessing box is checked, specify the Number of Processors available on the machine to allocate to the
current Quantus run.
Related Command Quantus: distributed_processing -multi_cpu
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Multiple Machines
Multi Machine requires one Quantus license for two machines on which it is executed.
This command enables Quantus and Techgen to run on multiple machines at the same time. A list of machines is specified
by their hostname or IP address, and is checked for validity prior to execution. The list of machines you specify to be used by
Quantus is written to a file called rcx.Machines.File in the current run directory, or is predefined in a file that is used as an
argument with the Multi Machine command.
Related Command Quantus: distributed_processing -multi_machine
Load Sharing (LSF)
LSF Queue requires one Quantus license for two machines on which it is executed.
For the LSF Queue command, documented LSF features are applied. The use of LSF requires that LSF executables are in
the execution path for the shell invoking Quantus programs. Refer to distributed_processing or to the RCX to EXT Migration
Guide for information the LSF command setup.
Machines in the LSF cluster will be applied as available. The number of machines in the cluster is specified with an integer
number. This also indicates the number of jobs that can be run in parallel. The command to use when launching Quantus
under LSF is specified as a string. The LSF Command defines job groups and available hosts among other things. You must
ensure that these LSF options are valid.
Note: Setting the LSF Command field in the Run Details tab allows you to submit and run the parent Quantus job on an LSF
machine, followed by the LSF submissions of the subsequent child jobs, one after the other.
Alternatively, you can set the queue names and resource strings in the Quantus Setup Form (see Run Details tab for details
on this method). Then, in the Quantus Parasitic Extraction Run Form, select queue from the Run Location drop-down list and
the queue name from the Queue Name drop-down list. You can select a queue name from the list of queue names that are
defined in the template file (.rcx_setup.tpl), or you can specify a queue name that corresponds to a different LSF setup.
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This method enables you to run all Quantus jobs (parent job including child jobs) on a single LSF machine.
LSF queue processing in UI is performed by reading LSF information from the following variable/files in the given
sequence:
1. QRCUI_LSF_RESOURCE environment variable
2. rcx_setup.tpl (Quantus UI template) file
3. .assuraUI.prf (Assura setup file)
The QRCUI_LSF_RESOURCE environment variable is used to set a 'bsub' command in the Quantus Parasitic Extraction
Run form. It's value is a 'bsub' command or a part of it . A couple of examples of how this variable is set are provided below:
setenv QRCUI_LSF_RESOURCE "bsub -q lnx64 -R 'OSNAME==Linux && OSBIT==64 && OSREL==(EE60|EE70)' -P
techgen -o Techgen.log -W 99:00 -eTechgen.err"
setenv QRCUI_LSF_RESOURCE "bsub -q lnx64 -R 'OSNAME==Linux && OSBIT==64 && OSREL==(EE60|EE70)'"
The variable value is parsed by Quantus UI and used to set fields on the Run Details tab of the Quantus Parasitic
Extraction Run form for Run Location - queue.
You can also click the Load from QRCUI_LSF_RESOURCE button to load inputs from
the QRCUI_LSF_RESOURCE environment variable.
Related Command Quantus: distributed_processing -lsf_number (Default Value: 64)
Run Location
Submit the Quantus run for either local execution, or remote execution on the specified machine name. You can select NC
queue to submit Quantus run in a network cluster. The NC Command field is displayed when you select NC queue from the
Run Location drop-down list. The NC Command field allows you to check and update the NC command from the current tpl
and/or state file. For more information, refer to the "Run Details Tab" section in the Setting Up the Quantus User Interface
chapter.
You can select queue to submit the LSF information directly from the GUI. The following fields will be visible when you
select queue from the Run Location drop-down list:
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Queue Name - select a queue name from the list of queue names that are defined in the template file (.rcx_setup.tpl), or
you can specify a queue name that corresponds to a different LSF setup.
Queuing Command - specify options of the bsub command other than -R.
If bsub is not specified in the Queuing Command field, then it will be automatically added to the Effective
Command field.
If the Number of Processors field (displayed when the Run Mode is Multi Processing) is not empty, then
the -n option is added/updated automatically in the Effective Command field.
If -o <bsub_log> has not been specified in the Queuing Command field, then the GUI will add –o
<qrc.log>.lsf to the bsub command in .QRC.run.
Queuing Resource - specify the bsub -R options.
Effective Command - A read-only field which shows the effective command string compiled from the Number of
Processors, Queuing Command, and Queuing Resource fields. This value will be used as the submission string to
LSF.
If the Queue Name field is empty, then the -q option will be removed from the Effective Command field.
Load from QRCUI_LSF_RESOURCE - Click this button to load inputs from the QRCUI_LSF_RESOURCE
environment variable. The Queuing Command, Queuing Resource, and Effective Command fields are populated with
the parameters as defined through the QRCUI_LSF_RESOURCE variable. By default the button is disabled. To
enable the button, set the environment variable QRCUI_LSF_RESOURCE.
The LSF information will be written to the Quantus UI *.state file.
Enable License Queue
Provides a license queue to enable Quantus to wait for the required licenses to become available before beginning an
extraction run. You can queue up multiple extraction runs to begin execution as licenses become available.
The queuing state information about Quantus licenses is reported in the Quantus log file. When the required license is
temporarily unavailable, you might have to wait for some time before the Quantus interface is displayed. During this wait
time, you can view the INFO messages on the screen or in the log file to find out if the slowdown is because of license
queuing. This is especially useful when Quantus is running on a remote host.
You can also specify a Timeout value in seconds (default is 1800 seconds), which enables Quantus to wait for a license(s)
for the specified time. If the license(s) is not available within the time specified, Quantus removes itself from the queue and
issues an error message stating that the license is not available.
The queuing sequence depends on the temporary unavailability of the license checking sequence. For example, if L is
permanently unavailable, but XL is temporarily unavailable, then, the queue chosen is XL. Similarly, if L is temporarily
unavailable (regardless of XL's temporary, or permanent unavailability), the queue chosen is L.
Reporting of the license queued state is supported for both cell level and transistor level.
The following is an example of the message that will be printed to the log file and the screen to indicate the queuing status:
INFO (xxxxxx-xxx) : Attempting to check out a license in wait mode with time-out value equals 60 second(s). Waiting for
feature `Virtuoso_QTS_Extraction_XL' to be checked in ...
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INFO (xxxxxx-xxx) : Checked out 1 license(s) for Virtuoso_QTS_Extraction_XL
The following is an example of the messages that will be printed when a certain license (say L) is permanently unavailable:
INFO (xxxxxx-xxx) : Attempting to check out 1 license(s) of 'Virtuoso_QTS_Extraction_L' in wait mode with time-out value
equals 60 second(s). Waiting for feature 'Virtuoso_QTS_Extraction_L' to be checked in ...
INFO (xxxxxx-xxx) : Unable to obtain 1 license(s) for Virtuoso_QTS_Extraction_L
INFO (xxxxxx-xxx) : Attempting to check out 1 license(s) of 'Virtuoso_QTS_Extraction_XL' in wait mode with time-out value
equals 60 second(s). Waiting for feature 'Virtuoso_QTS_Extraction_XL' to be checked in ...
INFO (xxxxxx-xxx) : Checked out 1 license(s) for Virtuoso_QTS_Extraction_XL
Related Command Quantus: quantus -lic_queue [ <timeout> ]
Substrate Tab
The Substrate tab provides the user-interface for Quantus AoT. For a complete description of the configuration and use of
Quantus AoT refer to the Substrate Extraction chapter.
The Command File​
When you run Quantus, the user-interface produces a command file, also called a CCL file that directs parasitic extraction
according to the settings you have specified on the Quantus Parasitic Extraction Run Form.
The file name of the CCL is in the form of qrc.< runName >.ccl, where < runName > is the Run Name specified on the Run
Details tab. For example, if the Run Name is specified as MyCell, the user-interface produces a CCL file named
qrc.MyCell.ccl.
The following is a CCL file that corresponds to the default Quantus settings established when you click Defaults from the
Quantus Run form button bar:
# OPTION COMMAND FILE created by Cadence Extraction Quantus UI Version 9.1.0
extract
-selection "all"
-type "r_only"
extraction_setup
-array_vias_spacing auto
-max_fracture_length infinite
-max_fracture_length_unit "MICRONS"
-max_via_array_size "auto"
-net_name_space "LAYOUT"
filter_res
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-min_res 0.001
input_db -type assura
-design_cell_name "3Wire_metal layout BASIC_STRUCT_1"
-directory_name "/home/kamal/LAB/LAB/ModuleI/Compatibility_Flow/xtor/assura_lvs"
-format "DFII"
-hierarchy_delimiter "/"
-library_definitions_file "/home/kamal/LAB/LAB/ModuleI/Compatibility_Flow/xtor/cds.lib"
-run_name "3Wire_metal"
output_db -type spice
-device_finger_delimiter "@"
-hierarchy_delimiter "/"
-include_cap_model "false"
-include_parasitic_cap_model "false"
-include_parasitic_res_model "comment"
-include_parasitic_res_width false
-include_parasitic_res_width_drawn false
-include_res_model "false"
-sub_node_char "#"
output_setup
-file_name "/home/kamal/LAB/LAB/ModuleI/Compatibility_Flow/xtor/3Wire_metal.sp"
-net_name_space "SCHEMATIC"
-temporary_directory_name "3Wire_metal"
process_technology
-technology_library_file "/home/kamal/LAB/LAB/ModuleI/Compatibility_Flow/xtor/assura_tech.lib"
-temperature 25.0
​Standalone Quantus UI
The Quantus UI is also available in the "standalone" mode and can be invoked without the Virtuoso environment. Like the
integrated Quantus UI, the standalone Quantus UI also supports the Assura-Quantus, Calibre-Quantus (QCI), and PegasusQuantus flows. It does not support cell-level extraction with DEF or OA input.
Note: The standalone Quantus UI requires an L license. When a Quantus job is submitted, the UI releases the license.
During the Quantus run, Quantus checks out whatever license(s) it needs for its run, depending on the use models and
technology modeling features used, as usual. The UI then checks-out the L license again immediately after the Quantus job
has completed.
Launching the Standalone Quantus UI
Note: Before launching the standalone Quantus UI, you must define the QRC_HOME environment variable, otherwise, the
standalone Quantus UI will not be invoked.
To launch the standalone Quantus UI, type the following at the command prompt:
quantusui &
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The standalone Quantus UI Main Form is displayed as shown in below figure.
Note: By default, the standalone Quantus UI uses the cds.lib file. Starting with IC version 6.1.4, the use of lib.defs file has
been discontinued. However, if you are using an IC 6.1 version that is earlier than 6.1.4, you can still use the lib.defs file by
setting the DD_USE_LIBDEFS environment variable to YES.
​Standalone Quantus UI Main Form
In addition to the Quantus UI Main Form, a cdshi window is also displayed. You can refer to this window for
error/info/warning messages.
The Quantus UI Main Form window contains the following buttons:
Run Assura-Quantus - invokes the Quantus (Assura) Interface form for specifying the Assura LVS input data, as shown
in the "Run Location" figure.
​Quantus (Assura) Input Form
For Assura - Quantus flow, you need to set the ASSURAHOME environment variable as an Assura installation may be
required to run Quantus. The standalone Quantus UI checks for ASSURAHOME and if Assura is not available, the
Run Assura- Quantus button is disabled.
For more information see Quantus UI and Assura LVS Input.
Run Calibre-Quantus - invokes the Quantus (Calibre) Interface form that enables you to specify the information
required to support Calibre LVS input, as shown in "Enable License Queue" figure.
Quantus (Calibre) Interface Form
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For more information, see "Quantus UI and Calibre LVS Input" .
Run Pegasus-Quantus - invokes the Quantus (Pegasus) Interface form that enables you to specify the name of the
Pegasus run to load, as shown in figure below.
​Quantus (Pegasus) Interface Form
For more information, see Quantus UI and Pegasus Input.
Setup Quantus - invokes the Quantus Parasitic Extraction Setup Form that enables you to define the template files that
contain default selections and valid options available when running Quantus, as shown in "Quantus (Assura) Input
Form" figure.
Quantus Parasitic Extraction Setup Form
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Quantus Parasitic Extraction Setup Form
For more information, see " Defining Quantus UI Templates .
Note: You can invoke only one GUI form at a time. For example, if you have invoked the Assura-Quantus form, and you also
invoke the Pegasus-Quantus or Calibre-Quantus forms, the Assura- Quantus form will close automatically.
When you specify the input data in the Quantus Interface form for Assura, Calibre, or Pegasus, the Quantus Parasitic
Extraction Run Form is displayed, as shown in below figure.
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Quantus Parasitic Extraction Run Form
Running Standalone Quantus UI in Replay Mode
The standalone Quantus UI provides you the ability to launch a UI session with the settings recorded in the last Quantus UI
run. However, to launch the UI with the last recorded settings you must first launch the Quantus UI session with the -log
command-line option as follows:
>quantusui -log <filename>
When you launch the Quantus UI with the -log option, Quantus records the run form settings in a log file <filename> in the
current working directory.
To launch the standalone Quantus UI in replay mode, type the following at the command prompt:
> quantusui -replay <filename>
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where:
<filename> is name of the log file present in the current working directory.
For more information on the standalone Quantus UI command-line options, see Standalone Quantus UI Command-line
Options .
Standalone Quantus UI Restrictions
The Standalone Quantus UI supports almost all features that are available in the Virtuoso Integrated Quantus UI with the
following restrictions.
No interactive features are available in the standalone Quantus GUI (for example, showing layout, probing nets,
picking nets and regions in the layout).
The standalone UI automatically removes the Lvs Extracted View and Extracted View options from Output Formatlist if
it does not locate the library definition file (in the working directory) and generates the following message:
*Info* Lvs Extracted View and Extracted View output formats will be not available because Library Definition File is not
found
The standalone GUI does not check the compatibility with the Assura LVS database. If an Assura LVS database is not
compatible with the current Assura version, it is known only after the Quantus run.
The standalone Quantus UI does not support the SND analysis functionality.
1
The Quantus UI in EXT8.1 requires the use of Assura 3.2 when used with Assura LVS input.
2
The Quantus Parasitic Extraction Run Form has variations for Assura, Pegasus, and Calibre input.
3
The installation directory for the Quantus release should already be in your PATH, so you should be able to execute
cdnshelp without the full path.
4
The presence of LVS macrocells cannot be determined while creating the RSF, so this condition
could result in an error during extraction.
5
This command is made redundant by the other two methods of defining the via effect and is no longer
recommended.
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Substrate Extraction
Setup Substrate Extraction
Substrate Tab - Substrate Extraction in Quantus AoT
Enabling Substrate Extraction
Substrate Technology Selection
Substrate Extraction Controls
Log Files
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Setup Substrate Extraction
Note: Starting in the 8.1 release, ensure that the sna.ini (or sna.cxt) file is not loaded through
.cdsinit (while launching the DFII executable) or manually. Instead, the Quantus context file must
be loaded. For more information, see the Setting Up the Quantus User-Interface chapter.
1. For the IC613 platform version and earlier IC versions, including IC514, edit your cds.lib or
lib.defs (OA only) file to add the substrateLib library:
DEFINE substrateLib $ASSURAHOME/share/sna/etc/cdslib/substrateLib
Starting with IC614 ISR10, and for all future IC61releases, the substrateLib library will be
available directly in the IC releases, and you should define the substrateLib library location
as follows:
DEFINE substrateLib $CDSHOME/share/sna/etc/cdslib/substrateLib
Note: For versions prior to ISR10, for the IC614 platform, refer to the IC613 version of the
substrateLib library, which is compatible with the IC614 platform.
SNA adds a cell to the extracted view output called substrate that is selected from the
substrateLib.
2. Define the location of the Substrate Tech Files:
setenv SUBSTRATESTORMSITE <path>
Where <path> is the location of the substrate technology files on your machine or network.
The substrate technology files (SCtechnology.<tech_name>) should be found in directories
under $SUBSTRATESTORMSITE/<technology_name>. See Quantus Substrate Technology
Characterization Manual for more information on setting up the required files.
A technology site is a directory containing setup files that pertain to a particular integrated
circuit fabrication process technology. The $SUBSTRATESTORMSITE environment variable
specifies the location of the different Substrate technology sites. You can specify more than
one site by using `:' in the $SUBSTRATESTORMSITE definition.
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Substrate Tab - Substrate Extraction in Quantus AoT
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Enabling Substrate Extraction
The Substrate tab provides the User Interface for the new Quantus AoT option to Quantus. The tab
is enabled through the use of the Substrate Extract command when either Spice or Extracted View
output has been specified on the Setup tab (see Spice Output or Extracted View Output).
In addition, when substrate extraction is enabled, it is dependent on other controls on the Extraction
tab (see Extraction Tab):
The Extraction Type determines what parasitic elements will be extracted from the devices
and interconnect of the design. Substrate extraction supports R-only, RC, RLC, or RLCK type
of extractions, but requires that at least RC extraction is performed (see Extraction Type).
Substrate reduction (see RC reduction) is affected by the Global Frequency command (see
GlobalFrequency). When global_frequency is specified as greater than 0, then the substrate
reduction frequency is calculated at three times the specified value. When global_frequency
is left as zero the default substrate reduction frequency is 5 GHz.
Quantus AoT can optionally connect both interconnect and devices to the substrate. Devices
are controlled through the Extract Substrate for Devices command (see Extract Substrate for
Devices) on the Substrate tab. However, the nets to connect to the substrate must be specified
with the use of the Enter Substrate Nets command on the Extraction tab (see Enter Substrate
Nets).
Substrate Technology Selection
Substrate Tech Dir
The Substrate Tech Dir field will be populated by the the Substrate Tech Dir field of Quantus
Parasitic Extraction Setup Form or environment variable $SUBSTRATESTORMSITE. However, if both
the environment variable $SUBSTRATESTORMSITE and the Substrate Tech Dir field of Quantus
Parasitic Extraction Setup Form are not specified, Quantus UI will check whether the
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substrate_techdir fixed directory exists in the Quantus Technology directory and will automatically
update the Substrate Tech Dir field. As a result, the Substrate Tech Dir field will be grayed out in the
Quantus Parasitic Extraction Run Form, and will point to the directory substrate_techdir.
substrate_techdir will contain sub-folders for technology names, and each technology name
folder will contain the substrate technology file. Quantus will first search for substrate_techdir in
the main Quantus technology directory, and if not found, then it will search for substrate_techdir in
the corner technology directories.
The substrate technology selection in Quantus Parasitic Extraction Run Form will have the priority
order as follows:
Substrate Tech Dir field in Quantus UI Setup Form
SUBSTRATESTORMSITE environment variable
substrate_techdir fixed directory
If the above options are not used, then you can manually specify the technology directory by
clicking the browse (...) button.
Tech Dir Name
Technology selector populated with subdirectories from the Substrate Tech Dir.
Tech File Name
The substrate technology file (SCtechnology.*) is generated by snatct. It includes all the
technological process information for regions, cross-sections, interface layers, and their electrical
parameters. See Quantus Substrate Technology Characterization Manual for information on
generating the substrate technology file.
Grid Control
The Grid Control command allows you to select the extension for one of the SCparameters.xtr files
that may be found in the specified Tech Dir Name directory.
The grid control file contains advanced directives for the substrate extraction engine (see "Substrate
Extraction Files" in Quantus Techgen Reference Manual). If no grid control file is specified, then
internal default grid settings are automatically used.
Related Command Quantus: substrate_extract -grid_control < name >
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Substrate Extraction Controls
High Accuracy Mode
This option, when selected, activates the high accuracy mode for substrate extraction and substrate
AC analysis (SNA). In the high accuracy mode, SNA uses more accurate mesh settings, however,
there may be an increase in the SNA runtime and the netlist size.
Note: The high accuracy mode is only recommended for teststructures, if needed. It is not
recommended for real designs where default accuracy mode has sufficient accuracy in the SNA
extraction.
Note: The High Accuracy Mode and Grid Control options are mutually exclusive.
Related Command Quantus: substrate_extract -use_high_accuracy [true | false]
Extract Substrate Only
Indicates that Quantus should perform extraction of the substrate and designed devices only,
without performing parasitic extraction of the design interconnect. In this case, the output
extracted_view or Spice netlist will contain only designed devices along with the parasitic substrate
network (i.e., no parasitics will be extracted for the interconnect).
When you choose Spice or Extracted View as the output from the Setup tab and select the Extract
Substrate Only option, only the Global Frequency option is enabled in the Extraction tab. See
"GlobalFrequency". In addition, only the following options are enabled in the Netlisting tab:
Design Capacitor Models
Design Resistor Models
Netlist with Names From (only for Spice output)
Hierarchy Delimiter (only for Spice output)
Device Finger Delimiter (only for Spice output)
XY Coordinates for R, C, D, M, and Q (only for Spice output)
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Output Postprocessing File (only for Spice input)
Note: The Filtering tab is disabled when this command is selected.
All substrate extraction commands are available with this command with the exception of the Only
Generate SAV command.
Only Generate SAV
When specified, this command bypasses all parasitic extraction (interconnect and substrate) and
only generates the Substrate Abstract View (SAV) required to perform Surface Noise Distribution
analysis.
Note: This option is only valid with extracted_view output, and does not support Spice output. The
SAV will be written to an empty extracted view folder created expressly to store the output.
No other Quantus extraction commands are valid with this flow, so the Extraction, Filtering, and
Netlisting tabs are disabled on the GUI when this command is enabled.
Since this command only creates the SAV output, the following substrate extraction commands are
not available for use with this command:
Grid Control
RC Reduction
Import Netlist
Backside Connection
Die Thickness
Scale Factor
Related Command -
Quantus: substrate_extract -only_generate_sav [ true | false ]
SAV Bounding Box
By default the size of the boundary box for the Substrate Abstract View (SAV) is automatically is set
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to 10 microns outside the bounding box of the layout.
The sav_boundary_box_file may be used to specify an area much larger than the layout area.
Changing the area of the substrate will also change the values of the extracted substrate parasitics.
Note: If you specify an area smaller than the layout size, Quantus will issue a warning and the
default SAV boundary box will be used.
Extract Substrate for Devices
Use the Extract Substrate for Devices command to allow for back-gate of transistors (e.g., MOS,
BJT, ...), the substrate connection of canonical devices (drawn Capacitors, Resistors...), and the
substrate connection of all generic devices to the substrate node below the device. For generic
devices, the terminals are those connected to LVS layers that are mapped to the substrate
(example, FOX ) in the layer_setup file, or in the p2lvsfile file used for older technologies.
Support for MOS and Generic Devices in the SNA Flow
Both Quantus and SNA use the FOX layer as the division. Quantus will extract parasitic RCs above
the FOX layer; while SNA will extract parasitic RCs below the FOX layer. The FOX layer is identified in
the ICT file as the dielectric object with height 0, as shown below:
dielectric “fox” {
height 0
}
There are two actions performed by Quantus to support the SNA flow. First, the coupling
capacitances are decoupled to the substrate layer. Artificial landing electrodes are created in the
substrate layer that are named as SCbk<number>. The second action is the device’s backgates are
connected to the new nodes on the FOX layer. These nodes are named as SCbk<number>. The SNA
extraction takes in the substrate LVS layers and the access ports, and generates RC networks
connecting the access ports. The SNA flow supports both the generic devices and the MOS
devices. There are two types of generic devices, one class of generic devices are declared by the genericMos option of the Techgen -compilation command; while the other class is not declared by
the -genericMos option.
The following diagram illustrates how the MOS and generic devices are handled in the SNA flow:
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Here, D is drain, G is gate, S is source, and B is backgate.
For a standard MOS device, the substrate pin is the 4th terminal or backgate.
For generic devices that are declared using -genericMos, the substrate pins are those which
are mapped to the FOX layer in the layer_setup file. If no substrate pins are found, Quantus
will exit with an error message. One or more substrate pins are required for the -genericMos
devices.
For generic devices that are not declared using -genericMOS, the substrate pins are those
which are mapped to the FOX layer in the layer_setup file. If no substrate pins are found,
Quantus does not issue an error or warning message.
Other than the substrate pin identification, a generic device is handled identically to that of a MOS
device. Since the substrate pins are identified by the mapping to the ICT file FOX layer, the layer
mapping requires the layer_setup file. The older technologies (using the p2lvsfile file) without the
layer_setup file are not supported in the SNA flow.
The following diagram illustrates the generic device support in the SNA flow:
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For the <dev1> generic device, it is a -genericMos device, and one pin “B” is identified as the
substrate pin.
For the <dev2> generic device, it is also a -genericMos device, but no pins are identified as
the substrate pin. A fatal error will be issued.
For the <dev3> generic device, it is not a -genericMos device. In this case, no pins are
identified as the substrate pin. There will be no error or warning messages.
Note: Devices must be extracted in LVS with a backgate terminal in order to be connected to the
substrate. Refer to the Assura Physical Verification Command Reference manual, or another
appropriate manual, for more information on extractDevice commands.
When Extract Substrate for Devices is enabled, you must select the devices that you want
connected to the substrate. This is done through the use of the Select bBoxes function. This
command allows you to select multiple areas of the layout (or bounding boxes) for connection of all
devices in the selected area(s) to the substrate. Any devices not inside a bBox will not have the
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device backgate connected to the substrate network. The All button of the Select bBoxes function
allows you to select the entire area of the design.
The below figure shows two regions of the design highlighted in white (when viewed in color) to
include devices for connection to the substrate during extraction. In some cases the access port of a
device will overlap an access port of the interconnect. In those situations the access port of the
device takes precedence, and the interconnect shape is cut at the intersection of the device shape.
Select Devices From the Layout by Bounding Boxes
When you have specified the areas of the design to include for device selection, you can click OK
and have the opportunity to Save the defined regions to a bBox file which contains the coordinates
of the specified regions. In the bBox file the coordinate pairs represent the Lower-Left and UpperRight corners of a rectangular area of the design. The bBox file can have multiple regions specified,
and the regions can overlap each other. This file can be reused for future extraction runs, so you will
not need to redefine the regions of interest for subsequent runs.
Note: If the bBox file is empty, all devices will be connected to substrate because bBox does not set
any constraints. If the regions defined in the bBox file do not contain any actual devices, the
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Substrate Extraction run will continue but no devices will be connected to the substrate network.
Devices in the specified regions of the design will be extracted with connection to the substrate
network in Quantus AoT. In other regions of the design any stamping rules specified (stamp=1,2)
will be respected. See the Assura Physical Verification Developer Guide for more information on
substrate stamping.
Multifingered MOS devices are special case that are handled differently depending on how they are
defined in the 'snaSelection' section in SCparameters.cds file, as in the following two cases:
If the device definition line contains 'new' at the end of the line, each finger of the device will
have its own connection into the substrate.
If the device definition line contains 'parallel' at the end of the line, all fingers of the device will
have the same connection into the substrate.
Note: In the new Quantus AoT flow, the file SCparameters.cds is no longer used, and is replaced by
the substrateFile which is integrated into the Quantus technology directory. The substrateFile
provides a mapping between the design data and the substrate extraction technology file. For more
information, refer to the "Substrate Extraction Files" chapter of Quantus Techgen Reference
Manual.
Example:
("nmos" nil (("B")("S" "D")("G")) "default" "channel" "Resistive" "device" "Unique" 1e4
-1 0 0 "parallel")
("pmos" nil (("B")("S" "D")("G")) "nwell" "channel" "Resistive" "device" "Unique" 1e4 1 0 0 "new")
Here all the fingers of the multifingered nmos device will have the same connection into the
substrate, while the multifingered pmos device will have individual connections on each of the
fingers.
Tie Bounding Box
By default, all TIE devices are connected to the parasitic substrate network. As an alternative, this
command allows you to specify an area or areas of the design where TIE devices are connected to
the parasitic substrate network. Outside of the areas defined by the bBoxes, the TIE devices will be
connected to ideal power and ground.
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Related Command Quantus: substrate_extract -tie_bounding_box_file < filename >
Well Voltage File
In a single design, there may be cases where different nwells can have different VDD voltages (for
example core vs. I/O). From the perspective of the substrate profile, other than the well bias, there is
no difference between the nwells. This command allows you to specify a file that defines different
bias voltages for different well regions of a given well in the same layout.
The default well bias is defined in the SCparameters.cds (see "Substrate Extraction Files" in
Quantus Techgen Reference Manual). You can override the default by specifying the Well Voltage
File.
Note: In the new Quantus AoT flow, the file SCparameters.cds is no longer used, and is replaced by
the substrateFile which is integrated into the Quantus technology directory. The substrateFile
provides a mapping between the design data and the substrate extraction technology file. For more
information, refer to the "Substrate Extraction Files" chapter of Quantus Techgen Reference
Manual.
The Well Voltage File must include one or more lines specified as follows:
<power_net_name> <voltage>
Where:
power_net_name must be valid net names in the design (VDD1, VDD2, etc).
voltage specifies the bias voltage for the power net.
Related Command Quantus: substrate_extract -substrate_well_voltage_file < filename >
RC reduction​
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Use this option to enable netlist reduction for simulation, or disable it if the substrate netlist size is
too large to be reduced using either the default or fast settings. RC Reduction is very important to
reduce the size of the netlist in simulation.
Note: The results of the RC reduction command (specifically the default mode) are affected by the
Global Frequency defined on the Substrate tab (see GlobalFrequency).
When RC Reduction is set to default, the complete RC reduction is performed, accurate up to the
3x the global frequency. This mode is limited by capacity and performance.
When RC Reduction is set to fast, an express RC reduction is performed which is faster and uses
less memory than the default mode. These results are independent of the global frequency setting.
Specify off to disable RC Reduction.
Related Command Quantus: substrate_extract -reduction [ default | fast | off ]
Import Netlist
Select Enable Import Netlist to import the substrate netlist into the extracted view output as separate
R and C elements, as opposed to a referenced RC netlist. If Import Netlist is disabled a single
substrate instance is created in the current extracted view to represent all of the extracted
parasitics from the substrate.
Note: This command is only available for use with extracted_view output.
Import Netlist requires that your cds.lib or lib.defs (OA only) file defines the analogLib library,
including res and cap devices.
Related Command Quantus: substrate_extract -import_netlist [ true | false ]
The environment variable CDS_INST_DIR should not be used to define library locations in the
cds.lib or lib.defs files, when generating extracted view output using rcxToDfII.
Otherwise, Quantus will not understand the location of the library, and the Quantus run may
fail since some libraries will not be correctly located.
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Using Import Netlist will add significant run time to both the extraction and simulation of the
results, and is not recommended.
Global Frequency
The Global Frequency option is used for substrate netlist reduction (when substrate extraction is
activated).
Global Frequency should be set to the frequency of interest, or to the maximum frequency if there is
a frequency range of interest. Quantus internally calculates the Substrate Reduction
Frequency based on Global Frequency. You must specify a value greater than zero in this field. The
default is no value (a blank). If you do not specify a value, Quantus internally uses 5 GHz as the
substrate reduction frequency.
When Global Frequency is specified as greater than 0, then the substrate reduction frequency is
calculated at three times the specified value to ensure a conservative substrate
reduction result applicable over the frequency range.
Related Command Quantus: extraction_setup -global_frequency
Backside Connection
Specifies the type of backside connection.
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None does not connect the backside of the substrate.
Grounded connects the backside to the universal ground node `0'.
Connected connects the backside of the substrate to the node name specified in the
Backside Node Name field.
Related Command Quantus: substrate_extract -backside_connection [ connected | grounded | none ]
Backside Node Name
Specify the node name of the Backside Connection when Connected is specified.
Related Command Quantus: substrate_extract -backside_node_name < name >
Connection Type
Allows you to specify the capacitance per unit area of the backside connection in units of
femtoFarads per square micron (fF/um2). This field is only enabled if the Backside Connection is
specified as Grounded or Connected.
Leaving this field blank, which is the default setting, indicates no capacitance for the backside
connection.
Related Command Quantus: substrate_extract -backside_capacitive_connection < value >
Die Thickness
Specifies the thickness of the die in microns.
Select Default if you want to use the default value defined in the SCtechnology file. The
user entry field is inactive with this setting.
Select User Defined if you want to specify a value other than the default. The user entry
field is active with this setting. Enter the die thickness value in microns.
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Related Command Quantus: substrate_extract -die_thickness < value >
Scale Factor
Specifies the scale factor by which to scale the layout from drawn units to physical units. The
default value is one.
Beginning in the EXT7.1 release, the Scale Factor is changed to work the same as the
layout_scale in Techgen. A scale of less than one shrinks the design, while a scale of more
than one grows the design. This is the opposite behavior from prior releases.
You must scale the design the same amount specified in the ICT file (layout_scale) in order for
Quantus AoT to compute the substrate R and C accurately. A scale factor of less than one shrinks
the design, while greater than one grows the design.
Related Command Quantus: substrate_extract -scale_factor < value >
Log Files
All log messages, warnings, errors, and information related to the substrate model extraction and
the netlist reduction are redirected to the Quantus log file and can be viewed in the same log
window.
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6
Quantus Substrate AC Analysis
Introduction
The Substrate Abstract View
Running Quantus Substrate AC Analysis
Quantus Substrate AC Analysis Menu and Form
Load Substrate Abstract View Form
Defining Details of the Design
Backside
Global Package Impedance
Define Region
Define Access Ports
Define External Nodes
Search
Saving the Substrate Abstract View
Surface Noise Distribution Analysis
Surface Noise Distribution Analysis
Computing a Surface Noise Distribution
Perturbing Path Analysis
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Introduction
Quantus AoT offers Substrate Surface Noise Distribution (SND) for AC analysis, generating visual
displays of the surface noise. SND computes the surface noise distribution of the three-dimensional
substrate model generated by the Quantus AoT Substrate Extraction engine (see the Substrate
Extraction chapter) and displays a color map of this distribution. SND can quickly calculate the
surface noise in several modes. It takes into account the whole substrate, but because it calculates
the noise distribution only for the surface, it can reduce the model from three dimensions to two. You
must identify one or more perturbing objects before using the surface noise distribution tool.
​ ​You can display the distribution of the surface potential generated by a perturbation. You can
consider one or two specific perturbing nodes at the same time. You can also introduce a phase
shift between the perturbing sources.
The input for the surface noise distribution analysis is given by one or two selected perturbing
nodes and applied voltages. Surface potentials are classified into ten discrete subranges and color
mapped across the design. You can perform what-if analysis on the design by comparing results at
different frequency points or employing different layout topologies.
The Substrate Abstract View
The Surface Noise Distribution tool requires the use of the Substrate Abstract View (or SAV)
created during the Quantus AoT Substrate Extraction run. The Only Generate SAV command on the
Substrate Extraction tab allows you to create the SAV required by SND without having to complete
a full substrate extraction on the design (see "Only Generate SAV").
​ ​ ​The information in the Substrate Abstract View determines the object interactions (access ports,
including well and substrate ties, sensitive and perturbing nodes) as well as the surface mesh.
Example of Surface Mesh
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​ ​ ​For the visual analysis, selecting the design's perturbing and sensitive sections is a particularly
critical task when you generate a Substrate Abstract View. Determining whether a section is
perturbing, sensitive, or neither depends on many factors. For example, the main parameters that
determine whether a digital transistor is perturbing include size, frequency, and efficiency of
grounding. Because of the complex and changeable nature of this data, it is impossible to form a
selection rule for perturbing sections. Similarly, the sensitivity of an analog design to noise depends
on load impedances, cell geometry, and shield efficiency. Sensitive parts cannot be defined in a
systematic way for perturbing sections. Moreover, the definition of perturbing or sensitive sections
depends on the specifications.
​ ​ ​ ​ ​To create an abstract view from the layout, Quantus AoT first automatically marks the regions
and the substrate and well ties. Next, you must identify the objects connected to sensitive and
perturbing nodes. The figure below presents an abstract view generated from the layout of an
operational amplifier. The sensitive section is represented by the differentiainput pair of the
operational amplifier. A large tap is added to indicate the perturbing section.
Operational Amplifier Layout (a) and Corresponding Abstract View (b)
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​ ​The Substrate Abstract View includes geometrical and electrical information. The geometrical
information is denoted by the position and size of each box. The extractor uses this data to generate
the surface mesh. A Substrate Abstract View includes the following:
Regions characterized by the well potentials. The extractor uses this data to determine the
potential applied to the well-substrate junction and to compute the well-substrate
capacitances.
​ ​Well and substrate taps, or access ports characterized by the vertical doping profile. The
vertical doping profiles provide resistance values for each small volume of the substrate.
Quantus AoT applies rules that automatically recognize regions and taps. You declare these
as rules in the SCparameters.cds file.
In the new Quantus AoT flow, the file SCparameters.cds is no longer used, and is
replaced by the substrateFile which is integrated into the Quantus technology
directory. The substrateFile provides a mapping between the design data and the
substrate extraction technology file. For more information, refer to the "Substrate
Extraction Files" chapter of Quantus Techgen Reference Manual.
​ ​ ​ ​ ​ ​ ​External connection information includes type (resistive, capacitive, or none for dummy
objects), connected layer (for polysilicon, metal, and device), and electrical node number.
Each external node must be characterized by a type and an external characteristic. The type
is either grounded, perturbing, or sensitive. The perturbing nodes are characterized by the
level of noise injected into the substrate, and the sensitive nodes are qualified by the
equivalent external impedance seen at that point.
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Running Quantus Substrate AC Analysis
Surface Noise Distribution (SND) analysis requires the user to open an extracted view generated
by Quantus AoT, or created using the Only Generate SAV command of the Substrate Extract tab
(see the Substrate Extraction chapter).
You must first open the extracted view from within Virtuoso, then execute the Quantus SND
Analysis command from the Assura or Quantus menu.
When running the SND analysis, the extracted view must be opened in the edit mode. The
SND results (which includes the SNA region and access port shapes) are then written into
the extracted view on special layers. This causes the extracted view to be modified. The
modified extracted view should not be saved because it will corrupt the view. You must
ensure that the Quantus Substrate AC Analysis form should be closed before closing the
extracted view. This will revert the extracted view to its original state.
Quantus Substrate AC Analysis Menu and Form
This will open the Quantus Substrate AC Analysis form, where you will configure and execute the SND
command. The form is initially blank with only two command options.
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Close to close the form, and Load SAV to open the Substrate Abstract View required for the AC
analysis.
Load Substrate Abstract View Form
Use the Load SAV form to specify the name of the SAV file to open for analysis. There may be one
or more selections, depending on the results of any prior substrate extraction runs. The SAV
created during substrate extraction is automatically given the same name as the extracted view
defined during the Quantus run (see Extracted View Output). In addition, as is discussed later, you
may save modifications to the SAV file for use in later AC analysis runs, allowing you to do some
what-if analysis on a design.
The first time a SAV is loaded, you must point to the Quantus Technology Directory that was used
during the Quantus AoT extraction, as well as the Substrate Tech Dir. This information is defined in
the technology settings of the Define tab (see Technology Settings).
When the SAV has been selected, press OK to close the form, and load the Substrate Abstract
View for AC analysis. This causes the Quantus Substrate AC Analysis form to be populated with
two tabs:
Define to set general parameters for the AC analysis, as well as modify some of the properties of
the Substrate Abstract View (see the figure, "Define Tab of Quantus Substrate AC Analysis Form"),
and
Surface Noise Distribution to select specific nodes and execute the surface noise distribution
analysis (see the figure "Surface Noise Distribution tab of Quantus Substrate AC Analysis form").
Note: Starting with the 11.1 release, when an SAV is loaded by Quantus, SND plot associated with
the SAV, if any, is automatically displayed. You may use the Hide/Show SND toggle switch to hide
the SND plot in the Virtuoso editor. In addition, parameters such as frequency, color map, phase
shift, and visualization units associated with the SND run are also displayed under Surface Noise
Distribution tab of the Quantus Substrate AC Analysis UI when the SAV is loaded.​
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Defining Details of the Design
Define Tab of Quantus Substrate AC Analysis Form
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On the Define tab of the Quantus Substrate AC Analysis form there are several fields for performing
general setup of the device package including backside connection and bonding wires. In addition,
there are commands to modify or add details to the open Substrate Abstract View such as Define
External Nodes, Define Access Ports, and Define Region.
Backside
Defining the Backside Connection
​ ​ Connection specifies the type of backside connection.
None
Does not connect the backside of the substrate.
Grounded
Connects the backside of the substrate to node 0. When the backside connection is of
type Grounded, the AC Analysis External Impedance is not specified.
Connected
Connects the backside of the substrate to a node other than node 0. When the backside
connection is of type Connected, the AC Analysis External Impedance can be
specified.
Note: The actual Connected node is not important since no netlist is output by the AC
analysis. This is different from substrate extraction, which does require you to specify an
actual node name.
Connection Type specifies whether the substrate backside connection is resistive or
capacitive. The Connection Type field appears when the backside connection is set to
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Grounded or Connected.
Resistive
Assumes a perfect metallic backside.
Capacitive
Enables you to enter the capacitance per unit area of the backside, in units of
femtofarads per square micron.
AC Analysis External Impedance
​ ​ Inductance
​ ​Specifies the inductance value of the bonding wire connected to the backside.
​ ​ Resistance
​ ​Specifies the resistance value of the bonding wire connected to the backside.
Global Package Impedance
Details of the Global Package Impedance
Inductance
Specifies the inductance value of the bonding wire that could be connected to an access port.
Resistance
Specifies the resistance value of the bonding wire that could be connected to an access port.
Technology Settings
The Define tab of the SND Run Form provides a section to define the technology settings for the
substrate technology files required by SND. These fields are automatically stored when the SAV is
saved, and loaded when an SAV is opened.
When the Quantus software is run, a text file named CCLFile, is automatically created in the
extracted_view directory. The file contains the CCL commands used for the Quantus Run. If the
CCLFile exists in the extracted_view directory, then the Quantus Substrate AC Analysis GUI PreForm (Technology Directory Location) is automatically pre-populated with the appropriate
information from the file. The Quantus Substrate AC Analysis form (see the figure, "Defining the
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Technology Settings") is automatically populated by the CCLFile information as well. Note that if
the CCLFile is not found, you will have to add the details manually. If changes are made to
the Quantus Substrate AC Analysis form (see the figure, "Define Tab of Quantus Substrate AC
Analysis Form"), then these changes are saved when the Save SAV button is pressed, and are
loaded automatically the next time the SAV is opened (overriding the CCLFile information).
The equivalent CCLFile commands for the GUI options are given below:
Option
Name
CCLFile Commands
Quantus
Tech Dir
process_technology -technology_library_file <filename> technology_name <techname>
Substrate
Tech Dir
process_technology -substrate_technology_directory <tech_dir>
Tech Dir
Name
process_technology -substrate_technology_file <extension>
Tech File
Name
process_technology -substrate_technology_name <tech_name>
Grid Control
substrate_extract -grid_control <value>
Die
Thickness
substrate_extract -die_thickness <value>
Scale Factor
substrate_extract -scale_factor <value>
Note: This feature has been validated for Virtuoso version 5.10.41_USR6.
Note: The extracted_view cannot be named CCLFile.
Defining the Technology Settings
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Quantus Tech Dir
Technology selector populated with the Quantus technology directory associated with the
currently opened SAV.
Substrate Tech Dir
The Substrate Tech Dir field will be populated by the the Substrate Tech Dir field of Quantus
Parasitic Extraction Setup Form or environment variable $SUBSTRATESTORMSITE. However, if
both the environment variable $SUBSTRATESTORMSITE and the Substrate Tech Dir field of
Quantus Parasitic Extraction Setup Form are not specified, Quantus UI will check whether the
substrate_techdir fixed directory exists in the Quantus Technology directory and will
automatically update the Substrate Tech Dir field. As a result, the Substrate Tech Dir field will
be grayed out in the Quantus Parasitic Extraction Run Form, and will point to the directory
substrate_techdir. substrate_techdir will contain sub-folders for technology names, and
each technology name folder will contain the substrate technology file. Quantus will first
search for substrate_techdir in the main Quantus technology directory, and if not found, then
it will search for substrate_techdir in the corner technology directories.
The substrate technology selection in Quantus Parasitic Extraction Run Form will have the
priority order as follows:
Substrate Tech Dir field in Quantus UI Setup Form
SUBSTRATESTORMSITE environment variable
substrate_techdir fixed directory
If the above options are not used, then you can manually specify the technology directory by
clicking the browse (...) button.
Tech Dir Name
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Technology selector populated with subdirectories from the SNA Tech Dir.
Tech File Name
The substrate technology file (SCtechnology.*) is generated by snatct. It includes all the
technological process information for regions, cross-sections, interface layers, and their
electrical parameters. See Quantus Substrate Technology Characterization Manual for
information on generating this file.
Grid Control
The Grid Control command allows you to select the extension for one of the SCparameters.xtr
files that may be found in the specified SNA Tech Dir Name directory. The extension file
contains advanced directives for the substrate extraction engine (see "Substrate Extraction
Files" in Quantus Techgen Reference Manual).
Die Thickness
Specifies the thickness of the die in microns.
Select Default if you want to use the default value defined in the SCTechnology file. The
user entry field is inactive with this setting.
Select User Defined if you want to specify a value other than the default. The user entry
field is active with this setting. Enter the die thickness value in microns.
Scale Factor
Specifies the scale factor by which to scale the layout from drawn units to physical units. The
default value is one.
The Scale Factor is changed to work the same as layout_scale in Techgen. A scale of less
than one shrinks the design, while a scale of more than one grows the design. You must scale
the design the same amount as specified in the ICT file (layout_scale) in order for Quantus
AoT to compute the substrate R and C accurately. A scale factor of less than one shrinks the
design, while greater than one grows the design.
Define Region
Substrate regions are automatically defined by Quantus AoT during the substrate extraction run that
generates the Substrate Abstract View. Regions that Quantus AoT automatically recognizes and
computes are defined by the snaRegions section of the SCparameters.cds file of the specified
technology. See the Substrate Extraction chapter for more information on creating this file.
Use the Define Region command to add new regions, or change the properties of existing regions
in the SAV. The specified bias potentials are applied to the well-substrate junctions in selected
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regions. When the Define Region form is open, you can select a region to modify in the Virtuoso
layout editor. You can also create new regions using the Virtuoso editing capabilities and define the
region properties.
Region Definition Form
​ Substrate Bulk Bias
Sets the default voltage for the substrate. This is a default value, and is not applied for specific
regions, but rather across the whole substrate. Changing this value changes the substrate
bias for the whole substrate.
Region
Selects the type of region. The list of defined regions is taken from the snaRegions section of
the SCparameters.cds file.
​ Bias Potential
Determines the well-substrate junction potential used during extraction. Use this field to check
or set the correct bias potential for the junction (may be several junctions) of the selected
region.
​ Junctions
Shows the number of p-n junctions from the surface of the substrate to the lowest junction.
This field is read-only.
​ Bias Node
​ ​ ​ Quantus AoT automatically chooses the bias node from those defined in the snaRegions
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section of the SCparameters.cds file. The Bias Node command allows you to choose a
different node for the junction.
Drawing New Regions
To add a new region to the Substrate Abstract View, follow these steps:
1. Display the Substrate Abstract View in the Virtuoso editing window by turning on the
appropriate layers as defined in the snaLayersAndPurposes section of the SCparameters.cds
file. See "Substrate Extraction Files" in Quantus Techgen Reference Manual.
2. Select the layer reserved for regions as defined in the snaLayersAndPurposes section of the
SCparameters.cds file.
3. ​ ​ Select Create - Rectangle or Create - Polygon.
4. Draw the region shapes of interest in the display panel. When you draw new regions, observe
these rules as illustrated in the below figure.
​ ​ Do not overlap different regions (see #1 in the below figure). If overlapping
shapes is needed for drawing purposes, merge these objects into a single region
by using the Edit - Merge command (see #2 in the below figure). This restriction
applies to access ports as well.
Access ports can be fully contained within a region, but no intersection is
supported (see #3 in the below figure).
Drawing Rules for Regions and Access Ports
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5. Use the Edit commands to reshape, move, merge, or delete the regions.
6. Press Escape to leave edit mode, and Select the newly created region.
7. Apply the appropriate properties to the region by setting the Define Region form as needed,
selecting the region, and pressing Apply.
Define Access Ports​
Quantus AoT uses access ports during the extraction sequence to determine the surface mesh, the
vertical doping, and the number and types of connections to external electrical nodes. Access ports
have many purposes:
They are part of the design where a coupling between the circuit netlist and the substrate
netlist will be defined (the connection can be resistive, capacitive, or none).
​ ​ ​ ​ They are linked to external nodes in the circuit netlist. For example, each of the substrate
taps is defined as an access port. All these access ports are linked to the VSS node. Nodes
can be perturbing, sensitive, or grounded.
​ ​ ​ ​ ​ They split the global regions into several local regions, so they can be used to refine the
surface mesh.
You can define access ports in two ways:
​ ​ ​ ​ Quantus AoT can automatically recognize and generate access ports when it creates the
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Substrate Abstract View. Access port parameters are automatically assigned from the
snaGeneration section of the SCparameters.cds file for the corresponding technology. The
access port parameters are as follows:
Recognition layer
Associated region and cross-section (doping profile)
External connection type
External connection layer
​ ​ ​N ode type and physical parameters like impedance, number of bonding wires, and
noise values for the surface noise distribution analysis
​ ​You can draw access ports by using the Edit commands in Virtuoso. These access ports are
uncharacterized when first drawn. You must set the appropriate parameters of any access
ports you add by drawing.
The Define Access Port command enables you to check and to modify the properties of access
ports. This command activates the Access Port Definition form. When the form is open, click on an
access port to modify it.
Access Port Definition Form
The Access Port Definition dialog box is divided into two parts:
Substrate Structure
Corresponds to the vertical substrate profile attached to the selected access port.
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Region
This field is related to the defined regions of the substrate and is automatically updated
according to the snaGeneration rules in the technology's SCparameters.cds file. For
access ports that you drew using the Virtuoso editing capability, the region is
automatically recognized according to the area where you draw the access port.
Cross-Section
Changes the type of doping profile associated with the access port. The list of available
cross-sections is determined according to the snaGeneration rules in the technology's
SCparameters.cds file. For access ports that you drew using the Virtuoso editing
capability, the cross-section is set to the default.
External Connection
​ ​ ​Sets the parameters of the connection between the substrate and the ideal circuit for the
access port.
​ ​ Type
Specifies the connection type for each access port.
​ ​ None
​ ​D isconnects the access port, so there is no connection between the substrate and
the ideal netlist at this location.
​ ​ Resistive
Makes a resistive connection between the substrate model and the ideal netlist at
this location. Quantus AoT uses a resistor to model this connection.
​ ​ Capacitive
Makes a capacitive connection between the substrate model and the ideal netlist
at this location. Quantus AoT uses a capacitor to model this connection.
​ ​ Layer
​ ​Lists the interface layers taken from the SCtechnology file of the related
technology. For access ports that you drew using the Virtuoso editing capability,
you must define an external connection layer from the provided list.
The selected layer defines the impedance of the connection to the substrate as follows:
The kind of vertical doping profile (region and cross-section) that is attached to the
access port
The interface parameters defined for the selected interface layer (see the SNA
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TCT manual)
The size of the access port
SCparameters.cds file.
Node
Displays the name of the external node that is attached to the selected access port. The
node can be changed by choosing an existing external node from the listbox or creating
a new one. For a newly created external node, the External Node Definition form is
automatically displayed to set the required parameters (see Define External Nodes).
Drawing New Access Ports
​ ou can create access ports in the layout by using the Edit menu of the Virtuoso editing window.
Y
These access ports are left uncharacterized and you must set the correct parameters. Follow these
steps to draw new access ports:
1. ​ ​ ​Select the layer defined in the snaLayersAndPurposes section of the SCparameters.cds file
that is reserved for access ports.
2. From the main menu of the Virtuoso editing window, select Create - Rectangle or Create Polygon.
3. Draw the access port shapes in the display panel. Observe the rules for creating regions and
access ports in Drawing New Regions.
4. You can use the commands on the Edit menu to reshape, copy, stretch, or move the edited
access ports.
5. Press Escape to exit Edit mode.
6. Select the newly drawn access port and assign it the needed parameters.
Define External Nodes
​ ​ ​ ​To investigate substrate coupling effects using surface noise distribution you must declare at
least one perturbing node and one sensitive node in the Substrate Abstract View.
​ ​ ​ ​Perturbing nodes are considered noise sources, that is, places where noise is injected into
the substrate. You must define a noise level for these nodes. The noise level is the main
external characteristic of a perturbing node for AC analysis. By using surface noise
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distribution, you can consider the effect of one or two perturbing nodes at a time with a
possible phase shift between the perturbing sources.
​ ​ ​ ​ ​ ​Sensitive nodes are characterized by a null noise level, but have a specified external
impedance. You must enter this impedance. It represents the equivalent impedance of the
ideal circuit seen from this node. The external impedance can support four different
topologies, as shown in the below figure:
​ Resistance (R)
​ Capacitance (C)
​ Parallel RC cell (R//C)
​ Series RC cell (R+C)
External Impedance in Series with the Package Bonding Wire
Note: For sensitive nodes, there are no noise sources. If perturbing nodes are defined as perturbing
sources during substrate analysis, package impedances do not apply.
​ ​Grounded nodes are characterized by a null noise level, null package impedance, and null
external impedance. Power supply nodes are an example of grounded nodes.
Note: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​Quantus AoT uses characteristics of external nodes when computing the surface
potential distribution generated by a specific perturbing node. The figure below shows how Quantus
AoT handles the different types of nodes. Node characteristics are only considered during the
surface noise distribution analysis. You must choose perturbing, sensitive, or grounded nodes
when you estimate the noise propagation through the substrate. This choice has no effect on the
generation of the substrate electrical model during substrate extraction.
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Setting Node Characteristics
​ The Define External Node command allows you to check and modify the characteristics of external
nodes to which the access ports or the regions are connected. It activates the External Node
Definition form shown in the below figure.
External Node Definition
​ Name
​ Lists the currently selected external node. The selection is made from the list of nodes in the
design on the right hand side of the form. The other fields of the External Node Definition form
are then populated according to the selected node's settings. Information related to these
fields is also displayed on the right hand side of the form.
​ Type
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​ ​ ​ Indicates whether the node is grounded, perturbing, or sensitive. The selection of the Type
of node determines the settings of the Noise and Impedance fields.
​ ​ When you create a new access port and connect it to a new node, the node type depends on
the snaGeneration and snaSelection rules defined in the SCparameters.cds file (see
"Substrate Extraction Files" in Quantus Techgen Reference Manual) or on the change in the
Access Port Definition dialog box, described in Define Access Ports.
​ ​ Perturbing
​ ​D efines a node whose noise value is not 0. This type of node is a noise generator
during a surface noise distribution analysis.
Note: Perturbing nodes that are also defined as Perturbing Sources during Substrate AC analysis
are not affected by bonding wire impedances.
​ ​ Sensitive
​ ​ ​D efines a node whose noise value is equal to 0, but whose impedance value is not 0.
Starting with PVE 12.1 release, the Substrate Analysis UI has been enhanced to use default value
setting on the Sensitive type.The default values are: resistance 1 ohm, and the number of binding
wires equal to 1.
Starting with PVE 12.1.1 release, the noise field is greyed out when sensitive node is selected.
​ ​ Ground
​ ​ ​D efines a node whose impedance and noise values are both equal to 0.
​ ​ Noise
​ ​ ​D efines the approximate voltage applied at a node during a surface noise distribution
analysis. You can override the default value by writing a new value in the field.
​ ​ ​ External Impedance
Sets the topology of the resistance and/or capacitance of the external impedance of the node
during analysis.
Import Quantus Impedance
Imports external impedance from a Quantus extracted view to perform Quantus substrate
AC analysis for a node. This option is mutually exclusive with the user-defined Topology
field. This is greyed out if the extracted view does not contain interconnect parasitics.
When the external node is a original LVS net (that is, a non-SCbk* node name), the
Apply to all button on the right becomes available as well. And whenever the user clicks
on the Apply to all, the current status (yes/no) of the Import Quantus Impedance will be
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propagated to all external nodes.
​ Topology
​ Defines how the selected external node is connected to the substrate during the
analysis (see the figure, "External Impedance in Series with the Package Bonding
Wire"). You can choose from the following:
​ R
​ Loads the external node by resistance during AC analysis.
​ C
Loads the external node by capacitance during AC analysis.
​ R//C
Loads the external node by resistance and capacitance in parallel during AC
analysis.
​ R+C
Loads the external node by resistance and capacitance in series during AC
analysis.
​ Resistance
​ ​ Defines the equivalent resistance seen from the external node during a surface noise
distribution analysis. You can override the default value by writing a new value in the
text field.
​ Capacitance
​ ​ Defines the equivalent capacitance seen from the external node during the surface
noise distribution analysis. You can override the default value by writing a new value in
the text field.
​ Package Parasitics
Number of Bonding Wires
​ ​ Defines the number of bonding wires connected to the selected external node. The
maximum number that can be specified is 5. If you specify a number greater than 5, it is
reset to 5 during Substrate AC analysis. The parameter values for a bonding wire are
specified in "Defining Details of the Design".
Inductance
Defines the inductance value in nH for the selected external node.
Resistance
Defines the resistance value in ohms for the selected external node.
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Note: The package impedances are not applicable to perturbing nodes. Starting with the PVE
12.1.1 release, the package impedance fields are greyed out for all perturbing nodes. The package
impedances are also greyed out for all grounded nodes.
​ New
​ Creates a new external node. A box to enter the name of the new node appears. You are
recommended to use the SCbk### node name.
​ Rename
​ Renames only the external node created by the New function. It brings up a box in which to
enter the new name of the node.
​ Delete
​ Deletes only the external node created by the New function. You must disconnect every
access port connected to this node before deleting it.
​ Disconnect
​ ​ Disconnects all access ports attached to the selected node from the ideal netlist. Once you
disconnect the external node, you can use the Delete button to delete the external node from
the database.
Note: The values in the Type, Impedance, and Noise fields are used only when Quantus AoT
computes the surface potential distribution. They do not affect the creation of the substrate netlist or
the connection between the substrate model and the ideal circuit. However, setting grounded,
perturbing, and sensitive nodes is important for a surface noise distribution analysis.
Note: The External Node Definition form also displays columns on the right hand side of the form
that contain the following information:
Name of external node
Type of external node (Perturbing, Sensitive or Ground)
External impedance of the node (topology, R & C values)
Package impedance of the node (number of bonding wires, their R & L values if the number is
set to > 0)
Search
Search Nodes
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Search command allows you to search for an element in the design view. It activates the Search
dialog boxes shown in the above figure. The Search dialog box contains the following fields:
​ Node
​ ​ ​ Lists the external nodes available. Click on a node name to select it.
Access Port
​ ​ ​ ​ Activates the Search dialog box shown in the figure below so you can search for access
ports.
Show
​ The Show button highlights the node selection or the selected access port in the design view.
Choosing a new node name refreshes the view window and highlights the new selection.
Zoom to Shape
Zooms closely to and highlights the selected node(s) to fit the screen.
Clear
Clears the highlight(s) on the selected node(s) and fits the screen to the original size of the
design.
Previous
Zooms closely to and highlights the previous node from the list of nodes.
Next
Zooms closely to and highlights the next node from the list of nodes.
Search Access Ports
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The Access Port Search dialog box shown in the above figure contains the following fields:
​ Connection
Searches for elements that match the selected property of the connection to the substrate
(Capacitive, Resistive, or None).
​ Type
​ ​ ​ Searches for elements that match the selected property of the type of element (Perturbing,
Sensitive, or Ground).
​ Both
Searches for elements that match the selected property of the connection to the substrate and
the type of element.
Show
Highlights the selected element in the design view.
Zoom to Shape
Zooms closely to and highlights the selected element to fit the screen.
Clear
Clears the highlight(s) on the selected element and fits the screen to the original size of the
design.
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Saving the Substrate Abstract View
​ ​The Save SAV command enables you to save the Substrate Abstract View of the current analysis.
Any modifications you have made to the External Nodes, Access Ports, or Regions will be saved to
the modified SAV. This command opens the Save Substrate Abstract View form shown inthe below
figure.
Note: If you have made changes to the Substrate Abstract View, and are attempting to run the
Surface Noise Distribution analysis, you will be prompted to save the SAV prior to the analysis run.
Save Substrate Abstract View Dialog Box
SAV Name
Indicates the name of the file to save the Substrate Abstract View.
If a CCLFile is created during a Quantus run, you cannot save the SAV file with the same
name.
​ ​ Boundary
​ ​D efines the boundaries of the Substrate Abstract View. You can choose from the three
methods listed. The size of the Substrate Abstract View determines the boundary of the
design for which the substrate model is computed and therefore affects the substrate model
extraction by determining the amount of material included.
Existing
Saves the existing Substrate Abstract View from a prior SND run rather than updating it.
Note: The default SAV bounding box used by the Surface Noise Distribution (SND) analysis tool
has been modified to yield results that are more consistent with previous Quantus versions. Since
the default SAV bounding box has changed, you will need to specify the Existing option to preserve
the SAV bounding box from a prior SND run in order to compare results with an earlier release.
​ ​ CurrentView
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Saves the Substrate Abstract View in the display area in the Virtuoso editing window.
​ ​ Bounding Box
​ ​Saves the Substrate Abstract View in an automatically determined bounding box. The
bounding box is determined by the location of the different well regions and access
ports.
​ ​ Custom
Saves the Substrate Abstract View in a custom bounding box. You can either input the
coordinates of the bounding box in the corresponding text field in user units, or you can
define a selection window in the Virtuoso editing window with the Select button. In the
latter case, Quantus AoT first prompts you to left-click at the first corner of the bounding
box in the Virtuoso editing window, then on the opposite corner to define the bounding
box. The Coordinates field is automatically updated with the coordinates of the selected
window.
​ ​ Select
Defines a customized bounding box. You must select the Custom button to use the
Select button.
​ ​ Coordinates
Displays the coordinates of the bounding box of the Substrate Abstract View. The
Coordinates field is automatically updated according to the specified Boundary condition.
This field is read-only unless the Custom button is checked. The values are in user units. The
format is as follows:
((Xlower_Left Y_Lower_Left) (X_upper_Right Y_upper_Right))
OK
Saves the Substrate Abstract View with the specified filename and closes the Save Substrate
Abstract View form.
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Surface Noise Distribution Analysis
Surface Noise Distribution Tab of Quantus Substrate AC Analysis Form
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Note: If you make changes to the Substrate Abstract View prior to executing the substrate noise
distribution analysis (changes to regions, access ports, external nodes for instance) the SAV file will
be saved prior to the analysis run. Therefore, for what-if analysis you are recommended to save the
SAV file to a new name prior to running the analysis. See Saving the Substrate Abstract View for
more information.
​ ​Quantus AoT allows you to perform an AC analysis on the RC substrate model to understand how
noise flows across the surface of the chip and the path of noise between two selected points. The
substrate model used for this analysis is more detailed than the reduced netlist generated during
substrate extraction for circuit simulations. Surface noise distribution analysis does not consider any
active devices from the design; only the substrate model is used. If you have already created the
three-dimensional model of the substrate for netlist generation, the AC analysis uses that model.
Otherwise, after the Substrate Abstract View has been created, Quantus AoT performs a full
substrate extraction, then computes the AC analysis information.
Surface Noise Distribution Analysis
​ ​ ​To obtain a surface noise distribution, you must have defined at least one perturbing and one
sensitive node. The Surface Noise Distribution command displays the potential distribution
generated by the noise source located at the surface of the substrate. The result is a set of
rectangles corresponding to the surface mesh of the model, with each rectangle characterized by a
voltage potential value. The computed voltages are converted into colors, using an internal scale
with ten discrete levels. All ten layers used to display the surface noise distribution are defined in
the snaLayersAndPurposes section of the SCparameters.cds file. See "Substrate Extraction Files"
in Quantus Techgen Reference Manual.
The Surface Noise Distribution tab contains the following fields:
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General Parameters
Setting General Parameters
The General Parameters section of the form allows you to define the parameters that affect the
surface noise distribution as a whole.
SAV Name
Displays the name of the SAV file that you previously loaded with the Load SAV command.
​ Color Distribution
​ ​ Sets the type of potential distribution display. Two of these types are called dynamic
because Quantus AoT automatically calculates the color scale to give the best visual effect for
each computation (it is neither a linear nor a logarithmic scale). The other mode is called static
because the color scale is kept constant to facilitate comparisons among successive
computations.
​ Dynamic Cell
Sets the potential distribution over the whole cell. The color levels are distributed over
the entire potential range, from zero volts up to the noise level of the source.
​ Dynamic View
Sets the potential distribution over the active window of the Virtuoso editing window.
The color levels are distributed from the minimum potential value up to the maximum
potential value existing in the active window.
​ Static
Uses the color distribution file to set the color scale (see Color Map Static Values).
Color Map Static Values
​The Color Map Static Values command displays the color map file used to draw the surface
noise distribution and to customize the color map so you can compare different potential
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distribution computations. It activates the Color Map Static Values dialog box, shown in the
below figure.
Color Map Static Values Dialog Box
Note: If you run dynamic analysis, then the color map setting value is obtained from this
analysis.
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The Color Map Static Values dialog box contains the following fields:
​ Volt
​ ​ Specifies voltage values. Color ranges defined with values greater than the noise level
of the source or less than zero are not drawn on the surface noise distribution.
​ Percentages
​ Uses percentage values. For each color level, the percentage value is a percentage of
the source level. The upper limit is defined by the lower limit of the previous upper
range. The sum of all percentage values must not exceed 100.
​ dB
​ Uses decibel values. For each color level, the active noise source is set to 0.0 dB. The
decibel values indicate how much the potential has dropped compared to the noise
source. Because the substrate is a lossy medium, the noise decibel values can only be
negative.
​ Load
​ Specifies the path and the name of the color map file to load.
​ Save
​ Specifies the path and name of the file in which to save the color map. The default path
is the current directory.
​ Set Static
Stores the current color distribution in the color distribution file.
​ Frequency
Specifies at what frequency, in gigahertz, you want to compute the surface noise distribution.
​ Visualization Unit
​ Sets the unit in which to visualize the potential values. You can select volts or decibels.
Volt
Gives the potential values in volts.
dB
​ Gives the potential values, in decibels, in a logarithmic scale based on the noise value
of the perturbing node.
Amp
Visualizes the current distribution.
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Writing Out a Simulation Netlist
Prior to 12.1HF1 release, most of the items in the snasnd simulation netlist were stored in binary
format, and were not directly available for debugging. The following two netlists were available in
extracted view directory:
library/cell/av_extracted/substrate.subckt
This netlist contained substrate parasitics extracted by Quantus. It was copied from Quantus
run directory. After that, it was never changed by snasnd.
library/cell/av_extracted/subextimp.subckt
This netlist was generated when you launched Quantus Substrate AC analysis for the first
time. It contained external impedance extracted by Quantus (all nets which could be imported
from Quantus).
Typically, subextimp.subckt appeared as:
.SUBCKT SubExtImpNetVDD VDD SCbk1 SCbk2
...
.ENDS SubExtImpNetVDD
.SUBCKT SubExtImpNetGND GND SCbk3 SCbk4
...
.ENDS SubExtImpNetGND
In this example, there are two nets (VDD and GND) which are connected to substrate through
substrate terminals: SCbk1, SCbk2, SCbk3, and SCbk4.
Starting with PVE 12.1HF1 release, you can write out full SPICE netlist which contains the
following information:
Subcircuit with actual substrate parasitics which are used in SND analysis. It can differ from
above mentioned substrate.subckt because you can change the following substrate
extraction setup during SND analysis: substrate size, die thickness, mesh settings, and so on.
This new feature will allow to get either unreduced or reduced substrate subcircuit.
* Substrate subcircuit without any external/package impedances
.SUBCKT SCav_extracted SCbk1 SCbk2 SCbk3 SCbk4 SCbk5
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...
.ENDS SCav_extracted
The name of substrate subcircuit is generated as: "SC" + snasnd_run_directory .
Subcircuits with external impedances extracted by Quantus.
.INCLUDE "/full_path_to/library/cell/av_extracted/subextimp.subckt"
A separate subcircuit to encapsulate substrate parasitics and external impedances imported
from Quantus. For example,
.SUBCKT SubAndQRC VDD SCbk3 SCbk4 SCbk5
XSubExtImpNetVDD VDD SCbk1 SCbk2 SubExtImpNetVDD
XSCav_extracted SCbk1 SCbk2 SCbk3 SCbk4 SCbk5 SCav_extracted
.ENDS SubAndQRC
In the given example, VDD is imported from Quantus. XSubExtImpNetVDD is the instance of VDD
net. The instance of SubExtImpNetGND is not present because GND is not imported in this
example.
In the case when both VDD and GND are imported, subckt SubAndQRC will appear as:
.SUBCKT SubAndQRC VDD GND SCbk5
XSubExtImpNetVDD VDD SCbk1 SCbk2 SubExtImpNetVDD
XSubExtImpNetGND GND SCbk3 SCbk4 SubExtImpNetGND
XSCav_extracted SCbk1 SCbk2 SCbk3 SCbk4 SCbk5 SCav_extracted
.ENDS SubAndQRC
Additional terminal will appear if backside connection is defined. Terminal name SCbs is
reserved for substrate backside connection. For example:
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.SUBCKT SubAndQRC VDD SCbs SCbk3 SCbk4 SCbk5
XSubExtImpNetVDD VDD SCbk1 SCbk2 SubExtImpNetVDD
XSCav_extracted SCbs SCbk1 SCbk2 SCbk3 SCbk4 SCbk5 SCav_extracted
.ENDS SubAndQRC
There is no separate backside terminal if it is grounded, substrate backside will be directly
reconnected to "0" terminal. Subcircuit name "SubAndQRC" is fixed.
Substrate and Quantus instance
XSubAndQRC VDD SCbk3 SCbk4 SCbk5 SubAndQRC
User-defined external and package impedance
* User-defined R-only impedance for sensitive node SCbk3
RSCbk3_e1 SCbk3 0 1.23
* User-defined R-only impedance for sensitive node SCbk4
RSCbk4_e1 SCbk4 0 4.56
* Voltage source for the first perturbing node VDD
* (noise level = 1V)
V1 0 VDD AC 1 0
* Voltage source for the second perturbing node SCbk5
* (noise level = 2V, phase shift = 90 degree)
V2 0 SCbk5 AC 2 90
Unique names RSCbk3_e1, RSCbk4_e1 are generated automatically for impedance elements and
temporary nodes.
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AC analysis statement
For example,
* Run AC analysis for only 1 point at frequency = 5GHz
* Here it is possible to specify more points for the analysis
.AC LIN 0 5e+9 5e+9
To obtain a netlist containing this information, use following new options in the
Quantus Substrate AC Analysis form:
Options to Write Out a Simulation Netlist
Output Simulations Netlist
Allows either to switch off the output of simulation netlist or to choose unreduced or
reduced simulation netlist. It has the following values: Off, Reduced default, Reduced
fast, and Unreduced. The default value is Off.
Reduction is applied to only substrate parasitics. It is not applied to interconnect
parasitics imported from Quantus. Extracted view should be regenerated to get reduced
Quantus impedance. Unreduced should be chosen to get exactly the same netlist which
is simulated by snasnd. Snasnd doesn't work with reduced netlist because all surface
nodes and their coordinates are needed to visualize the result.
Netlist Only
Used to avoid long substrate analysis simulation. By default, this option is disabled. If it
is enabled, then substrate analysis will dump simulation netlist and exit without running
the entire simulation.
Netlist File Name
Specifies the output netlist file name.
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Perturbing Source
Selecting Perturbing Nodes for Analysis
Enables you to select noise sources to assign a node to the source.
​ ​ ​ Perturbing Source
​ Node
Lists the nodes available as perturbing sources. This option can be used to select a
perturbing node from a list of perturbing nodes. For perturbing path analysis, only one
noise source can be defined. Both surface noise distribution and perturbing path
analysis will show the same list of perturbing nodes.
​ Level
Specifies the noise level of the source, in volts.
​ Compute
​ ​ Computes the surface noise distribution according to the related perturbing source. The
Quantus AoT SND program starts to compute the surface noise distribution. The
calculated potential for each surface grid element is converted to a corresponding color.
The color scale is displayed using a surface noise color map, shown in the figure,
"Report Noise".
​ Combination Parameter
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Computes the surface noise distribution resulting from the combined effect of the perturbation
created by two different perturbing nodes from both Source #1 and Source #2.
​ Phase Shift
​ Specifies the phase shift between the two noise sources, in degrees. You must have
previously defined the two noise sources.
​ Combine
​ Computes the surface noise distribution resulting from the combination of both noise
sources. The computation includes the phase shift between the sources.
Selecting Noise Parameters
Noise at specific depth
um.
Visualizes noise distribution at the specified substrate depth Z. The value Z is measured in
Noise at the point
Visualizes noise distribution at the specified substrate surface (x, y). At this point, noise can be
visualized as the function of substrate depth Z during substrate AC analysis. In addition, for a
given point (x,y), you can also view the location of p-n junctions. The position of p-n junction is
helpful in interpreting the results correctly.
Note: In case of SOI processes, insulators are extracted in a special way, and they cannot be
visualized in the SND flow. SND visualizes noise in n or p regions, but noise in insulator layers
have zero value. For example, in the case of stack "n - insulator - p", 1D noise distribution will
have a gap between n and p regions. So noise between n and p will have zero value.
Select Point
Allows you to select a point directly in the Virtuoso window.
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Display Noise
Displays noise distribution. Before using this option, ensure that the selected point (x,y) is
inside the substrate region. If the point is outside the substrate region, a warning message is
displayed. The Display noise button opens up new window which shows the following information:
The coordinates of the point X,Y
SAV region name where the point is located (“default”, “nwell”, …)
z-position of p-n junctions for given point X,Y
Noise as function of substrate depth (1D noise distribution). Here, noise will be
displayed only in the case when SND results are available (the Compute button or the
Combine button has been already used). The Display noise button will not launch SND
analysis, that is, it will just visualize SND results if they are available.
1D noise distribution can be visualized using viva (OA) or wavescan (CDBA) functionality.
Reporting Noise, Log File, Distributed Processing, and Viewing SND
Report Noise
Generates the noise report. When you click on this button, the software prompts with the following
message, "Dump noise output to file?" The units alongside this button are in sync with those of the
selected visualization.
Dump potential to file?
The noise report generated has units for noise source in accordance with the noise source type
chosen. In addition to the "SENSITIVE NODES SECTION", the report now has "PERTURBING NODES
SECTION" that includes the noise values for all perturbing sources. The noise report contains noise
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values in both [Volt] and [Amp] irrespective of the noise source type chosen during the run.
​ ​ Display Log File
Displays a log of the transactions on the screen as your design is processed.
Hide/Show SND
Toggle switch to disable the view of the surface noise distribution analysis. When the switch
is enabled, the results are hidden in the Virtuoso editor. Disabling the switch redisplays any
previously calculated results.
Multi CPU
The Multi CPU option enables you to trigger the multi cpu support for the substrate extraction
phase of Quantus AC Noise Analysis.
Computing a Surface Noise Distribution
To compute a surface noise distribution, do the following:
1. Make sure that you defined at least one sensitive and one perturbing node in the Substrate
Abstract View before the extraction. See "Define External Nodes" for information on defining
sensitive and perturbing nodes.
In the Frequency field (see the figure, "Setting General Parameters"), select the frequency at
which you want the surface noise distribution to be computed.
2. Choose the visualization unit in the Visualization Unit field:
3. ​ ​Select the perturbing node of interest in the Perturbing Source list.
The Level field, which you can change, is updated with the characteristics of the node.
4. Change the Level value, if necessary.
5. Turn on the Display Log File button if you want Quantus AoT to display its output onscreen as
you work.
6. Click on Compute.
In a few seconds, you will also see the actual surface noise distribution visualized in the Virtuoso
editor as shown in below figure.
Visualization of Surface Noise Distribution
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Visualization of Surface Noise Distribution
​ ou will also see the legend for the different noise levels in the Color Map shown in the below
Y
figure. The Color Map shows the colors, their noise values, and the frequency of operation. All ten
layers used to display the surface noise distribution are defined in the snaLayersAndPurposes
section of the SCparameters.cds file.​
Color Map Dialog Box
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Color Map Dialog Box
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Perturbing Path Analysis
Perturbing Path Analysis Form
Quantus substrate noise distribution (SND) allows analysis of perturbing paths in the substrate. A
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perturbing path is the main path from a perturbing node to a sensitive location within the substrate.
Note: Perturbing path analysis also supports the “Import Quantus impedance” feature.
You can select the “Perturbing Path” tab on the Quantus Substrate AC Analysis form.
The General Parameters section of the form allows you to define the parameters that affect the
perturbing path as a whole.
SAV Name
Displays the name of the SAV file that you previously loaded with the Load SAV command.
Frequency
Specifies at what frequency, in gigahertz, you want to perform perturbing path analysis.
Visualization Unit
Sets the unit in which to visualize the potential values. You can select the following options:
Volt
Gives the potential values in volts.
dB
Gives the potential values, in decibels, in a logarithmic scale based on the noise value
of the perturbing node.
Amp
Visualizes the current distribution.
Perturbing Source
Enables you to select perturbing path source and target points - Perturbing Source, Target
Point.
Node
Lists the nodes available as perturbing sources. This option can be used to select a
perturbing node from a list of perturbing nodes. The functionality is the similar to that in the
“Substrate Noise Distribution” tab (see Substrate Noise Distribution Analysis). For perturbing
path analysis, only one noise source can be defined. Both surface noise distribution and
perturbing path analysis will show the same list of perturbing nodes.
Level
Specifies the noise level of the source, in volts.
Compute
Computes the surface noise distribution according to the selected perturbing path source and
target points. The Quantus AoT SND program starts to compute the surface noise distribution.
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Display Log File
Displays a log of perturbing paths on the screen as your design is processed.
Hide/Show Path
Toggle switch to disable the view of the perturbing path analysis. When the switch is enabled,
the results are hidden in the Virtuoso editor. Disabling the switch redisplays any previously
calculated results.
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7
Quantus Command-Line
Quantus Command Syntax
Quantus Command-line Options
Restarting a Quantus Extraction Run
Cell-Level Extraction
Transistor-Level Extraction
Comparing Resistance and Capacitance
Examples
Output File Formats
Quantus Compatibility Modes
Standalone Quantus UI Command-line Options
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Quantus Command Syntax
The Quantus command line syntax is given below:
% quantus [ -v | -h | -u ]
-cmd <command_file>
[-debug3264 ]
[<design_input_file> | -oa <oaLibDefFile> <oaLib> <oaCell> <oaView>]
[-drm_number <np> -drm_command <drm submit command>]
[-dump_cmd]
[-lic_queue <timeout_value>]
[-log_file <file_name>]
[-lsf_number # [-lsf_command "string"] | -multi_machine hosts | -multi_cpu #]
[-32 | -64]
[-plat <platform>]
[-restart]
[-sge_number <np> -sge_command <sge command>]
[-v3264]
Quantus Command-line Options
Help and Version
​-v
Displays the current Quantus version number and copyright
information but does not start Quantus.
​-h
Displays the available command-line parameters but does not
start Quantus.
​-u
Prints a list of command-file commands and variables but does
not start Quantus.
Multiprocessor Commands
-drm_number <np> drm_command <drm
submit command>
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This argument enables Quantus to run on distributed systems at
the same time.
The drm submit command can be started on DRM farm, such as
bsub for LSF, or qsub for SGE, with options to make sure that it
should not return until the executed program exists.
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lic_queue
<timeout_value>
Instructs Quantus to add itself to a queue to wait for an available
license. When run in distributed_processing, Quantus will wait
for the required number of licenses to become available prior to
starting the extraction run.
You can also specify a timeout value in seconds (default is 1800
seconds), which enables Quantus to wait for a license(s) for the
specified time. If the license(s) is not available within the time
specified, Quantus removes itself from the queue and issues an
error message stating that the license(s) is not available.
The default timeout value is 0. The unit of the -lic_queue option
is seconds.
The queuing sequence depends on the temporary unavailability
of the license checking sequence. For example, if L is
permanently unavailable, but XL is temporarily unavailable, then,
the queue chosen is XL. Similarly, if L is temporarily unavailable
(regardless of XL's temporary or permanent unavailability), the
queue chosen is L.
Note: If both L and XL licenses are permanently unavailable,
then Quantus will abort regardless of the lic_queue option.
To terminate a queued Quantus run use Ctrl-C to kill the Quantus
command, or for Quantus jobs run in the background use:
kill -9 <quantus_pid>
Note: Quantus does not check out RCX licenses. In addition,
license queuing does not apply to the SND flow.
-lsf_number #
The lsf_number argument applies documented features of Load
Sharing Facility (LSF). The number of jobs which can be run in
parallel is defined by value, which is specified as an integer
greater than 1.
Refer to distributed_processing for more information.
-lsf_command
string
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The default LSF prefix can be changed through the lsf_command
argument.
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-multi_cpu #
Specify this argument if the extraction run is to be performed on
single machine with multiple processors. The value is a positive
integer indicating the number of available processors on the
multiprocessor machine to allocate to the Quantus run.
Note: By default Quantus runs on two processors for multiprocessor machines since this only requires a single license.
You can limit Quantus to run on a single processor by specifying:
-multi_cpu 1
Refer to distributed_processing for more information.
multi_machinehosts
This argument enables Quantus to run on multiple machines at
the same time. The hosts file specifies a list of machines by their
hostname or IP address.
Refer to distributed_processing for more information.
-sge_number <np> sge_command <sge
command>
This argument enables Quantus to run on sun grid machines at
the same time.
Command Options and Design Files
​-cmd command_file
​Specifies the required keyword -cmd and the name of the
Quantus command file.
While Quantus also supports the RCX
RSF and QXC command languages,
you cannot mix commands from the
various languages or Quantus will exit
with an error.
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-debug3264
Prints out a minimum set of information to aid in troubleshooting
the application, including:
1. The setting of CDS_AUTO_64BIT
2. The value of the PATH updated by the wrapper
3. The value of the LD_LIBRARY_PATH (and platform specific
equivalents) updated by the wrapper
4. The exact command launched (including the binary full path
and name and the options)
5. Information is also provided about the OA mode
design_input_file
Specifies the name of the input DEF design file. You can only
specify one file on the command line.
The design_input_file is an optional input, as the Quantus
command file can also define the design data for input (see
"input_db"). The <design_input_file> argument is included for
backward compatibility, to allow existing QX command files to be
used without modification. If the DEF input is given on the
command line, this will override the input_db command in the
command file with a warning.
-log_file
file_name
Quantus writes log file information to stdout and to a file named
qrc.log. This argument directs Quantus to write the log to the
specified file_name (see "log_file").
-oa [<libDefFile>]
Specifies an OpenAccess database as input. The arguments are
the OA Library to find the cell, the OA cell name for the top-level
design, the OA viewname for the design (usually layout), and the
OA Library Definitions file for locating cells needed by the design.
The libDefFile optional argument should be the first argument if
you need to specify it.
<oaLib>
<cellName>
<viewName>
These command-line arguments are also available as commandfile commands (see "input_db").
-plat <platform>
Allows you to select the executable for another platform to run
under "cross-platform" mode.
quantus -plat lnx86
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-restart
This optional command-line control indicates that you would like
to enable Quantus to restart a cell-level extraction run in the
event of a hardware failure such as a disk or network error, after a
user abort (Ctrl-C), or in the event of certain limited changes to
the command-file.
Starting with the Quantus 15.20 release, the -restart option can
also be used to restart a transistor-level extraction. The behavior
of this option is different in the transistor-level and cell-level
flows.
See "Restarting a Quantus Extraction Run" for more information.
-32
This option is no longer supported. Specifying this option gives a
message that 32-bit version is no longer supported. So, 64-bit
version will be launched.
-64
This is the default version of the application.
-v3264
Reports the version of the Cadence application wrapper in use,
but does not run the application.
QX to Quantus Command Conversion
-dump_cmd
Takes a QX command file and outputs a Quantus command file
with the converted commands.
Restarting a Quantus Extraction Run
This option allows you to restart an extraction run:
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Cell-Level Extraction
This option allows you to restart a cell-level extraction run (with DEF or OA input) in the event of a
hardware failure, or even in the case you need to make a limited change to the command file during
the extraction run. A Quantus extraction run can be restarted from any of the following points: design
input processing, resistance extraction, capacitance extraction, or output creation. While there is no
impact to the extraction runtime due to the -restart option, there is a cost of specifying -restart in
that it increases the disk space consumed by Quantus by as much as 50%. In addition, the -restart
option must be specified on the command-line when initially launching Quantus in order for the run
to be restarted later if needed. For this reason, you may want to consider when to use the -restart
option.
You cannot restart an extraction run after a hardware failure, unless the run was
originated with the -restart option.
The command line with -restart is as follows:
quantus - restart -cmd <command_file>
In this case, if Quantus terminates due to a hardware failure, such as a disk full error, or a network
access problem, the extraction run can simply be restarted approximately from where Quantus
terminated by executing the same command line, with the same command_file.
quantus - restart -cmd <command_file>
When restarting an extraction run, Quantus will consume the same licenses that it used when
initially starting the extraction run. In addition, you must use the same number of processors or
machines in the restarted run. You cannot change the distributed processing options or Quantus
will exit with an error.
The -restart command also supports the QX compatibility mode when specified with a QX
command file. See Quantus Compatibility Modes. However, Quantus compatibility mode and the
RSF command file are not supported.
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Command File Changes
You can use the -restart option to stop Quantus (using ctrl-C) and then make a change to the
command file to alter the output of the run prior to completion. Or you can use this feature to restart
Quantus with a new command file, to generate a new output, even after the extraction runs to
completion. In this case, you would simply specify a new command file:
quantus -restart -cmd first_run.cmd
quantus -restart -cmd second_run.cmd
The command files in this case must reference the same design, library, and technology data files.
Changes to the input data filenames will cause Quantus -restart to fail and restart extraction at the
beginning. However, if input processing has been completed, changes to the input data content
(design, library, or technology) will not be recognized by Quantus -restart, and extraction will
continue where it left off with the previously input design data.
Specific commands that can be changed under Quantus -restart are as follows:
filter_coupling_cap
-total_cap_threshold
-coupling_cap_threshold_absolute
-coupling_cap_threshold_relative
-cap_filtering_mode
output_setup
-directory_name
-file_name
-file_max_size
output_db
-type dspf | spef | coupling_cap_reports | output_incomplete_nets |
output_unrouted_nets | promoted_feedthru | unconnected_pins | oa
-units
-compressed
-pin_delimiter
-busbit_delimiter
-hierarchy_delimiter
-add_cap_prefix
-output_unrouted_nets
-output_incomplete_nets
-predefined_spef_cells_file
-use_name_map
-name_map_start_index
-output_name
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parasitic_reduction
-enable_reduction
-exclude_nets_file
Note: Changes to other commands will reset Quantus and restart extraction from the beginning.
Transistor-Level Extraction
In the transistor-level flow, the -restart option allows you to re-netlist a previously generated
xDSPF without having to re-run the entire extraction. This saves runtime on all the subsequent renetlisting runs.
The use model of the -restart option has the following steps:
1. Base Quantus run with the -restart option that contains the maximum information. This run is
a full extraction run with RCc extracted for all the nets. The first Quantus run with the -restart
option is the base run. This memory cannot be erased. The only way to erase this memory is
to start with a fresh run directory.
You can use the output_setup -delete_output_file true option to remove the output of the
first restart run for conserving disk space.
2. Subsequent runs with the -restart option that contains less information as it is a proper
subset of the base run CCL commands. Once the base run is complete, all the subsequent restart runs will refer to the base run. This run is very fast in comparison to the base run.
The subsequent restart command file must have the same command file options as the first restart
command file with the exception that:
Output file name has to be different
Log file name has to be different
Selected nets extraction can be done in any of these modes: r_only, rc_decoupled,
c_only_coupled, c_only_decoupled, or none.
Apart from only selected nets extraction, Quantus can perform selected nets extraction by dividing
layer. The selected nets are extracted only on/above/below the specified dividing layer. For detailed
information, refer to the extract -selection_dividing_layers_type section in the Quantus
Command Files chapter.
Note: The output_setup -directory_name and -temporary_directory_name options have to remain
the same as in the first restart command file.
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For example, once we extract all nets in the RCc mode in the base run, in the subsequent runs we
can extract a subset of those nets (extract -selection nets_file) in any of the following modes:
r_only, rc_decoupled, c_only_coupled, c_only_decoupled, or none. All these subsequent runs will
refer to the base RCc run. A re-netlisting request is not valid if the new request contains more
information.
This feature is supported only for the xDSPF format. Within xDSPF, hierarchical extraction is
supported. That means, the xDSPF file may contains multiple sub circuits.
Note: When the output_setup -compressed true or the output_db -type dspf -compressed true
CCL command is specified, the Transistor level extraction restart mode generates a zip
compressed output file wherein the output file name will be appended with the .gz extension.
The -restart option does not require an additional license, however, the second run license
should be identical to that of the first run. For example, if the first run was done on 8 CPUs, the
second run must be done on 8 CPUs. Similarly, if the first run used Field Solver, the second run
must also use Field Solver.
Use Model
The -restart option allows you to re-netlist in different extraction modes. You can perform multiple
subsequent restart runs based on the first restart run.
The first Quantus run must have the -restart option. The command line with -restart is as
follows:
quantus -restart -cmd <base_command_file>
The subsequent runs must also have the -restart option.
quantus -restart -cmd <restart2_command_file>
quantus -restart -cmd <restart3_command_file>
For the first run, use extract -type “rc_coupled” and -selection “all”, and the following can be
used in the subsequent runs:
r_only
r_only with -selection nets_file
c_only_decoupled
c_only_decoupled with -selection nets_file
c_only_coupled
c_only_coupled with -selection nets_file
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rc_decoupled
rc_decoupled with -selection nets_file
none
none with -selection nets_file
Note: You can specify multiple -selection nets_file option in the second run.
Examples
Valid use of restart
CCL for base run
extract \
-selection "all" \
-type "rc_coupled"
CCL for subsequent restart run
extract \
-selection "all" \
-type "rc_coupled"
extract \
-selection "nets_file ./netsfile" \
-type "c_only_decoupled" \
OR
extract \
-selection "all" \
-type "rc_coupled"
extract \
-selection nets_file "./netsfile" \
-type "c_only_decoupled"
extract \
-selection nets_file "./netsfile_2" \
-type "rc_decoupled"
OR
extract \
-selection "all" \
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-type "rc_coupled"
extract –selection nets_file “nets.file” –type “c_only_coupled” \
–selection_dividing_layers_type GT
Invalid use of restart
CCL for base run
extract \
-selection "all" \
-type "rc_coupled"
extract \
-selection "all" \
-type "c_only_coupled" \
-use_field_solver "default_accuracy" \
-field_solver_type "probabilistic"
CCL for subsequent restart run
extract \
-selection "all" \
-type "rc_coupled"
extract \
-selection "nets_file ./netsfile" \
-type "c_only_decoupled" \
Here, the CCL for the subsequent restart run is invalid because it does not include the field solver
extraction option. The valid CCL for the subsequent restart run would be as shown below:
extract \
-selection "all" \
-type "rc_coupled"
extract \
-selection "all" \
-type "c_only_coupled" \
-use_field_solver "default_accuracy" \
-field_solver_type "probabilistic"
extract \
-selection "nets_file ./netsfile" \
-type "c_only_decoupled" \
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The following is an example of the -restart mode with extract -type none for all nets in the
subsequent restart run:
CCL for base run
extract \
-selection all \
-type "rc_coupled"
CCL for subsequent restart run
extract \
-selection all
-type "none"
Fixed Voltage Decoupling
Using the -restart option, you can perform decoupled capacitance extraction on fixed voltage nets,
such as power and ground nets, to reduce the output file size. This feature allows you to perform
selective extraction by supporting a combination of coupled and lumped type of extraction.
Fixed voltage decoupling requires two Quantus runs. That is, in the base run, you need to specify
rc_coupled as the extraction mode and in the subsequent run, specify c_only_decoupled as the
extraction mode for fixed voltage nets in <nets_file>.
Note: Fixed voltage decoupling is not supported in the hierarchical extraction flow.
The following is an example of fixed voltage decoupling with multiple outputs:
quantus –restart –cmd <CCL1>
CCL1
extract \
-selection all \
-type rc_coupled \
quantus –restart –cmd <CCL2>
CCL2
extract \
-selection all \
-type rc_coupled \
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extract \
-selection nets_file <nets_file> \
-type c_only_decoupled \
In <CCL1> and <CCL2>, the input name space must match that of the output name space. For
example, if the input name space (extraction_setup –net_name_space) is “schematic”, then the
output name space (output_setup –net_name_space) must also be in “schematic” and the
<nets_file> must be specified in the schematic name space. <nets_file> in <CCL2> cannot have
wild cards.
Support for DPF File Format
The first run in the restart mode can be either of the following:
Extract all nets in the rc_coupled mode – In this case, the subsequent extraction modes can
be r_only, rc_decoupled, c_only_coupled, c_only_decoupled, and none.
Extract nets in any mode (such as r_only, rc_decoupled, c_only_coupled, c_only_decoupled)
– In this case, the subsequent extraction can only be of the type none.
Extraction with the type none yields the DPF file format. In the DPF format, Quantus prints only the
device connections but does not print the parasitic resistance and capacitance. Quantus prints the
LVS net names that are connected to the device instance pins.
The CCLs for the DPF output format are:
extract \
-selection all \
-type none
output_db –type dspf \
-net_name_space “schematic” \
<= optional
For the DPF file format, the first run can be any of the supported extraction modes, while the second
run can only be DPF (extract -selection all -type none). The following is an example of this
use model:
CCL for base run
extract \
-selection "all" \
-type "r_only"
CCL for subsequent restart run
extract \
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-selection "all" \
-type "none "
In transistor-level extraction, you can specify output netlist names for the subsequent runs
that are different from the output netlist name specified for the base run. Quantus will
accordingly save the output netlist as per the user-specified output name in the userspecified output directory.
Comparing Resistance and Capacitance
The rccompare command can be used on the command line to compare existing SPEF/DSPF files
of a design. Run the command with the names of the golden and target SPEF/DSPF files to
compare the total capacitance, coupling capacitance, and/or pin-to-pin resistance values between
the specified files for a particular design.
Note the following:
Set the Display before running the rccompare command.
The SPEF/DSPF files to be compared can be specified in the compressed format.
The two SPEF/DSPF files to be compared should have the same R unit.
The following output files are generated by default:
*.tcap - total capacitance comparison
*.ccap - total coupling capacitance
*.csv – the differences between the two specified files (golden and target) are provided in csv
file format. This makes it easier for the files to be exported to excel for comparison.
*.p2p – pin-to-pin resistance comparison
*_abs.png,*_rel.png, and *_hist.png - Absolute plot, relative plot, and histogram
For example,
compare.tcap_abs.png - absolute plot for total capacitance comparison
compare.tcap_rel.png – relative plot for total capacitance comparison
Note: Plots are not available by default in the Standalone Quantus mode.
The command has the following options:
rccompare [Options] [-spef|-dspf] base [-spef|-dspf] new
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Where,
base refers to the golden SPEF/DSPF file
new refers to the target SPEF/DSPF file
The Options listed in the table below can be specified.
Argument
Description
-log <log_file>
Specify the name of log file generated by rccompare. This file contains
information about the time and memory consumed.
-tcap
Compare the total capacitance.
-ccap
Compare the coupling capacitance.
-p2p
Compute pin to pin resistance and compare.
--use_qreduce
Use the qreduce command to compute pin-to-pin resistance comparison.
This is ON by default.
-use_spefchecker
Use spefchecker command to compute pin-to-pin resistance comparison.
-nets_file
file_name
Specify the nets file. Only output the nets in the nets file. This option is only
applicable to tcap and ccap comparison report.
-Cth thld1
[thld2 ...]
Set the threshold capacitance values (fF) for the total capacitance to
separate buckets.
Default: 4.0, 10.0, 20.0, 50.0, 100.0
-CCth thld1
[thld2 ..]
Set the threshold capacitance values (fF) for the coupling capacitance to
separate buckets.
Default: 1.0, 2.0, 4.0
-Rth thld
Check only nets in the base (golden) SPEF file with pin-to-pin resistance
greater than the specified Rth threshold (Ohms).
Default: 2.0
-Ruth thld
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Check only nets in base (golden) SPEF file with pin-to-pin resistance less
than Ruth threshold (Ohms).
Default: Inf
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-err errorbound
(%)
Set an error bound.
Default: 5%
-err2
errorbound (%)
Set a second error bound.
Default: 10%
-abs
Display absolute error in addition to percent error.
-plot
Plot figures.
-hist
Plot the histogram of errors.
-out_tcap
Customize the output file path for the total capacitance comparison. By
default, the file is saved in the current directory.
Default file name is compare.tcap.
-out_ccap
Customize the output file path for the coupling capacitance comparison. By
default, the file is saved in the current directory.
Default file name is compare.ccap.
-plot_title
title_name
Set the title for both figures.
Default: 'Percent Error (%) vs. Reference Cap Value' and 'Target vs.
Reference Cap Values'
Note: This option is used with with the -plot option.
plot_rel_xlabel
xlbl
Set x label for the 'Percent Error (%) vs. Reference Cap Value' figure.
Default: Reference Cap Value
Note: This option is used with with the -plot option.
plot_rel_ylabel
ylbl
Set the y label for the 'Percent Error (%) vs. Reference Cap Value' figure.
Default: Percent Error (%)
This option is used with the -plot option.
-plot_rel_ymax
ymax
Set the maximum y value for the 'Percent Error (%) vs. Reference Cap
Value' figure.
Note: This option is used with the -plot option.
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-plot_rel_ymin
ymin
Set the minimum y value for the 'Percent Error (%) vs. Reference Cap Value'
figure.
Note: This option is used with the -plot option.
-plot_errbound
Plot the error bound for the 'Percent Error (%) vs. Reference Cap Value'
figure.
Default: off
Note: This option is used with the -plot option.
-plot_err
errbound(%)
Set the error bound for the 'Reference Cap Value vs. Percent Error (%)
figure, which is corresponding to the specified criterion.
Default: 5%
Note: To use this option, the -plot_errbound option should be turned on.
-h, -help
Show help message.
Examples
Use the below command to compare the total capacitance between the two SPEF files and
log the time and memory consumed in the specified log file:
rccompare -tcap -log <log_file> -spef<golden>
-spef<target>
Use the below command to compare the total capacitance between the two SPEF files, plot
the figures, and log the time and memory consumed in the specified log file:
rccompare -tcap -plot -log<log_file> -spef<golden> -spef<target>
Output File Formats
Samples of output file formats are provided below.
Total Capacitance Comparison Report Sample
Default report file name is compare.tcap
Base input: /lan/csv/extpe_testout6/log/ishav/testing/quantusfs.dspf
New input: /lan/csv/extpe_testout6/log/ishav/testing/quantus.dspf
Scale Factor: 0.927973
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Cap Range | > 0 fF | > 4 fF | > 10 fF | > 20 fF | > 50 fF | > 100 fF
--------------+------------+------------+------------+------------+Nets
| 6
| 4
| 3
| 0
| 0
| 0
<5%Err(%) | 0.000 | 0.000 | 0.000
| 100.000 | 100.000 | 100.000
<10%Err(%)| 33.333 | 50.000 | 66.667 | 100.000 | 100.000 | 100.000
Mean (%) | 16.982 | -4.112 | 5.032
| 0.000
| 0.000
| 0.000
Std.Dev(%)| 58.608 | 17.607 | 8.881
| 0.000
| 0.000
| 0.000
Min (%)
|-31.544 |-31.544 | -7.351 | 0.000
| 0.000
| 0.000
Max (%)
|142.926 | 13.045 | 13.045 | 0.000
| 0.000
| 0.000
Cap Range | 0 fF ~ 4 fF | 4 fF ~ 10 fF | 10 fF ~ 20 fF | 20 fF ~ 50 fF | 50 fF ~ 100 fF
| >100 fF
--------------+-------------+--------------+---------------+---------------+---------------+----Nets
| 2
| 1
| 3
| 0
| 0
| 0
<5%Err(%) | 0.000
| 0.000
| 0.000
| 100.000
| 100.000
| 100.000
<10%Err(%)| 0.000
| 0.000
| 66.667
| 100.000
| 100.000
| 100.000
Mean (%) | 59.170
| -31.544
| 5.032
| 0.000
| 0.000
| 0.000
Std.Dev(%)| 83.756
| 0.000
| 8.881
| 0.000
| 0.000
| 0.000
Min (%)
| -24.586
| -31.544
| -7.351
| 0.000
| 0.000
| 0.000
Max (%)
| 142.926
| -31.544
| 13.045
| 0.000
| 0.000
| 0.000
Base Cap (fF) | New Cap (fF) | Abs Diff (fF) | Diff(%)| Net Name
--------------+--------------+---------------+------------+-----------------2.24077
| 5.44341
| 3.20264
|142.926 | nhvt_sip_dnw_0000003_g
17.59410
| 19.88920
| 2.29510
| 13.045 | nhvt_sip_dnw_0000003_s
15.55770
| 17.02050
| 1.46280
| 9.402 | nhvt_sip_dnw_0000003_d
14.48440
| 13.41970
| -1.06470
|-7.351 | ln_5
0.21539
| 0.16243
| -0.05295
|-24.586 | 0
4.97337
| 3.40456
| -1.56881
|-31.544 | ln_1
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Coupling Capacitance Comparison Report Sample
Default report file name is compare.ccap
Base input: /lan/csv/extpe_testout6/log/ishav/testing/quantusfs.dspf
New input: /lan/csv/extpe_testout6/log/ishav/testing/quantus.dspf
Cap Range | > 0 fF | > 1 fF | > 2 fF | > 4 fF
--------------+------------+------------+----Nets
| 9
| 7
| 3
| 3
<5% Err(%)| 33.333 | 28.571 | 33.333 | 33.333
<10%Err(%)| 66.667 | 71.429 |100.000 | 100.000
Mean (%) | 42.596 | 12.776 | 2.424 | 2.424
Std.Dev(%)| 93.574 | 36.179 | 4.601 | 4.601
Min (%)
|-10.637 |-10.637 | -4.075 | -4.075
Max (%)
|291.244 |100.273 | 5.952 | 5.952
Cap Range | 0 fF ~ 1 fF | 1 fF ~ 2 fF | 2 fF ~ 4 fF | > 4 fF
--------------+-------------+-------------+-------------+---Nets
| 2
| 4
| 0
| 3
<5% Err(%)| 50.000
| 25.000
| 100.000
| 33.333
<10%Err(%)| 50.000
| 50.000
| 100.000
| 100.000
Mean (%) | 146.967
| 20.539
| 0.000
| 2.424
Std.Dev(%)| 144.277
| 46.196
| 0.000
| 4.601
Min (%)
| 2.690
| -10.637
| 0.000
| -4.075
Max (%)
| 291.244
| 100.273
| 0.000
| 5.952
Base Cap(fF) | New Cap(fF) | Abs Diff(fF) | Diff(%) | Net Name
--------------+--------------+---------------+------------+--------------------------------------0.51176
| 2.00222
| 1.49046
| 291.244 | nhvt_sip_dnw_0000003_g
nhvt_sip_dnw_0000003_d
1.70506
| 3.41478
| 1.70972
| 100.273 | nhvt_sip_dnw_0000003_g
nhvt_sip_dnw_0000003_s
7.01108
| 7.42836
| 0.41728
| 5.952
| nhvt_sip_dnw_0000003_s ln_5
6.92337
| 7.29684
| 0.37348
| 5.394
| nhvt_sip_dnw_0000003_s
nhvt_sip_dnw_0000003_d
0.01022
| 0.01050
| 0.00028
| 2.690
| nhvt_sip_dnw_0000003_g ln_5
1.20864
| 0.00000
| -0.00000
| -0.000 | ln_1 ln_5
6.20298
| 5.95022
| -0.25276
| -4.075 | nhvt_sip_dnw_0000003_d ln_5
1.85272
| 1.71416
| -0.13855
| -7.478 | nhvt_sip_dnw_0000003_d ln_1
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1.89161
| 1.69040
| -0.20121
| -10.637 | nhvt_sip_dnw_0000003_s ln_1
Pin-to-Pin Resistance Report Sample
Default report file name is compare.p2pRes. The below report is in csv format.
Plot Samples
Histogram of Coupling Capacitance Comparison
compare.ccap.hist.png
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Histogram of Absolute Values of Coupling Capacitance Comparison
compare.ccap_abs.png
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Histogram of Relative Values of Coupling Capacitance Comparison
compare.ccap_rel.png
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Histogram of Total Capacitance Comparison
compare.tcap.hist.png
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Log File Sample
Sample log file showing details of the pin-to-pin resistance and total capacitance comparison run.
[INFO] P2P Res report:
Range (abs value percentage) | Count
-------------------------------+----0-5% | 11
5-10% | 0
10-15% | 0
15-20% | 0
20-% | 0
Mean (%): 0.000
Std. Dev. (%): 0.000
Min (%): 0.000
Max (%): 0.000
Scale Factor: 1.000
[INFO] Completed p2p res comparison at 2020-02-18 01:39:41
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[INFO] pin to pin res comparison used: 1.42s.
[INFO] p2p res Memory: 216.59
[INFO] Tcap report:
Cap Range | > 0 fF | > 4 fF | > 10 fF | > 20 fF | > 50 fF | > 100 fF
--------------+------------+------------+------------+------------+--Nets
| 6
| 4
| 3
| 0
| 0
| 0
<5% Err(%) | 0.000 | 0.000 | 0.000
| 100.000 | 100.000 | 100.000
<10%Err(%) | 33.333 | 50.000 | 66.667 | 100.000 | 100.000 | 100.000
Mean (%)
| 16.982 | -4.112 | 5.032
| 0.000
| 0.000
| 0.000
Std.Dev.(%)| 58.608 |17.607 | 8.881
| 0.000
| 0.000
| 0.000
Min (%)
|-31.544 |-31.544 | -7.351 | 0.000
| 0.000
| 0.000
Max (%)
|142.926 | 13.045 | 13.045 | 0.000
| 0.000
| 0.000
Cap Range | 0 fF ~ 4 fF | 4 fF ~ 10 fF | 10 fF ~ 20 fF | 20 fF ~ 50 fF | 50 fF ~ 100
fF | > 100 fF
--------------+-------------+--------------+---------------+---------------+---------------+-----Nets
| 2
| 1
| 3
| 0
| 0
| 0
<5% Err(% )| 0.000
| 0.000
| 0.000
| 100.000
| 100.000
| 100.000
<10% Err(%)| 0.000
| 0.000
| 66.667
| 100.000
| 100.000
| 100.000
Mean (%)
| 59.170
| -31.544
| 5.032
| 0.000
| 0.000
| 0.000
Std.Dev.(%)| 83.756
| 0.000
| 8.881
| 0.000
| 0.000
| 0.000
Min (%)
| -24.586
| -31.544
| -7.351
| 0.000
| 0.000
| 0.000
Max (%)
| 142.926
| -31.544
| 13.045
| 0.000
| 0.000
| 0.000
[INFO] Dumping detailed comparison to
/lan/csv/extpe_testout6/log/ishav/testing/compare.tcap
[INFO] Dumping scatter plots to
/lan/csv/extpe_testout6/log/ishav/testing/compare.tcap_*.png
Dumping histogram plots to
/lan/csv/extpe_testout6/log/ishav/testing/compare.tcap_hist.png
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Quantus Compatibility Modes
When Quantus is supplied a QX or RCX command file, Quantus runs in a compatibility mode that
allows it to accept technology files and command files from the older tool. In addition, there are
features in Quantus that can be executed from a QX command file, that are not available in Quantus
outside of this compatibility mode.
The following are some possible compatibility use models.
To run Quantus In QX compatibility mode with DEF input and a QX command file:
quantus -cmd <QX_command_file> <design.def>
To run Quantus In QX compatibility mode with OA input and a QX command file:
quantus -cmd <QX_command_file> -oa oaLib oaCell oaView oaLibDefs
To output a Quantus command file from a QX command file:
quantus -dump_cmd <QX_command_file> <quantus_command_file>
To Run Quantus in RCX compatibility mode with Assura LVS input and an RCX RSF:
quantus -cmd <RCX_command_file>
quantus <RCX_command_file>1
Example
The following example demonstrates invoking Quantus with OA as input specified on the
command-line. In this example defoalib is the design library, full_chip is the design, layout is the
cellview of the design and lib.defs is the library definition file which defines libraries that can be
used in the design.
quantus -cmd oa.cmd -oa defoalib full_chip layout lib.defs
Standalone Quantus UI Command-line Options
% quantusui [ -help | -h | -H ]
[-log filename]
[-nograph]
[-nocdsinit]
[-replay filename]
[-V | -v]
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Option
Description
-help | h | -H
Displays the available command-line options but does not start the
standalone Quantus UI.
-log
filename
Records the Quantus run form settings in the log file filename. The log
file is saved in the current working directory.
nocdsinit
Standalone Quantus skips reading the .cdsinit file.
-nograph
Starts the standalone Quantus UI in non-graphical mode
-replay
filename
opens the standalone Quantus UI in replay mode with the settings
recorded by the user in the log file filename.
Note: You can use the -replay option only when you have run the
Quantus UI with the -log filename command-line option.
-V | -v
1
Displays the Quantus version information.
The -cmd keyword is not required when running Quantus in RCX compatibility mode with an
RCX RSF.
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8
Quantus Command Files
Introduction
Format of the Quantus Command File
Case Sensitivity of Commands
Included Command Files
Quantus Command Syntax and Input Restrictions
Command File Commands
capacitance
Description
Options
device_reduction
Description
Options
distributed_processing
Description
Standard Options
extract
Description
Options
extraction_setup
Description
Options
filter_cap
Description
Options
filter_coupling_cap
Description
Options
filter_res
Description
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Options
global_nets
Description
Options
graybox
Description
Options
hierarchical_extract
Description
Options
inductance
Description
Options
input_db
Description
Options
layer_blocking
Description
Options
log_file
Description
Options
metal_fill
Description
Options
mos_diffusion_parameter_extraction
Description
Options
output_db
Description
Options
output_setup
Description
Options
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parasitic_reduction
Description
Options
process_technology
Description
Options
substrate_connection
Description
Options
substrate_extract
Description
Options for Lightly Doped Substrates
Option for Heavily Doped Substrates
Example Quantus Command Files
DEF / DSPF Flow
DF2 / SPICE flow
GDS2 / DSPF flow
Substrate Extraction Flow
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Introduction
Quantus uses a command file to define the various commands and options that define the extraction run. The command file
defines the various input files and libraries that make up the design, the output format, and the desired parasitics to extract
from the design. See "Example Quantus Command Files" . You can use any text editor to enter to define the Quantus
command file.
Format of the Quantus Command File
Lines in the Quantus command file are in the following general tcl format:
command { argument_list }
where argument_list is a list of name-value pairs. The fields in this syntax are separated by white space. Quantus
ignores blank lines.
The order of commands in the command file is significant only when commands are specified more than once. If a
command or option is repeated in the Quantus command file, the last command or option will be used.
A backslash `\' indicates that a command continues on the next line. The line must end in a backslash for line
continuation.
The backslash character must be the last character on the line, or the line will not be continued and the command file
will result in an error.
The length of a line in the Quantus command file is 4096 characters. An error will occur if a line exceeds this limit.
Quantus commands which support long input strings have a complimentary command form that accepts a file as input
instead. For instance:
extract \
-selection net < regexpr >
extract \
-selection nets_file < file >
A pound-sign character `#' at the beginning of a line indicates a comment line.
You can combine the `\' character on the preceding line with the `#' on the comment line, to create in-line comments. For
instance:
filter_coupling_cap \
# In line comment text goes here...\
-coupling_cap_threshold_relative .03 \
-total_cap_threshold 5 \
<....>
Note: in-line comments must end with a `\' for line continuation, or an error will occur.
The special characters [] (square brackets), $ (dollar sign), and \ (backslash) have special meaning in CCL command
inputs. You can use the backslash character to escape these special characters in CCL inputs so that they are
interpreted by the software as normal characters.
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Following examples illustrate how to use the backslash character to escape special characters in the CCL input given
in the string format:
use -net "fdx\[0\]" for actual net name "fdx[0]"
use -net "fdx\\\[0\\\]" for actual net name "fdx\[0\]"
use -parameter_name area "\\\$a" for actual name "\$a"
If the input is within curly braces {…}, then you do not need to escape the special characters as the CCL itself escapes
these characters:
for -net {fdx[0]}, the actual net name is "fdx[0]"
for -net {fdx\[0\]}, the actual net name is "fdx\[0\]"
for -parameter_name area {\$a}, the actual net name is "\$a"
Case Sensitivity of Commands
All keywords in the Quantus command file are case-insensitive. Keywords consist of all command and field names. However,
the command arguments are case-sensitive.
Included Command Files
​ ou can specify additional command files in the main command file using the standard TCL include command. To import
Y
additional command files, do the following:
In your main command file, enter:
include filename
filename is the name of the additional command file to be included.
You can group any number of commands in a separate file and use the include statement in your command file to add that
predefined set of commands. For example, this can be used to include a file with the necessary extraction_setup technology_layer_map commands for a specific technology.
Quantus Command Syntax and Input Restrictions
While Quantus also supports the RCX RSF and QXC command languages, you cannot mix commands from the
various languages or Quantus will exit with an error.
The following pages describe the Quantus commands available for use in a command file.
Each Quantus command is a two-level command, that includes the primary command, and various options to that commands.
In addition, each option can have one or more arguments.
Using the log_file command as an example:
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The primary Quantus command is log_file, and -file_name is an option to that command, with the specified <filename> as
an argument to the option.
Each command, or command option, also has restrictions to the types of input that it supports. For instance, some commands,
like output_db -type extracted_view, can only be used with LVS input, including Assura, Pegasus, or Calibre input as
defined by the input_db -type command.
Quantus supports both PVS and Pegasus LVS.
In order to clarify which commands and options are available for use with specific input formats, the Input Restrictions appear
in a table with the Command Syntax definition. A portion of the table for the capacitance command is shown below:
Capacitance Command Syntax Definition
Command Syntax
Input Restrictions
capacitance
-coupling [ default | advanced ]
ALL
-ground_net <netname>
LVS
On the left side the Command Syntax defines the primary command, options, and arguments for the Quantus command.
Note: In this case only a partial capacitance command is shown for illustration purposes.
On the right side, the Input Restrictions defines the inputs the command or option is restricted to as either LVS, DEF, OA or
ALL input formats.
Command File Commands
This section describes the commands available for definition in the Quantus in the command file.
List of Command-file Commands
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capacitance
Command Syntax
Input Restrictions
capacitance
-coupling [ default | advanced ]
ALL
-decoupling_factor <value>
LVS
Default value: 1
-ground_net <netname> | 0
LVS
–ground_substrate_floating_nets [true | false]
LVS
–max_checking_distance [ default | extended ]
LVS
-mode [ default | fast ]
DEF/OA
-partial_cap_blocking [ true | false ]
LVS
-substrate_fill [ auto | ground ]
LVS
-virtual_ground_net <net_name>
ALL
Description
Quantus supports three modes of parasitic capacitance extraction: coupled between nets, decoupled to a specified ground
net, or decoupled to the specific well or substrate net immediately below the interconnect.
The capacitance command is provided to allow you to specify the ground_net for decoupling capacitance. This ground_net is
required in all decoupled capacitance extractions for Assura, Calibre, or Pegasus input.
Since the filter_coupling_cap command can result in some coupling capacitance being decoupled, the capacitance
-ground_net command should always be specified (see "filter_coupling_cap" ).
In addition, the decoupling_factor allows you to apply a derating factor to the extracted decoupled capacitance to change the
results as desired. You may wish to derate the decoupled capacitance to be more conservative in your analysis for instance.
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Options
coupling [ default | advanced ]
Quantus offers an advanced coupling mode to better account for shapes beyond the nearest neighbor, or shielded
neighbors.
Note: The advanced coupling mode requires an additional capacitance model which can be added to an
existing qrcTechFile by running the Techgen -compilation command to recompile the capacitance models. If you
create a new qrcTechFile using Techgen -simulation, the models for advanced coupling mode are also created.
The advanced coupling mode only works with coupled capacitance extraction (extract -type xxx_coupled), otherwise
the capacitance -coupling command setting is ignored. It offers improved coupling accuracy in special applications,
but is not normally needed.1
Because Quantus extracts additional coupling capacitors, the advanced coupling mode requires additional runtime for
capacitance extraction, and also results in a larger output due to the added capacitors.
If capacitance -coupling advanced is specified, but the qrcTechFile does not contain the advanced capacitance
models, Quantus will issue a warning and continue execution in the default coupling mode.
decoupling_factor < value >
Decoupled capacitors are multiplied by the specified factor to enable the user to establish a more conservative parasitic
capacitance calculation if needed. This parameter is only meaningful when extract -type is set to one of
the decoupled or decoupled_to_substrate modes. The default value is 1.0.
ground_net < netname >
Specifies the net to which decoupled parasitic capacitors will be lumped in the Transistor-level flow. The ground_net
must be specified using either the layout or schematic name as defined by the net_name_space option of the
extraction_setup command (see "extraction_setup" ).
If you do not specify the ground net using this command, Quantus will determine the ground net by selecting the first net
specified with the global_nets command (see "global_nets" ). If you do not specify the global_nets command, then
Quantus will use the net defined by the Techgen -cap_ground_layer command (see Quantus Techgen Reference
Manual). If Quantus cannot locate the ground net, it displays an error.
Starting with the EXT 9.1 release, Quantus has been enhanced to choose 0, a non-existent net, as the ground node (ground_net 0). Once the non-existent net (0) is chosen, Quantus assumes some shape (in the substrate layer) as the
name of the non-existent net. The 0 net does not exist in the LVS input to Quantus (Calibre, Pegasus, or Assura).
Quantus enforces the non-existence of 0 in LVS in the data import phase.
The 0 net support is available in the Quantus transistor-level flow with SPICE, xDSPF, xSPEF, and the extracted view
format, in both flat and hierarchical mode.
Until 12.1.1HF2, the only way to define non-existent ground nets for capacitance extraction was by using the Quantus
CCL command “capacitance –ground_net “0”. Starting with the EXT 12.1.1 HF2 release, this restriction of using nonexistent ground net 0 has been removed, and now Quantus can also accept names (followed with “!” character) for nonexistent ground nets. That is, If a ground node does not exist, a user-defined name can be used that must end with “!”
character.
To enable this feature, you can use the following command:
capacitance –ground_net <ground_node_name>
For example,
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capacitance –ground_net sub!
When LVS is incomplete (that is, if the netlist comparison step was omitted during LVS), then the –
net_name_space cannot be set to schematic. Also, the output name space cannot be set to schematic. In such a case
the extracted_view output format is not available. Similarly, the global 0 or “<user_defined_name!>” feature is also not
available. When –ground_net is specified as 0 or “<user_defined_name!>", Quantus reverts to the old behavior without
any warning messages. That is, if 0 or <user_defined_name!> already exist in the name space, it is accepted as ground
net. Otherwise, Quantus will resort to –cap_ground_layers in the Techgen setup.
The following scenarios may result in error messages because of the existence of ground_net 0|<user-name!>:
a. ground_net “0|<user-name!>” is a schematic net name: The name does not exist in the schematic, but exists in
layout.
b. ground_net “0|<usr-name!>” is a layout net name: The name does not exist in layout, but exists in the schematic.
If capacitance –ground_net “0” has been defined, then the resulting extracted view has node named “0” which may have
issues with down stream simulators. In 12.1.1HF2 release, Quantus will output “gnd!”, instead of “0”, to the extracted view
when the following Quantus commands are used:
capacitance –ground_net 0
output_db –type extracted_view
In this case the ADE netlister will convert “gnd!” back to “0” for Spectre.
If the following CCL commands are used, then ADE will netlist “gnd!” as “.global 0” to Spectre:
capacitance –ground_net “gnd!”
output_db –type extracted_view
Note: The above mentioned ground_net 0 behavior for extracted view output is supported in Pegasus-Quantus and QCI
flows only. At present this feature is not supported in Assura-Quantus flow, but may be available in future releases.
Note: The -ground_net 0 option is not supported with cell-level DSPF flow. If you specify this option for the cell-level
DSPF flow, Quantus displays the following warning message:
Capacitance -ground_net 0 feature is not available with cell level dspf flow.
Note: The -ground_net 0 option is not supported with substrate extraction.
Note: For the cell-level flow with DEF or OA input, the ground net is simply assumed to be `0'.
​
ground_substrate_floating_nets [true | false]
The ground_substrate_floating_nets option converts all floating net shapes in the substrate layer to ground nets,
where the ground net is defined explicitly by the –ground_net CCL option. It can be used in both the Quantus and
Quantus FS flows. This option will help to improve the accuracy correlation against other random walk field solvers that
cannot cope with floating nets in the substrate layer. A floating net is an LVS net that is not connected to any device,
cell instance pin, primary IO pin, and probe text.
The option is supported only in the transistor-level flow for all LVS inputs and all output formats. It is supported in both
SP/DP, and single and multiple process corners.
max_checking_distance [ default | extended ]
Quantus offers extended checking distance between two wires on a layer for designs having wider wires for routing and
requiring larger checking distance. Here, the default argument results in the existing Quantus behavior of checking the
maximum spacing for capacitance computation and the extended argument allows even larger checking distance for
capacitance extraction. You must use the latest version of Techgen (EXT 14.1 and onwards).
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It is not recommended to use manually added simulation points (such as, manual_simulation_points, or
extra_simulation_points) in the ICT file/qrcTechFile. If manually added simulation points exist in the ICT file/qrcTechFile
then it will take precedence over the -max_checking_distance extended command. This feature does not require any
new license.
mode [ default | fast ]
Quantus supports a variety of capacitance modes to suit specific situations in cell-level extraction with DEF or OA input.
The fast mode offers significant performance gains at reduced accuracy for early analysis.
The standard cell-level capacitance engine can continue to be accessed with the capacitance -mode default option,
which is the default setting for this command.
Fast Capacitance
Quantus also supports a fast capacitance and resistance extraction mode for early estimation of the timing of a block of
the design for instance.
At different stages of physical implementation, designers would like to trade off different levels of accuracy and
performance for parasitic RC extraction. For example, designers may accept a rough estimation of parasitic extraction
for early cell timing as the design is being implemented, and in this case fast extraction is important. The RC accuracy is
not critical since there are unresolved issues in the design. Later, as the design nears completion, turn-around time is
still important, but accuracy for total capacitance, coupling capacitance and resistance is increasingly important
because it not only impacts the quality of the results, but also affects timing/SI closure.
In EXT8.1, the capacitance -mode fast option enables Quantus to run a faster capacitance extraction with the same
set of models, same handling of manufacturing effects, but with much faster performance.
partial_cap_blocking [ true | false ]
Currently in Quantus , when Techgen -blocking is specified with a grow value (:grow_amt), the lateral capacitance
between the blocked shapes is completely blocked even if the sized blocking shape does not completely cover both
shapes. However, the field solver will extract the lateral capacitance outside the blocking region (beyond the specified
grow value). With partial_cap_blocking set to true, Quantus will also extract capacitors outside the blocking region,
beyond the grow value, in order to make the Quantus blocking behavior consistent with the field solver.
Note: partial_cap_blocking does not support DSPF/SPEF output.
Region Blocked for Capacitance Extraction
As shown in the above figure , the field solver will extract partial capacitance between object one and object four (C 1-4),
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but will not extract any capacitance between object one and object two (C 1-2) or object three (C 1-3) since they are
completely covered by the sized-up blocking region. The blocking of C 1-4 capacitor will decrease as the grow amount is
increased, but will continue to be extracted until object four is completely blocked. However, by default in Quantus , the
C 1-4 capacitor will be completely eliminated as soon as the blocking region is grown to cover any portion of object four.
The capacitance -partial_cap_blocking command allows Quantus to extract the C 1-4 capacitor value in the same
manner as the field solver.
Note: The partial_cap_blocking only applies in cases where the Techgen
-blocking command has been specified with the optional grow_amt value. Refer to Quantus Techgen Reference
Manual for more information on this command.
substrate_fill [ auto | ground ]
You can use this option for applying substrate hole repairs. By default, this option is set to auto which selects the
nearest neighboring net. The ground option is used to select the capacitance ground net.
virtual_ground_net <net_name>
Specifies the nets to be assigned to assignable virtual ground plane. For example,
capacitance -ground_net <net_name1> \
-virtual_ground_net <net_name2>
The argument <net_name2> of the -virtual_ground_net is a string. The virtual ground net specified should be nonexistent in the schematic and layout name space. To ensure there are no name collisions, like <net_name1>, the
<net_name2> must end with the exclamation mark (!). If this rule is violated, the CCL parser errors out. The exception is
“0”, which can be specified without the exclamation mark.
By default, -virtual_ground_net will use -ground_net. Therefore, it is an optional CCL option. Note that <net_name1>
need not be reused in <net_name2>. For example, the following CCLs may be specified:
capacitance -ground_net “fsub!” \
-virtual_ground_net “top_sub!”
In the example shown below, the -virtual_ground_net option is not required.
capacitance -ground_net “0” \
[-virtual_ground_net “0”]
For details, refer to “Process” in the Creating the ICT File chapter of the Quantus Techgen Reference Manual.
Printing of Assignable Virtual Ground Plane
The printing of 2ndGND ground net depends upon the format. For example, let the first ground net specified using the
capacitance -ground_net option be “VSS”. For the SPICE/SPEF language format, the <2ndGND> is added to the.global
card and *GROUND_NETS card respectively. For the DSPF syntax, the *|GROUND_NET card is repeated.
Just as the first ground net, the 2ndGND net does not appear in the*INET section in DSPF.
For the Quantus (DEF/OA) flow, the first ground net comes from DEF input, while the 2ndGND net comes from CCL. The
SPICE format output is not available. In this flow, the GROUND_NET is not printed.
Instead, it is printed if the ground net is selected for extraction and it is printed as *|NET. If there is no blocking, the
<2ndGND> is printed as *|NET. Otherwise, it is not printed.
The table below illustrates the above example.
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xtor
SPICE
xDSPF
SPEF
.global VSS <2ndGND>
*|GROUND_NET VSS
*GROUND_NETS VSS <2ndGND>
*|GROUND_NET <2ndGND>
Cell
NA
*|NET VSS (only if selected)
*D_NET VSS (only if selected)
…
…
*D_NET <2ndGND> (conditional)
…
*|NET <2ndGND> (conditional)
…
device_reduction
Command Syntax
Input Restrictions
device_reduction
This command and all of
its options are restricted
to LVS input only.
-m_factor < value >
-m_factor_exclude_file < filename >
-m_factor_keep_res [true | false]
-m_factor_summed_widths [ true | false ]
-split_hv_mos_options
“<device_layer>,<aux_device_layer>,<width_threshold>,
<min_width>[,<m_factor_string>]:
<diffusion_lvs_layers>:<contact_lvs_layers>” “……”
“………”
-split_wide_mos [true | false ]
-split_wide_mos_options
“<device_layer>,<width_threshold>,<min_width>[,
<m_factor_string>]” “...” ...
Description
The Quantus device_reduction command offers a method to reduce the number of MOS and LDD transistors in the output
netlist by merging parallel transistors in the layout. The device_reduction command recognizes both standard MOS (and
LDD) devices (created by extractMOS, extractLDD and extractDevice namePrefix `M'), and generic MOS devices (created
by extractDevice without the use of namePrefix `M'). Please refer to the Assura Command Reference for more information
on defining MOS and LDD devices.
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To use M-Factor reduction with generic MOS devices, in addition to standard MOS and LDD devices, you must specify the
use of the -genericMos command during Techgen compilation (see Quantus Techgen Reference Manual for more
information).
This feature complements any M-Factor in the input design. The M-Factor is annotated to a transistor in schematic capture
and the resultant layout should contain "m" transistors laid out in parallel. These parallel transistors are designed such that
the parasitics from gate to gate, source to source, and drain to drain are minimal. Quantus modifies the extracted output to
contain a merged transistor with an M-Factor parameter equal to the count of merged transistors (m=n).
Transistors are merged based on the following criteria:
The devices are the same model type.
The devices share the same source/drain/gate, however they might have different backgate connections.
The devices have equal lengths (L)
and equal widths (W) when the m_factor option is specified,
or unequal widths (W) if the m_factor_summed_widths is specified.
Note: Transistors with width=0 are excluded from device_reduction.
The shortest path resistance between the source/drain/gate of adjacent devices is less than the value specified in
m_factor value .
By specifying the m_factor option, parallel transistors of equal widths (W) will be merged into one. The merged transistor is
assigned an M-Factor property that is set to the number of transistors in the merged group.
By specifying the m_factor_summed_widths option, parallel transistors of unequal widths will also be merged. The merged
transistor will have a width that is the summed width of all transistors in the group (W = ΣW), but will not have an M-Factor
(m=n) parameter added.
Devices can be explicitly excluded from the device_reduction command by using the m_factor_exclude_file option.
Device Reduction Example
The device_reduction command will examine the Length ("L") and Width ("W") parameters to determine which devices can
be merged, and it will average standard MOS parameters (AS/AD/PS/PD/NRD/NRS) for all the merged devices. However, for
non-standard parameters, a representative value is selected from one of the merged devices and applied as the value for the
non-standard parameter to the final merged device.
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In the schematic above, transistors M1 and M2 have lengths L1 and L2, and widths W1 and W2. These transistors are
connected in parallel through nets S, D, and G, where each net is a resistor network. In this example, if the following
conditions are true, then M1 and M2 are merged and the surviving transistor is assigned an M-Factor property set to 2 (m=2):
R1 + R2 < m_factor value
R3 < m_factor value
R4 + R5 < m_factor value
L1 = L2 (L1 and L2 > 0)
W1 = W2 (W1 and W2 > 0)
The merged transistor will have the following parameters in the output netlist:
m=2 (M-Factor is set to 2, the number of merged transistors)
W = ΣW/m (the average width of the devices, in this case W1 = W2)
AS and AD = ΣA/m (the area calculations are averaged)
PS and PD = ΣP/m (the perimeter calculations are averaged)
NRD and NRS = m * (1/(1/NR1 + 1/NR2))
However, if in the above example M1 and M2 have different widths (W), then the transistors will not be merged unless
m_factor_summed_widths true is specified with the device_reduction command. In that case the transistors are merged with
the following parameters:
No M-Factor is assigned
W = ΣW (the sum of the width of the devices)
AS and AD = ΣA/m (the area calculations are averaged)
PS and PD = ΣP/m (the perimeter calculations are averaged)
NRD and NRS = m * (1/(1/NR1 + 1/NR2))
The process Quantus uses for device reduction is to identify candidate groups prior to parasitic extraction, then merge based
on the parasitic resistance derived from the nets. This allows a comparison between the resistance of the nets connecting the
transistors, and the m_factor value. After transistors are merged parallel capacitors are also merged as needed.
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Options
m_factor < value >
Specify the value of the shortest path resistance between the source/drain/gate of adjacent devices. Transistors are
merged when this resistance is less than the specified value .
M-Factor Resistance Paths
As shown in the above figure, if the m_factor value is set to 350, none of the transistors will be merged due to the
resistors paths. While the resistance of the interconnect between M1 and M2 is less than the specified value of 350
ohm (R1 + R2 = 310), the transistors cannot be merged because R1 is also used in the M1 to M3 path. M1 and M3
cannot be merged because the resistance between them (R + R3 = 360) exceeds the specified m_factor value. If the
value is increased to 360, then all the transistors could be merged.
Specify a value of "infinite" to merge all parallel transistors whenever possible, regardless of
resistance. The m_factor option requires an L license in Quantus.
Note: When specifying m_factor reduction with C-only extraction, the value is always assumed to be "infinite" because
there are no parasitic resistances to consider.
To support the m_factor feature for finFET devices, the device parameter nfin= (number of fins per finger) will be
used instead of the device parameter W= (width of the device). Therefore, if the finFET device is declared as:
a generic device in the LVS deck, the m_factor feature will work automatically. In the following Techgen
syntax, you need to specify “nfin” for Wname:
-genericMos <device_recognition>,D_name,G_name,S_name:L_name,Wname,…
an element MOS in the LVS deck, then Quantus will read nfin as if it were W.
m_factor_exclude_file < filename >
Specify an ASCII file containing a list of transistor devices which should be excluded from
the device_reduction process. The transistor devices are specified by their model name as defined in the cell view of a
dfII cell, or in the SPICE model name or the device name of the extractMOS, extractLDD, or extractDevice commands.
Each transistor device is listed on a separate line in the m_factor_exclude_file, and no quotes are required around the
model names.
Example Exclude File
nfet auLvs analogLib
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pfet auLvs analogLib
m_factor_keep_res [true | false]
The m_factor_keep_res option, when set to true, preserves the shortest path source, drain, and gate resistances
between devices merged using the m_factor option, resulting in accurate parasitic results. The m_factor_keep_res
option increases the number of parasitic resistors (and corresponding capacitors) in the Quantus output but does not
have any effect on the parallel devices merged using the m_factor option.
If the technology file is created in Techgen through the delta_gate_ckt command, the m_factor_keep_res option
preserves the negative resistor values as well. For more information on the delta_gate_ckt command, refer to
Quantus Techgen Reference Manual.
Note: The m_factor_keep_res option must be used in conjunction with the m_factor option.
The m_factor_keep_res option is supported only in the transistor-level flow with all LVS front ends. It is supported for all
output formats. In addition, it is supported in the hierarchical extraction mode.
Note: The m_factor_keep_res option requires an XL license in Quantus .
m_factor_summed_widths [ true | false ]
Changes the default behavior of m_factor such that transistor devices of unequal width will also be merged and be
output to the netlist with widths summed (W = ΣW), and no M-Factor (m=n) parameter added.
With m_factor_summed_widths, the length (L) of merged transistors must be equal, but the widths do not need to be
equal. The widths of the merged parallel transistors are summed and stored in the surviving transistor. This surviving
transistor, which is arbitrarily selected from the merged group, retains its original parameters with the exception of the
new summed widths.
Note: If m_factor_summed_widths is defined in the device_reduction command file without m_factor also being
explicitly defined, then m_factor is assumed to have a value of "infinite" during the extraction run.
split_hv_mos_options “<device_layer>,<aux_device_layer>,<width_threshold>,<min_width>[,<m_factor_string>]:
<diffusion_lvs_layers>:<contact_lvs_layers>” “……” “……”
The -split_hv_mos_options specifies to split high voltage MOS devices. For wide high voltage MOSFETs devices, you
need to specify the following layers in addition to what is required for splitting regular wide MOSFETs:
Auxiliary Layer (aux_device_layer) to guide the splitting of wide finger MOSFETs. These layers are used to
facilitate measurements of the L and W device parameters. For simple device recognition layer, the auxiliary layer
is not required.
Diffusion Layers (diffusion_lvs_layers) that must be split. It should at least include the two terminal layers. In
addition, it should also include all the diffusion layers (from lvsfile) which connect the two terminal layers.
Contact Layers (contact_lvs_layers) whose shapes must be avoided during splitting of the wide high voltage
devices.
This CCL can modify or add to the existing Techgen –split_hv_mos options, however, it cannot delete the existing ones.
A high voltage MOS device can be a generic device, a MOS, or LDD, in the LVS deck. It does not have to be
declared as -genericMos in Techgen. However, if a regular MOS is of the type generic, it must be declared as genericMos in Techgen.
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Auxiliary marker shapes are required to mark the poly gate regions. The auxiliary shape is used for splitting, instead of
the gate shape in the poly layer. You must ensure that splitting the auxiliary device shapes is identical to that of the
original poly shapes. The quality of splitting depends on the quality of auxiliary device shapes. The auxiliary device
shape must be a rectangle with directions. That is, the long side corresponds to the W= side of the device; while the
short side corresponds to the L= side of the device.
The device recognition shape can be simple (rectangular) or complex (non-rectangular shapes). The auxiliary marker
layer shape should be able to provide a good cut line that cuts through the device recognition shapes and diffusion
shapes. Likewise, the cut lines obtained from the splitting can be used to cut the diffusion layer shapes and achieve the
intended splitting.
The following diagram illustrates a high voltage device (red dotted) with simple device recognition shapes, where the
auxiliary layers are optional:
The following diagram illustrates a high voltage device (red dotted) with complex device recognition shapes, where the
auxiliary layers are required for splitting:
The auxiliary device shapes are directional. It forms the cutting region in the y-direction. Objects outside the y-range are
ignored for device splitting.
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The contacts from the specified contact layers are projected to the y-range, and the cut lines are formed in the horizontal
direction. For the poly layer, the cut lines also include the top and bottom most partitions. The device recognition shape
formed by the auxiliary device layer, after splitting, may not be the original size. The new device recognition shapes are
restricted to be inside the auxiliary device layer shapes.
The following diagram shows simple device recognition shapes after splitting into 8:
The aux_device_layer shapes need not to abut or overlap the diffusion region. However, the diffusion shapes must
continue to abut or overlap the new split device recognition shapes that are generated by Quantus. This behavior is
illustrated in the following diagram:
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Here, there is one device recognition polygon (orange dashed box), while there are three <aux_device_layer> polygons
(blue dotted box). Each <aux_device_layer> polygon is split in half, and a total of six parallel devices are generated.
The six new device recognition shapes (red dashed box) are not confined within the <aux_device_layer> shapes. They
extend beyond the <aux_device_layer> shapes, but are still confined within the original device recognition layer shape.
In addition, the six new device recognition shapes are not confined to the poly gate.
If all the <aux_device_layer> shapes abut the diffusion shapes, then the <aux_device_layer> shapes will be used
directly as the new device recognition shapes for the split devices. If some diffusion shapes do not abut
the <aux_device_layer> shapes, the new larger sized version of the <aux_device_layer> shapes will be used as the
new device recognition shapes for the split devices.
You can now use the following environment variable to output two additional gate boundary cuts for the diffusion layer
splitting of HV MOS devices:
QUANTUS_SPLITWIDEMOS_ADD_2_CUTS Y
The diffusion cut lines are applied to the diffusion layer, and to all the specified companion diffusion layers. The
purpose of the two extra cut lines is to prevent diffusion shorting, as illustrated in the following diagram:
split_wide_mos [true | false ]
The split_wide_mos option, when set to true, enables the device splitting feature for the device types specified using
Techgen -compilation -split_wide_mos. The default value is false. The split_wide_mos option is supported only in
the transistor-level flow with all LVS front ends.
The supported parasitic resistance models for split wide MOSFETs are as follows:
- For poly layer, square counting method should be used, and non-geometric models cannot be used (for example, 1/3
gate factor). There will be parasitic resistors on the poly layer connecting the newly formed devices.
- For the diffusion layer, Mesh R (diffusion as a conductor in ICT file), and 0 resistivity (diffusion as a diffusion in ICT
file) are supported.
Mesh R model - the diffusion R network will be fully connected, and there will be extra electrodes from the gate to
connect to the diffusion mesh. The following diagram illustrates that after a wide MOSFET is split into 3; 2 poly gate Rs
are generated to connect them:
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When the diffusion layer is meshed, the mesh resistance network over diffusion does not change. However, instead of
interfacing with one source drain electrode, the mesh will interface with many source drain electrodes.
0-R diffusion model - the diffusion shapes will be split such that the R network over diffusions are not connected. Each
of the 3 diffusions would carry different subnodes. The following diagram illustrates that after a wide MOSFET is split
into 3; diffusion layer is fully split:
The device recognition shape will change after splitting for the 0-R diffusion model. The output netlist for the above
scenario is:
Device
D#1 G#1 S#1
B
Device@1
Device@2
D#2 G#2 S#2
D#3 G#3 S#3
B
B
In case the source/drain area of MOSFETs is not fully strapped by contacts, some cutting would be skipped or merged
back. In the below figure, instead of splitting into 3 MOSFETs with 3 gates, 3 source/drain diffusions, only 2 source/drain
diffusions are realized due to floating diffusions.
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The poly gate is always split per the splitting requirements, while the source/drain may be merged back to avoid floating
diffusion. The floating diffusion can be merged to either the left side, or the right side. The output netlist for the above
scenario is:
Device
Device@1
Device@2
D#1 G#1 S#1
D#1 G#2 S#1
D#3 G#3 S#3
B
B
B
Note: Quantus NRD/NRS feature is not supported if a device is to be split. If the NRD/NRS parameters are generated
by LVS, then they will be preserved in Quantus output.
When a wide MOSFET is split into smaller ones, the device recognition shapes are split. Originally, the MOSFET has a
device instance name, say “M1”. After splitting, the newly formed smaller devices would be named “M1@1”, “M1@2”, and so
on, where “@” is the device finger character, which is specified by the following CCL:
output_db –device_finger_delimiter string
The default device finger delimiter string is "@". The delimiter must be chosen such that it is not a character that is
already used in the LVS layout instance name. For example, Assura device instance names may have a "_#" suffix as
in avD100_1, therefore the "_" character cannot be used as the finger delimiter in this case. The device finger delimiter
string is used when multiple layout devices are mapped into a single schematic device, and when the output name
space is set to schematic. For example, this allows grouping of 4 layout MOSFETs into the original single MOSFET.
If “M1” is split into 4 smaller devices, the new device names are “M1”, “M1@1”, “M1@2”, and “M1@3”. The m_factor device
parameter is defined in LVS. After splitting, the value will be changed in the split devices, such that they would add up
to the original value.
An example of a wide MOSFET can be as follows. It is split into 4 devices, each has 25% of M= values.
M1 s g d bg model L=0.020 W=40 M=1.0 NRD=0.25 NRS=0.25 PS=0.35U PD=0.44U ...
After it is split into 4, the 4 new MOSFETs would print as:
M1
s#1 g#1 d#1 bg model L=0.020 W=40 M=0.25 NRD=0.25 NRS=0.25 PS=0.35U PD=0.44U ...
M1@1
s#2 g#2 d#2 bg model L=0.020 W=40 M=0.25 NRD=0.25 NRS=0.25 PS=0.35U PD=0.44U ...
M1@2
s#3 g#3 d#3 bg model L=0.020 W=40 M=0.25 NRD=0.25 NRS=0.25 PS=0.35U PD=0.44U ...
M1@3
s#4 g#4 d#4 bg model L=0.020 W=40 M=0.25 NRD=0.25 NRS=0.25 PS=0.35U PD=0.44U ...
Note that other device parameters “NRD=0.25 NRS=0.25 PS=0.35U PD=0.44U” do not change in the split devices.
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Recommendations for Splitting Wide MOSFETs
a) For the split MOS functionality to work correctly, proper mapping of the gate/source/drain terminal layers in the
layer_setup file is very important. For instance, the gate layer should be mapped in layer_setup, and should not
have sheet_res=0 else different split devices will be created but their gate terminals will be shorted together.
Similarly, the diffusion layer should be mapped to the ICT diffusion layer.
A layer_setup file sample for the gate layer and source/drain diffusion layers is shown below:
pro_layer=POLY ext_layer=Poly,gate_layer sheet_res=10,0.001 ;
pro_layer=SOURCE_DRAIN ext_layer=drain_layer,source_layer ;
The split MOS feature is also supported when source/drain is mapped to the substrate layer, however, you need
to specify the substrate_connection CCL command.
A layer_setup file sample for the substrate layer and source/drain diffusion layers is shown below:
pro_layer=BOTTOM ext_layer=drain_layer
pro_layer=SOURCE_DRAIN ext_layer=source_layer
The following is an example of the substrate_connection CCL command:
---------------------------------------------------------------------substrate_connection \
-remove_contact layers "none" nets "none"
-----------------------------------------------------------------------
b) For the split MOS functionality in the Assura LVS Extracted View flow, the Assura LVS rule deck should
properly use the saveInterconnect command so as to save the LVS output layers (gate/source/drain layers) for
Extracted View creation. These layers should be mapped in the layer_setup file as well. Following is the Assura
LVS rule deck sample for Extracted View creation:
saveInterconnect(( gate_layer ( "POLY" "drawing" )))
saveInterconnect( ( drain_layer “DIFF" ) )
saveInterconnect( ( source_layer “DIFF" ) )
c) For the split MOS functionality in the QCI/Pegasus Quantus Extracted View flow, the extview.rul file should
properly use the Interconnect command so as to save the LVS output layers (gate/source/drain layers) for
Extracted View creation. These layers should be mapped in the layer_setup file as well. Following is the
extview.rul sample for Extracted View creation::
interconnect gate_layer POLY DRAWING
interconnect drain_layer DIFF DRAWING
interconnect source_layer DIFF DRAWING
Note: You can use either the “net” or “drawing” purpose for the proper layer output setting in the Assura LVS rule
deck, and extview.rul. If the layer purpose is not used in the Assura LVS rule file in the saveInterconnect rule,
then Quantus will use “net” as layer purpose in output. However, if layer purpose is not used in extview.rul, then
Quantus will not output that layer.
split_wide_mos_options “<device_layer>,<width_threshold>,<min_width>[,<m_factor_string>]” “...” ...
The split_wide_mos_options option specifies to split wide MOSFETs into many smaller ones that are connected in
parallel. The CCL can be defined only once. The options of the CCL are:
device_recognition_layer is a MOS device in the LVS deck, or defined by the Techgen -compilation genericMos option.
width_threshold specifies the threshold value such that only MOSFETs wider than the specified value will be
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split into smaller ones.
min_width specifies the minimum width of the smaller MOSFETs.
m_factor_string specifies the M factor character strings. This is an optional parameter. The default value is "m".
This CCL can modify or add to the existing Techgen –split_wide_mos options, however, it cannot delete the existing
ones.
distributed_processing
Command Syntax
Input Restrictions
distributed_processing
-drm_number <np> -drm_command <drm submit command>
DEF/OA
-field_solver_config < filename >
LVS
-lsf_command < string >
ALL
-lsf_number < number >
Default value: 64
ALL
-multi_cpu < number >
ALL
-multi_machine < filename >
ALL
-sge_number <np> -sge_command <sge qsub command>
DEF/OA
-stacksize [<integer_value> | unlimited]
ALL
Description
Quantus supports several distributed processing options to speed the extraction run. The various options of the
distributed_processing command are mutually exclusive, so that lsf_number or multi_machine may be specified, but the
two can not be used together.
Multiple Quantus licenses will be required to support distributed processing across multiple machines or on multiple
processors. The number of licenses required is equal to X/2 rounded up to the nearest whole number, where x is the number
of machines or processors desired to run Quantus .
Running Quantus on four CPUs requires two licenses (4/2 = 2).
Running Quantus on five machines requires three licenses (5/2 rounded up = 3).
This means that a single Quantus extraction run executed on two processors (or two machines) is supported with a single
Quantus license (2/2=1). Because of this, the default for Quantus is to run on two CPUs in machines equipped with multiple
CPUs.
If you want to disable Quantus from running on multiple processors, you can specify the use of a single processor: 2
distributed_processing \
-multi_cpu 1
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Starting EXT15.1, the following distributed processing CCL commands are supported in the flat, macro cells, cell blocking,
and partial HRCX (with netlist=none or netlist=noSubckt control statements in the hierarchical_cell_list_file)
transistor-level flows:
distributed_processing –multi_cpu <number>
distributed_processing –lsf_number <value>
distributed_processing –multi_machine <file_name>
Standard Options
drm_number <np> -drm_command <drm submit command>
This option enables Quantus to run on distributed systems other than LSF and SGE. The -drm_number and drm_command CCL command options are not supported in the transistor-level flow.
field_solver_config < filename >
This option enables the Quantus FS massively parallel feature. The -field_solver_config option can be used for
large designs to run all nets or a large selection of nets with maximum accuracy. The option allows you to use 100’s of
CPUs for Quantus FS. The following is the use model of this option:
distributed_processing -field_solver_config <filename>
Quantus FS can be invoked in the distributed processing mode using one of the following use models:
distributed_processing -multi_cpu <no. of CPUs>
With this distributed processing mode, the massively parallel license option (QTS315) will be checked out
depending upon the availability of this license option on the license server, and also when the number of
CPUs is greater than or equal to 5.
distributed_processing -multi_cpu <no. of CPUs> -field_solver_config <filename>
When this option is used with the -multi_cpu option, Quantus will use -multi_cpu whereas Quantus FS
will use -field_solver_config. To invoke the massively parallel license options, the number of CPUs
specified in the config file must be greater than or equal to 5.
For Quantus FS massively parallel runs, it is recommended to use distributed_processing -multi_cpu
option for Quantus. The distributed_processing -lsf_command/-lsf_number/-multi_machine option for
Quantus is not recommended.
The specified field_solver_config <filename> can have the following commands:
local -processes <value> -threads <value>
network -processes <value> -threads <value> -command_line "rsh machine_name“
lsf -processes <value> -threads <value> -command_line "bsub command with LSF resource string”
The field_solver_config <filename> also supports environment variables. For example,
local -processes $NUMCPU -threads $NUMTHREADS
Multiple commands of each type and combination of commands are allowed. The recommended number of threads per
process is 32 because this results in the lowest memory consumption. If 32CPUs are not available, then you can
configure field_solver_config depending on the number of available CPUs. To use more than 32 CPUs on a single
machine, it is recommended to increase the number of processes to get optimal scaling. If the -processes option is not
specified in the config file, then by default its value is assumed to be 1.
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The following examples illustrate the FS config file for different number of CPUs available on hosts:
Single machine multi-threading example:
For 32 CPUs, you can use: local -processes 1 -threads 32
For 48 CPUs, you can use: local -processes 3 -threads 16
Multi machine distributed processing example:
For 64 CPUs, you can use:
local -processes 1 -threads 32
network -processes 1 -threads 32 -command_line “rsh <machine_name>”
For 128 CPUs, you can use:
local -processes 1-threads 32
network -processes 1 -threads 32 -command_line “rsh <machine_name1>”
network -processes 1 -threads 32 -command_line “rsh <machine_name2>”
network -processes 1 -threads 32 -command_line “rsh <machine_name3>”
You should be able to rsh to the machines specified in the network command. SSH is supported if it is passwordless login, that is, SSH is not supported if you need to enter login credentials to access the host machine.
LSF example :
For 64 CPUs, you can use:
local -processes 1 -threads 32
lsf -processes 1 -threads 32 -command_line “bsub -q quantus-big -W 10:0 -n 32 -R
'rusage[mem=50000]
span[hosts=1]‘”
For 128 CPUs, you can use:
local -processes 1 -threads 32
lsf -processes 3 -threads 32 -command_line “bsub -q quantus-big -W 10:0 -n 32 -R 'rusage[mem=50000]
span[hosts=1]‘”
As shown in the above example, the -n <number> of the bsub command should be aligned with the -threads
<number> setting. The recommended and non-recommended LSF options are:
Recommended options: -W, rusage[mem=<value>], -n, span[hosts=1]
Not recommended: -o, -e, -K, -J
The following is an example Quantus FS run snapshot from the log file:
First line
Jobs: Gives a history of all the jobs that are running, done, failed, and pending
Avg CPU shortage: Indicates average shortage of CPUs across all local/network/LSF computational resources
during the Quantus FS run. For example, if the number of CPUs requested using the -field_solver_config file is
160 and the log file indicates avg CPU shortage as 10, then the Quantus FS run actually used only 150 CPUs.
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Second line
Disk: Indicates disk usage for the temporary directory produced during the Quantus FS run. A warning message is
logged when the free disk space is smaller than the temporary directory size.
Peak RAM: peak RAM consumption across all finished/in progress Quantus FS jobs
Peak Wall: peak elapsed time across all finished/in progress Quantus FS jobs
Table
Top machines: All local and network machines are displayed. However, only the top 3 LSF hosts are shown - a)
maximum Quantus FS CPU load, b) maximum Quantus FS RAM usage (apart from a,c) , c) Least RAM free (apart
from a,b)
FS CPU load: Number of CPUs loaded by all Quantus FS processes, number of CPUs that are free, and total
number of CPUs available on the host
FS RAM usage: RAM used by all Quantus FS processes, free RAM, and total RAM available on the host
FS jobs: Indicates the number of Quantus FS jobs running, done and failed on the host
lsf_command < string >
Specifies the command to use when launching Quantus under LSF. The -lsf_command <string> defines job groups,
resource strings, and available hosts among other things. You must ensure that these LSF options are valid.
The bsub command must be explicitly stated for the lsf_command. The specified <string> must be enclosed in double
quotation marks " ", and the resource string should be enclosed in single quotation marks ' ', as shown below:
-lsf_command "bsub -o quantus.bsub.%J.out -q lnx64 -P QUANTUS:14.2:PE:build -R 'select\[(OSNAME==Linux)
&& (OSREL==EE50) && (SPEED==2700) && (OSBIT==64) && (mem>=64000)\] rusage\[mem=64000\]' "
Starting with EXT 10.1.1 HF1, support for lsf_command has also been added for LVS inputs (Assura, Pegasus, and
Calibre). In earlier releases, you had to set the LSFCOMMAND environment variable to define this option:
setenv LSFCOMMAND < string >
Note: In the Quantus transistor-level flow, you can specify LSF distributed processing using one of the following three
methods:
Through the command line. For example:
quantus -lsf_command <string>
Using the distributed_processing -lsf_command CCL option. For example,
distributed_processing \
-lsf_number <value>
-lsf_command <string>
Using the LSFCOMMAND environment variable. For example:
setenv LSFCOMMAND <string>
Note: If all three options are specified together, LSF distributed processing specified through the command line
takes the highest priority followed by the lsf_command CCL option and then the LSFCOMMAND environment variable.
lsf_number < value >
The -lsf_number option applies documented features of Load Sharing Facility (LSF). The number of jobs that can be
run in parallel is defined by value, which is specified as an integer greater than 1. The default value is 64.
Based on the requirement from the resource string (-R), the jobs will be distributed by the LSF scheduler according to
the available LSF resources. Multiple jobs may be submitted to the same machine if the available resources on the
machine meets the request for each job. As an example, "-lsf_number 10" creates 10 parallel jobs which might be
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distributed as follows:
10 jobs on a single LSF machine
Jobs 1-8 on machines 1-8, one job on each machine. Jobs 9 and 10 on machine 9
Jobs 1-5 on machine 1 and jobs 6-10 on machine 2
The number specified by -lsf_number is the total number of parallel jobs. You cannot force the LSF system not to
submit multiple jobs to the same machine with reasonable resource string -R. Similarly, you cannot specify the exact
number of LSF machines and number of CPUs to be used on each machine even with the usage of the LSF -R options,
such as 'span\[hosts=123\]' or 'span\[ptile=123\]'.
The use of LSF requires the LSF executables to be in the execution path for the shell invoking Quantus. These usually
exist at $LSF_HOME=/lsf/local/bin.
multi_cpu < number >
If the extraction run is to be performed on a single machine with multiple processors, the multi_cpu option allows
Quantus to divide the extraction run into concurrent extraction processes to quicken extraction runtimes.
The specified number is a positive integer indicating the number of available processors on the multiprocessor machine
to allocate to the Quantus run. For instance, if your multiprocessing system has 8 CPUs, you can allocate up to 8 CPUs
to the current Quantus run. If you run multiple extractions simultaneously on the same machine, you can allocate CPUs
to both jobs--for example, by allocating 4 CPUs to each of two runs.
multi_machine < filename >
This option enables Quantus to run on multiple machines at the same time. The filename specifies a list of machines
by their hostname or IP address, and is checked for validity prior to execution.
$PINGDIR indicates the path to the ping utility used to determine if a specified machine is network accessible. The
default location used by Techgen is /usr/sbin. Note: this is not the location for ping on the Linux platform.
Note: You can combine the effect of the multi_cpu option with the multi_machine option by repeating the hostname of
a machine with multiple processors in the list of machine names. For instance, if a machine has four processors,
repeating its hostname four times in the machine list will allow Quantus to utilize all four processors as needed.
Sample Machine File
alaska.usa.com
hawaii
hawaii
158.140.219.80158.140.219.80
sge_number <np> -sge_command <sge qsub command>
This option enables Quantus to run on sun grid machines. For information on launching Quantus jobs on sun grid
machines, refer to Quantus UI Setup for SGE. The -sge_number and -sge_command CCL command options are not
supported in the transistor-level flow.
stacksize [<integer_value> | unlimited]
Sets the process stacksize. The default value is unlimited. It is recommended that the default value be used unless the
machine has a limitation that unlimited stacksize cannot be used. You can also set a value but if the design is large,
Quantus may exit because of the limited stacksize. The integer_value is specified in bytes.
This option has the same effect as the Linux command, limit stacksize <value>. For more information about the linux
command, see the Linux manual.
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extract
Command Syntax
Input
Restrictions
extract
-extract_gate_diffusion_fringing_cap [ true | false ]
# Extract the transistor device fringing cap
LVS
-extract_via_cap [ true | false ]
# Include the capacitive effect of the via and contacts in
extraction
LVS
-field_solver_type [ deterministic | probabilistic ]
ALL
# Enables Quantus FS for transistor level extraction
-inductance_nets_file <filename>
LVS
# Define nets for inductance extraction
-selection
[ all |
def_special_nets | all_pg_nets |
def_regular_nets |
def_mustjoin_nets |
ALL
DEF/OA
DEF/OA
DEF/OA
DEF/OA
ALL
LVS
LVS
net <regexpr> |
nets_file <filename> |
instances_file <filename> |
selected_path_file <filename>]
-selection_dividing_layers_type [ LT | LE | GT | GE ]
LVS
–selection_layers “<layer_set1>” “<layer_set2>” …
LVS
-substrate_nets_file <filename>
LVS
# Extract the substrate under the specified nets
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-type
[ none |
substrate_only |
r_only |
c_only_decoupled |
c_only_coupled |
c_only_decoupled_to_substrate |
rc_decoupled |
rc_coupled |
rc_decoupled_to_substrate |
rlc_decoupled |
rlc_coupled |
rlc_decoupled_to_substrate |
rlck_decoupled |
rlck_coupled |
rlck_decoupled_to_substrate ]
ALL
LVS
ALL
ALL
ALL
LVS
ALL
ALL
LVS
LVS
LVS
LVS
LVS
LVS
LVS
–unselected_type <type>
LVS
-use_field_solver [ none | default_accuracy | high_accuracy
]
LVS, and
DEF/OA
# Specify the use of the capacitance field solver for the
net selection
Description
Quantus only extracts nets in accordance with the extract command explicitly defined in the Quantus command file.
The extract command can be used multiple times and the results are inclusive. The combinations of multiple selection and
type options determine the nature of extraction performed on a specific net, for a given extraction run.
The extract commands are accumulated from the command file from first to last. The last command specification overrides
previous specifications. Specifying r_only extraction for all nets, can be overridden by subsequently specifying rc_coupled
extraction for clk* nets.
For instance:
extract -selection all -type r_only
extract -selection net clk* -type rc_coupled
has the opposite meaning of:
extract -selection net clk* -type rc_coupled
extract -selection all -type r_only
The last command file definition simply results in all nets having resistance only extraction.
​​​​​​​
Options
extract_gate_diffusion_fringing_cap [ true | false ] ​
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This command enables Quantus to extract the transistor device gate-to-diffusion fringing cap (C f) when
the gate_diffusion_fringing_cap table is defined in the qrcTechFile. By default Quantus will extract the C f when the
ICT file includes the required information. Refer to Quantus Techgen Reference Manual for more information on
defining the gate_diffusion_fringing_cap table.
The fringing cap is intended to be used in conjunction with metal diffusion contacts. The spacing parameters of
the gate_diffusion_fringing_cap table originate from the metal diffusion contacts.
Note: When the qrcTechfile includes the gate_diffusion_fringing_cap table
the Virtuoso_QTS_Extraction_XL license is required by Quantus.
Intrinsic device capacitance is typically modeled as part of the device model. However, at the smaller process nodes
these intrinsic caps become more geometry dependent, and should be extracted from the design data for greater
accuracy.
Device Gate-to-Diffusion Fringing Capacitance
In the above figure, you can see that the parasitic capacitance between the bottom of the gate (poly) to the side of the
source/drain diffusion is still covered by the device model. The fringing cap (Cf) extracted by this command is the
parasitic capacitance between the sidewall of the gate to the top surface of the source/drain diffusion.
The parasitic capacitance between the sidewall of the gate and the contact (Cco) is extracted by Quantus with the use of
the extract -extract_via_cap command. You must specify the extract_via_cap option to extract Cco.
The default setting of the extract_gate_diffusion_fringing_cap option is true. However, the fringing cap will not be
extracted unless the gate_diffusion_fringing_cap table is also defined in the qrcTechFile.
It is not recommended to use this option since the Cf values, if defined in the qrcTechFile, are necessary
for accurate device extraction results.
The capacitance -partial_cap_blocking option may also cause Quantus to extract fringing caps (see
"capacitance" ). In this case the value of the device fringing cap will be the sum of the caps extracted by the two
separate options.
The extraction of fringing caps is also subject to capacitance blocking by the Techgen -compilation -blocking or p commands, or at Quantus runtime by the extraction_setup -parasitic_blocking_device_cells_file command.
The extract_gate_diffusion_fringing_cap option causes the poly-to-diffusion capacitance to be extracted regardless
of the use of the Techgen -p command, which might otherwise suppress the extraction of these capacitors.
See Quantus Techgen Reference Manual for more information.
For -blocking, the Cf will be extracted only if the metal diffusion contacts are not blocked from the poly gate. If the metal
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diffusion contact is blocked no fringing caps will be extracted. See Quantus Techgen Reference Manual for more
information.
For -parasitic_blocking_device_cells_file, the Cf will not be extracted in the blocked cells.
See "extraction_setup" or for more information.
Extraction of the fringing cap is supported when extracting multiple process corners in Quantus, however only
the cf_values can vary between process corners. All process corners must specify
the gate_diffusion_fringing_cap table or no corners should specify it. All process corners must also have the same
number of spacings, and the same spacing values specified.
Disable the extraction of fringing caps (extract_gate_diffusion_fringing_cap false) if
the gate_diffusion_fringing_cap table varies across process corners.
extract_via_cap [ true | false ]
This command option is set to true as a default, so that both Quantus and the Field Solver will extract via effect
capacitance, or the capacitance between vias and between vias and other objects (like gate poly) when extracting
capacitance.
The parasitic capacitance between the sidewall of the gate and the contact (Cco) is also extracted by Quantus with the
use this option (see figure, "Device Gate-to-Diffusion Fringing Capacitance" ) when the qrcTechFile includes
the via_edge_enlargement table (refer to Quantus Techgen Reference Manual ).
When set to false, this option specifies that Quantus should not include parasitic capacitance extraction on vias.
Note: This via capacitance extraction option is for use with LVS (Assura, Calibre, or Pegasus) input only, and does not
support cell level DSPF or SPEF output.
There are two recommended methods for defining the via effect in the technology file:
min_contact_poly_spacing parameter (standard via cap model)
the explicit Via definition including min_top_encl, min_bot_encl, and min_width to define the via enclosure
(advanced via cap model).
The "via effect" is the influence of the via on parasitic capacitance in the design. Explicit via effect modeling deals
with the improved handling of the via metal in Quantus. This is increasingly important due to the reduced parasitic
capacitance of the smaller devices at smaller technologies (i.e. 65nm and below). In this case the added
capacitance of the via metal can be a significant contribution.
The advanced cap model applies to both "short" vias passing between adjacent metal layers, and "long" vias passing
from metal1 to the diffusion layer, through the poly layer(s). Refer to Quantus Techgen Reference Manual for more
information.
When the ICT file is simulated in Techgen and compiled into the unified qrcTechFile, it is possible to have both the
standard via cap model and the advanced via cap model. When more than one via cap model is available in
the qrcTechFile, Quantus will use the most advanced via capacitance model available. 4
Note: When no via cap is modeled in the qrcTechFile the extract_via_cap option will be ignored without warning.
With the extract_via_cap option set to true, standard Quantus (without the field solver) extracts the contact-to-contact or
contact-to-poly capacitance using the standard via cap model. It does not extract capacitance from the "short" vias
between metal layers (via1_2-to-via1_2 for instance). The advanced via cap model is required to model the capacitance
between these vias.
In addition, the via or contact bias can be modeled in the ICT file as either a constant bias, or as a spacing-dependent
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table. The contact bias is also taken into consideration by Quantus during extraction of the contact or via capacitance.
Note: When the qrcTechfile includes either the advanced via cap model, or the spacing-dependent contact bias,
the XXX_QTS_Extraction_XL license is required by Quantus.
When the qrcTechFile specifies contact or via bias as a spacing-dependent table, the use of the process_technology technology_corner command is only supported when all process corners have the spacing-dependent contact bias
specified. In addition, each process corner must have the same number of spacings, and the same spacings values
specified, only the bias values can vary.
If these conditions are not met, you can enable extraction of multiple process corners by setting extract_via_cap to false
and disabling the extraction of the via effect.
Spacing-dependent bias in the qrcTechFile is not supported for sensitivity extraction (extraction_setup enable_sensitivity_extraction). Disable via cap extraction with extract_via_cap false to enable sensitivity extraction
in this case.
The Quantus Field Solver (extract -use_field_solver) extracts via capacitance without any additional contact or via
modeling in the qrcTechFile using the actual design data to extract the via capacitance. However, the Quantus Field
Solver will apply the constant via bias to adjust the size of the contact shape when it is specified in the qrcTechFile.
field_solver_type [deterministic | probabilistic ]
The deterministicoption is used to activate the QRCFS engine (also called Deterministic FS).
The probabilistic option is used to invoke the random walk field solver (also called Probabilistic FS or Quantus FS).
Quantus FS produces results (Total Capacitance-TC and Coupled Capacitance-CC) with statistical error bounds. The
error bound is set by using the CCL commands for default vs high accuracy modes (extract -use_field_solver [
default_accuracy | high_accuracy] ), and then Quantus FS runs until it converges to within the specified bound. The
error bound is expressed using the sigma term.
For the LEF/DEF or OA flow (cell level extraction) and the LVS flow (transistor level extraction), Quantus FS is the
default field solver for all process nodes. The Quantus FS mode offers better performance, accuracy, and capacity. It
requires the QTS310 Advanced Analysis license (XL + AA).
For 28nm and above process nodes, you can invoke Deterministic FS by setting the extract field_solver_type option to deterministic, which requires only an XL license. Note that this FS mode is not
supported for 20nm and below (that is, it cannot be used for those nodes).
inductance_nets_file < filename >
Specifies a file that contains the list of nets (one net per line) to be used for inductance extraction. If
an inductance_nets_file is not defined to limit the nets then inductance extraction occurs for all nets in the
current extract -selection when either RLC_xxx or RLCK_xxx type extraction is specified.
This option is very important to manage the size of the output netlist for simulation. It provides a more efficient and
effective method of analyzing RF designs in which only certain nets in the design may be of interest.
The nets in the filename must be specified as layout or schematic names according to the extraction_setup net_name_space command. The nets listed should also be a subset of the current extraction selection.
The inductance_nets_file option reduces the number of nets that are selected for inductance extraction from the
current extraction -selection. For instance, in the case of the following extract commands:
extract \
-selection all \
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-type c_only_coupled
extract \
-selection nets_file <nets_file> \
-type rlc_coupled \
-inductance_nets_file <inductance_nets>
Quantus will perform coupled capacitance extraction on all nets in the design, and will perform RLC-coupled extraction
on the inductance_nets , and then perform RC-coupled extraction on the nets_file . In this case, the inductance
extraction specified by the -type rlc_coupled option has been limited by the -inductance_nets_file option.
Note: In this case, Quantus will check to confirm that the nets specified by inductance_nets_file are a subset of nets
specified in the nets_file.
In the case of excluded nets, you must first define RLC extraction on all nets, and limit that selection
with inductance_nets_file, and then exclude some nets with -type c_only_coupled. In the example that follows,
Quantus will perform RC-coupled extraction on all nets except those specified in the nets_file , and RLC-coupled
extraction only on the nets in filename , and coupled cap extraction on the nets in nets_file .
extract \
-selection all \
-type rlc_coupled \
-inductance_nets_file <inductance_nets>
extract \
-selection nets_file < nets_file > \
-type c_only_coupled
In the case of excluded nets extraction, the nets specified in the inductance_nets_file must NOT be excluded from
resistance extraction.
Note: In this case, Quantus will check to confirm that the nets specified by inductance_nets_file are not also specified
in the nets_file.
The inductance_nets_file includes an optional fracture length specification ( signal_fracture_length ) for the net. In
this case, each line of the inductance_nets_file may contain one net name (in either the schematic or layout name
space) and a fracture length specified in units of microns or squares in accordance with the extraction_setup
- max_fracture_length_unit option (see "extraction_setup" ). The net name and fracture length are separated by a
space or tab.
Note: The < signal_fracture_length > must be specified as greater than or equal to 5. When the value is less than 5,
Quantus internally resets the value to 5.
An example inductance_nets_file follows:
< net_name > [< signal_fracture_length >]
netA 24
netB 50
netXYZ 100
Without the specification of < signal_fracture_length >, the nets in the inductance_nets_file will be fractured at the
bends in the net, and further fractured according to the specification of extraction_setup -max_fracture_length option.
However, any net specified with a < signal_fracture_length > will be fractured first at the bend, then also at the smaller
of the < signal_fracture_length > or the extraction_setup -max_fracture_length.
Therefore, it is only beneficial to specify a < signal_fracture_length > smaller than the max_fracture_length, or it has
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no effect. However, when the < signal_fracture_length > is set to 0, the net is fractured at the bend, and in accordance
with the max_fracture_length.
selection [ all | def_special_nets | all_pg_nets | def_regular_nets | def_mustjoin_nets | net <regexpr> | nets_file
<filename> | instances_file <file_name> | selected_path_file <filename> ]
all - select all nets in the design, except power and ground nets, as defined by the global_nets command (see
"global_nets" ). This option is the default.
all_pg_nets - selects all the power and ground nets. The PG nets are identified by the “USE POWER” and “USE
GROUND” keywords in DEF. If the all_pg_nets argument is set, Quantus selects all the PG nets marked by these
keywords. You must not use names, such as VDD or VSS, to determine a PG net.
By default, the power and ground nets are excluded from extraction in the cell-level flow (except if you
enable power or ground net extraction). However, the impact from the power and ground nets to the
neighboring signal nets are still included in the total capacitance of each neighbor's signal nets.
The following table gives the different use models and expected result for each model:
Use
Model
Command
Result
1
extract \
-selection “all_pg_nets”
-type “rc_coupled”
All the PG nets will be extracted with the rc_coupled type.
2
extract \
-selection “all_pg_nets”
-type “none”
Excludes the PG nets from extraction.
3
extract \
-selection “all”
-type “c_only_coupled”
All the PG nets will be extracted with the rc_coupled type, and all nets
other than the PG nets will be extracted with the c_only_coupled type.
extract \
-selection “all_pg_nets”
-type rc_coupled
​ ​ ​def_mustjoin_nets - selects only mustjoin nets, which are nets that are identified by the MUSTJOIN keyword in the
DEF file.
def_regular_nets - selects all nets that are not special, mixed, or mustjoin nets.
def_special_nets - selects only special nets such as clock nets. Any net that is listed in the SPECIALNETS section
of the DEF file is considered a special net. Mixed nets, which are listed partially in the DEF SPECIALNETS section
and partially in the DEF NETS section, are also considered special nets.
instances_file <file_name> - selects the list of device instances for extraction listed in the specified file such that
the nets connected to the instance pins are selected for extraction. Each line in the file must contain one instance
name. The device instance names are those from the LVS DB. They are flattened with the character (‘/’) as the
hierarchy delimiter.
Instance selection is not supported in HRCX mode ( -hierarchical_cell_list_file).
Instances inside a macro cell cannot be specified because the content of black boxes is not included in the
extraction netlist, and instances inside the blocking cells are also not supported. If specified, Quantus will issue a
“device not found” warning message.
Note: The -selection instances_file option is mutually exclusive with -selection nets_file option for the
Quantus net selection.
For example, you can select nets by using either of the below CCLs:
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extract \
-selection nets_file <file_name>
-type rc_decoupled
The same set of nets can be provided by specifying a shorter list of devices:
extract \
-selection instances_file <file_name>
-type rc_decoupled
However, you cannot specify the nets using both options together:
extract -selection instances_file “file_name”\
-type “rc_coupled”
extract -selection nets_file “netfile” \
-type “none”
You may define device instances in the file using wildcards. However, wildcard support is provided only in the
schematic name space and not in the layout name space.
The option supports the output formats: SPICE, xDSPF, xSPEF, EV, and SV. The DSPF and SPEF output
formats are not supported because there are no device names.
Selecting Nets using Device Instance Names
The example below illustrates net selection by device instance names. A four-pin device, such as a MOSFET,
connects to four nets. By specifying a MOSFET instance name, you can specify four nets. In the figure below,
there is an inverter, where two MOSFET devices, M1 and M2, are connected. To select all four nets, you would
have to specify A, Z, VDD, and VSS. With this option, you can specify the four nets by specifying just the two
devices, M1 and M2, instead.
Selecting Device Instance Names
You can choose either of the following sets of device instance names:
The device instance names in the LVS DB, and in the schematic name space.
The device instance names in the LVS DB, and in the layout name space.
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These are the device instance names without device prefixes, spice characters, and other netlisting options
added during the extraction.
If extraction_setup -net_name_space is schematic, instance names are in the schematic name space.
For example:
XI1/XAB5/XAG2/M1
XI3/M6
If extraction_setup -net_name_space is layout, instance names are in the layout name space.
For example:
X16/X392/X1/X1/M1
M28
Both sets of names are hierarchical, because the LVS DB is hierarchical. When a hierarchical device name is
flattened, a hierarchy delimiter is added. The hierarchy delimiter used is a “/” (slash), which is also the default.
Note:
The -selection instances_file option is neither supported for the Substrate Network Analysis (SNA) nets
file nor the inductance nets file.
The option is not supported for Quantus FS.
net < regexpr > - Selects all nets whose names match the pattern specified by regexpr . For instructions on
defining the regular expression please refer to Using Wildcards with Quantus.
nets_file <file> - select nets for extraction as listed in the specified file. Each line in the file must consist of a single
net name. If you specify multiple net names in a single line, you may get unexpected capacitance values in the
output netlist. You may define nets in the file using wildcards. See Using Wildcards with Quantus.
Note: You cannot specify wildcards in the nets_file for DEF or OA input. In this case, you should use the selection net option instead.
selected_path_file <file> - Outputs only designed devices and components on the nets specified in the
selected_path_file plus extracted parasitic devices. Note the partial list of designed devices is different from the
complete device output of other extraction modes.
You may define nets in the file using wildcards. See Using Wildcards with Quantus.
Quantus uses the nets listed in the selected_path_file together with a net expansion algorithm to define the
selected paths. The net expansion algorithm expands the listed nets through MOSFET diffusion paths until they
terminate at a MOSFET gate, or a global net (see global_nets ).
selection_dividing_layers_type [ LT | LE | GT | GE ]
The command enables selected net extraction by a dividing layer. It is used in excluded nets extraction, which is
defined by two consecutive selection options. The first selection performs maximum extraction (extracts RC network for
all nets); while the second selection performs less extraction (performs extraction for selected nets). The command
restricts the second selection by specifying dividing layers so that only a portion of the selected nets are extracted.
The command can have one of the following values:
GT - specifies that all the layers above and not including the dividing layers are selected.
GE - specifies that all the layers above and including the dividing layers are selected.
LE - specifies that all the layers below and including the dividing layer are selected.
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LT - specifies that all the layers below and not including the dividing layers are selected.
The four layer groupings are illustrated in the below figure:
Note that there are LVS layers which are not mapped in the ICT file. They have neither R nor C extracted, and are not in
the scope of the dividing layers.
You must specify the dividing layers using the Techgen -compilation option:
Techgen –compilation –selection_dividing_layers <layer1>[,<layer2>…]
An example of the Techgen/CCL pair is given below:
Techgen
Techgen –compilation –selection_dividing_layers V0
CCL
extract –selection “all” –type “rc_coupled”
extract –selection nets_file “nets.file” –type “c_only_coupled” –selection_dividing_layers_type GT
In this example, all nets will be extracted in the rc_coupled mode; while selected nets specified in “nets.file” will be
extracted in the c_only_coupled mode. Within the selected nets, only the layers above V0 will be extracted in
the c_only_coupled mode.
This example is illustrated in the following diagram:
In stage one, all nets are selected for RCc. In stage two, some nets are selected for C only. In stage three, some layers
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of the stage two are selected for Cc only. That is, all layers above, but not including V0, are selected for C only. All
layers below and including V0 are to maintain stage one selection (RCc).
The dividing layer feature will only work in the restart mode. That is, there is a base line run, where the RCc mode is
used, and the layer names are printed. Then, in the second run, the dividing layer CCL is added to get the desired
second netlist. The restart mode is supported only in the xDSPF/DSPF format. Therefore, the dividing layer feature is
also supported only in the xDSPF/DSPF format. The other formats, such as SPICE and extracted view do not have the
dividing layer feature. For more information on the transistor-level restart mode, refer to the Quantus CommandLine chapter.
Note: The parasitic resistor printing should have layer names when the layer division feature is requested. To support
layer division, output_db -include_parasitic_res_model must be set to true or comment.
This feature is supported in the transistor-level flow for the DSPF/xDSPF output formats.
selection_layers “<layer_set1>” “<layer_set2>”…
Specifies to enable extraction on selected layers for the specified selected nets. This option is used in combination with
the unselected_type option.
The general CCL command syntax is shown below:
extract –selection “all” –type <type1>
extract –selection nets_file “nets.file” –type <type2> \
–selection_layers “<layer_set1>” “<layer_set2>” … –unselected_type <type3>
Here,
For the selected layers within the selected nets, the outcome is <type2>. Otherwise, for the unselected layers
within the selected nets, the outcome is <type3>.
the layer sets must be predefined using the following Techgen –compilation option:
Techgen –compilation –selection_layers <layer_set_name1>,<lvs_layer1>,<lvs_layer2>...
–selection_layers <layer_set_name2>,<lvs_layer3>,<lvs_layer4>...
The < layer_set_name > is a unique identifier for the LVS layer set. This name will be used in the selection_layers CCL option. Also, layer set names have to be disjoint.
Example:
extract \
-selection all \
-type "rc_coupled"
extract \
-selection nets_file "nets.file" \
-type r_only \
-selection_layers layer_set_tcn \
-unselected_type none
extract \
-selection nets_file "nets.file.2" \
-type c_only_coupled \
-selection_layers “layer_set_metal1”
-unselected_type none
“layer_set_metal2”
\
Techgen
-selection_layers layer_set_tcn,diffcon \
-selection_layers layer_set_metal1,m1,tm_m1 \
-selection_layers layer_set_metal2,m2,tm_m2 \
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substrate_nets_file < filename >
Specifies a file that contains the list of nets (one net per line) whose capacitance-to-ground values are to be explicitly
connected to the substrate parasitic network created during substrate extraction. Unlike the inductance_nets_file,
the substrate_nets_file must be explicitly defined, or no nets will be extracted as connected to the substrate.
The nets in the filename must be specified as layout or schematic names according to the extraction_setup net_name_space command. The nets listed should also be a subset of the current extraction selection.
Quantus allows -substrate_nets_file < filename > to be specified with the following extract commands:
extract \
-selection [ all | net | nets_file ]
-type [ rc_xxx | rlc_xxx | rlck_xxx ]
The -substrate_nets_file option requires at least R and C to be extracted for the specified nets. In addition, the substrate_nets_file option can only be specified during Full Chip extraction, Selected Nets Proper extraction, or
Excluded Nets extraction, as demonstrated in the following examples.
The substrate_nets_file option limits the number of nets that are selected for substrate extraction from the
current extraction -selection. For instance, in the case of the following Full Chip extraction:
extract \
-selection all \
-type rlc_coupled \
-substrate_nets_file < filename >
Quantus will perform RLC-coupled extraction on all nets in the design, and will perform RLC-coupled extraction with
substrate imaging on the nets specified in filename .
In the case of Selected Nets Proper extraction:
extract \
-selection nets_file < file1 >\
-type rlc_coupled \
-substrate_nets_file < file2 >
Quantus will perform RLC-coupled extraction on all nets specified in file1 , and will perform RLC-coupled extraction
with substrate imaging on the nets specified in file2 .
Note: The nets specified in file2 must be a subset of nets specified in file1
In the case of Excluded Nets, you must first define RLC extraction on all nets, and specify the nets for substrate extraction
with substrate_nets_file, and then exclude other nets with -type c_only_coupled.
extract \
-selection all \
-type rlc_coupled \
-substrate_nets_file < filename >
extract \
-selection nets_file < netsfile > \
-type c_only_coupled
Note: For Selected Nets Proper, the substrate_nets_file must be a subset of the nets specified in nets_file. For
Excluded Nets, the substrate_nets_file must not be specified with the nets_file.
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type [ none | substrate_only | r_only | c_only_decoupled | c_only_coupled | c_only_decoupled_to_substrate |
rc_decoupled | rc_coupled | rc_decoupled_to_substrate | rlc_decoupled | rlc_coupled | rlc_decoupled_to_substrate |
rlck_decoupled | rlck_coupled | rlck_decoupled_to_substrate ]
Note: The various *_decoupled_to_substrate options are only valid when the output format is specified as Spice,
Extracted View, or Transistor DSPF.
The Techgen -dsub compilation option to specify substrate layers takes precedence but is not required for the
*_decoupled_to_substrate extract options. If -dsub is not specified, Quantus will automatically use the
substrate layers from the layer_setup file.
none - Enables you to exclude nets from extraction. For example, nets specified with the command: This option is
the default.
extract -selection net < regexpr > -type none
Starting with the EXT 10.1.1 HF1 release, you can use the extract -type none option to generate xSPEF,
xDSPF, and SPICE netlists (specified using output_db -type CCL option) with no parasitics at all for any of
Assura, Pegasus, or Calibre LVS input (specified using input_db -type CCL option). Like the LVS extracted
view, the generated netlists are also flat.
Note: When extract -type none is specified, the capacitance -ground_net option is automatically set to 0.
Note: The CCL command extract -type none has no impact and is ignored if you specify it when you generate an
LVS extracted view using the output_db -type lvs_extracted_view CCL command.
substrate_only - Indicates that Quantus should perform extraction of the substrate and designed devices only,
without performing parasitic extraction of the design interconnect. In this case, the output extracted_view or Spice
netlist will contain only designed devices along with the parasitic substrate network (i.e., no parasitics will be
extracted for the interconnect).
You must also specify one or both of the substrate_extract
-extract_under_contacts or -extract_under_devices options for the extract -substrate_only option to work
(see substrate_extract ). Otherwise, no substrate extraction is called for, and Quantus will exit with an error.
Note: When extract -type substrate_only is specified, no other extract commands may appear in the Quantus
command file or an error will occur.
r_only - Extracts only parasitic resistance on the specified net or nets.
Note the following:
When Quantus extracts only parasitic resistance, or when the promote_pin_pad option is set to logical, then
the net total cap values in the cell-level DSPF/SPEF output may contain zero cap entries.
When extract -type r_only is specified, the capacitance -ground_net option is automatically set to 0.
Resistance only extraction is not recommended when LEF/DEF input is used.
c_only_coupled - Extracts only parasitic capacitance coupled between the specified net or nets and adjacent
nets.
c_only_decoupled - Extracts only parasitic capacitance between the specified net or nets and adjacent nets
decoupled to the specified cap ground (see "capacitance" ).
c_only_decoupled_to_substrate - Extracts only parasitic capacitance decoupled to the ground net in the
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substrate or well immediately below the specified net or nets.
rc_coupled - Extracts an RC network for the specified net(s) with both parasitic resistance and capacitance
coupled between the specified net or nets and any adjacent nets.
rc_decoupled - Extracts an RC network for the specified net(s) with both parasitic resistance and capacitance
decoupled to ground.
rc_decoupled_to_substrate - Extracts an RC network for the specified net(s) with both parasitic resistance and
capacitance decoupled to the ground net in the substrate or well immediately below the specified net or nets.
rlc_coupled - Extracts an RLC network on the specified net or nets with parasitic resistance, and self-inductance,
and parasitic capacitance coupled between the specified net or nets and any adjacent nets.
rlc_decoupled - Extracts an RLC network on the specified net or nets with parasitic resistance, and selfinductance, and parasitic capacitance decoupled to ground.
rlc_decoupled_to_substrate - Extracts an RLC network on the specified net or nets with parasitic resistance,
and self-inductance, and parasitic capacitance decoupled to the ground net in the substrate or well immediately
below the specified net or nets.
rlck_coupled - Extracts an RLCK network on the specified net or nets with parasitic resistance, and both mutual
and self-inductance, and parasitic capacitance coupled between the specified net or nets and any adjacent nets.
rlck_decoupled - Extracts an RLCK network on the specified net or nets with parasitic resistance, and both
mutual and self-inductance, and parasitic capacitance decoupled to ground.
rlck_decoupled_to_substrate - Extracts an RLCK network on the specified net or nets with parasitic resistance,
and both mutual and self-inductance, and parasitic capacitance decoupled to the ground net in the substrate or
well immediately below the specified net or nets
unselected_type <type>
Species the extraction type for the unselected layers for the selected net and selected layer extraction. This option takes
the following arguments: rc_coupled|rc_decoupled|c_only_coupled|c_only_decoupled|r_only|none
use_field_solver [none | default_accuracy | high_accuracy ]
This command determines the use of the Quantus 3D capacitance field solver. The field solver performs capacitance
extraction using the actual design data to extract parasitic capacitance in place of matching design structures to the
capacitance models defined in the technology file. The field solver is disabled by default.
If set to high_accuracy, this option indicates that the field solver should be run with the highest available accuracy,
which consumes additional processor time. The default_accuracy setting provides sufficient accuracy in most cases
and reduces extraction run time.
The use of the field solver should be specified for each instance of the extract command where it is needed:
extract \
-selection all \
-type c_only_coupled \
-use_field_solver default_accuracy
extract \
-selection nets_file < file > \
-type rlck_coupled \
Each line in the file specified with the -selection nets_file option must consist of a single net name. If you specify
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multiple net names in a single line, you may get unexpected capacitance values in
the output netlist.
extraction_setup
Command Syntax
Input
Restrictions
extraction_setup
-analysis [ em | timing ]
ALL
-array_vias_spacing [ <value> | "auto" | "deterministic" ]
LVS
#New in Quantus 20.1
-assignable_partial_virtual_ground_plane <x11> <y11> <x12> <y12>
<x21> <y21> <x22> <y22>...
DEF/OA
-background_density_map <design_layer_name1>
All
<background_density1> ...
#New in PVE 11.1.1 HF2
-change_lithobias_direction [true | false]
ALL
#New in EXT 19.1.3
-change_overhang_direction [true | false]
All
-cluster_vias_in_em [true | false]
DEF/OA
-copy_port_to_obs [ true | false ]
DEF/OA
#New in PVE 11.1.2 HF1
ALL
-custom_dpt_corner corner_definition_file_name
-enable_dpt_color_import[true | false]
#New in Ext 15.1
-delete_layers <lvs_layer1> <lvs_layer2> …
LVS
#New in Ext 15.13
LVS
-delete_layers_file <full_path_name_deleteLayers.defs>
LVS
-delta_gate_ckt [true | false]
-delta_gate_ckt_by_device “<devLayer1>”
-delta_gate_ckt_by_gate
“<devLayer2>” …
LVS
“<gate1>” “<gate2>” …
LVS
#New in EXT 19.1.3
-delta_gate_ckt_pi_distribution [true | false]
LVS
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-density_bounding_box
[ design_data | diearea | perlayer | rectangle xlo ylo xhi yhi ]
DEF/OA
-density_bounding_box [ design_data | perlayer | path_data ]
LVS
-double_gate_conn [true | false]
LVS
#New in EXT 16.11
-enable_active_via_fill_processing [ true | false ]
DEF/OA
#New in PVE 12.1
-enable_bump_instance [true | false]
ALL
#New in EXT 9.1
-enable_corner_relaxation [ true | false ]
DEF/OA
#New in EXT 10.1
-enable_diffusion_resistance_equations false
LVS
#New in PVE 11.1.2 HF1
ALL
-enable_dpt_color_import[true | false]
#New in PVE 12.1
-enable_eco_mode [true|false]
DEF/OA
–enable_HPB_extraction [ true | false ]
All
-enable_sensitivity_extraction [ true | false ]
DEF/OA
#New in PVE 12.1
-enable_TSV_Cc_model [true|false]
LVS
#New in EXT 13.2
–enable_TSV_STA_Cc_model [true | false]
ALL
#New in PVE 12.1
-enable_tsv_instance [true | false]
ALL
#New in Quantus 20.1
-force_array_via_by_layer <v1> <v2> ...
LVS
-fs_window_file <window_file_name>
LVS
#New in EXT 13.2
-gds_active_fill_layer_map <layer_name> <layer_number> <datatype>
DEF
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-gds_layer_map <design_layer_name1> <gds_layer_number1>
<gds_datatype1>
[ <design_layer_name2> <gds_layer_number2> <gds_datatype2>
...]
-oasis_layer_map <design_layer_name1> <oasis_layer_number1>
<oasis_datatype1>
[ <design_layer_name2> <oasis_layer_number2>
<oasis_datatype2> ...]
DEF/OA
#New in EXT 10.1.1 HF1
-gds_fill_layer_map <layer_name> <layer_number>
<data_type>
DEF/OA
-oasis_fill_layer_map <layer_name> <layer_number>
<data_type>
DEF
#New in EXT 14.14
-gds_layer_map_by_color -|0|1|2 <designLayer1> <gdsLayer1>
<gdsDataType1> <designLayer2> <gdsLayer2> <gdsDataType2> …
-gds_fill_layer_map_by_color -|0|1|2 <designLayer1> <gdsLayer1>
<gdsDataType1> <designLayer2> <gdsLayer2> <gdsDataType2> …
-global_frequency <value>
ALL
-HPB_layer_map designLayer1 gdsLayer1 gdsDatatype1 …
DEF/OA
-ignore_cells_file <filename>
DEF/OA
#New in EXT 17.2.1
-ignore_conn_to_bump [true | false]
DEF/OA
#New in PVE11.1.1
-ignore_invalid_vias [ true | false ]
DEF/OA
#New in Quantus 20.11
LEF/DEF
-ignore_invalid_colored_shape [ true | false ]
-ignore_pin_list <pin_name1> <pin_name2> ...
DEF/OA
-ignore_pushdown_blockages [ true | false ]
DEF/OA
-ignore_unconnected_bump_cells [true | false]
DEF/OA
-include_gate_forming_layers [true | false]
DEF/OA
-keep_multi_port_pin [true | false]
DEF/OA
#New in EXT 19.1.3
-layer_max_etch_aspect_ratio_map "all <aspectratio>" or
"<layer1> <aspectratio1>" "<layer2> <aspectratio2>"
All
-layout_scale <number>
Default Unit: 1.0
DEF/OA
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#New in EXT 19.1.1
-lic_queue <timeout_value>
DEF/OA
#New in EXT 19.1.3
-low_memory_usage [true | false]
DEF/OA
-macro_cells_type [ default | white ]
LVS
–max_fracture_length_by_layer “<layer> <value>” [“<layer>
<value>” …]
LVS
#New in PVE 12.1 HF2
-max_fracture_via_count <value>
Default Value: 100
LVS
-max_resistance_mesh_size_error <value>
LVS
-max_via_array_count <value>
LVS
#New in EXT 14.1
-max_via_array_count_by_layer <layer> <count>
LVS
#New in EXT 14.1
-max_via_array_size [<size>|auto]
LVS
#New in EXT 14.1
-max_via_array_size_by_layer <layer> [<size>|auto]
LVS
-net_name_space [schematic | layout]
LVS
#New in PVE11.1.1 HF3
-nonmanhattan_resistance [default_accuracy | high_accuracy]
LVS
#New in Ext 14.11
OA
-oasis_active_fill_layer_map <layer_name> <layer_number>
<datatype>
-oasis_layer_map_by_color -|0|1|2 <designLayer1> <oasisLayer1>
<oasisDataType1> <designLayer2> <oasisLayer2> <oasisDataType2> …
DEF/OA
-oasis_fill_layer_map_by_color -|0|1|2 <designLayer1>
<oasisLayer1> <oasisDataType1> <designLayer2> <oasisLayer2>
<oasisDataType2> …
-parasitic_blocking_device_cells_file <file>
LVS
-parasitic_blocking_device_cells_type
[ gray | white ]
LVS
-parasitic_blocking_device_cells_file <file>
LVS
-parasitic_blocking_device_cells_type
[ gray | white ]
LVS
-parasitic_res_width_change_percentage <value>
LVS
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-promote_bump_ports [true | false ]
DEF/OA
-promote_feedthru_ports
[ none | r_only | c_only | rc | true | false ]
DEF/OA
-promote_feedthru_ports_nonoutputpins [true | false]
DEF
-promote_instance_ports
[ none | r_only | c_only | rc ]
DEF/OA
-promote_pin_pad [ none | logical | physical ]
DEF/OA
#New in Quantus 20.11
-rccompare [ true | false ]
LEF/DEF
-remove_fill_fill_overlap [true | false]
DEF/OA
#New in Ext 15.2
DEF/OA
-remove_net_pin_overlap [ true | false ]
LEF/DEF
#New in Quantus 20.11
-report_invalid_colored_shape [ true | false ]
#New in EXT 17.1
-res_gate_default_factor
LVS
<value>
-res_gate_factor “<value1> <devLayer1>” “<value2> <devLayer2>” …
LVS
-resistance_mesh "<lvsLayer1> <meshSize1>" "<lvsLayer2>
<meshSize2>" ...]
LVS
#New in EXT 13.2
–resistance_mesh_adaptive [default | false]
LVS
-resistance_mesh_advanced_via_merging
[true | false]
LVS
LVS
#New in EXT 17.12
–resistance_mesh_automatic_size <layer1> <layer2> …
-resistance_mesh_automatic_via_layers [true | false]
LVS
-resistance_mesh_corner_square_counting [true | false]
LVS
#New in Ext 15.13
LVS
-resistance_mesh_file <full_path_name_meshR.defs>
-resistance_mesh_more_square_counting [true | false]
LVS
#New in EXT 10.1.2
-resistance_mesh_region <regfile>
LVS
-resistance_mesh_size_k_factor <value>
LVS
-resistance_mesh_square_counting_buffer width_ratio
LVS
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#New in EXT 14.1.0
–resistance_mesh_via_layers <lvsLayer1> <lvsLayer2> ...
LVS
-short_res_devices “<DRL1>” “<DRL2>” …
LVS
-stacked_via_effect [ true | false]
All
#New in PVE 12.1
-stitch_bump_model [true|false]
LVS
#New in PVE 12.1
-stitch_tsv_model [rlc|r_only|rc|none]
LVS
#New in EXT 16.1
-stream_layer_map “<LEF-layer-name> <stream-layer-ID> <DT> <usetype> <color-ID> ”
DEF/OA
-stream_layer_map_file <filename>
DEF/OA
#New in Quantus 20.11
DEF/OA
-strict_maskshift_checking [ true | false]
DEF/OA
#New in Ext 14.2
-technology_auto_layer_map [ true | false]
-technology_layer_map <design_layer_name1>
DEF/OA
<technology_layer_name1>|none
[ <design_layer_name2> <technology_layer_name2>|none ...]
-technology_lef_map <techlef_file_1> <def_file_1> <techlef_file_1>
<def_file_2> ... <techlef_file_2> <def_file_1>
DEF/OA
-technology_lef_map_file <techlef_mapping_file>
DEF/OA
#New in EXT 18.2.1
All
-tsv_subckt_file <file> <file2> …
-ubump_subckt_file <file> <file2> …
All
-verify_min_width [ true | false ]
DEF/OA
Description
The extraction_setup command and its options allows you to specify the naming convention for nets and devices selected
for specific extraction functions, define the limits of parasitic resistor lengths, establish handling instructions for vias and via
arrays, and exclude specific cells or pins from consideration during extraction.
In addition, the extraction_setup command defines the layer scaling and bias needed for the input design data prior to
extraction, and also allows you to define layer mapping between the design and technology files.
Options
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analysis [ em | timing ]
The analysis option is used to handle the fracturing of stacked metal lines such that false EM violations are minimized.
If the analysis type is set to timing, stacked via metal width checking is not performed. If you do not specify any option,
the default analysis type is set to timing.Once stacked via metal width checking is turned on by specifying the value as
em, the width of the metal resistor between stacked vias is artificially set to a large value so that no false violation is seen
on such resistors during downstream Electro Migration (EM) analysis.
Note: When the output_db em_extract CCL command is set to true, the extraction_setup analysis is automatically
set to em.
Starting with the PVE 11.1.1 HF3 release, Quantus (cell-level flow) has been enhanced to report change of the metal
segment width around the via bounding box that has different peak current and is essential to the signal EM analysis.
Quantus performs fine fracturing at the metal pieces that lead to the via/via array, and also reports the width changes (if
the change is more than 10%) at the metal segments from the via boundary to the center-point of via . These resistors
can be extracted by using the extraction_setup -analysis em CCL command.
Metal Segment With Large Via Metal Overhang
If a via array has more than two cuts, as shown in the below figure, Quantus clusters the via array and uses the center
as the connection point. However, if a via array has exactly two cuts, then Quantus creates a wire resistor (with its own
length and width) between the center of the two cuts of the via. The length of this resistor is the distance between the
center points of the two cut geometries, and the width is the width of the metal overhang of the via definition.
Double-cut Via Array
Note: If a via definition has multiple rectangle shapes (more than one), or more than two cuts, then Quantus does not
decluster the vias.
20nm EM Features
In earlier releases, the 20nm EM features were activated using a specific environment variable. Starting with PVE
12.1.1 release, the following commands are relevant to activating the 20nm EM.
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extraction_setup –analysis em \
-parasitic_res_width_change_percentage value
output_db –include_parasitic_res_length true|false
-include_parasitic_res_width true|false
-include_parastic_res_width_drawn true|false
The output_db commands result in a Quantus behavior change when 20nm features are present.
The extraction_setup -analysis em has a default behavior change for all process nodes, while the parasitic_res_width_change_percentage must be explicitly set.
The new 20nm EM functionalities include the following major components: R network generation in dangling wires,
parasitic R’s L definition is extended to wire ends, and parasitic R’s width definition changes under certain
configurations.
Keep Dangling Resistors
The dangling wires feature is automatically included by the existing –analysis em CCL command. This is a default
behavior change, and customers in other process nodes such as 28nm will experience Quantus output size increase.
Note: For the cell-level (LEF/DEF, OA) flow, the dangling wires feature is not automatically included by the -analysis
em CCL command. You need to specify the -output_incomplete_nets option to include the dangling parasitic resistors
(for the incomplete nets) in the netlist output.
Keep Dangling Resistors
Note: By default, or by using extraction_setup –analysis timing, Quantus R engine does not trace parasitic resistors
into a dead end wire. But, with the new behavior of extraction_setup –analysis em, it is changed and it traces parasitic
resistors into a dead end wire. The outcome is more resistors in the output. However, in addition to the -analysis em
CCL command, if -remove_dangling_res is set to true, then these additional parasitic resistors are removed.
Contact Resistor Printing
In 20nm EM, contact printing has three formats. The first and second syntax are applicable when the contact array via
count is one. In the first syntax, the contact parameters printed are as follows:
$L= $W= $A=
$L and $W represents the long and short size of the contact, while $A is the area. Even though $A could have been
derived from $L and $W, it is printed for backward compatibility. That is, in the past, only $A= was printed. Now, under
20nm EM, $L and $W are printed.
In the second syntax, the L and W parameters refer to a via’s dimension in the x and y directions respectively. The
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printing of this format is enabled by the EM CCL commands (output_db –em_extract true or extraction_setup –
analysis em), and when the vias of a given layer are not merged. If the vias are merged, then this format does not apply.
That is, vias are printed with only the $A= (area) parameter, and not the $L and $W parameter pairs. Following is an
example of the second syntax:
Ra1 VDD#11 VDD#12 10.0 $VIA1 $L=0.032 $W=0.050 $X=1.123 $Y=3.112 $lvl=20
In this example, horizontal dimension represents $L and vertical dimension represents $W
for rectangular slots
Ra1 VDD#11 VDD#12 10.0 $VIA1 $L=0.050 $W=0.032 $X=1.123 $Y=3.112 $lvl=20
In this example, horizontal dimension represents $L and vertical dimension represents $W
for rectangular slots
If the number of contacts in the given array contact is more than one, then the contact parameters printed are as follows:
$N=
$A=
where $N= is the number of merged contacts.
The activation for contact parameter printing is done by the existing CCL command:
output_db –include_parasitic_res_length true
Width Change Parameter
Quantus, by default, traces parasitic resistors over wires without considering width change so that the parasitic resistor
length, L= , can be maximized in value. Consequently, the width parameter, W=, of the parasitic resistor uses the
measurement at the narrowest passage.
Under the environment variable, the following CCL command was set automatically. extraction_setup –
parasitic_res_width_change_percentage 0.1
This CCL now requires you to explicitly set a very small value.
Resistor Length Parameter
The parasitic resistor length definition in 20nm EM mode does not depend on process node. The default resistor
length, L=, definition is the distance from contact center to contact center over the wire. However, under 20nm EM, the
length is stretched. The activation of this feature is done by the following CCL command: output_db –
include_parasitic_res_length true
array_vias_spacing [ < value > | "auto" | "deterministic"]
Quantus groups vias and contacts into arrays in order to reduce the size of RC networks for large via counts and to
speed resistance extraction. Vias or contacts are grouped according to the distance between them. If the distance
between contacts or vias does not exceed a specified maximum distance, (the array_vias_spacing), they are grouped
within the same array.
Vias Collected into Arrays
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This option is intended to provide user-level control over the value of the array_vias_spacing parameter at Quantus run
time.
< value > specifies the maximum edge-to-edge distance between vias or contacts that will be grouped into an array.
The specified value applies to all the via layers, and overrides any layer-specific value defined in the layer_setup file.
Refer to Quantus Techgen Reference Manual for more information.
Note: defeat_array_vias in the layer_setup file overrides array_vias_spacing specified in either the Quantus
command file or in the layer_setup file.
If you specify "auto", the value of array_vias_spacing specified in the layer_setup file is honored. This is the default
value. If no value is specified in the layer_setup file, Quantus will determine a value for creating via array based on the
size and spacing of the vias. That is, the default array via spacing value is 2.5 times the via or contact size. In addition,
the array_vias_spacing has an upper limit of 2.5um.
If you specify "deterministic", the array via spacing is computed based on the ICT file and it is independent of the
actual layout data. This option sets the array via spacing using the following formula:
-array_vias_spacing (deterministic) = 1.25*(min_width + min_spacing)
For each via layer, the ICT file parameters of min_width and min_spacing are used. An excerpt of ICT file via is shown
below.
Note: The min_width and min_spacing parameters are always available in a via object, even in a slot via.
via "VIA6" {
top_layer "M7"
bottom_layer "M6"
area_resistance 10 0.001600 6 0.004000
min_top_encl
0.00
min_bot_encl
0.01
min_width
0.04
min_spacing
0.075
area_dependent_tc
temp_areas
temp_tc1
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0.004000
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temp_tc2
-3.678e-08
slot_via_long_edge
-1.388e-07
0.04
0.1
slot_via_short_edge 0.04
0.04
slot_via_long_edge_enlargement
0.0035
0.015
slot_via_short_edge_enlargement
0.0035
0.015
}
If you specify a <value> of zero, the vias are not collected into arrays since all vias will fall outside the specified
distance. In this case a value of zero has the same effect as specifying defeat_array_vias for every contact (ext_cont)
defined in the layer_setup file.
assignable_partial_virtual_ground_plane <x11> <y11> <x12> <y12> <x21> <y21> <x22> <y22>...
Specifies multiple bounding boxes that are non-overlapping. Each bounding box is specified by <xi1> <yi1>, <xi2>
<yi2> representing the lower left and upper right coordinates pairs of the ith rectangle, starting from 1. The unit of the
coordinates are given in micrometers. If there is process scaling (layout_scale in the ICT file), the bounding box
coordinates are specified before process scaling.
This option is used for the Through-Dielectric-Via (TDV)-based 3DIC technology in the cell-level flow.
For more information, refer to TDV Extraction with Partial Second Ground.
background_density_map <design_layer_name1> <background_density1> ...
The background_density_map option specifies to map the design layers with the corresponding background density.
This option allows you to specify the surrounding density information of a design block. When specified, the block
density is calculated by considering the nets inside and around the design block boundary.
<layer_name> is a valid layer name in the design, and <background_density> is a number between 0 and 100
(corresponding to 0% to 100%). For layers not specified, the default background_density is 0.
The background_density_map option is for the block-level design extraction. It allows you to set the estimated design
density around the design block. The specified background density will be included when Quantus calculates the block
design density around the boundary. This CCL option is applicable to both the LEF/DEF and LVS flows. In the
LEF/DEF flow, for the technology nodes >20nm, the background_density_map option will work only if
the extraction_setup -density_bounding_box diearea CCL is specified. However, for the advanced nodes (<=20 nm),
you do not have to specify the -density_bounding_box diearea CCL option because this option is set by
default. Therefore, it is recommended that you always set the -density_bounding_box option to diearea when using
the -background_density_map option.
change_lithobias_direction true | false
This feature is related to advanced process modeling that requires special access. For more information, please
contact Quantus Product Engineering team.
Set this option to enable Quantus to apply horizontal direction bias on vertical edges and vice versa. You can use this
option only if the qrcTechFile has been built using the lithoBias file during Techgen simulation. In addition, this option is
valid only when output_db -type is dspf, spef, spice, or extracted_view .
change_overhang_direction true | false
Specifies to change the direction of the overhang via. This option affects the overhang via’s xy overhang parameters.
When the -change_overhang_direction option is set to true, the x-overhang becomes y-overhang, and vice versa. The
option has effect on the drawn dimension enclosure as well as the silicon dimension enclosure. It does not affect the
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lithobias table operations.
cluster_vias_in_em [true | false]
The cluster_vias_in_em option allows you to keep the double-cut vias clustered and eliminates the bridge resistor
between the two node (terminals) in the EM analysis flow (extraction_setup –analysis em). The default is false.
copy_port_to_obs [ true | false ]
When the copy_port_to_obs option is true, Quantus reads instance pin geometries for connectivity checking and loads
the instance pin geometries as gray data (similar to OBS geometries) for consideration during capacitance extraction.
The default is true.
Following example illustrates the behavior of the copy_port_to_obs true option when Top DEF, Block A DEF, Block A
LEF, and Block A GDS are available:
Case 1: If only Top DEF and Block A LEF are available
Quantus uses the LEF port location, LEF port shape, and LEF OBS shape.
Case 2: If Top DEF, Block A LEF, and Block A DEF are available
Quantus does not use the LEF port location, LEF port shape, and LEF OBS shape. It only uses the data from the
Block A DEF.
Case 3: If Top DEF, Block A LEF, and Block A GDS are available
Quantus uses the LEF port location only. The LEF port shape and LEF OBS shape are ignored.
In addition, when the LEF port/OBS location and shape are used, Quantus refers to ORIGIN in LEF.
custom_dpt_corner corner_definition_file_name
Defines a shift corner. The corner_definition_file_name has the following syntax for GDS flow.
marker_layer ictfile_layer shift_x=amt_in_um shift_y=amt_in_um
where,
marker_layer is the colored mask layer used in the GDS.
shift_x and shift_y are keywords used to define the mask shift in x/y direction.
The absolute value of amt_in_um must be less than or equal to max_shift valuedefined in the ICT file.
Quantus will have zero shift in cases where marker_layer/ictfile_layer combination not included in the corner
definition file.
Sample Corner Definition File
*this is a comment line. Metal1_A, Metal1_B are the mask layers used in GDS
Metal1_A Metal1 shift_x=0.002 shift_y=-0.002
Metal1_B Metal1 shift_x=-0.002 shift_y=0.001
The corner_definition_file_name has the following syntax for LEF/DEF flow.
mask_number ictfile_layer shift_x=amt_in_um shift_y=amt_in_um
where,
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mask_number comes from DEF mask number.
shift_x and shift_y are keywords used to define the mask shift in x/y direction.
The absolute value of amt_in_um must be less than or equal to max_shift value defined in ICT file.
Sample Corner Definition File
1
Metal2
shift_x=0
shift_y=0.00165
2
Metal2
shift_x=0
shift_y=-0.00165
1
Metal3
shift_x=0.00165
shift_y=0
1
Metal4
shift_x=0
shift_y=0.0016 5
delete_layers <lvs_layer1> <lvs_layer2>
Specifies the LVS layer names that need not be promoted to the top cell in the white mode macro cell RC extraction.
You can specify one or more LVS layers using this option. The behavior of extraction_setup -delete_layers
<lvs_layer1> <lvs_layer2> … is identical to that of the delete_layer=<lvs_layer1>,<lvs_layer2>,… in
the layer_setup file. In the layer_setup file, the delete_layer= keyword can be used multiple times; while in CCL, delete_layers can be specified only once.
Quantus will merge the two lists as the full set of delete layers. Therefore, if layers are deleted by the CCL –
delete_layers, they need not be specified in the layer_setup file.
Example:
In CCL: extraction_setup –delete_layers metal1_bboxlayer metal2_ bboxlayer metal3_ bboxlayer
In -layer_setup file: delete_layer=metal1_ bboxlayer,metal4_ bboxlayer
The net effect is that four LVS layers are deleted: metal1_ bboxlayer, metal2_ bboxlayer, metal3_ bboxlayer,
and metal4_ bboxlayer.
delete_layers_file <full_path_name_deleteLayers.defs>
Specifies the location of the deleteLayers.defs file. This option is the file-based version of the -delete_layers CCL
option. The file-based version of the option is mutually exclusive with the non-file-based version.
The Quantus UI translates the contents of the deleteLayers.defs file into a set of CCLs and includes them in the output.
Use the delete_layers_file option to enable this Quantus UI functionality in the batch mode. The specified file need
not be located in the technology directory, nor does it have to be named as deleteLayers.defs.
This feature is supported in the transistor-level flow for the Assura, Pegasus, and Calibre LVS front ends, and all output
formats, except lvs_extracted_view.
delta_gate_ckt [ true | false ]
Instead of detecting whether the gate is one-end connection or double-end connection in
Quantus, delta_gate_ckt produces an equivalent circuit to model gate resistance. The equivalent circuit is the same for
either a single connected gate or a double connected gate, and the equivalent gate resistance will be adjusted
automatically based on the interconnect connection outside the gate. This CCL option is equivalent to the delta_gate_ckt Techgen compilation option. The extraction_setup -delta_gate_ckt false CCL command option is
the default (this is same as the -delta_gate_ckt CCL option not being specified). Therefore, the -delta_gate_ckt
false CCL does not disable the Techgen -delta_gate_ckt option. To turn off the -delta_gate_ckt Techgen option,
you can specify the res_gate_factor CCL command option to override, or specify the -double_gate_conn false CCL
command option.
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The equivalent delta circuit is shown in the following diagram:
Assume N1 is connected to outside circuitry node A, and N2 node is dangling, the equivalent resistance from N1 to gate
is 1/3 R g, same as a single connected gate using a gate res factor of 3.0 (see " res_gate_default_factor " for more
information). Assume both N1 and N2 are connected to node A, then N1 and N2 has same node voltage, therefore the
equivalent resistance between N1 is 1/12 R g, which is same as a double-gate connection.
The advantage of this delta model is that it handles single/double connected gates automatically. However, some circuit
simulators do not support using negative resistor (-1/2 R g) in the circuit representation. Therefore, while
the delta_gate_ckt may offer greater flexibility in calculating gate resistance and performing circuit simulation, it may
not be a practical choice for you.
An alternative to the delta_gate_ckt command is to use the res_gate_factor or
the res_gate_default_factor commands that take into consideration the effect of single and double connected gates
on resistance. This is an effective alternative to the use of the delta_gate_ckt if your simulator does not support
negative resistor values.
delta_gate_ckt_by_device “<devLayer1>” "<devLayer2>” …
This option allows the existing -delta_gate_ckt compilation option to be applied to a subset of devices. The
argument is a list of MOS/LDD device recognition layer names as taken from the LVS rule file, or layers declared in the
Techgen compilation command -genericMos. This CCL option is equivalent to the
- delta_gate_ckt_by_device Techgen compilation option.
delta_gate_ckt_by_gate “<gate1>” “<gate2>” …
This option allows the existing -delta_gate_ckt compilation option to be applied to a subset of devices.
The delta_gate_ckt_by_gate option is similar to delta_gate_ckt_by_device, except that -delta_gate_ckt_by_gate will
also automatically set Techgen -genericMos commands for the device layers of the devices that have the specified gate
layers. However, this command should only be used if the genericMos pin names from the LVS rule file have caseinsensitive D and S for the source and drain pins. The gate pin name has no restrictions. Since D and S share the same
LVS diffusion layer, the auto-generation of the genericMos command may inadvertently swap them if not D and S.
The argument is a list of LVS gate layers. For example, in an LVS file, two generic devices may use the same “gate1” as
the gate layer.
element generic[model] device1
element generic[model] device2
term1[D] gate1[G] term3 [S] term4[B]
term5[D] gate1[G] term6[S] term4[B]
The “gate1” layer, also the G terminal, is declared in the –delta_gate_ckt_by_gate. From “gate1”, multiple device
recognition layers (device1, device2) may be found. This CCL option is equivalent to
the -delta_gate_ckt_by_gate Techgen compilation option.
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delta_gate_ckt_pi_distribution [ true | false ]
Specifies that the partial gate to diffusion capacitance (Cgd, Cgs) distribution should be done in the PI fashion, that is,
50% each on g1 and g2 (far sides of the gate region). The partial Cgs and Cgd refers to the amount that is defined in the
poly sub_conductor’s gate_diffusion_fringing_cap section (a function of cf_poco_spacings) in the ICT file.
The following diagram illustrates vertical gate resistance (Rg) with optional PI capacitance distribution:
This diagram shows that the capacitance from node “g” is evenly distributed to s and d (or the diffusion nodes) from the
2 new nodes “g1” and “g2” on the poly layer. By default, the gate capacitance is distributed fully on the gate node “g".
The partial gate to diffusion capacitance distribution will be done on all device types that are used with delta_gate_ckt (either by Techgen setup or by CCL specifications). Unlike other -delta_gate_ckt CCL options, the delta_gate_ckt_pi_distribution is not available as a Techgen -compilation option.
The delta_gate_ckt_pi_distribution CCL option can be used with or
without lw_dependent_vertical_gate_resistance (vertical gate resistance) in the ICT file. This option is recommended
for the FinFET process nodes. It should not be used in the mature process nodes
where gate_diffusion_fringing_cap is defined as a 2D table. The -delta_gate_ckt_pi_distribution option is
supported in Quantus FS but not in QRCFS.
density_bounding_box [ design_data | diearea | perlayer | path_data | rectangle xlo ylo xhi yhi ]
The density of interconnect can affect the thickness of the interconnect due to erosion. The effect of erosion due to
density on the interconnect thickness, and therefore on both the resistance and capacitance calculations are defined in
the technology file (see Quantus Techgen Reference Manual).
The calculation of density is the key to determining how the rules defined in the technology file will be applied to the
design. The density_bounding_box command allows you to specify a method for calculating the density of the design.
The command selects the method that Quantus uses to check the wire density of the chip for the purposes of wire
thickness adjustments, or erosion. The possible choices are:
design_data
Checks the wire density in the area defined by the lower-left corner to upper-right corner of the layout
database. It checks the area on all layers.
The area is divided into tiles as defined by the erosion specification of the technology file (usually 50
to 100 microns square).
This option is recommended for block-level checking and is the default.
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​ diearea
​ ​ Checks the wire density in the area defined by the diearea keyword in the DEF file. It checks the
area on all layers. It checks the area by dividing it into a tile size defined by the erosion specification
of the technology file.
This option is recommended for full-chip checking. This argument is only supported in the LEF/DEF
flows.
Note: For advanced nodes (20nm and below), the default value for -density_bounding_box is
diearea.
path_data
Specifies to use the nominal density of 0.5 in a design. This argument is only supported in the LVS
flows.
​ perlayer
Checks the wire density in the area defined by the extent of routing on each area of a layer.
This option is recommended for validating layout accuracy only.
rectangle
xlo ylo xhi
yhi
Checks the wire density in a rectangular region defined by the lower-left corner and upper-right
corner specified (xlo ylo xhi yhi). This argument is only supported in the LEF/DEF flows.
double_gate_conn [ true | false ]
The double_gate_conn command affects the way in which the res_gate_default_factor command is applied by
Quantus (see " res_gate_default_factor ").
When you expressly define a res_gate_default_factor or res_gate_factor, Quantus will handle double connected
gates differently from single connected gates. To change the res_gate_default_factor while still treating all devices as
single connected gates or to disable the delta_gate_ckt option at Quantus run time, you must set
the double_gate_conn command to false.
This CCL option is equivalent to the -no_double_gate_con Techgen compilation option. The default is true for double_gate_conn. If set to false, it is the same as Techgen -no_double_gate_conn.
enable_active_via_fill_processing [ true | false ]
This option can be used to control the processing of active via fill that are connected to the signal nets. The default
value of this option is true. When set to false, Quantus will ignore the processing of the active via fill shapes
corresponding to the design via layers. Active via fill can be specified in a GDS/OASIS file, similar to active metal fill
specification, but with a different datatype. The same layermap CCL can be used for active metal fill and active via fill,
as given below:
-gds_active_fill_layer_map <design_layer_name> <gds_layer_number>
<gds_datatype> [...]
-oasis_active_fill_layer_map <design_layer_name> <oasis_layer_number> <oasis_datatype> [...]
enable_bump_instance [true | false]
Starting with PVE 12.1 release, you can report micro-bump as .subckt in DSPF for critical net timing analysis with
SPICE using the following CCL command:
extraction_setup -enable_bump_instance true
In this case, Quantus will report micro-bump as an instance call in DSPF output using the IO interface defined in the IPF
file under the sub_circuit string. You need to provide micro-bump modeling for SPICE.
This option should be used with -bump_map_file together.
For more information, see 3DIC Extraction .
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enable_corner_relaxation true | false
At times, specifying the corner conditions may present situations that are statistically unlikely to happen, thus resulting
in extracted RCs being too pessimistic. Starting with the EXT 9.1 release, Quantus (at cell-level) has been enhanced to
relax the corner conditions to make the extracted RCs more realistic.
The enable_corner_relaxation option enables the relaxation of corner conditions.
In many cases, you may want to relax the corner condition towards the typical (or center) corner, therefore, it is
recommended to specify the typical corner as the first corner when specifying the corners in CCL command file. The
results after relaxation may vary depending on the specification of the first corner (reference corner).
Note: This feature is applicable to Quantus cell-level flow only.
This feature is supported in multiple-corner extraction mode and applicable to:
RC (coupled) and RC (decoupled) modes only
Note: C-only type of extraction is not supported because a resistor network is required.
All capacitance modes (default, fast)
Dual output mode, reduction, and SP/DP
Note: With topological corner, the decoupled capacitance values between dual output mode and standalone
mode might not be the same due to differences in topology between the coupled and decoupled modes.
You must use the enable_corner_relaxation option in conjunction with the following:
Multiple process corner (process_technology -technology_corner).
Explicit vias (output_db -add_explicit_vias true).
No sensitivity (extraction_setup -enable_sensitivity_extraction false).
RC extraction (extract -type rc_coupled | rc_decoupled).
enable_diffusion_resistance_equations false
The enable_diffusion_resistance_equations option requires and XL license and an Advanced Modeling (AM)
GXL option.
Set this option to make Quantus ignore the diffusion resistance equations specified in the ICT file. If this option is not
specified and the ICT file contains the user-defined diffusion resistance equations, Quantus, during run time, enables
the explicit netlisting of S/D contacts and also does not merge them with one another.
For more information on the diffusion resistance equations, refer to Quantus Techgen Reference Manual .
enable_dpt_color_import [true | false]
Starting with PVE 11.1.2 HF1 release, you can turn off color information in both Quantus(LEF/DEF) and
Quantus(GDSII) flows using the folllowing CCL command:
extraction_setup -enable_dpt_color_import [true | false]
In the DPT corner mode, all wires will have unknown color. That means, the DPT corner will not have pessimism
reduction. Each corner can be calculated independent of typical corner.
For more information, see Support for Pessimism Reduction with Triplet DPT Corners Flow.
enable_eco_mode [true|false]
When this option is set to true, enables incremental extraction with support for automatic detection of design changes.
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Automatic incremental extraction has 2 steps:
1. Base run with full extraction - you need to run full extraction to automatically detect design changes when
running incremental extraction. Use -enable_eco_modetrue to enable incremental extraction from the base run.
2. Incremental run - you need to run incremental extraction with the same CCL command option, using the same
setup but the updated design. Quantus will automatically detect the design changes, and apply incremental
extraction to the changed design area. The output file is generated from the full design.
In the automatic incremental extraction flow, the re-extracted (incremental) nets information is printed to
the filename.incrext file by default after the Quantus run. The name of filename.incrext is same as the filename
specified with the output_db -user_defined_file_name option.
This feature is supported only with the DEF/LEF input. The incremental extraction flow does not support hierarchical
DEF files. The automatic incremental extraction flow supports change in the input GDS metal fill file name between the
base run with full extraction and incremental extraction.
If you are specifying the DEF or OA input using the command line option in the incremental extraction flow, the
DEF file name or the OA view name can be different but the remaining arguments must be same in the
subsequent runs.
Quantus incremental extraction is targeted for small or localized design changes at the signoff stage for shorter runtime
compared to full extraction for every ECO loop. Quantus will keep the temporary database for use during next
incremental extraction.
enable_HPB_extraction [ true | false ]
Enables the High Performance Blocking (HPB) dielectric feature. If this option is not set to true, the other HPB related
CCL commands (input_db –type HPB and extaction_setup -HPB_layer_map) are ignored.
For more information on HPB airgap dielectric, refer to the "Advanced Node Modeling" chapter of Quantus Techgen
Reference Manual.
enable_sensitivity_extraction [ true | false ]
When you set this option to true, Quantus performs a statistical extraction of the design using the typical process corner
defined in the techfile ( techfile ), and statistical variations from the typical process as defined in the sensitivity
techfile ( techfile .sens). The sensitivity techfile is created through the use of the Techgen -cell variation command and is located in the same directory as the techfile (see "process_technology" ). Refer
to Quantus Techgen Reference Manual for more information on creating the sensitivity techfile.
Note: Sensitivity extraction is mutually exclusive with multiple process corner extraction (process_technology technology_corner). Quantus will exit with an error message if both are specified in the command file.
Sensitivity extraction has been extended to support coupled capacitance extraction as well as decoupled extraction. In
addition, Quantus supports an expanded resistance sensitivity that considers the effects of temperature variation on the
design.
Sensitivity extraction is only supported for the SPEF netlist output, and produces a new form of SPEF called sensitivity
SPEF, or sSPEF. If no SPEF output is specified for the extraction, Quantus will exit with an error. DSPF output can be
specified in addition to SPEF, however the DSPF netlist will only reflect the results of the typical technology file
specified with the process_technology -technology_name command.
Sensitivity SPEF format is a Cadence developed extension to the SPEF standard format. sSPEF is automatically
created when the output_db -type spef command is specified with sensitivity extraction. Although some Cadence
tools work directly with the sSPEF format, a standard SPEF netlist can be extracted from the sSPEF file for use with
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tools that do not support sSPEF. Please see the sSPEF2SPEF Utility chapter.
IEEE 1481 has finalized an official IEEE sSPEF format, which has become the industry standard. Therefore, starting
with the EXT 9.1 release, Quantus has been enhanced to produce a new sSPEF netlist output that maps to the IEEE
sSPEF format (see "Sensitivity SPEF Netlist" ). The new sSPEF is created when
the enable_ieee_sensitivity command is set to true.
Restrictions on sensitivity extraction:
Supports DEF or OA type input only.
Requires the presence of the sensitivity techfile ( techfile .sens) in the specified technology directory, or
Quantus will exit with an error.
Does not support inductance extraction (extract -type rlc_xxx or rlck_xxx).
SPEF output is required (output_db -type spef) or Quantus will exit with an error.
Requires output_db -add_explicit_vias to be enabled (true).
enable_TSV_Cc_model [true|false]
Starting with PVE 12.1 release, for transistor level 3DIC extraction, you can use following command to stitch TSV predefined coupling RC models defined in ICT file under frequency_dependent_tsv_rc section into the Quantus output file
(SPICE). Depending on the TSV spacing, Quantus will apply corresponding coupling resistance and capacitance in
SPICE output between TSVs.
extraction_setup -enable_TSV_Cc_model true
When this option is set to true, only one Rsub/Csub pair is inserted connecting the two T-RC groups.
enable_TSV_STA_Cc_model [true | false]
In STA mode, the inter-TSV Cc topology of Rsub/Csub can be reduced to a single Cc_effective. This is controlled by
the –enable_TSV_STA_Cc_model option.
The –enable_TSV_STA_Cc_model option is mutually exclusive with –enable_TSV_Cc_model option.
enable_tsv_instance [true | false]
Starting with PVE 12.1 release, you can report TSV as a .subckt in DSPF for critical net timing analysis with SPICE
using the following CCL command:
extraction_setup -enable_tsv_instance true
In this case, Quantus will report TSV as instance call in DSPF output using the IO interface defined in ICT file
under sub_circuit string. You need to provide TSV modeling for SPICE.
force_array_via_by_layer <v1> <v2> ...
This option specifies the LVS via layer names for which array vias are to be formed. When this option is specified, the
corresponding ICT file vias must have overhang_dependent_via keyword. This keyword is used to specify the relation
between the via overhang values and the final via resistance value (or area). This is illustrated in the figure below. On
the left side, array vias are not formed. On the right hand side, array vias are formed. The array via’s R value is
computed by parallel resistors of R1 and R2. Due to the simplified R network, the distributed R4 becomes lumped. In
this case, half of the R4 value will be lumped to R5. The relation of the R values are as follows:
R5’ = R5 +0.5*R4
R3
= R1||R2 = R1*R2/(R1+R2)
Array Via for Overhang Via
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This feature is only applicable to the Quantus(LVS) flow.
Note: Bridge vias and abutment vias are forbidden from forming array vias. They cannot be used in force_array_via_by_layer.
fs_window_file <window_file_name>
The fs_window_file option enables the window feature in Quantus field solver. In the window feature, you need to
specify a rectangular window with two choices of boundary conditions (periodic or reflective) available in each direction
(x or y). The window is specified by a rectangle in a text file. Quantus FS will calculate the capacitances for objects
inside the window, and with the specified boundary conditions applied.
A window can be described in a text file using the following syntax:
x_window <xmin> <xmax> reflective|periodic
y_window <ymin> <ymax> reflective|periodic
top_ground_plane <z value in µm>|infinity
x_ground_planes <x1 value in µm>|infinity
y_ground_planes <y1 value in µm>|infinity
#optional
<x2 value in µm>|infinity
<y2 value in µm>|infinity
The x_window and y_window are keywords, indicating the direction in x-axis and y-axis respectively. The < xmin >
< xmax >, < ymin >, < ymax > are the two coordinate ranges that define the window. The coordinates are specified in an
unscaled manner matching the GDSII. The specified window may cut the conductors. The window is layer
independent. That is, one window is specified for all layers in the layer stack of the given ICT file.
The reflective or periodic keyword indicates the boundary conditions. There are a total of 4 combinations, in the
order
of x_window and y_window: reflective+reflective, reflective+periodic, periodic+reflective, periodic+periodic.
top_ground_plane can be set to a value (in µm) or inifinity (default). It defines the ground plane position above the
design. It is defined relative to the lowest substrate. There is always a ground plane at the lowest substrate bottom
(defined under the height keyword in the ICT file). For example, if a substrate has negative height, the z-coordinate
here will be above that negative height. Therefore, top_ground_plane is always positive.
The x_ground_planes and y_ground_planes keywords define two XY ground planes. This keyword requires two
coordinates, each is either a number or the infinity keyword. If a number is provided, Quantus FS will not replicate the
design cell in the specified x or y direction. This is an approximation to the boundary cell, where the ground plane
models another circuit at some distance. You can use the infinity keyword in place of x1 x2y1 y2, which states to
keep infinite replication of a cell on the specified axis. The default value
for x_ground_planes and y_ground_planes is infinity infinity.
The following is an example of defining the cell boundary conditions:
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Here, the window file has the following information:
x_window 0.1 0.2 periodic
y_window 0.2 0.3 periodic
x_ground_planes 0.0 infinity
For finite ground coordinate, the software will disable cell replication. Therefore, the cell boundary will model free space
till the ground plane.
The window mode support is not available for Quantus (2.5D) extraction
The following diagram illustrates a window over a 3x3 memory cell layout with periodic boundary condition:
In this diagram, the window is drawn over the center cell. The reported capacitance C(1c, 2c) will include the portions
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C(1c,2), where 2 is the shapes on all the other virtual cells; while C(2c, 2) will be ignored as self capacitance.
Additionally, C(1c, 1_left) and C(1c, 1_right) will be skipped as self capacitance.
The following is a finFET example of a window with mixed boundary conditions:
Finfet layout is repetitive due to the fin structures. The window feature may cut down the field solver computation time,
where the computation is focused only in a small area.
Note that the capacitance from a window extraction may not match that of the full layout. In this case, the full layout does
not have infinite repetitions. However, window extraction is expected to run faster if window is small, while full layout is
large. If the full layout has many repetitions and is large, and the window is relatively small, that is the ideal
combination: window extraction is fast and accurate, as compared to the full layout extraction.
The following are the alternate layouts of the above finFET example with mixed boundary conditions:
The capacitance values and the display will be identical for the three different layouts with identical windows and
boundary conditions.
The specified boundary condition is recorded in the log file. The following is a snippet from the command file and log
file:
Command file:
x_window 11.385 11.565 reflective
y_window 25.080 25.584 reflective
top_ground_plane 2
Log file:
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INFO (NEBULAM-135085): Found boundary cell in fs_window_file_bitcell.txt_1x1:
x_window: [11.385,11.565] reflective
y_window: [25.08,25.584] reflective
top ground plane: 2
gds_active_fill_layer_map <design_layer_name> <gds_layer_number> <gds_datatype>
[<design_layer_name> <gds_layer_number> <gds_datatype>] …
This option is required to import the fill data (of touching or overlapping LEF/DEF wires) to Quantus. The option
specifies the fill layer number and data type that is stored in the GDSII file.
The Quantus LEF/DEF flow now supports extraction of fills that may touch or overlap LEF/DEF wires. The capability to
support third party metal fill GDSII file input has been added. Quantus can extract metal fill from third party tool (GSDII),
which contains both metal and other supported fills. The fill data can be imported into the design using the
same input_db command for metal fill through GDSII file input.
gds_layer_map <design_layer_name1> <gds_layer_number1>
[ <gds_datatype1> ] [ <design_layer_name2> <gds_layer_number2> [ <gds_datatype2> ] ...
and/or
oasis_layer_map <design_layer_name1> <oasis_layer_number1>
[ <oasis_datatype1> ] [ <design_layer_name2> <oasis_layer_number2> [ <oasis_datatype2> ] ...
Note: If you are using both formats, it is recommended to use GDS-II for library cells and OASIS for metal fills.
The gds_layer_map or oasis_layer_map option maps the layer names in the design file to the layer names in the
GDS/OASIS file. You only need to use this command if you are using a GDS/OASIS file to import layout data for the cell
library or metal fill into the design.
<design_layer_name> specifies the layer name from the LEF/DEF input.
<gds_layer_number> [ <gds_datatype> ] | <oasis_layer_number> [ <oasis_datatype> ] specifies the GDS/OASIS layer
number and layer datatype from the GDS/OASIS file.
Note: The optional gds_datatype | oasis_datatype will be defined as -1 if you do not specifically define it as part of
the gds_layer_map or oasis_layer_map command.
Note: If both GDS and OASIS layer mappings are specified together, they are combined. Duplicate cells are ignored
regardless of the type of input.
Example:
extraction_setup
-gds_layer_map
CM102 12 0
CM130 13 0
-oasis_fill_layer_map
CM102 24 0
CM103 25 0
gds_fill_layer_map < layer_name > < layer_number > < data_type >
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and/or
oasis_fill_layer_map < layer_name > < layer_number > < data_type >
The gds_fill_layer_map or oasis_fill_layer_map options specify the cell/macro-level metal fill layer number and data
type specified in the GDS/OASIS library.
Note: The gds_fill_layer_map/oasis_fill_layer_map option is needed when the metal fill data is hierarchical (that is,
the cell/macro library includes both the library data and the metal fill data for the library while the metal fill data for the
top-level routing is stored in separate GDS/OASIS). Metal fill data sets for top-level routing and for the library must be
complimentary (no overlapping between top-level metal fills and cell-level metal fills). You must specify a unique layer
number or data type for Quantus to correctly distinguish metal fills and the layout data (no duplicate layer number and
datatype between this option and -gds_layer_map/oasis_layer_map).
Note: The top-level metal fills can be specified using the input_db -type metal_fill CCL command.
gds_layer_map_by_color -| 0 | 1 |
2 designLayer1 gdsLayer1 gdsDataType1 designLayer2 gdsLayer2 gdsDataType2 … \
This option is needed to map the layer names in the macro/cell level GDSII files with color information. You need to use
the color-based layermap if there are colored design layers. For more information on mapping of layer names in the
GDS gray data file with color information, refer to the "Advanced Node Modeling" chapter of Quantus Techgen
Reference Manual.
<color mask value> specifies the LEF/DEF color mask number. The possible values are -, 0, 1 and 2. For color-based
layer map, if there is any layer without color, use "-" or "0" to define the color value.
<design_layer_name> specifies the layer name from the LEF/DEF input.
<gds_layer_number> [ <gds_datatype> ] specifies the corresponding GDS layer number and layer datatype from the
GDS file.
This option is similar to the -gds_layer_map option. The only difference is that this option has the LEF/DEF color mask
number as the first argument.
gds_fill_layer_map_by_color |0|1|2 designLayer1 gdsLayer1 gdsDataType1 designLayer2 gdsLayer2 gdsDataType2 …
This option is needed to map the metal fill layer number and data type specified in the GDS file with color
information. For more information on mapping of layer names in the GDS metal fill file with color information, refer to the
"Advanced Node Modeling" chapter of Quantus Techgen Reference Manual.
This option is similar to the -gds_fill_layer_map option. The only difference is that this option has the LEF/DEF color
mask number as the first argument.
global_frequency <value>
The global_frequency option is used for substrate netlist reduction (when Substrate extraction is activated).
Specify the frequency in MHz. You must specify a value greater than zero as the global frequency. The default is no
value (blank). If you do not specify a value, Quantus internally uses 5 GHz as the substrate reduction frequency.
When global_frequency is specified as greater than 0, then the substrate reduction frequency is calculated at three
times the specified value to ensure a conservative substrate reduction result applicable over the frequency range.
The global frequency should be set to the frequency of interest, or to the maximum frequency of operation if there is a
frequency range of interest, so that signals in the circuit to be simulated have major spectral content below the specified
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value. For example, if an LNA is designed to operate at 2.1 GHz then the frequency of interest is 2.1 GHz
and global_frequency should be set accordingly. However, if the frequency range of interest is between DC and 10
GHz, then global_frequency should be set to 10000.
Note: The global frequency does not have any impact on the interconnect parasitic reduction result.
Note: For TSV support in Quantus (STA flow), a qrcTechfile may be coded with “tsv_effective_Cc” 2D table, which can
be used to find the effective coupling capacitance between neighboring TSVs, not just based on their spacings but also
on operating frequencies.
So extraction_setup –global_frequency option can be used to specify the operating frequency during Quantus
runtime, for the ictfile look up table to obtain the effective Cc between two neighboring TSVs.
HPB_layer_map designLayer1 gdsLayer1 gdsDatatype1 …
Specifies the HPB layer name from the LEF/DEF input, and the GDS layer number and layer datatype from the GDS
file. The option enables the mapping of one GDSII layer name to one design layer name. Note that the designLayer1 is
not necessarily the ICT file layer name. The design layer and ICT layer mapping is controlled by the following CCL:
extraction_setup –technology_layer_map designLayer1 techLayer1 …
ignore_cells_file <filename>
​ ​ The ignore_cells_file option excludes certain macros, or cells, from the Quantus resistance and capacitance
extraction. If a net refers to a pin of an excluded cell, Quantus excludes the pin as well. It does not generate warnings or
errors pertaining to excluded cells.
<filename> specifies the file that lists the cells to ignore during extraction. The file lists one cell per line.
Starting with the PVE 11.1.2 release, you can also comment a line in < filename >by appending a pound-sign
character "#" at the beginning of the line (tab or space before # is allowed). Anything after # is considered a comment.
You cannot use # in the middle of a line if a non-space character exists before it. You can also have multiple comment
lines in a file.
ignore_conn_to_bump [ true | false ]
Specifies to output the bump pin name to the SPEF and DSPF files when a net is connected to a bump cell. The default
value is true. You can use this option if you want to print the bump pin name instead of the top design pin name in the
output file. When you set this option to false, Quantus prints the bump cell pin name to the output file. This feature is
supported only for the DSPF and SPEF format output in the cell-level flow. This option is useful when you want to check
pin-to-pin resistance up to the bump cell pin.
The following table describes the tool behavior when the ignore_conn_to_bump option is specified with
the promote_bump_ports option:
Cases
CCL Command
Quantus Behavior
Case
1
-ignore_conn_to_bump
true
-promote_bump_ports
true
Promote bump ports, and does not print the bump pin names in the output.
Case
2
-ignore_conn_to_bump
false
-promote_bump_ports
true
Promote bump ports, and print the bump pin names in the output.
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Case
3
-ignore_conn_to_bump
true
-promote_bump_ports
false
Does not promote bump ports, and does not print the bump pin names in the
output.
Case
4
-ignore_conn_to_bump
false
-promote_bump_ports
false
Does not promote bump ports, but prints the bump pin names in the output.
ignore_invalid_colored_shape [false | true]
Controls ignoring of invalid color shapes in the LEF/DEF flow. By default, this option is set to true.
ignore_invalid_vias <true | false>
When Quantus reads in the design data from a LEF/DEF and OA input, it errors out if it finds invalid via data (for
example, undefined layer in the techfile). The ignore_invalid_vias argument enables Quantus to ignore invalid via
definitions found in the LEF/DEF and OA input files. The default value is false.
The extraction_setup -ignore_invalid_vias option replaces the input_db -ignore_invalid_vias option, which is
applicable only to LEF/DEF input.
ignore_pin_list <pin_name1> <pin_name2> ...
​ ​ ​ The ignore_pin_list option allows you to specify certain instance ports, such as the power and ground ports, which
are not extracted for timing.
ignore_pushdown_blockages [ true | false ]
Controls the use of BLOCKAGES marked with "+ PUSHDOWN" in the DEF input file. The BLOCKAGES section is used to define
placement and routing blockages in a design. To ignore the PUSHDOWN-BLOCKAGES in the DEF input file during extraction,
set this option to true. Depending upon the number of input DEF files, Quantus behavior varies for different settings of
this option.
If you run extraction with only single DEF file, then:
when you set this option to false (the default value), Quantus includes all PUSHDOWN BLOCKAGES during the
extraction.
when you set this option to true, Quantus ignores all PUSHDOWN BLOCKAGES during extraction.
If you run extraction with multiple input DEF files, then:
when you set this option to false (default value), Quantus only includes all PUSHDOWN BLOCKAGES defined in
the top-level DEF file and ignores all those defined in block-level DEF files. This is applicable only to
Standalone Quantus because extraction launched from Innovus does not have multiple DEF flow.
when you set this option to true, all PUSHDOWN BLOCKAGES are ignored during extraction.
ignore_unconnected_bump_cells <true | false>
The -ignore_unconnected_bump_cells option when set to true, excludes the unconnected/floating bump cells from the
Quantus resistance and capacitance extraction. The default value is false. In some cases, at the tapeout stage, you
may remove all unconnected bump cells from the design. This option is helpful to simulate the same situation during
extraction.
This option is required only when –promote_bump_ports is set to true to control the handling of the unconnected/floating
bump cells.
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include_gate_forming_layers [true|false]
Specifies to extract parasitics on the poly layer (routed in DEF/OA) or the non-planar top-most conductor layer of a
design. It is not mandatory to regenerate the Quantus technology file (if you already have the simulated technology file
with a recent version of Techgen), as Quantus will create some special RC models during run time using this option to
handle the extraction of coplanar poly layers and non-planar conductor present in designs.
This option is supported only in the cell-level flow (DEF/OA input).
keep_multi_port_pin [true | false]
The keep_multi_port_pin option preserves and outputs subnodes in the extended SPEF for multi-ports pin extraction.
This option must be specified with extraction_setup –analysis em. When -keep_multi_port_pin is set to true, the
software preserves the physical connection to a multi-port pin as the connection to the pin and its subnodes. There will
be a logical minimum resistor connecting those subnodes to the pin. The default is false.
layer_max_etch_aspect_ratio_map "all <aspectratio>" or "<layer1> <aspectratio1>" "<layer2> <aspectratio2>"
Specifies to clip the width index of the wire_edge_enlargement and wire_edge_enlargement_by_color table (first order
and color wee) by the length of the wire edge multiplied by a factor called the aspect ratio of the wire. Aspect ratio is
width to the wire length (W/L). The measured drawn width is clipped by an amount equal to the edge length multiplied
by a factor called max etch aspect ratio (W/L), as shown in the following diagram:
The following examples illustrate the different use models of this option:
extraction_setup -layer_max_etch_aspect_ratio_map "all 1.0"
Specifies to use the max aspect ratio of 1.0 for all layers.
extraction_setup -layer_max_etch_aspect_ratio_map "M0 1.05" "M1 1.01"
Specifies to use a space-separated list of layers (M0 and M1 only) and their max aspect ratio, and no max aspect
ratio for the other layers.
extraction_setup -layer_max_etch_aspect_ratio_map "all 1.0" "M0 1.05" "M1 1.01" "M2 1.02"
Specifies to use a space-separated list of layers (M0, M1, and M2) and their max aspect ratio, and set a max
aspect ratio of 1.0 for all the other layers.
The layer_max_etch_aspect_ratio_map option is supported in all output formats. This option is applicable to both
Quantus and Quantus FS flows.
layout_scale <number>
The recommended method of defining scale is to specify the layout_scale keyword in the ICT file. The use of this
command is no longer suggested. Refer to Quantus Techgen Reference Manual for more information on
defining layout_scale in the techfile.
If layout_scale is defined in the techfile and with this command, the values must match or an error will occur.
​ The layout_scale option scales the drawn dimensions in the layout by the scale factor number that you specify. Using
this option enables Quantus to scale the drawn dimension of the design data to match the silicon dimensions of the
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techfile.
The specified number can range from 0.01 to 1.2. The default is 1.0, indicating that no scaling is performed. For
example, a layout_scale of 0.75 indicates a scale reduction of 25%
lic_queue <timeout_value>
Instructs Quantus to add itself to a queue to wait for an available license. When run in the distributed processing mode,
Quantus will wait for the required number of licenses to become available prior to starting the extraction run. The default
timeout value is 0 (-lic_queue is not specified). However, if you specify the -lic_queue option without a timeout value,
the license wait time will be 1800 seconds.
This CCL command option is equivalent to the quantus -lic_queue <timeout_value> command line option. For
information on the command line option, refer to Quantus Command-Line.
Note: The -lic_queue option specified using the Quantus command line has higher priority over that specified using the
CCL option.
low_memory_usage [true | false]
Allows you to make a trade-off between memory usage and hard disk usage.
false - uses memory first till the assigned memory of the job is consumed. Memory is used for persistent data
storage. This is the default value.
true - uses hard disk for persistent data storage, and uses limited memory.
This option is applicable only to the cell-level flow.
macro_cells_type [ default | white ]
Use this option to specify whether the net parasitics (resistances and capacitances) between the top-level nets and the
nets within the macro cells should be considered during RC extraction. The default value of this option is default,
which means that the macro cells are treated as black boxes, and the net parasitics between the top-level nets and the
nets within the blocked cells will not be considered during RC extraction.
When this option is set to white, the parasitic resistance network penetrates into the macro cells. For the white mode,
you must specify all pin texts required to clearly mark the pin locations. If IO nets do not have pin texts, the R network
cannot enter the macro cell, and the net will be capacitive only.
Quantus checks out the Extraction XL license when the white mode macro cell extraction (for transistor level flow) is
invoked.
The white mode macro cell extraction (extraction_setup -macro_cells_type white) is not supported for the
Pegasus and Calibre LVS inputs except when used for the Voltus-Fi Hierarchical EMIR flow where it is a
required option.
The following diagram illustrates the cross-section view of the white mode macro cell RC extraction:
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Preferably, there should be one pin text per IO pin of the macro cell across all layers. If identical pin texts appear
multiple times, they are shorted. The quality of the R network is determined by the quality of user-supplied macro cell
pin texts, as shown below:
When the white mode macro cell is run in the C only mode, the user-supplied macro cell pin texts are not used. The
macro cell’s IO net pin shapes are then promoted to the top cell and carry the top cell’s net name.
In both the default and white modes, the top cell's pin order from LVS DB may be changed by an externally supplied pin_order_file. However in the white mode, the macro cell’s pin orders should not be changed by the pin_order_file, and pins should not be added or deleted.
Feedthrough pins in the macro cells are not promoted to the top level if they do not have labels or pin texts. You must
put one label for all IO/feedthrough nets in the macro cell.
​
Macro Cell Gray Mode Extraction
The macro cell gray mode extraction is not activated using the existing CCL command (extraction_setup macro_cells_type default|white). Instead, Quantus (transistor-level) supports the macro cell gray mode extraction
using the following CCL to improve capacitance accuracy:
graybox –type layout
In the macro cell gray mode extraction flow, the macro cell list is automatically recognized during the LVS DB import. If
cell blocking is also needed, then the blocking cells should be explicitly declared by the following CCL:
extraction_setup –parasitic_blocking_device_cells_file <file_name>
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You can also perform macro cell gray mode extraction together with white cell blocking (enabled
using extraction_setup -parasitic_blocking_device_cells_type white). In this flow, the macro cell shapes will be
seen in gray whereas the blocked cell shapes will be seen in white.
For the capacitance model in the gray mode, the cell content will be visible at the top cell as the capacitance ground
net. If there is an overlap of the cell content and top cell routings, the cell content (gray) will take precedence. The
macro cell gray box mode is supported across all output formats. The RC models with respect to various CCLs are
summarized in the following table:
graybox
-type
extraction_setup
-macro_cells_type
R model
C model
none
default
black box
(cell pin shapes visible to top cell routing)
black box
(cell shapes invisible)
none
white
white mode R network
white mode C network
layout
default
black box
(cell pin shapes visible to the top cell routing)
Gray box
(cell shapes visible as ground)
layout
white
Invalid CCL combinations
(white gray conflict)
Invalid CCL combinations
(white gray conflict)
max_fracture_length <value>
The <value> specifies the maximum length of resistors produced in the distributed parasitic RC networks. Extracted
parasitic resistors are limited to the specified maximum length.The default value of max_fracture_length for an LVS
input is infinite (no limit on interconnect length). In the cell-level (DEF/OA input) flow, the default value is 25 microns
for the advanced nodes (<=20 nm) and is 100 microns for the mature nodes (>20nm).
The -max_fracture_length option is not applied for the slanted metal layers.
Note: value cannot be less than 5 microns for both LVS and DEF/OA inputs. If you specify a value less than 5 microns
(or 5 squares), Quantus issues an error.
max_fracture_length_by_layer “<layer> <value>” [“<layer> <value>” …]
Specifies to fracture wires on a layer basis for resistance extraction. Here, the < layer > argument is the LVS layer
name and the < value > argument is the fracture length value. All the other LVS layers will be per
the max_fracture_length option. –max_fracture_length is optional. If not specified, the fracture length is “infinite”.
The –max_fracture_length_unit option is for both –max_fracture_length and -max_fracture_length_by_layer.
Therefore, both can be specified either in microns or squares.
Example :
extraction_setup –max_fracture_length_by_layer “M1 10.5” “M2 20”
For the M1 layer, the fracture length is 10.5um in GDSII dimension. Assume that the ICT file has 0.9 process scaling. On
silicon, the 10.5um long wire would actually be only 9.45um long.
For the M2 layer, the fracture length is 20um.
For the M3 layer, the fracture length is infinite.
max_fracture_length_unit [ microns | squares ]
Specifies the units for max_fracture_length as either microns or squares. The default is microns.
max_fracture_via_count < value>
Specifies how many fractures are created when modelling vertical resistors for vias that have zero thickness and are
defined using the ictfile via{} definition keyword fracture_vias true. If the R network is large, the via fracturing limit by
count can be controlled. The default value is 100. To reduce data volume, an alternative recommended value of 5 or 10
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can be used.
For more information on ictfile definitions, refer to Quantus Techgen Reference Manual.
max_resistance_mesh_size_error <value>
Specifies that the automatic mesh size for all layers is subject to the given error limit for the upper bound constraint. The
<value> is specified in percentage. This parameter is used in situations where the layout needs the most conservative
mesh size to achieve the highest possible accuracy.
For example, if 5 LVS layers need to be meshed, where the lowest LVS layer is M1; while the highest LVS layer is MTOP.
Here, the automatic mesh size is computed for the M1 layer, without the mesh size upper bound constraint. However, for
the M2 layer and above, the 1% error and the lower neighbor layer’s mesh size form the upper bound constraint. The
process continues sequentially until MTOP’s mesh size is calculated. Therefore, M2’s mesh size will be determined
by M1’s mesh size; and M3’s mesh size will be determined by M2’s mesh size, and so on.
The -max_resistance_mesh_size_error option can be used with the -resistance_mesh_size_k_factor option.
When both the CCLs are specified together, the -max_resistance_mesh_size_error will be applied first to limit the
mesh size based on the lower layer mesh size and the relative contact resistance.
The -resistance_mesh_size_k_factor and -max_resistance_mesh_size_error options can only be used with
the –resistance_mesh_automatic_size option.
max_via_array_count < value >
Note: This option is not supported for DEF or OA input.
To limit the via array size for LVS input, Quantus also provides the command option: extraction_setup max_via_array_count < value >
Where < value > specifies the number of vias per side allowed in an array.
The smaller the value , the higher the accuracy of the R network (in general), but the output resistor network will be
larger.
Note: -max_via_array_count is mutually exclusive with -max_via_array_size.
Arrays of Maximum Via Count
As shown in the above figure , the value of the max_via_array_count has been set to 2. This means that the number of
maximum vias allowed per array side is two. Quantus will group the vias into six arrays and create six via resistors
located at the center of each array.
For an array of X vias by Y vias, and -max_via_array_count has a < value > of N, where:
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X < N and Y > N, then the merged via arrays will be X by N. That is, the side with fewer vias than N will only have
X vias.
X > N and Y < N, then the merged via array is N by Y.
X < N and Y < N, then the merged via array is X by Y.
X > N and Y > N, then the merged via array is N by N.
The method that Quantus uses to determine via count is based on the via_count as defined in the process description.
Refer to Quantus Techgen Reference Manual for more information on defining contacts in the ICT file.
Note: By specifying a -max_via_array_count of 1, you can effectively disable the via array feature. Note that this is the
same as specifying defeat_array_vias for all layers in the layer_setup file.
max_via_array_count_by_layer “<layer> <count>”
This option controls the max via array count by the layer name. To limit the via array size for LVS input, Quantus also
provides the command option: –max_via_array_count_by_layer
where,
< layer > specifies the LVS via layer name.
< count > specifies the number of vias per side allowed in an array.
Since there is no default count value, all the applicable via layers should be specified. The smaller the count, the higher
the accuracy of the R network (in general), but the output resistor network will be larger.
Note: -max_via_array_count_by_layer is mutually exclusive with -max_via_array_size_by_layer for a given via layer.
The following is an example of this option:
extraction_setup
-max_via_array_count_by_layer "Via1 5" \
-max_via_array_count_by_layer "Via2 5" \
-max_via_array_count_by_layer "Via4 5" \
-max_via_array_count_by_layer "Via6 2" \
...
The following is an example of this option used in combination with -max_via_array_size_by_layer:
extraction_setup
-max_via_array_size_by_layer “via3 4.0”
-max_via_array_count_by_layer "Via2 5" \
When the small vias are merged, Quantus calculates the area as the sum of the areas of all small vias merged.
But, since the via’s area_resistance is not linear with the area, the super position principle is not applicable.
Thus, for via merging, single pair area resistance model should be used in the ICT file, as shown below:
via “via_name” {
area_resistance R1 A1
}
max_via_array_size [ <size> | auto ]
Quantus clusters groups of vias together into arrays to speed extraction by reducing the number of elements that have to
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be examined during extraction. However, when vias are merged into an array they are abstracted as to their centre point
in terms of resistance extraction. Therefore the parasitic resistance network may be overly pessimistic due to some
parallel paths not being modelled as a result of center-to-center resistance calculation.
With max_via_array_size, if a cluster of vias becomes larger than a specified size, Quantus can break the via arrays
into smaller clusters. You can specify the array size limit with the max_via_array_size command.
If max_via_array_size is smaller than the minimum width of a via, the via would be split. This design rule violation
situation should be avoided. The intended use model for max_via_array_size is to limit the size of a continuous via.
Quantus will fracture long vias if the via length is greater than the specified max_via_array_size. For example,
extraction_setup \
-max_fracture_length “infinite”
-max_fracture_length_unit "MICRONS” \
-max_via_array_size “5"
If the length of a via is 20 um, then Quantus will fracture the long via into 4 vias (each of 5 um length) because
the max_via_array_size is specified as 5. That is, each individual via (created after split) will have size equal to the value
of max_via_array_size.
< size > | auto - Specified in microns, reflecting the drawn dimensions of the shapes. The size is the maximum length of
any side of the via array.
You can specify "auto" for <size> to retain the Quantus internal value for merging via arrays. The default value is auto.
When you specify "auto", Quantus automatically sets the cluster size to 40 times via size. However, in the RLCK mode,
the auto option would set the cluster size to 40 microns. Note that via size is typically much smaller than 1 micron.
In addition, if the size specified is less than the array_vias_spacing, then a warning will be issued, and via arrays will
not be merged (this has the same affect as specifying the defeat_array_vias in the layer_setup file).
Consider an example in which the maximum via array size is specified as 1.0 um
Arrays of Maximum Via Size
As shown in the above figure , the size 1.0 um is meaured between the via boundaries. Quantus will group the vias into
four arrays and create four via resistors located at the center of each array.
See Quantus Techgen Reference Manual for more information.
max_via_array_size_by_layer “<layer> [<size>|auto]”
This option controls the max via array size by the layer name. Quantus clusters groups of vias together into arrays to
speed extraction by reducing the number of elements that have to be examined during extraction. However, when vias
are merged into an array they are abstracted as to their centre point in terms of resistance extraction. Therefore, the
parasitic resistance network may be overly pessimistic due to some parallel paths not being modelled as a result of
center-to-center resistance calculation.
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< layer > - Specifies the LVS via layer name. You can specify the max_via_array_size_by_layer option multiple times,
specifying different sizes for different layers.
< size > | auto - Specified in microns, reflecting the drawn dimensions of the shapes. The size is the maximum length of
any side of the via array. You can specify "auto" for <size> to retain the Quantus internal value for merging via arrays.
The default value is auto. If via layers are not explicitly mentioned in the CCL, it is set to the “auto” max size. Therefore,
you do not need to specify all sizes.
The following is an example of this option:
extraction_setup
-max_via_array_size_by_layer “via1 2.0”
-max_via_array_size_by_layer “via2 3.0”
-max_via_array_size_by_layer “via3 4.0”
The following is an example of this option used in combination with -max_via_array_count:
extraction_setup
-max_via_array_size_by_layer “via3 4.0”
-max_via_array_count 2
net_name_space [ schematic | layout ]
Indicates whether input net names are from the layout database or from the schematic. Specifically, this parameter
specifies the source of the net names referenced by various commands, such as extract -selection nets_file
<file> | -selected_path_file <file>.
nonmanhattan_resistance default_accuracy | high_accuracy
LCD/MEMS designs may feature near orthogonal routing features, angled from 0 to 10 degrees away from manhattan,
as opposed to perfect Manhattan or 45 degree lines. Set the nonmanhattan_resistance CCL option to handle such
routing features with better accuracy.
The nonmanhattan_resistance CCL option when set to high_accuracy, requires an XL license and a Display
Technology (DT) GXL option. However, if the qrcTechFile is created using the Techgen -non_planar simulation
option then this feature is automatically enabled and an additional DT GXL option is not required.
oasis_active_fill_layer_map <layer_name> <layer_number> <datatype> [<layer_name> <layer_number> <datatype>] ...
This option is required to import the fill data (of touching or overlapping LEF/DEF wires) to Quantus. The option
specifies the fill layer number and data type that is stored in the OASIS file.
The Quantus LEF/DEF flow supports extraction of fills that may touch or overlap LEF/DEF wires. The capability to
support third party metal fill OASIS file input has been added. Quantus can extract metal fill from third party tool
(OASIS), which contains both metal and other supported fills. The fill data can be imported into the design using the
same input_db command for metal fill through OASIS file input.
oasis_fill_layer_map_by_color |0|1|2 designLayer1 oasisLayer1 oasisDataType1 designLayer2 oasisLayer2 oasisDataType2 …
This option is needed to map the metal fill layer number and data type specified in the OASIS file with color
information. For more information on mapping of layer names in the OASIS metal fill file with color information, refer to
the "Advanced Node Modeling" chapter of Quantus Techgen Reference Manual.
This option is similar to the -oasis_fill_layer_map option. The only difference is that this option has the LEF/DEF color
mask number as the first argument.
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The color-based GDS/OASIS layermap (including -gds_layer_map_by_color, -gds_fill_layer_map_by_color, oasis_layer_map_by_color, and -oasis_fill_layer_map_by_color) is mutually exclusive with the non-color
based GDS/OASIS layermap (including -gds_layer_map, -gds_fill_layer_map, -oasis_layer_map, and oasis_fill_layer_map).
oasis_layer_map_by_color |0|1|2 designLayer1 oasisLayer1 oasisDataType1 designLayer2 oasisLayer2 oasisDataType2 … \
This option is needed to map the layer names in the macro/cell level OASIS files with color information. You need to
use the color-based layermap if there are colored design layers. For more information on mapping of layer names in the
OASIS data file with color information, refer to the "Advanced Node Modeling" chapter of Quantus Techgen Reference
Manual.
<color mask value> specifies the LEF/DEF color mask number. The possible values are -, 0, 1 and 2. For color-based
layer map, if there is any layer without color, use "-" or "0" to define the color value.
<design_layer_name> specifies the layer name from the LEF/DEF input.
<oasis_layer_number> [ <oasis_datatype> ] specifies the corresponding OASIS layer number and layer datatype
from the OASIS file.
This option is similar to the -oasis_layer_map option. The only difference is that this option has the LEF/DEF color
mask number as the first argument.
parasitic_blocking_device_cells_file < filename >
Note: Parasitic blocking of cells can be used with multiple process corner extraction (see "process_technology" ).
This command is used to block parasitic resistance and capacitance extraction for specific cells in the design. Use this
command to specify cells that already include parasitic RC values in their device models to avoid double counting. By
default, the coupling capacitances between the top-level nets and the nets within the blocked cells are considered
during capacitance extraction of the top-level of the design. However, the resistance inside the cell is not extracted.
Although the coupling capacitances within a blocked cell will not be extracted, the coupling capacitances of internal
nets between nearby blocked cells will be extracted.
Cells that participate in parasitic cell blocking must honor the following requirements:
Pin layers inside the cell must be the mapped to the LVS physical layers.
Connections to a cell from outside must occur by means of the same LVS layer as the pin shapes, and must
overlap the pin shapes. When several LVS layers are merged into a single layer, they count as the same LVS
layer. For example, if the LVS layers A and B are merged, layer A in the top cell can connect to layer B inside the
cell.
Connections to the cell by layer abutment is supported.
If the connection of a top cell to a blocking cell is through via, then via resistance is also extracted. For example, there is
an M8 layer inside the blocking cell, and there is an M9 layer at the top cell that overlaps the M8 layer, and the
overlapping area has the V8 via at the top cell. Quantus creates the port at the M8 LVS layer, and V8 resistance will be
extracted and output in the netlist.
The following diagram illustrates parasitic cell blocking:
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In this example, the cell content through the metal2 layer is blocked. The total capacitance for metal2 routing is correctly
computed while taking all neighboring cell content into consideration. All capacitors from metal2 routing to shapes
inside the cell are extracted as coupling cap to the instance pin node. The coupling capacitance from metal2 (outside
cell) to shapes inside the cell is extracted and netlisted.
Note: To treat the contents of the blocked cells as gray data during top-cell routing, set the parasitic_blocking_device_cells_type option to gray.
<filename> specifies a list of cells, one cell per line, to block RC extraction. These cells should have RC accounted for
in the device model instead. The cell names can be triplets "cell view libname" or just the cell name. Cell names can
also be specified with wildcards such as leading or trailing `*'. For a complete explanation of using wildcards to define
cell names, please refer to the Using Wildcards with Quantus chapter.
Note: The cell names specified in the filename cannot have leading `$', but can have `$' embedded in the cell name.
The blocking cell's capacitive effect is similar to specifying the hierarchical_cell_list_file with the
"+ netlist=lvsNetlist" and "+ capacitanceView=grayBox" control statements. By default, the coupling capacitances
between the top-level nets and the nets within the blocked cells are retained during capacitance extraction. In other
words, the nets of the child cells are visible as white data to the cell parent. Resistance inside the cell is not extracted.
However, the cell is flattened in the output netlist unlike the hierarchical output created by hierarchical
extraction (see "hierarchical_extract" ).
When the extraction_setup -parasitic_blocking_device_cells_file option is specified, Quantus prints the
*|I cards of devices inside the blocking cells if either of the EM CCL commands is enabled (output_db –
em_extract true or extraction_setup –analysis em). Multiple devices within the blocking cells may share the
same *|I card if they connect to the same I/O of the blocking cell. Without the EM options, the *|I cards are
omitted for certain cases where there is no resistance connected to the pin of the device.
You should not block specified cells with shapes using the Techgen -blocking and -res_blocking commands. If this
occurs, then blocking is done both within the cell and on layers specified in the -blocking commands.
See Quantus Techgen Reference Manual.
In the QCI flow, if the parasitic blocking device cells (specified using the parasitic_blocking_device_cells_file CCL
option) move up the hierarchy due to the incorrect use of the LVS PUSH DEVICES option, Quantus issues the following
warning message (in the log file):
Devices have moved up from cell <cell_name>. Quantus extracted netlist may have issue. Please review LVS
deck for hierarchy correction function.
Since the specified cells are blocked for extraction, none of the extraction commands in the RSF will apply to the
specified cells. For instance, device_reduction will not apply to the specified cells.
The supported output formats for this command are Spice, transistor-level DSPF and SPEF netlists, and DFII
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(Extracted View). See output_db .
Cell-level DSPF/SPEF are not supported outputs.
Selected Path extraction is not supported with this command. See "extract" .
Because this command creates a hierarchical extract cells file containing the top-level design cell (top.hcl) it is
subject to the same limitations as hierarchical extraction.
Preserving Cells in LVS: You must preserve cells using the ?preserveCells command in LVS or the cells will be
flattened and will not be recognized as cells by Quantus during extraction. A warning is issued if a cell that is
specified in the cell file is not preserved hierarchically in the design. See the Assura Command Reference for
more information on ?preserveCells.
You can also specify cells for hierarchical extraction and different cells for parasitic blocking. However, you should
not specify a cell for hierarchical extraction (in the hierarchical_cell_list_file) and then block the cell from
extraction (in the parasitic_blocking_device_cells_file). If you do list the same cell in both files the cell will be
blocked from extraction and will be ignored during hierarchical extraction. Quantus will issue a warning when this
condition occurs.
Note: In the case where both hierarchical extraction and cell blocking is used, all the cells specified in
the parasitic_blocking_device_cells_file and the hierarchical_cell_list_file should be preserved with
the ?preserveCells command.
Unblocking the Coupling Capacitance From the Cell to Substrate: New in EXT 10.1.1 HF1, you can specify
the +unblockSubstrateCap keyword in the blocking cells file to unblock the coupling capacitances from the cell
content to the cell's substrate layer, if the blocking cell contains a substrate shape. If you specify
the +unblockSubstrateCap keyword for a specific cell in an hcell/blocking cells file, then a later occurrence of the
same cell in the blocking cells file will not override the unblockSubstrateCap keyword for that cell.
For example:
Example 1
nmos_rf*
+ unblockSubstrateCap
nmos_rf25*
nmos_rf33*
The above example will unblock the substrate capacitance of the substrate layers of cells with the name nmos_rf.
Substrate capacitance of layers nmos_rf25* and nmos_rf33* will also not be blocked. This is
because nmos_rf25* and nmos_rf33* are subsets of nmos_rf*, and a later condition in the blocking cells file will
not override the former.
Example 2
nmos_rf*
nmos_rf25*
+ unblockSubstrateCap
nmos_rf33*
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In the above example, the substrate capacitance is unblocked only for nmos_rf25* cells. The nmos_rf33* cells will
not have this option. In general, nmos_rf* cells do not have this option. Only the subset of nmos_rf*, (nmosrf25* in
the example), have this option.
Note: If the -parasitic_blocking_device_cells_type option is set to gray, the +unblockSubstrateCap keyword
does not have any effect and the substrate capacitance is not unblocked for the cell. If a blocking cell does not
contain any substrate shape, then also this keyword does not have any effect.
Specifying Blocking Cell File with Fixed Name in Quantus Technology Directory
In this flow, the blocking cell feature can be activated without specifying the extraction_setup parasitic_blocking_device_cells_file <file1> CCL. Quantus reads the blocking cell file with the fixed
name, blocking_cells_file that is present either in the Quantus technology corner directories or in the technology setup
directory. If the CCL is specified, and blocking_cells_file is also found, the final blocking cell list is the union of the two
files.
The blocking_cells_file supports wild cards indicated by (*).
For multiple process corner extraction, if a blocking_cells_file is used, it can be placed in the technology setup
directory, otherwise identical copies of blocking_cells_file need to be placed in each process corner’s technology
directory.
If you do not want to use this feature, remove the blocking_cells_file from the Quantus technology directory, and the
setup directory. Removing the CCL, -parasitic_blocking_device_cells_file does not turn off the feature.
parasitic_blocking_device_cells_type [ gray | white ]
Use this command in the Quantus command file to specify whether the coupling capacitances between the top-level
nets and the nets within the blocked cells should be considered during capacitance extraction. The default value of this
option is white, which means that the coupling capacitances between the top-level nets and the nets within the blocked
cells will be considered during capacitance extraction.
Previously, the cell blocking feature treated the contents of the blocked cells as gray material during top cell
routing. As a result, the net parasitics (resistances and capacitances) of such cells were not extracted. In
previous releases, this behavior was enabled by default when you specified the
-parasitic_blocking_device_cells_file option.
If you want to ground the blocked cells so that their net parasitics (resistances and capacitances) are not extracted, set
this option to gray. This will enable the old default behavior.
Note: Although the coupling capacitances within a blocked cell will not be extracted, the coupling capacitances of
internal nets between nearby blocked cells will be extracted.
Important Considerations
Before enabling the advanced cell blocking feature using this option, be sure to consider the following points:
The -parasitic_blocking_device_cells_type option should always be used with the parasitic_blocking_device_cells_file option if you want to set its value to gray.
This option works with both coupled and decoupled modes. If you use this option in the decoupled mode, Quantus
yields less pessimistic results.
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This enhancement is applicable in the Quantus transistor-level flow only and not the cell-level flows, such as
LEF/DEF and OA.
parasitic_res_width_change_percentage < value >
By default, Quantus will fracture a wire along its length according to the extraction_setup max_fracture_length command. However, for Assura Pegasus and Calibre input, Quantus does not fracture wires due
to width changes but instead produces a single minimum-width parasitic resistor for a variable-width wire. The width of
the resistor can be reported to the output in either silicon dimensions (see output_db -parasitic_res_width), or drawn
dimensions (see output_db - parasitic_res_width_drawn).
Note: For DEF or OA input Quantus will fracture the wire at any width change.
The parasitic_res_width_change_percentage option causes Quantus to perform width-based fracturing of a wire when
the width of a wire changes by the specified percentage value , where value is specified as a positive number usually
less than 10. This command is very similar to the output_db -parasitic_res_length command, except that it does not
result in either the width or length of the resistor being reported to the output. This command only enables wire fracturing
based on changes in wire width.
This command can be used with output_db -parasitic_res_length to redefine the default 10% width change that
causes fracturing, while reporting both length and width of parasitic resistors. This command can also be used
with output_db -parasitic_res_width or output_db -parasitic_res_width_drawn to cause width-based fracturing of a
wire, while reporting only parasitic resistor width.
promote_bump_ports true | false
The promote_bump_ports option when set to true, enables Quantus to promote resistance and capacitance values of
bump/pad cells in the design. This option promotes the shapes of connected pins by flattening the pin shapes in the
DSPF/SPEF outputs.
The shapes that are promoted include rectangles, polygons, and vias.
Note: Quantus identifies the bump pad cell as a LEF macro whose definition contains CLASS COVER BUMP.
Note: The promote_bump_ports option promotes only the shapes of connected pins and ignores all gray data (OBS or
GDS). If a GDS for a bump cell macro is provided, it is ignored with a warning.
promote_feedthru_ports [ none | r_only | c_only | rc | true | false ]
By default, or when this command is set to none or false, Quantus does not consider the effect of feedthru geometries
during capacitance or resistance extraction. When you set promote_feedthru_ports to true, during extraction Quantus
adds the resistance and capacitance of the promoted feedthru pins on the net to which they are attached.
For multilayer pin ports to be considered as feedthrus, they must be connected by the same layer segments and
by vias. Without a connecting piece, such as a via or a layer segment, the pin ports are not considered as
feedthrus. In addition, a net should have more than one connection with the pin ports.
Quantus detects feedthru ports using the following approach:
If a port abuts another port, then they are both considered feedthrus,
If a port is intersected by wires in multiple regions it is also a feedthru. If it is only intersected by wires in one
region, it is not a feedthru.
This command has been enhanced to allow you to specify the consideration of promoted feedthrus during either
resistance or capacitance extraction as well as for both RC extraction or not at all:
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rc | true - include the parasitic resistance and capacitance of the promoted feedthrus to the nets they are connected
to.
r_only - include only the parasitic resistance into the total for the attached net. This allows you to exclude the
capacitance effect of the promoted feedthru in cases where it has been accounted during library characterization.
c_only - include the parasitic capacitance in the total for the attached net.
none | false - do not consider the effect of the promoted feedthru on the attached net during either resistance or
capacitance extraction. This is the default.
Promoted feedthru ports can be reported in an output file by specifying the output_db -type
promoted_feedthru command (see output_db ).
If the promote_instance_ports command is set to RC, R_ONLY, or C_ONLY, the promote_feedthrough_ports will be
ignored and the value specified for promote_instance_ports will be applied to feedthroughs as well.
promote_feedthru_ports_nonoutputpins [true | false]
Specifies to extract pin resistances only for the input pins, and to not extract pin resistances for the output pins. The
LEF PINS section is used to determine the input pins, as shown below:
PIN pinName
[DIRECTION {INPUT | OUTPUT [TRISTATE] | INOUT | FEEDTHRU} ;]
…
END pinName]
Here, ‘ INPUT’, ‘INOUT’ and ‘FEEDTHRU’ are considered as the non-output (input) pins.
The -promote_feedthru_ports_nonoutputpins CCL option will only work if the -promote_feedthru_ports option is also
set to a value other than none. The following example illustrates the use model of this option:
extraction_setup -promote_feedthru_ports r_only \
extraction_setup -promote_feedthru_ports_nonoutputpins true \
The -promote_feedthru_ports_nonoutputpins option is supported for all output formats, including the output_db -type
promoted_feedthru format. The option is not supported in the OA input flow.
promote_instance_ports [ none | r_only | c_only | rc ]
By default, or when this command is set to none, Quantus does not consider the pin resistance or capacitance of cell
instance port geometries during extraction. When you set promote_instance_ports to anything other than none, Quantus
adds the resistance and/or capacitance of the promoted instance ports to the net to which they are attached.
Note: When using the promote_instance_ports command you should be sure you are not double counting any pin
capacitance that may already be modeled as part of the cell in the cell library.
rc - include the parasitic resistance and capacitance of the promoted instance ports to the nets they are connected to.
r_only - include only the parasitic resistance into the total for the attached net.
c_only - include the parasitic capacitance in the total for the attached net.
none - do not consider the effect of the promoted instance ports on the attached net during either resistance or
capacitance extraction. This is the default.
promote_pin_pad [ none | logical | physical ]
​ The promote_pin_pad option determines how Quantus will handle parasitic extraction of external pins (from the PINS
section of the DEF input) that do not have associated location and geometry information.
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Note: External pins that do have geometry data should not be affected by the promote_pin_pad option.
​ ​ logical
New in 11.1, connects the external pin to the physical routing in the output netlist with a small 1.0e-06
ohm resistor. In earlier releases, Quantus used 0 ohm resistors to connect the external pin to the
physical routing. In other words, the pin is viewed as logical and without physical effect.
Note: When the promote_pin_pad option is set to logical, or when Quantus extracts R-only (extract type r_only), then the net total cap values in the cell-level DSPF/SPEF output may contain zero cap
entries.
physical
Promotes the port geometry of the associated instance pin and extracts the parasitic data for that
geometry. In other words, the physical shape of an associated instance pin is promoted for use by the
external pin.
none
Ignores those logical top-level pins and extracts no parasitic data for them and does not output them to
the netlist. The default is none.
The promote_pin_pad command does not apply to either feedthru pins or regular instance pins. Use
the extraction_setup -promote_feedthru_ports command to manage feedthru pins.
rccompare [ true | false ]
This option is used to compare the output SPEF/DSPF files that are generated when you run a mixed Quantus and
Quantus FS flow. This option is only applicable to the cell-level flow. By default, this option is set to false. When set to
true, the software automatically runs the comparison and creates the following output files by default:
*.tcap – total capacitance comparison
*.ccap – coupling capacitance comparison
*.p2p – pin-to-pin resistance comparison
*.csv – the differences between the two specified files (golden and target) are provided in csv file format. This
makes it easier for the files to be exported to excel for comparison.
*_abs.png,*_rel.png - Absolute plot and relative plot
For details of this feature, see Comparing Resistance and Capacitance in the Quantus Command-Line chapter.
remove_fill_fill_overlap [ true | false ]
This option enables overlap area cleanup between passive, floating metal fill shapes, before the shapes are passed to
the extraction engine. The fill shapes can be present in the GDS/OASIS files or in the DEF files. The signoff extraction
engine expects non-overlapping, clean fill shapes, so the default value for the option is false. However, if the design
has overlapping, passive, floating metal fill shapes, there may be a slight change in the accuracy. When this option is
set to true, the extraction accuracy is improved with a slight degradation of runtime.
remove_net_pin_overlap [ true | false ]
The remove_net_pin_overlap option ignores the net overlap pin geometry during RC extraction to eliminate the double
counting at the pin region. The -remove_net_pin_overlap option cannot be used together with the promote_instance_ports option. If these two options are used together, then -remove_net_pin_overlap will be disabled.
report_invalid_colored_shape [error | warn | none]
Reports invalid color shapes in the LEF/DEF flow. The default value of this option is error, although for some older
technology nodes, it can display a warning.
res_gate_default_factor <value> ​
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By default, Quantus will consider all gates as single connected gates with a default gate factor of two when calculating
the gate resistance. However, delta_gate_ckt and res_gate_factor (or res_gate_default_factor) consider the effects
of a single or double connection to the gate when calculating the gate resistance. This CCL option is equivalent to the res_gate_default_factor Techgen compilation option.
Single Connected Gates
For a single connected gate, Quantus calculates gate resistance (R g) as: R g = (R sheet * (W/L))/res_gate_factor
Where:
R sheet is the sheet resistance of the gate material
W is the width of the gate
L is the length of the gate
res_gate_factor is the gate resistance factor used by Quantus.
The default res_gate_factor is two based on the understanding that the parasitic resistance of the gate should be
measured to the middle of the gate, or half the gate.
You can specify a new gate resistance factor with res_gate_default_factor < value >: value is the factor that
Quantus applies when calculating gate resistances. The value should be greater than or equal to 0.1. Quantus uses two
as the default setting.
However, if you specify the res_gate_factor command for specific devices, the default of res_gate_default_factor is
implicitly changed to three to be consistent with the BSIM4 model regarding gate resistance calculations. You may
override this internal default by expressly setting the res_gate_default_factor < value >.
Handling Double Connected Gates
When you expressly define a res_gate_default_factor or res_gate_factor, Quantus will handle double connected
gates differently from single connected gates.
To change the res_gate_default_factor while still treating all devices as single connected gates, use
the double_gate_conn CCL command option. The following diagram illustrates the double connected gates:
A different calculation needs to be applied for transistors with double connected gates because the double connected
gate has two sources of current flow. There will be two parasitic resistors in parallel on the double connected gate. The
gate width is also cut in half to account for the current flow through the two terminals. In the above figure, assume 80
ohms of total resistance due to the gate material. In the single connected gate (Device A) this would equate to an actual
gate resistance of 40 ohms. However, on the double connected gate (Device B), the gate width is cut in half (0.5W) to
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account for the two terminals and this is then applied to the gate resistance calculation:
Rg = (Rsheet * (0.5W/L))/2
When the -res_gate_factor CCL command option is not set, this results in two parallel 40 ohm resistors so the
effective R is 20 ohms for the gate resistance. The gate resistance for a double connected gate is one quarter (1/4)
the sheet resistance of the gate material.
When -res_gate_default_factor 2.0 is set, this results in two parallel 20 ohm resistors, so the effective R is 10
ohms for the gate resistance. The gate resistance for a double connected gate is one eighth (1/8) the sheet
resistance of the gate material.
If any of the following six gate resistance CCL command options are specified, then the equivalent six Techgen –
compilation gate resistance options are ignored:
extraction_setup -res_gate_default_factor
extraction_setup -res_gate_factor
extraction_setup -double_gate_conn
extraction_setup -delta_gate_ckt
extraction_setup -delta_gate_ckt_by_device
extraction_setup -delta_gate_ckt_by_gate
The extraction_setup -delta_gate_cktfalse CCL command option is the default (this is same as the delta_gate_ckt CCL option not being specified). Therefore, the -delta_gate_ckt false CCL does not disable
all the Techgen gate resistance options, including the Techgen -delta_gate_ckt option. To turn off the delta_gate_ckt Techgen option, you can specify the res_gate_factor CCL command option to override, or
specify the -double_gate_conn false CCL command option.
In addition, the delta_gate_ckt, delta_gate_ckt_by_device, and delta_gate_ckt_by_gate commands are
mutually exclusive with the res_gate_factor, res_gate_default_factor, and double_gate_conn commands.
res_gate_factor “<value1> <devLayer1>” “<value2> <devLayer2>” …
By default Quantus will consider all gates as single connected gates with a default gate factor of two when calculating
the gate resistance. However, the res_gate_default_factor and res_gate_factor commands considers the effects of a
single or double connection to the gate when calculating the gate resistance. The res_gate_factor command changes
the factor applied by Quantus when calculating the gate resistance for specified devices with either single or double
connected gates. This CCL option is equivalent to the -res_gate_factor Techgen compilation option. Refer
to res_gate_default_factor for specific details of how Quantus calculates the gate resistance.
value1 is the factor that Quantus applies when calculating the gate resistances of specified devices. The value should
be greater than or equal to 0.1.
Note: When you specify the res_gate_factor command for specific devices, then the res_gate_default_factor is
implicitly set to 3.0 unless you have to expressly define it.
devLayer1 specifies the device recognition layers for the specific transistor devices. Layer names must come from the
LVS extract.rul file.
value2... are the optional additional statements to specify multiple gate resistance factors for additional groups of
transistors.
resistance_mesh " lvsLayer1 meshSize1 " [ " lvsLayer2 meshSize2 " ... ]​
This feature requires the Virtuoso_QTS_Extraction_XL license and the Advanced Analysis (AA) GXL option for
Quantus.
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This command improves resistance extraction under specific situations. For irregular wide metal regions, traditional
resistance extraction technique such as square counting no longer provide accurate estimates for resistance values
between vias since current flow is not straight. The width and length of a parasitic resistor are difficult to clearly define in
this case. With the extraction_setup -resistance_mesh command, Quantus overlays a mesh resistance network on
top of a metal region, and eliminates the mesh points (or nodes) which fall outside the metal. The figure below shows an
example on how the mesh is created.
Resistance Mesh Network Defined by Quantus
The above figure illustrates a large slanted metal region with two contacts (A and B) contained within the region. A
resistance mesh square with a number assigned means the centerpoint of the mesh falls inside the metal region. The
mesh centerpoint will be used to connect the resistor networks. Parasitic resistors for each resistance mesh connecting
to an adjacent mesh centerpoint will be created first. For example, R(1,2), R(1,7), ... R(18,19) will be generated. Contact
resistances such as R(A,7) and R(A,1) will then be created. If a resistance mesh contains all or part of a contact, the
centerpoint of the mesh is assumed to be connected to the contact. If there is no contact resistance specified for the
layer in the techfile, the contact resistances will be zero, or shorted.
Note: Vias will be grouped into arrays prior to the resistance_mesh command being executed, and will affect the way
the resistance mesh is applied. See extraction_setup -array_vias_spacing for information on via arrays.
The resistance_mesh option also requires output_db -add_explicit_vias to be enabled (see output_db ) for proper
netlisting of the calculated contact resistance. In case of long continuous via arrays, via merging (if via size is not
controlled properly) before MeshR may result in incorrect resistance value. Therefore, it is recommended to set
the extraction_setup -max_via_array_count <n> CCL command to limit the via array size (and ensure that it is less
than the mesh size) to produce correct resistance value, as shown in thefigure below.
meshR Behavior with Via Merging
Note: For R calculations on shapes where resistance mesh is applied, metal biasing for those shapes is not applied.
The R accuracy impact is expected to be minimal since resistance mesh is typically applied to wide wire structures.
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The final resistance network will consist of a mesh of parasitic resistors connected between the contacts. To
accompany the mesh resistance network, parasitic capacitance distribution will also occur on the mesh. Inductances
will not be extracted on the layers or in the regions defined by the resistance_mesh command. Do not use this feature
for RLC or RLCK type of extraction.
No inductances will be extracted on the layers and in the regions defined with the resistance_mesh command. In
addition, no warning will be provided by Quantus.
Since resistance extraction is based on LVS layers, you can specify the lvsLayers to which
the resistance_mesh command is applied, and the size of the mesh. For example:
extraction_setup -resistance_mesh "metal1 -" "metal2 0.5" "metal3 -"
lvsLayer specifies an LVS layer name as defined in the extract.rul file or the ext_layer name from
the layer_setup file. The lvsLayer must be defined as a resistive layer in the techfile. An lvsLayer may only be
specified once in the resistance_mesh command.
If a layer specified in the CCL command file for resistance meshing is not found in the qrcTechFile, Quantus
gives a warning message for such layers, and enables the resistance mesh flow for the layers specified in the
CCL command file that exist in the qrcTechFile as well as in the design. Similarly, if a layer exists in the
qrcTechFile, and is also specified in the CCL command file, but does not exist in the design, Quantus gives a
warning message.
meshSize defines the granularity of the mesh as specified in microns. You can specify a `-' to use the default mesh size
calculated for the layer by Quantus, or specify a value yourself to override the default. The default mesh size is the
minimum wire width (min_width) of the metal layer as defined in the techfile. The min_width is defined in the "drawn"
dimension prior to any scaling. You can optionally override the default value by specifying a meshSize option for a
specific lvsLayer. If you specify a meshSize , the value should be a number that is smaller than the "SMALLEST
SHAPE" which is used as an input to mesh resistance calculation. Shapes smaller than the specified value will
continue to use the regular field solver for resistance computation.
Using a very small meshSize should be avoided since it will increase the number of parasitic resistors extracted
unnecessarily, and increased extraction and simulation times. The resistor network size is inversely proportional to the
square of the meshSize, so doubling the mesh size will reduce the resistor network by four times.
Note: For resistance mesh extraction, there is a trade-off between resistance accuracy and the output file size
depending on the mesh size. The smaller the mesh size, the greater is the accuracy but bigger the file size. The R
Mesh Accuracy drop-down on the Extraction tab of the Quantus Parasitic Extraction Run Form can be used to select
between V. Conservative and Liberal accuracy settings.
If the minimum width of any region 6 on a specified lvsLayer is less than twice (2X) the specified meshSize for
that layer, the resistance mesh extraction will not be performed on that region. Traditional net fracturing and
resistance extraction will be used for that region instead. Starting with the 11.1 release, if a wider region (defined
as greater than 2X meshSize for that layer) is connected to such regions, then Quantus automatically splits the
selected mesh region into wide and narrow regions. The wide region receives the meshR treatment whereas the
narrow region uses the standard resistance calcuation method.
resistance_mesh is for use with Assura, Pegasus, or Calibre inputs only, and is available for the Spice format outputs
(including transistor-level DSPF and SPEF) and the extracted_view output. The resistance_mesh command does not
support cell-level DSPF or SPEF outputs. In addition, resistance_mesh will work for both flat and hierarchical
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extraction.
The resistance_mesh command should only be specified once with all the required lvsLayers. However, if
multiple resistance_mesh commands occur in the command file, then the commands will be combined into a
single resistance_mesh command during the extraction run.
Width-Dependent Sheet Resistivity and WEE Bias in Resistance Mesh
Quantus can handle different width based sheet resistivity values for mesh resistance extraction. The ICT file syntax for
sheet resistance as a function of width is given below:
resistivity R1 W1 R2 W2 … Rn Wn
The following diagram illustrates that the orange color region uses W1 as the width and the green color region
uses W2 as the width for mesh resistance:
Therefore, these two different mesh regions will get different sheet resistivity values as per the resistivity table in the ICT
file.
The WEE bias is included for resistance calculation for the resistors at the border of the mesh regions. Mesh Resistance
extraction will take WEE into account when computing boundary mesh resistance value.
The following diagram illustrates this behavior:
Here, the orange portion of the polygon contains 4x9 grids. All 36 mesh grids use the same width to look up the
resistivity (Wsi) values. This width does not include the WEE bias. For the parasitic resistor located at the border of the
orange region (left side of the diagram), the width includes the WEE bias (shown as the yellow strip). The higher order
WEE is not supported. If higher order WEE is specified in the ICT file, the bias value will be 0.
resistance_mesh_adaptive default | false
Allows the use of parasitic resistor mesh for higher accuracy. When this option is set to default (square adaptive
meshing), the software enhances the Quantus output by reducing the output size without causing accuracy
degradations. By default, this option is set to false.
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This option should be used with existing mesh R commands, extraction_setup resistance_mesh_region and extraction_setup -resistance_mesh. The adaptive mesh feature requires the
< meshSize > to be explicitly specified. The < meshSize > is the smallest mesh size for the LVS layer. This feature does
not include adaptive via merging, that is, extraction_setup -max_via_array_count option.
resistance_mesh_advanced_via_merging [true|false ]
Specifies whether via merging should consider the top and bottom layer shapes.
If the option is set to false, via merging does not consider the top and bottom layer shapes, that is, vias are
merged from left to right.
If the option is set to true, via merging considers the top and bottom layer shapes, that is, merging is based on the
different wire width regions.
The following diagram illustrates via merging considering the top and bottom layers shapes (true, shown in red), and
via merging from left to right (false, shown in yellow):
The rotational accuracy improves with this via merging CCL option. When the resistance_mesh_advanced_via_merging option is used, the path R value will have less variations in comparison to
the max_via_array_size or max_via_array_count option.
The following features can be used for both the user-specified and automatic mesh sizing:
Resistance Mesh More Square Counting (-resistance_mesh_more_square_counting)
Interface Depth to Square Counting Region (-resistance_mesh_square_counting_buffer)
Corner Square Counting (-resistance_mesh_corner_square_counting)
Resistance Mesh Advanced Via Merging (-resistance_mesh_advanced_via_merging)
resistance_mesh_automatic_size <layer1> <layer2> …
This option enables the Advanced Adaptive Mesh feature. It specifies to automatically determine the mesh size for the
specified layers. Once the mesh size is determined, the merge via size for each via is also determined. The option takes
a list of LVS layers for mesh resistance extraction. This option must be used with adaptive mesh (resistance_mesh_adaptive) and automatic via size (-resistance_mesh_automatic_via_layer).
Quantus checks out the XL and AA GXL licenses when automatic mesh sizing is invoked with the resistance_mesh_automatic_size CCL option.
The following is an example of this option:
extraction_setup –resistance_mesh_automatic_size \
“met1” \
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“met2” \
“met3” \
“mettop”
-resistance_mesh_adaptive “true” \
-resistance_mesh_automatic_via_layer “true”
The Advanced Adaptive Mesh feature (-resistance_mesh_automatic_size) is mutually exclusive with the
Adaptive Mesh feature (-resistance_mesh). The Adaptive Mesh feature is based on the user-specified mesh
size for the conductor layers that are to be meshed. Alternatively, Advanced Adaptive Mesh feature is based on
automatic mesh sizing for the conductor layers.
The -resistance_mesh_size_k_factor and -max_resistance_mesh_size_error options can only be used with
the –resistance_mesh_automatic_size option. The following options can be used for both the user-specified and
automatic mesh sizing:
Resistance Mesh More Square Counting (-resistance_mesh_more_square_counting)
Interface Depth to Square Counting Region (-resistance_mesh_square_counting_buffer)
Corner Square Counting (-resistance_mesh_corner_square_counting)
Resistance Mesh Advanced Via Merging (-resistance_mesh_advanced_via_merging)
resistance_mesh_automatic_via_layers [true | false]
The resistance_mesh_automatic_via_layers option allows you to automate via layer meshing. The resistance_mesh option must be specified to use this option as the automation is based on the specified conductor
meshing layers. When -resistance_mesh_automatic_via_layers is set to true, the via layers connecting to one or two
meshed conductor layers will be automatically meshed or merged depending on the via size. The small vias are
merged and large via shapes are cut into small vias. The proper via size is determined by the smaller of the top and
bottom meshR sizes. If only one of the top or bottom layer is meshed, then that mesh size will be used.
The array_vias_spacing option is ignored for via meshing and merging, when resistance_mesh_automatic_via_layers is set to true.
The manual via meshing requires you to specify both the conductor layers to be meshed and the connecting via layers
to be meshed, whereas the automatic meshing requires you to specify only the conductor meshing layers. The existing
manual via meshing CCLs can be used with the automatic via meshing CCL, however, the manual via meshing CCL
takes precedence. The following are the CCLs for manual via meshing:
extraction_setup –resistance_mesh_via_layers <LVS_layer> …
extraction_setup –max_via_array_size_by_layer “<LVS_layer> <size>” …
resistance_mesh_corner_square_counting [true|false ]
Specifies to include the bends (corners) or junctions in the long wide wire regions into square counting. If this option is
set to false, the corners remain meshed.
The following diagram illustrates that once the two corners are turned into square counting, the four buffer zones are
also turned into square counting:
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This diagram shows that the entire U shaped wire has turned into square counting.
resistance_mesh_file <full_path_name_meshR.defs>
Specifies the location of the meshR.defs file. This option is the file-based version of the -resistance_mesh CCL option.
The file-based version of the option is mutually exclusive with the non-file-based version.
The Quantus UI translates the contents of the meshR.defs file into a set of CCLs and includes them in the output. Use
the resistance_mesh_file option to enable this Quantus UI functionality in the batch mode. The specified file need not
be located in the technology directory, nor does it have to be named as meshR.defs.
This feature is supported in the transistor-level flow for the Assura, Pegasus, and Calibre LVS front ends, and all output
formats, except lvs_extracted_view.
resistance_mesh_more_square_counting [true|false ]
Enables additional square counting, which includes long and wide wires and non-Manhattan (slant lines) wires. The
following diagram illustrates more square counting in adaptive mesh using the resistance_mesh_more_square_counting option:
resistance_mesh_region <regfile>
This option enables you to specify regions for mesh resistance extraction. The <regfile> is a text file that contains the
co-ordinates to specify a rectangular region defined by the lower-left corner and upper-right corner
(xlow ylow xhigh yhigh), the process layer name in the ICT file, and the mesh size in the following format:
(xlow,ylow) (xhigh,yhigh) layername mesh_size
The co-ordinates are specified with respect to the top cell. You can define more than one user region in
the <regfile> file. Each region may have a different mesh size. In addition, the specified regions are allowed to
overlap. If the overlapping regions on the same metal layer have different mesh sizes, the smallest mesh size is used for
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mesh resistance calculation.
If non-overlapping regions on the same metal layer have different mesh sizes, then each region is meshed with its
respective mesh size.
The regions specified in user region file use the mesh resistance calculation, while the rest of the regions (not defined in
the user region file) use the standard resistance calculation. If one region is split into two types, equi-potential butting
vias are created between the regions to connect the resistor networks.
resistance_mesh_size_k_factor <value>
Specifies that the automatic mesh size is based on a k factor value, as shown below:
final_mesh_size = <automatic_mesh_size>/<k_factor_value>
This value allows you to modify the mesh size calculated using the –resistance_mesh_automatic_size option.
For example, if lower accuracy is tolerable, a <k_factor_value> of 0.5 will multiply the automatically generated mesh
size by 2x. Conversely, if higher accuracy is of essence, the <k_factor_value> of 2.0 would halve the automatically
generated mesh size.
resistance_mesh_square_counting_buffer width_ratio
Specifies the interface depth of the mesh region to the square counting region, that is, how far a mesh region extends
into a non-meshed region. The width_ratio should be between 0 and 1. The default width ratio is 1.
The following diagram illustrates the square counting interface depth (red dotted lines), wherein the left image has a
width ratio of 1.0, and the right image has a width ratio of 0.5:
resistance_mesh_via_layers <lvsLayer1> <lvsLayer2> …
This option enables you to specify Via layers for mesh resistance extraction. <lvsLayer1> <lvsLayer2> … are the LVS
via layers for mesh resistance extraction. The -resistance_mesh option must be specified to use the –
resistance_mesh_via_layers option. The fractured via size is controlled directly by the smaller of the top and bottom
meshR size.
The –resistance_mesh_via_layers option cannot be used with the –resistance_mesh_region option. The following
example explains the reason for not using the two options together:
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As shown above, a via between two mesh R layers may be partially inside the meshR region. In such cases, the entire
via shape will be fractured. Once the mesh R via fracture feature is requested, the via is not subject to the traditional
via merging treatment.
The Techgen –compilation command can also specify meshR layers and meshR regions in an LVS marker layer. The
command has the following syntax:
-resistance_mesh region_lvs_layer:mesh_size[:grow_amt],lvs_layer1,lvs_layer2,…
There are CCLs that specify meshR LVS layers and meshR regions for those layers. For mesh vias, they will only be
specified by the CCL. A mesh via layer requires either one or both, top and bottom layers, be in meshR. This means the
meshR layers can come from either CCL, or Techgen –compilation –resistance_mesh option. However, for mesh via,
the Techgen originated meshR layers are not supported. This is illustrated in the figure below:
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When a large via exists on a layout and overlaps with the metal layers that are meshed, then the via should also
be meshed. Otherwise, the large via runs the risk of shorting out all or parts of the meshR network which it
covers.
Stacked Via
In a stack via configurations, shapes two different via layers are on top of each other.
In a stack via configurations, shapes two different via layers are on top of each other. Each via would be meshed
independently as long as one or both of their top and bottom layers are meshed. This is illustrated in the figure
below. Specifically, the mesh via is not related to stack via.
short_res_devices “<DRL1>” “<DRL2>” …
Specifies to short and discard the Chip-on-Wafer-on-Substrate (CoWoS) dummy R elements. <DRL> refers to the
device recognition layer name in the lvsfile.
The double quotes around <DRL> is optional in the CCL syntax. The resistor device must be a generic device, must
have 2 terminals, and both terminals must connect to different LVS layers. The <DRL> layer names should not have
encodings like “_0”, “_1”. It should be the original layer name in the Calibre/Pegasus LVS deck. This option requires
the 3DIC licenses, that is, an XL license and an Advanced Analysis (AA) GXL option. For more information, refer to the
"Advanced 3D IC Packaging Technologies" section in the 3DIC Extraction chapter.
stacked_via_effect [ true | false]
If a wire segment is very short between the inner layers of adjacent stacked vias, the current flowing in the short
horizontal segment is expected to be mostly vertical, whereas the horizontal currents may be non-real. Thus, by default,
the W parameter is set to 1,000,000 microns to prevent false EM violations.
The stacked_via_effect option allows you to modify this default behavior and print the actual width values. The actual
width values are supported in certain foundry-provided EM rules for advanced nodes, therefore, contact your foundry
provider before changing the default behavior.
The use model of the parameter is:
when set to true (default), reports the W parameter as 1,000,000 microns
when set to false, reports the actual wire width for the short horizontal metal segment.
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stitch_bump_model [true|false]
Starting with PVE 12.1 release, for transistor level 3DIC extraction, you can use following command to stitch microbump pre-defined RC model defined in IPF file under sub_circuit string into the Quantus output file (SPEF, SPICE, or
DSPF).
stitch_tsv_model [rlc|r_only|rc|none ]
For 3DIC extraction, you can use following command to stitch TSV pre-defined RC model defined in the ICT file
under sub_circuit_rc string into the Quantus output file (SPEF, SPICE, or DSPF).
extraction_setup -stitch_tsv_model rc
When this option is set to rc, only one Rsub/Csub pair is inserted connecting the two T-RC groups.
When this option is set to r_only, the TSV model does not include capacitor elements.
When this option is set to rlc, the TSV model includes the RLC elements. This argument can only be used in the Chipon-Wafer-on-Substrate (CoWoS) transistor-level flow, and the output will be a SPICE file.
Note: When this option is set, the output_db -add_explicit_vias option is automatically set to true.
stream_layer_map “<LEF-layer-name> <stream-layer-ID> <DT> <use-type> <color-ID> ”
The option maps the layer names in the design file to the layer names in the GDS/OASIS file. You need to use this
command if you are using a GDS/OASIS file to import layout data for the cell library or metal fill into the design.
Here,
<LEF-layer-name> is the LEF layer name in the design
<stream-layer-ID> is the layer ID in the GDS/OASIS file
<DT> is the datatype of the layer in the GDS/OASIS file
<use-type> is the keyword for identifying the use of the data. The valid values are:
gray: library data in the GDS/OASIS file
fill: regular metal fill data in the GDS/OASIS file
active: active metal fill data in GDS/OASIS file
<color-ID> is the color ID (Use 1, 2, 3, 4, 5, or 6) if the layer is colored, or use hyphen “-” if the layer is not colored.
“” quotes for the entire layer map is optional
This feature is applicable only for the cell-level flow. For more information on the use model for this option, refer to Layer
Mapping GDS and LEF/DEF Layers using -stream_layer_map.
stream_layer_map_file <filename>
The option specifies the filename of the GDS/OASIS layer map file. The file contains the content
of stream_layer_map . -stream_layer_map and –stream_layer_map_file are mutually exclusive. This feature is
applicable only for the cell-level flow.
strict_maskshift_checking [ true | false]
Starting from the 19.13EHFx release, Quantus, by default, checks the mask-shift consistency across technology LEF,
library LEF, and DEF files. If any issues are encountered, Quantus errors out with an error message like below.
ERROR (EXTGRMP-723) : The mask-shift on layer via1 of component ENDCAP_PDSYS_671 is not allowed to be
shifted from the original mask color in the LEF. Check the tech LEF, library LEF and DEF files for
consistency of the syntax.
When this option is set to false, the software ignores the error and lets the Quantus run continue. This behavior is then
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similar to older releases of Quantus.
technology_auto_layer_map [ true | false]
The technology_auto_layer_map option automatically generates a layer map if a user-specified layer map
(extraction_setup -technology_layer_map) is not available. This layer map maps the LEF/DEF layer names in the
design file to the layer names in the Quantus technology file.
This option requires at least one of the layers defined with the gate_forming_layer true argument in the ICT file
(usually a poly layer). Auto layer mapping does not happen if the technology file has a MIMCAP layer.
This option is mutually exclusive with -technology_layer_map.
technology_layer_map <design_layer_name1> <technology_layer_name1>|none <design_layer_name2> <technology
_layer_name2> | none ...
The technology_layer_map option maps the layer names in the design file to the layer names in the Quantus technology
file. You only need to use this command if the layer names specified in the technology file are different from those used
in the input design file.
<design_layer_name> specifies the layer name from the LEF/DEF or OA input.
<technology_layer_name> specifies the layer name from the Quantus technology file (or ICT file). If a layer is referenced
or used in the design (DEF/LEF or OA) but is not defined in the Quantus technology file, you need to map those layer
names to “none”.
Quantus cell-level extraction does not use layers below metal1 for extraction. The layers defined with the keyword
“gate_forming_layer true” in an ICT file are recognized as transistor-level (device forming) layers, and are ignored
during cell-level extraction even if these layers are set by using the technology_layer_map option.
For cell-level Quantus layermap, the LEF/DEF layer names (design_layer_name) are case sensitive, but ICT
layer names (technology_layer_name) are not case sensitive.
Example Technology Layer Map
Layer Type
Design Layer
Techfile Layer
metal
metal_1
M1
metal
metal_2
M2
extraction_setup \
-technology_layer_map \
metal_1 M1 \
metal_2 M2
technology_lef_map <techlef_file_1> <def_file_1> <techlef_file_1> <def_file_2> ... <techlef_file_2> <def_file_1>
The Quantus cell-level flow supports multiple technology LEFs for multi-DEF designs but with a single extraction
technology file (qrcTechFile). The - technology_lef_map option maps the technology LEFs to the DEF files. The
technology LEFs should have non-conflicting layer stacks. That is, if a layer M1 is defined in
both techlef1 and techlef2, they must refer to the same layer in qrcTechFile. You can specify a maximum of
16 technology LEF files.
For the specified multiple technology LEF files, only the following three parameters can vary:
LAYER WIDTH (defaultWidth)
VIA definition
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NONDEFAULTRULE
This flow allows a many-to-many mapping between the DEFs and technology LEFs. That is, Block1.def may be
associated with techlef1, techlef2, techlef3, and Block2.def may be associated with techlef1, techlef4. This option
supports all output formats.
technology_lef_map_file <techlef_mapping_file>
The option specifies the filename of the technology LEF map file. This mapping file contains the same content as
specified with the technology_lef_map CCL option. You can specify the absolute or relative path of the filename.
tsv_subckt_file <file> <file2> …
For 3DIC extraction, you can use this option to specify that the .subckt models for TSV are placed in the technology
directory. This option is used when the Inter-Process-File (IPF) is fully integrated into the ICT file (no .ipf file). This
option takes a single file name as the argument. The format of the file is Spice. In the process corner mode, multiple
files from each technology directory should be specified. The order of the files should match that of the technology
directories.
For example, the Quantus technology directory may contain the tsv.subckt Spice file. The tsv.subckt file may contain
only one model for TSV (for example, R, or RC, or RLC), and its model type is based on the parameter value of the stitch_tsv_model CCL option.
In the following example, the two models are separated into 2 subckt files in the technology directory. They are named
tsv.subckt and tsv_r_only.subckt respectively.
File (tsv.subckt):
.SUBCKT TSV M1 MB
RTSV1 M1 n1 0.01
RTSV2 MB n1 0.01
CTSV n1 0 0.15f <= must be “0”
.ENDS
File (tsv_r_only.subckt):
SUBCKT TSV M1 MB
RTSV1 M1 n1 0.01
RTSV2 MB n1 0.01
.ENDS
ubump_subckt_file <file> <file2> …
For 3DIC extraction, you can use this option to specify that the .subckt models for ubump are placed in the technology
directory. This option is used when the IPF is fully integrated into the ICT file (no .ipf file). This option takes a single file
name as the argument. The format of the file is Spice. In the process corner mode, multiple files from each technology
directory should be specified. The order of the files should match that of the technology directories. For example, the
Quantus technology directory may contain the ubump.subckt Spice file. The ubump.subckt file may contain only one
model for ubump (for example, R, or RC, or RLC), and its model type is based on the parameter value of the stitch_bump_model CCL option.
verify_min_width [ true | false ]
Reports a warning message in the log file for those design geometries that have the silicon width (post WEE) smaller
than the layer minimum width in qrcTechFile. The default value is false.
A sample warning message is as follows:
WARNING (EXTHPY-222): Net ABC with geometry (1220 9998240 1300 9999900) on layer meta1 has width of 0.04
(um) which is less than layer minimum width of 0.045 (um).
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filter_cap
Command Syntax
Input Restrictions
filter_cap
-exclude_floating_decoupling_factor
<value>
LVS
-exclude_floating_nets [ true | false]
LVS
-exclude_floating_nets_limit [<limit>
| auto]
LVS and DEF/OA in advanced
capacitance mode
-exclude_self_cap [ extended | true |
false]
LVS
-extended_self_cap_recursive [ true |
false]
LVS
Description
The filter_cap command provides a general capacitance threshold which eliminates all caps below that threshold, excludes
self capacitance, and eliminates the capacitors associated with floating metal.
While the filter_coupling_cap command reduces the number of coupling capacitors in the design by converting them to
decoupled capacitance and lumping them to the ground_net, the general purpose filter_cap command reduces the number
of all types of capacitors in the design.
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Options
exclude_floating_decoupling_factor < value >
This option is used in conjunction with exclude_floating_nets to specify the amount of capacitance that is decoupled
to ground when the approximation algorithm is employed. With this option, Quantus will multiply the coupled
capacitance between a floating node and a non-floating node by the specified value and convert that to decoupled
capacitance.
The < value > must be in the following range: 0 < value <= 1.0.
Note: There is no default value for exclude_floating_decoupling_factor. If you do not specify a value, then Quantus
applies an automated algorithm when decoupling the coupling caps. Therefore, it is recommended not to set
the exclude_floating_decoupling_factor option for best accuracy.
exclude_floating_nets [ true | false]
exclude_floating_nets is used to remove floating nets and merge capacitors attached to those floating nets. Floating
nets are typically introduced by area fill patterns for which there are no conducting paths to power or ground. The nodes
are fully isolated from the rest of the circuit except by capacitive coupling. This option causes Quantus to remove
floating capacitive nets from the extraction output.
Note: The exclude_floating_nets command is internally specified by Quantus to remove added virtual metal fill from
the design when metal_fill -type virtual is specified (see "metal_fill" ).
Floating capacitive nets are defined as follows:
A net that is not an I/O net
A net with parasitic capacitance
A net that is not connected to any device or parasitic resistor
Merging Capacitors of Removed Floating Nodes - Parasitic capacitors attached to floating nodes are merged
serially as the floating nodes are eliminated from the design. This has the effect of reducing both the number of
parasitic capacitors and the quantity of parasitic capacitance from the output netlist.
Floating Node Removal
In the diagram above, node B is a floating node with coupled capacitance to node A and node C, neither of which is
floating. Node B is removed, and the two coupling capacitors cab and cbc are merged serially to become a single
coupling capacitor between nodes A and C (cac ).
Floating Nodes to Ground
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In the above figure, M1 is a floating node on metal1, with capacitive coupling to Ground (c0) and to M2 (c1), and there is
also coupling between M2 and Ground (c2). With the removal of M1, the capacitors c0 and c1 are merged serially as
previously discussed. However, that now leaves two parallel capacitors between M2 and Ground (c2 and the merged
c0/c1 cap. These two capacitors can be merged in parallel to further reduce the parasitic capacitor count of the design.
Approximation of Large Clusters - To gain efficiency, Quantus identifies disjoint clusters of floating nodes, then applies
a reduction algorithm to each cluster. A cluster is a set of floating nodes that are connected by coupling capacitors. For
example, if node A and node B are floating and there is a parasitic capacitor joining A and B, then A and B are grouped
into the same cluster. If node C is also floating and there is a capacitor between node B and node C, then A, B, and C are
assigned to the same cluster. If there is a connected path of capacitors between two floating nodes then those two nodes
are grouped into the same cluster, regardless of the path length.
Non-floating nodes can also be attached by capacitance to these cluster. In the reduction process for a cluster, there are
three kinds of capacitance that are involved: capacitors between floaters in the cluster, capacitors between the nonfloaters attached to the cluster, and capacitors between a floater in the cluster and a non-floater.
The most important quantity in determining the size of a cluster is the number of attached non-floating nodes. When this
number exceeds the value defined by exclude_floating_nets_limit, an approximation is triggered. The other
consideration in sizing a cluster is the number of floating nodes contained within it. When this number exceeds
5,000,000, then the approximation is also triggered.
Note: A warning is reported when Quantus performs the approximate reduction.
The approximate reduction works as follows:
Drop all parasitic capacitors between two floating nodes.
Multiply the coupled capacitance between a floating node and a non-floating node by the value of
exclude_floating_decoupling_factor and convert that to decoupled capacitance.
Exclude all floating nets.
The approximate reduction is used to avoid very long extraction run times. Therefore, when approximation is employed
by Quantus, clusters which are smaller than the specified limit are handled more accurately than clusters exceeding the
float limit.
exclude_floating_nets_limit [<limit>|auto]
Defines the limit of non-floating nodes that can be connected to a cluster before the approximate reduction algorithm is
employed for exclude_floating_nets.
Starting with Quantus 20.1, the “auto” option has been introduced to automatically optimize accuracy vs. performance in
floating net removal within Quantus.
Note: In case you want to override auto, maximum speed is obtained with limit set to 0, but comparable speed and
greater accuracy can be achieved by using a moderate limit. For AMS/RF type of application, it is recommended to set
the limit to 10,000. The maximum integer value that can be set as a limit is 2,147,483,647.
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Quantus will treat the floating fills as grounded, if the following CCL options are specified:
filter_cap \
-exclude_floating_nets true \
-exclude_floating_nets_limit 1 \
It is also recommended that you set the value of the filter_cap -exclude_floating_decoupling_factor CCL option to
1.
exclude_self_cap [ extended | true | false ]
This CCL is used to exclude parasitic capacitance between distributed RC nodes on the same net. This option only
applies to extract -type rc_coupled. Quantus automatically excludes self-capacitance from the extraction output
during decoupled parasitic capacitance extraction.
Note: You should not specify -exclude_self_cap when extracting inductance (extract -type
rlc_coupled or rlck_coupled).
When the extended parameter is specified, it removes coupling capacitors between the two LVS nets across resistor
devices. The resistor devices are defined by Techgen -compilation commands of -canonical_res_cap_by_device, or canonical_res_cap_by_device_proper.The effect of the self-cap removal is not cumulative. This is illustrated in the
below figure. A resistor is a void in the LVS DB. In Quantus, if -canonical_res_cap_by_device, or canonical_res_cap_by_device_proper is specified, the yellow shapes are filled in for capacitance extraction. Under
normal circumstances, there will not be a coupling capacitance between nets A and B. However, as a result of
filter_cap -excluding_floating_nets true, there may be coupling capacitors generated between A and B. The CCL
-exclude_self_cap extended will remove this self-capacitance as shown in below figure.
Figure: filter_cap -exclude_self_cap extended
Note:
The extended parameter is not supported in the Assura flow, where -canonical_res_cap is used.
The extended parameter is not supported for the DSPF/SPEF output, CCL command, input_db library_cell_list, because there are no devices in this flow.
The extended self-cap removal is supported in Quantus only, QuantusFS only (with -standalone_fs techfile),
and any combinations of Quantus (such as all nets) and QuantusFS (such as selected nets).
extended_self_cap_recursive [ true | false]
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When set to true, all capacitances between the nets connected through resistor devices (or a series of them) will be
treated as self-capacitance. Specifically, the effect of self-capacitance will be propagated recursively on all resistor
devices. When set to false, which is the default value, Quantus will remove coupling capacitors between the two
nets/sub-nodes across each resistor device. This action will not propagate recursively into other resistor devices.
This is illustrated in the below figure, where C1 and C2 are self-caps and they will be removed; while C3 is not a selfcap, so it will not be removed. In the C only mode, the coupling capacitors between the two LVS nets connected by the
resistor devices are considered self-capacitances. The effect is not recursively applied across other resistor devices.
So, C3 will not be removed.
It is also possible that nets B and net C are extracted in C only mode, while net A is Rcc-extracted. In that case, C2
connects a B sub-node (for example, B#20) to C; while C1 connects 2 sub-nodes (A#15 to B#5).
The resistor devices are defined in the SPICE syntax. Additional resistor devices are defined by Techgen -compilation
commands, -canonical_res_cap_by_device, or -canonical_res_cap_by_device_proper.
Figure: filter_cap -exclude_self_cap extended and -extended_self_cap_recursive false
Note:
The -extended_self_cap_recursive CCL can only be used, when -exclude_self_cap option is set to extended. If
-exclude_self_cap is set to either true or false, -extended_self_cap_recursive will be ignored.
The -extended_self_cap_recursive CCL option is not supported in the Assura flow, where -canonical_res_cap
is used.
For 5nm and below nodes, if -exclude_self_cap true is set, it will automatically be set to extended.
Rcc and C-only Behavior Difference in -extended_self_cap_recursive false
When -extended_self_cap_recursive CCL is set to false, which is the default setting, the behavior in Rcc mode vs that
in C-only mode is different.
In general, the sub-nodes are smaller than the net. Therefore, the self-cap effect is stronger for C-only nets than for the
Rcc nets. This self-cap exclusion effect can be viewed in the figure below by using the abstract concept of self-cap
regions shown as boxes with dashes as outlines.
The upper part of the diagram shows C-only mode, in which the R1 device connects to nets A and B, which forms the
larger self-cap region #1. The R2 device connects nets B and net C, which defines self-cap region #2. Both regions
overlap by the net B.
In the RCc mode, the R1 device connects sub-node A#15 and B#5. The self-cap region of the same R device is smaller
than that of the C-only mode. The three capacitances between A#15 and B#20, B#5 and A#5, and B#20 and A#5,
respectively, are in the same self-cap regions – which means they are not self-caps. So, they will not be removed.
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Similarly, the R2 device connects B#20 and C#3, forming the self-cap region #2. This region is smaller than its C-only
counterpart. Also, note that the two self-cap regions formed by the two resistor devices do not overlap in the Rcc mode.
Figure: Exclusion by Sub-Nodes and Nets when -extended_self_cap_recursive is Set to false
Rcc and C-only Behavior in -extended_self_cap_recursive true
If -extended_self_cap_recursive is set to true, the self-cap regions are much larger than those shown above. This is
because of recursion. Therefore, the behavior of RCc and C-only is identical. This is illustrated in below figure. In the Rcc
mode, the three capacitances between A#15 and B#20m, B#5 and A#5, and B#20 and A#5, respectively, are all in the
same large self-cap region. They are self-caps and will be removed.
Figure: Exclusion by Sub-Nodes and Nets when -extended_self_cap_recursive is Set to true
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filter_coupling_cap
Command Syntax
Input
Restrictions
filter_coupling_cap
DEF/OA
-cap_filtering_mode [absolute_and_relative |
absolute_or_relative]
-coupling_cap_threshold_absolute <value>
ALL
-coupling_cap_threshold_relative <value>
ALL
-decoupled_to_substrate {true|false}
LVS
-total_cap_threshold <value>
Default Value: 5 femtofarads
DEF/OA
Description
This command enables you to reduce the total number of parasitic capacitors in the design, by decoupling coupled capacitors
from nets whose total capacitance does not exceed a specific amount, or whose coupling capacitance does not exceed a
specific amount, or merely by decoupling very small coupling capacitors. Filtering out coupling capacitors reduces the size of
the output file.
Starting with the EXT 10.1 release, the filter_coupling_cap option is no longer disabled if the Techgen -c ctfile
compilation option is specified. The ctfile is used to specify different parasitic capacitor models based on capacitor
connection layers. Quantus processes each model group independently and takes into account the total net-to-net
capacitances only from capacitors in the same model group as shown in the Example .
Note: Starting with the EXT10.1.2HF3 release, Quantus behavior has been enhanced for filtering the coupling capacitances,
when metal fills exist in the design. Quantus excludes the coupling capacitances which are smaller than the relative threshold
(specified by the filter_coupling_cap -coupling_cap_threshld_relative CCL command) of the total capacitance of the
net. In the case of metal fills, the total capacitance of a signal net used (for filtering threshold), is the capacitance after floating
capacitances are reduced.
The following table explains the default behavior for the -coupling_cap_threshold_relative and coupling_cap_threshold_absolute options of the filter_coupling_cap command in various scenarios in both the cell-level
and transistor-level flows:
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Options
cap_filtering_mode [ absolute_and_relative | absolute_or_relative ]
The cap_filtering_mode variable uses the capacitance values specified by the
options total_cap_threshold, coupling_cap_threshold_absolute, and coupling_cap_threshold_relative to determine
which nets in the design will have their coupling capacitance lumped to ground.
absolute_and_relative (default) - Decouples the coupling capacitance of nets with coupling capacitance values
less than the threshold value set by either the total_cap_threshold option, or by
the coupling_cap_threshold_absolute and the coupling_cap_threshold_relative variables.
absolute_or_relative - Decouples the coupling capacitance of nets with coupling capacitance values less than the
threshold value set by either the total_cap_threshold option, or by
the coupling_cap_threshold_absolute option, or by the coupling_cap_threshold_relative option.
In both modes the coupling caps are decoupled if their value is less than the specified total_cap_threshold.
However, if the total_cap_threshold does not apply, then in the default mode of absolute_and_relative the total
coupling capacitance between two nets must both be less than a specified value
(coupling_cap_threshold_absolute), and must not be greater than the specified percentage of the total
capacitance on either net (coupling_cap_threshold_relative) in order to be decoupled.
In the absolute_or_relative mode, the coupling capacitance between two nets is decoupled if either condition is
met.
The following table displays the capacitance filter settings that are recommended for various process nodes (celllevel flow only).
Process Node
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coupling_cap_thr
eshold_absolute
coupling_cap_thr
eshold_relative
total_cap_thresho
ld
Above 130nm
3.0000
0.03
5.0000
130nm and below
0.4000
1
0.0000
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90nm and below
0.2000
1
0.0000
65nm and below
0.1000
1
0.0000
45nm and below
0.1000
1
0.0000
coupling_cap_threshold_absolute <value>
The coupling_cap_threshold_absolute option sets an absolute threshold for grounding coupling capacitors. This
means that the absolute coupling capacitance value is considered regardless of whether the value is positive or
negative. For example, if you set the threshold as 3 femtofarads, the coupling capacitance value of -4fF will be
considered as 4fF and will not be filtered.
The allowable range of values is 0 to 100 femtofarads. If the user-specified value is either less than the minimum value
or greater than the maximum value, Quantus ignores the user-specified value and replaces it with the default
value. This option works as follows:
Note: This description assumes a simplified design with net A, net B, and a ground net. It is also assumes that Quantus
has extracted parasitic coupling caps between net A and net B, as well as parasitic caps between net A and the ground
net.
a. Quantus sums the parasitic coupling cap absolute values between the nodes of net A and net B.
b. If the total parasitic coupling capacitance from net A to net B is less than or equal to the
coupling_cap_threshold_absolute value, all of the parasitic caps between the nodes of net A and net B are
decoupled to the ground_net, then multiplied by the decoupling_factor (see "capacitance" ).
If the filter_cap -exclude_self_cap true command is specified, then self-capacitance will be removed from the
net (not decoupled) if the total self-capacitance on the net is less than or equal to the
coupling_cap_threshold_absolute value.
Note: This option is used only during coupled extraction and must be used with the
coupling_cap_threshold_relative and cap_filtering_mode options.
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Example
Consider the following example:
A#1 B#2 4ff model1
A#2 B#3 2ff model1
A#1 B#5 2ff model2
A#2 B#5 2ff model2
A#1 B#8 1ff model3
A#2 B#8 1ff model3
Let the coupling_cap_threshold_absolute option be specified as 5 femtofarads.
In the above example, the total capacitance value of only model1 is greater than 5. Therefore, Quantus will couple
the parasitic caps between net A and net B for model1 and decouple all parasitic caps between net A and net B to
the ground net for all other models, as follows.
A#1 B#2 4ff model1
A#2 B#3 2ff model1
A#1 GND 2ff model2
A#2 GND 2ff model2
B#5 GND 4ff model2
A#1 GND 1ff model3
A#2 GND 1ff model3
B#8 GND 2ff model3
coupling_cap_threshold_relative < value >
The coupling_cap_threshold_relative variable sets a fractional threshold value between 0 and 1.0 that determines
when Quantus decouples a net's coupling capacitance to ground. If the user-specified value is either less than the
minimum value or greater than the maximum value, Quantus ignores the user-specified value and replaces it with the
default value.
Note: In the batch mode, the <value> is a floating point number which represents <value>*100 % of total capacitance.
Alternatively, in the Quantus UI mode, you can directly give a percentage in the MinC field on the Filtering tab of
Quantus Parasitic Extraction Run Form.
The following formula determines the value to compare to the threshold value:
where:
T AB is the coupling capacitance of each sub net between net A and net B.
Min(A, B) is the smaller of the total capacitance of net A and net B.
Note: The formula for total capacitance adds all the coupling capacitances (not absolute values). However, before
determining if a specific capacitance is decoupled, its absolute value is compared.
For instance, if the total capacitance of net A and net B is the coupling capacitance between them, then the results of
the preceding formula is 1, or 100%. That is to say that the total coupling capacitance between net A and net B is 100%
of the capacitance on net A (or net B).
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For DEF or OA input, if the percentage value computed by the described formula is larger than the specified
coupling_cap_threshold_relative value, Quantus outputs the coupling capacitance for the net. If the calculated
percentage is smaller than the threshold value, Quantus decouples all the capacitance between nets A and B to
ground. The nets may still have coupling capacitance to other nets that will not be grounded.
However, for Assura, Pegasus, or Calibre input, Quantus progressively decouples capacitors between subnets of Nets
A and B from the smallest to the largest until the sum of the decoupled capacitance exceeds the threshold. The larger
coupling capacitors between net A and net B will be preserved. In either case the objective of this command is to
eliminate a number of insignificant capacitors to help reduce the output netlist.
decoupled_to_substrate {true|false}
The -decoupled_to _substrate {true|false} option has been introduced to control decoupling. This option has an
effect on decoupling behavior only when extract -type is c_only_coupled | rc_coupled | rlc_coupled
|rlck_coupled. It uses coupling_cap_threshold_absolute and coupling_cap_threshold_relative command options to
control the decoupling.
The -decoupled_to_substrate behavior is identical to that of decoupling to substrate specification: extract -type
"*_decoupled_to_substrate". Specifically, in extract -type "*_decoupled_to_substrate", the decoupling (to
substrate) is done for all Cc's; while in filtering_coupling_cap -decoupled_to_substrate, the decoupling (to
substrate) is done for those Cc's which would otherwise be decoupled to ground.
This CCL option is supported in all Quantus(xtor) output formats: SPICE, extracted view, xDSPF, and xSPEF format. In
addition, option is also supported in SP/DP, single/multiple process corners.
Quantus UI has also been updated to include the Decoupled to Substrate option.
Note: This feature is applicable only for the transistor-level flows, and has no effect in the LEF/DEF flow.
Error Handling
If you run filter_coupling_cap -decoupled_to_substrate without using extract -type c_only_coupled | rc_coupled
| rlc_coupled |rlck_coupled, an error is displayed.
total_cap_threshold <value>
The total_cap_threshold variable sets a fixed threshold value that determines when Quantus lumps a net's coupling
capacitance to ground and when it records the coupling capacitance of the net. If the total parasitic capacitance of a net
is larger than the specified value, Quantus records the net's coupling capacitance. If the total capacitance is smaller
than the specified value, Quantus lumps the coupling capacitance to ground.
The allowable range of values is 0 to 20 femtofarads. The default is 5 femtofarads. If the user-specified value is either
less than the minimum value or greater than the maximum value, Quantus ignores the user-specified value and
replaces it with the default value.
Note: This option is used only during coupled extraction and must be used with
the coupling_cap_threshold_relative and cap_filtering_mode options.
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filter_res
Command Syntax
Input
Restrictions
filter_res
-merge_parallel_res [ true | false ]
LVS
-merge_parallel_via [ true | false ]
LVS
-min_res <value>
LVS
Default Value: 0.001
-min_res_by_layer “<lvs_layer1> <minRval_1>” “<lvs_layer2>
<minRval_2>” …
LVS
-min_res_centering [ true | false ]
LVS
-remove_dangling_res [ true | false ]
ALL
Description
This command enables you to reduce the total number of parasitic resistors in the design, by eliminating resistors whose
value do not exceed a specific amount, or removing resistors that do not connect to other elements of the design, or merging
parallel resistors when possible.
Options
merge_parallel_res [ true | false ]
If set to true, merge_parallel_res specifies that parallel parasitic resistors should be merged in simple parallel fashion
before netlisting. For the merged parasitic resistors, the L/W parameters are merged as follows:
L - is the length taken from one of the merged resistors (L1 | L2).
W - is the sum of the widths of the merged resistors (W1+W2)
The resulting merged parasitic resistor value is calculated according to Ohms law.
Note: merge_parallel_res merges parallel resistors, not resistor networks. The resistors must share the same
nets.
The -remove_dangling_res option also merges parallel resistors before analyzing nets for dangling resistors only
if -merge_parallel_res is not set to false.
That is, you can enable -merge_parallel_res manually (by setting it to true in the command file), or by default (by
not setting the option in the command file) when enabling -remove_dangling_res.
To remove merge parallel resistors behavior, specify the following CCL commands:
filter_res –remove_dangling_res true
filter_res –merge_parallel_res false
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To enable merge parallel resistors behavior, specify the following CCL commands:
filter_res –remove_dangling_res true
filter_res –merge_parallel_res true
or
filter_res –remove_dangling_res true
The two figures below illustrate why remove_dangling_res must first execute merge_parallel_res before
analyzing nets for dangling parasitic resistors (to simplify the example, parasitic capacitors are not shown). The
Figure 7-15 shows the outcome of remove_dangling_res if parallel resistors are not merged; the
figure, remove_dangling_res with merge_parallel_res shows the correct result obtained by Quantus when
parallel resistors are merged prior to the removing dangling resistors.
remove_dangling_res without merge_parallel_res
remove_dangling_res with merge_parallel_res
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merge_parallel_via [ true | false ]
The -merge_parallel_via true option is used in conjunction with the resistance_mesh_automatic_via_layers option
to merge parallel via resistors. When used together, resistance_mesh_automatic_via_layers will not merge the via
shapes within a mesh so that they are extracted, and then the resulting via resistors are merged by
merge_parallel_via. The -merge_parallel_via CCL option should only be used with the extraction_setup resistance_mesh_automatic_size option (Advanced Adaptive Mesh feature).
In the Quantus transistor-level flow, vias are merged to a larger size to reduce the output R network size. After via
merging, the via and its top and bottom conductor layers are not aligned by default, as shown in the following example:
In this diagram, the M1 conductor is subject to the mesh size of “Msize1” and the upper M2 conductor has the mesh size
of “Msize2”. “Msize1” is the smaller of the two mesh sizes. Once meshed, each distributed mesh area is represented by
one lumped node (shown as green circles). Horizontal resistors are used to connect the mesh nodes. The via layer “V1”
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is merged to the size of “Msize1”. Once merged, the center points (shown as red circles) are used to connect the top
conductor layer to the bottom conductor layer. The merged via resistor will connect to the upper and lower mesh nodes.
The resulting R network can be fairly random. The vertical resistor snaps to the nearest mesh nodes on the top and
bottom layer respectively (shown as black dotted ovals). The red circles are the surviving via resistors and may not be
the best choice for alignment with the green mesh nodes.
You must use the -merge_parallel_via true option in conjunction with the extraction_setup resistance_mesh_automatic_via_layers CCL command option to disable the default via merging. When these two
options are specified, the small via shapes under the conductor mesh are not automatically merged. Instead, they are
extracted, and the extracted via resistor subnodes (red circles) are aligned with and snapped to the appropriate mesh
nodes (green circles), as shown below:
For example, if four via resistors connect to the same top and bottom green circle, they are in parallel and will be
merged into a single resistor.
-merge_parallel_via and -merge_parallel_res are mutually exclusive. The behavior of -merge_parallel_via is
identical to that of -merge_parallel_res, except that the merging will be restricted to some vias. The resulting via R
values will follow the Ohm’s law and the via parameter A= will be summed. This option can only be used for the one
pair via resistance model. The other via resistance models are not supported.
The -merge_parallel_via option requires an additional AA license with the Advanced Adaptive Mesh feature.
Therefore, when both the extraction_setup -resistance_mesh_automatic_size and filter_res -merge_parallel_via
options are specified, XL and 2AA GXL licenses are checked out.
min_res <value>
Specifies the minimum resistance value for extracted parasitic resistors. Any parasitic resistors with values smaller than
or equal to the specified value are discarded by Quantus (the resistor terminals are shorted). min_res will not remove
resistors which would result in the loss of device ports or named nets even if they are smaller than the
specified min_res value.
The value is specified in ohms. The default value is 0.001. Since Quantus uses 0.001 ohm resistors for internal
connections, it is safe to use a minimum value of 0.001 (which eliminates these internally produced resistors). In
addition, if you are running IR-drop or electromigration (EM) analysis, it is recommended that you use the default value
of 0.001 ohms (or smaller) to minimize the filtering of parasitic resistors.
Note the following:
If you specify a min_res value less than 0.001 while extracting inductance (either RLC or RLCK), Quantus will
issue a warning message and use the default value of 0.001.
A value of 0.0 disables min_res reduction.
When parasitic inductance is extracted, changing the min_res value does not have any effect on the Quantus
output. In other words, min_res values do not apply to the inductance nets. However, other nets for which
inductance is not extracted still have min_res reduction.
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min_res_by_layer “<lvs_layer1> <minRval_1>” “<lvs_layer2> <minRval_2>” …
Specifies the minimum resistance value for the extracted parasitic resistors on a layer basis. Here, the <lvs_layer>
argument is the LVS layer name (includes both the connect and via layer) and the <minRval > argument is the minimum
resistance value in Ohm. A value of “0” disables the minimum resistance filter for that layer. When this option is
specified for a specific layer, it overwrites the minimum resistance value specified by -min_res, which is the setting for
all the LVS layers.
Example:
filter_res -min_res 0.001 \
-min_res_by_layer “M12 0.0001” “V11 0.0005”
In this example, the minimum resistance filter for all the layers is 0.001 Ohm; while that for the M12 layer is 0.0001
Ohm and V11 layer is 0.0005 Ohm.
min_res_centering [ true | false ]
Controls the sub-nodes to be selected after eliminating resistors with small resistance values. The default behavior is
that the survivor sub-nodes, among a group of sub-nodes that are formed by the filtered resistors, are arbitrarily chosen.
The default value of this option is false. With -min_res_centering set to true, the survivor sub-nodes are chosen based
on their proximity to the geometric center of the group.
The following diagram illustrates the via centering feature:
Via Group with 3 Vias
Via Group with 4 Vias
Here,
in the left column, three sub-nodes 1, 2, and 3 will be shorted by filter_res -min_res 0.001 CCL. By default, the
survivor sub-node is arbitrarily chosen. However, if -min_res_centering is set to true, the center node “2” is
chosen.
in the right column, there are 4 (even) vias, and both “2” and “3” are close to the center point of the via group, and
“2” is chosen.
The -min_res_centering option should be used in EM mode (extraction_setup -analysis em or output_db em_extract true) of extraction to meet certain EM rule requirements for 7nm and below process nodes. Quantus will
issue an error if the -min_res_centering option is used without the EM mode CCL commands. If the group of subnodes contains primary pins or device I cards, those sub-nodes will be preserved, and will have priority over the
geometric center.
remove_dangling_res [ true | false ]
A dangling resistor is defined as one that has a terminal which does not connect to an I/O pin, a device terminal (not
counting connections to parasitic capacitors), or another parasitic resistor. If set to true, the remove_dangling_res option
specifies that dangling parasitic resistors will not be included in the netlist output.
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If remove_dangling_res is enabled, Quantus will short out and remove dangling parasitic resistors. The removal of
dangling resistors does not affect parasitic capacitors attached to the eliminated resistors--these parasitic capacitors are
retained in the output. Further, if the removal of a dangling resistor results in the parallel placement of two parasitic
capacitors, the parallel capacitors are merged into one parasitic capacitor.
Recursive Application of remove_dangling_res
The figure above illustrates that the application of removing dangling resistors is recursive--that is, once a dangling
resistor is shorted and removed, Quantus reevaluates the net and continues to short out any dangling resistors created
by removing the previous dangling resistor. This mechanism continues until no dangling resistors remain on the net. As
inductor extraction occurs after RC extraction, the elimination of dangling resistors will also eliminate parasitic inductors
which would be connected to those resistors.
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global_nets
Command Syntax
Input Restrictions
global_nets
This command and all of its options are restricted
to LVS input only.
-force_global_nets [ true | false ]
-import_from_lvs [ true | false ]
-nets < netnames >
-nets_file < filename >
Description
Quantus does not extract parasitic resistance or capacitance on declared global nets as a default behavior. In the case of
capacitance extraction, the global net is excluded from acting as an aggressor net, but not as a victim net. Coupling
capacitance is not extracted from the global net to a signal net, but it may be extracted from a signal net to the global net.
The USE POWER and USE GROUND constructs in the DEF file are recognized by Quantus as global_nets and are not extracted.
The global_nets command is mutually exclusive with excluded_nets extraction. You should not specify both in a
single Quantus run.
Global nets should be excluded from extraction by specifying the global_nets command:
global_nets \
-nets "vdd" "vss" \
-import_from_lvs true \
-force_global_nets true
or, global nets should be excluded from extraction with other nets by specifying them together in an excluded_nets file:
extract \
-selection "all" \
-type "rc_coupled"
extract \
-selection nets_file "exclude_nets" \
-type "c_only_coupled"
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Options
force_global_nets [ true | false ]
When a cell has a local net that is declared as global (either through the use of global_nets nets, or -nets_file, or import_from_lvs), and different instances of the cell have that net connected through a pin to a different external net,
Quantus will not recognize the internal net as a valid global net. You must set force_global_nets to true to allow
Quantus to evaluate the net inside the cell as a global net.
This option is only valid when the output_db -type is either "dspf" or "spef". Nets defined as global nets will not appear
in the output DSPF/SPEF netlist.
import_from_lvs [ true | false ]
If set to true, this option specifies that global power and ground nets declared in the LVS input data (such as "power:P"
and "gnd:G") will be imported into Quantus as power and ground nets.
nets <netnames>
List of nets to treat as power and ground nets. Net names are specified within parenthesis. Default is an empty list ("").
Specify each net name within the list in quotes, and separate each quoted net name with a space or comma, for
example, ("gnd1" "gnd2") or ("gnd1","gnd2").
Note: If import_from_lvs is true, global power and ground nets declared in the Assura LVS input data (for example,
power:P, ground:G) also are treated by Quantus as global nets and do not need to be explicitly listed here.
nets_file <file>
Path and file name that contains the set of nets to treat as power and ground nets. Specify one net per line in the file.
The default value is "/dev/null" (empty filename).
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graybox
Command Syntax
Input
Restrictions
graybox
-blackbox_cells_file < filename >
DEF/OA
-def_cells_file < filename >
DEF/OA
-density_cell_list_file <filename>
DEF/OA
-foreign_name_map < LEF_cellname > [ < GDS_cellname > |
oasis_cellname> ]
DEF/OA
-foreign_name_map_file < filename >
DEF/OA
-halt_on_missing_foreign_data [ true | false ]
DEF/OA
-type [ layout | lef_obstruction | none ]
DEF/OA
-type [ layout | none ]
LVS
-use_macro_density [ true | false ]
DEF/OA
Description
Quantus provides three extraction modes for gate-level extraction: blackbox, graybox obstruction, and layout. These three
modes determine how much library data Quantus will evaluate in performing RC extraction, impacting both extraction results
and time.
The default graybox setting is determined both by the input_db command, and by the type of library data provided as input:
Assura/Pegasus/Calibre input defaults to graybox -type none, and views all DSPF cells as blackbox cells.
OA input default depends on the input commands:
If graybox is not explicitly set and the GDS/OASIS files are specified, Quantus defaults graybox to layout.
If graybox is not explicitly set and the LibGen cell library (.cl) is specified, Quantus defaults graybox to layout.
Note that the LibGen cell library overrides the OA cell library.
If graybox is not explicity set and neither the GDS/OASIS files or LibGen cell library are specified, Quantus
defaults graybox to lef_obstruction and sets OA cellviews to “abstract” when loading the OA cell library.
In the graybox -type layout mode, Quantus automatically sets the OA cellview search order to “layout,abstract”
when loading the OA cell library. This is done in order to load the “abtract” view in case the cell in question does
not have the “layout” view.
DEF input default depends on the library input commands:
If lef_file_list is specified the graybox -type is set to lef_obstruction.
If gds_file_list is specified (either alone or with lef_file_list) the graybox -type is set to layout.
If libgen_library_name is specified, the graybox -type is set to layout, if there is no layout data in the .cl file, the
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graybox -type becomes lef_obstruction, if there is no obstruction data in the .cl file the graybox - type
becomes none.
The copy_port_to_gray command should only be used in Libgen when GDSII data is available for all macros in the
library. Otherwise it should be disabled. Libgen will copy the LEF port data as layout data in the library file when the
copy_port_to_gray command is specified. If there is no other GDS data for the cell in the library file, the copied port
data will prevent Quantus from using the lef_obstruction data for that cell, and the capacitance extraction will be
incorrect. For more information please refer to the VoltageStorm Data Preparation Manual.
You can override the default graybox setting by explicitly setting graybox -type to a different value in your command file.
Options
blackbox_cells_file <filename>
​ The blackbox_cells_file command excludes the contents of selected cells from graybox extraction. In the file, specify
one cell or macro per line. Use this command when you want Quantus to ignore the effect of large megacells that
reside under areas of the routing layer that have no routing, while viewing the remaining cells as graybox.
Starting with the PVE 11.1.2 release, you can also comment a line in < filename > by appending a pound-sign
character "#" at the beginning of the line (tab or space before # is allowed). Anything after # is considered a comment.
You cannot use # in the middle of a line if a non-space character exists before it. You can also have multiple comment
lines in a file.
def_cells_file < filename >
New in EXT 10.1, use this option to selectively specify hierarchical DEF files (cells) as grayboxes. Here, < filename >
is name of the file containing a list of grayboxed DEF cells or regular expressions, one cell name or regular expression
per line. See the Using Wildcards with Quantus chapter for more information.
Starting with the PVE 11.1.2 release, you can also comment a line in < filename > by appending a pound-sign
character "#" at the beginning of the line (tab or space before # is allowed). Anything after # is considered a comment.
You cannot use # in the middle of a line if a non-space character exists before it. You can also have multiple comment
lines in a file.
You can specify either all blocks or a few blocks as grayboxes. In addition, you can specify the blocks as grayboxes at
any level of the hierarchy.
Note: The def_cells_file option is only applicable in hierarchical DEF flow and must be used in conjunction
with input_db -type def -def_file_list_file < filename >. In addition, the grayboxed DEF cells must have
corresponding LEF macros specified using the input_db -lef_file_list or input_db - lef_file_list_file options.
Quantus does not graybox DEF cells that do not have corresponding LEF macros. If such DEF cells are specified in
the -def_cells_file, Quantus issues a warning and treats the DEF cells as usual.
density_cell_list_file <filename>
Specifies a file containing the list of LEF macro cells for which the LEF macro DENSITY syntax will be used.
foreign_name_map <LEF_cellname> <GDS_cellname> | <oasis_cellname>
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Sets up a name translation for FOREIGN cell name referenced in the LEF file to a different cell name in the GDS/OASIS
file. This is useful for mapping to a different revision of a GDS/OASIS cell. This command can be used repeatedly as
needed.
foreign_name_map_file <filename>
Sets up a name translation for FOREIGN cell name referenced in the LEF file to a different cell name in the GDS file.
The specified filename can have multiple cell mappings, specifying one LEF cell mapped to one GDS cell per line.
Starting with the PVE 11.1.2 release, you can also comment a line in < filename > by appending a pound-sign
character "#" at the beginning of the line (tab or space before # is allowed). Anything after # is considered a comment.
You cannot use # in the middle of a line if a non-space character exists before it. You can also have multiple comment
lines in a file.
halt_on_missing_foreign_data [ true | false ]
Quantus will report a warning when cells in the LEF file with FOREIGN statements do not have matching cells in the
GDS/OASIS file if this option is set to false and terminates with a fatal error when set to true.
type [ layout | lef_obstruction | none ] - For the cell-level flow, the default depends on the input type.
type [ layout | none ] - For the transistor-level flow, the default is none.
Graybox extraction recognizes the capacitance effects of graybox cells on the interconnect. The effect varies based on
the type of gray data found in the graybox.
Note: For the cell-level flow, if the graybox -type command is not specified in the CCL, then Quantus automatically
assigns the graybox type depending on the type of input (LEF/DEF/OA or GDSII/OASIS).
layout - Indicates that the source of the gray data is the layout data from the cell library or the design.
For DEF/OA input, the layout data for the cell can be imported by using the input_db -type def/oa gds_file_list <filename+>, or -oasis_file_list <filename+> command, or can be read from a LibGen library
(.cl) file. If no layout data is provided during Quantus extraction by either of these methods, a fatal error will be
issued if graybox type is layout.
For Assura/Pegasus/Calibre input, the layout data is imported with the design. The layout option is required to
invoke macro cell gray mode extraction in the transistor-level flow. Quantus checks out the Extraction XL license
when the macro cell gray mode extraction is invoked. For details on macro cell gray mode extraction, refer to
Macro Cell Gray Mode Extraction .
lef_obstruction - Indicates that the source of the gray data is the obstruction data type from LEF input cell library.
Note: lef_obstruction is not a valid setting for Assura/Pegasus/Calibre input.
none - Performs blackbox extraction rather than graybox extraction. Use this option to view all cells as blackbox.
Note: Use graybox -blackbox_cells_file to specify individual cells to view as blackbox instead.
use_macro_density [ true | false ]
Specifies to use the LEF macro DENSITY syntax to state the block density information, that is, the density percentage
for all the shapes. This option enables better accuracy for the top-level design nets outside the design block boundary.
The option must be used with the density_cell_list_file option. If use_macro_density is set to false but
density_cell_list_file is specified, then Quantus ignores the density_cell_list_file setting.
You must specify one of the following options to use the use_macro_density and density_cell_list_file CCL
options:
graybox -type lef_obstruction
graybox -type layout , and the LEF macros that do not have corresponding GDS | OASIS cell through FOREIGN
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Note: If a cell exists in the density_cell_list_file and the cell's GDS/OASIS is also specified, then Quantus will use
the GDS/OASIS data and ignore the LEF density.
For all the LEF macro cells mentioned in <filename>, Quantus ignores the data under the OBS section in the LEF, and
instead uses the RECT information in the DENSITY section to create new OBS shapes. The OBS shape is equivalent to the
DENSITY RECT shape with 100% density.
hierarchical_extract
Command Syntax
Input Restrictions
hierarchical_extract
This command and all of its options are
restricted to LVS input only.
-hierarchical_cell_list_file <filename>
-split_feedthrough_pins [ true | false ]
-split_feedthrough_pins_delimiter
<delimiter>
Default Value: %
-split_feedthrough_pins_distance <value>
Default Value: 5 microns
Description
Note: Hierarchical extraction cannot be used with multiple process corner extraction (see "process_technology" ).
Hierarchical netlist generation is required to support certain design flows. Hierarchical netlists can be significantly more
compact than the equivalent flat netlists, and can therefore be key to enabling simulation and analysis. Hierarchical netlists
enable you to perform simulations hierarchically and/or incrementally.
The hierarchical_extract command is available for use with Assura, Pegasus, and Calibre input and for creating output_db
types Spice, Extracted View, LVS Extracted View, and transistor-level DSPF/SPEF output. It does not support cell-level
DSPF or SPEF output.
Hierarchical extraction is also not supported for inductance extraction (extract -type rlc_xxx and rlck_xxx).
In hierarchical_extract a cell or block is extracted only once, and the extracted data re-used for each recurring instance.
Hierarchical extraction can produce significant gains in performance and capacity due to the fact that cells or blocks are often
reused many times in a design.
Each cell specified for hierarchical extraction should be fully contained and complete with its own reference to power and
ground to insure correct results. All layers that form a cell must be found on the same level of the design hierarchy. An error
condition occurs if layers forming a specified cell exist on different levels of the hierarchy.
Note: For design input coming from Assura LVS, the RSF for the LVS run should include the ?preserveCells avParameter
(see the Assura Command Reference manual for more information). This ensures that specified hierarchical cells will not be
flattened during the LVS run.
You should also be careful when using resistance blocking in Techgen (see Quantus Techgen Reference Manual). Blocking
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resistance on a specific layer makes shapes on that layer non-resistive. However, hierarchical extract requires resistive
materials for extracting netlist connectivity between cells. The res_blocking shapes can unintentionally block interconnect
shapes in a cell resulting in connection errors. Shapes in a cell making connection with other cells in the hierarchy must not
be blocked.
Options
hierarchical_cell_list_file <filename>
The hierarchical cell list file is an ASCII file specifying the names of cells for hierarchical extraction, one cell per line,
and control statements that are used to manage extraction and output characteristics of the specified cells.
Cell Name: The cell names can be specified as triplets (cell name, view name, and lib name) or just the cell name. In
cases where only the cell name is specified, Quantus expands the cell name to a triplet. The cells are extracted in the
order they are specified.
Note: You may define cells in the file using wildcards or regular expressions. See Using Wildcards with Quantus.
The following restrictions apply to the specified cells:
The hierarchical_cell_list_file must not have `$' characters in the cell names or an error will occur. Cell
names should also not begin with the `+' character as this is reserved for control statements.
A cell should be listed only once in the hierarchical_cell_list_file. If multiple occurrences of a single cell
name appear in the file, only the last occurrence of the cell and its control statements will be used.
A cell must have a single layout view. Quantus will issue an error if a specified cell has multiple layout views.
Control Statements: are specified as + keyword=value pairs. The control statement lines must begin with "+" as the first
character.
Netlisting Control Statements
+ netlist=noSubckt | none | lvsNetlist | extractedNetlist
netlist=noSubckt
This control statement will prevent the extraction of the given cell and eliminate the .subckt definition from
the output netlist.
Note: The Extracted View output does not support netlist=noSubckt.
netlist=none
This statement will prevent the extraction of the specified cell, and will result in only an empty .subckt and
.ends call for the cell in the resulting netlist file. It is an empty cell with I/O pins only.
netlist=lvsNetlist
This will result in a full netlist for the given cell with no parasitics being extracted.
netlist=extractedNetlist
This will result in a full netlist for the given cell including all the extracted parasitics. This is the default.
Capacitance Extraction Control Statements
+ capacitanceView=grayBox | blackBox
The capacitanceView control statement directs how the shapes in this cell and its children are to be viewed by the
parent (see Hierarchical Extraction ).
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capacitanceView=grayBox
This will result in all the shapes being seen by the parent. The shapes will be considered connected to the
ground net. This is the default.
capacitanceView=blackBox
The shapes inside the cell are not seen by the parent, and therefore are not considered during extraction.
Controlling Split Pins for Specific Cells
+ splitPins=true | false
The hierarchical_extract -split_feedthrough_pins command generally controls this function for all cells in the
design. However, this control statement overrides the global setting of the hierarchical_extract split_feedthrough_pins command for the specified cell.
splitPins=t[rue]
Split pins of the specified cells when they occur at distances greater than the specified
split_feedthrough_pins_distance.
This setting is not meaningful for the top cell and should not be used.
splitPins=f[alse]
Do not split the pins of the specified cell.
Example Hierarchical Cells File9
(1) AND layout 622_layout
(2) OR
(3) RIB layout 622_layout
(4) + netlist=lvsNetlist
(5) QUAD
Line 1: cell "AND" is defined with cell name, view name, and lib name.
Line 2: cell "OR" is defined using only the cell name.
Line 3: cell "RIB layout 622_layout" is defined with control statements on Line 4.
Line 4: the control statement "+ netlist=lvsNetlist" is used to limit the parasitic extraction on the RIB cell.
Line 5: the top cell name "QUAD" is defined.
Note: Hierarchical extraction loops through all cells and considers the geometric shapes inside cells as grounded
during extraction. The HRCX_GRAY_BOX_FILL environment variable causes Quantus to fill any small gaps in
these shapes to reduce the number of shapes and reduce extraction time.
setenv HRCX_GRAY_BOX_FILL Y
split_feedthrough_pins [ true | false ]
A net in a cell might make connection at several places with the parent or neighbor. The split_feedthrough_pins
option enables hierarchical_extract to identify these connection points and label them as different pins in cases
where the distance between them is greater than the split_feedthrough_pins_distance value. The default is false.
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If -split_feedthrough_pins true is set, Quantus will not create split pins for macro cells when the following
CCL command options are specified:
output_db -pin_order_file file
-force_subcell_pin_orders true
Only top cell split pins will be created for any duplicate I/O ports.
For example, the CLK net could be split into CLK, CLK%1, CLK%2, resulting in the following:
.SUBCKT RBLK (CLK, CLK%1, CLK%2)
Note: This option is automatically set by output_db -em_extract to a value based on the output format. See em_extract
for the value of the setting.
split_feedthrough_pins_delimiter <"delimiter">
Specifies the delimiter used for splitting pins. The default delimiter is %.
The character specified with -split_feedthrough_pins_delimiter "delimiter" and output_db -sub_node_char
“delimiter” must not be the same.
split_feedthrough_pins_distance <value>
Specifies the minimum distance for splitting pins. The default value is 5 microns.
inductance
Command Syntax
Input Restrictions
inductance
-extract_layer_list <layername+>
LEF/DEF
-filter_size <value>
Default Value: 2.0 microns
LVS
-interaction_region <filename>
LVS
-peec_model [ true | false ]
LVS
-wide_band_model [ true | false ]
All
Description
Quantus performs parasitic extraction of parasitic self and mutual inductance for on-chip interconnect, and is targeted for
block/chip level extraction in mixed-signal, analog, and RF applications.
Quantus includes complementary inductance extraction algorithm Partial Element Equivalent Circuit (peec_model) which
outputs partial inductance values. This method calculates inductance for 90 and 45 degree interconnect.10 An optional
broadband interconnect model (wide_band_model) can capture high frequency effects such as the skin and proximity effects.
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The default numerical values of the following options have been optimized to insure quality extraction results. The
defaults should not be changed without expert knowledge of the tool.
Options
extract_layer_list <layername+>
Specifies the layers to process for cell-level inductance extraction. The layer names are defined in the technology LEF
file. By default, all layers in the design are included in inductance extraction.
filter_size <value>
This option directs Quantus to disregard rectangles that are smaller than the value specified in microns. If this value is
increased there will be less inductance extracted because the number of excluded polygons is increased. Specify
filter_size as a positive integer or positive floating point number in units of microns. The default is 2.0 microns.
The value of filter_size should not be set greater than the resistor fracture length or interconnect that is
fractured for resistance extraction will be excluded from inductance extraction (see "extraction_setup" ).
interaction_region <filename>
This option allows you to manually create an interaction region for performing inductance extraction in that region. You
must specify this command when performing inductance extraction (for which the -peec_model option should also be set
to true).
Both mutual and self-inductance are effected by the interaction region and extraction results may vary if user
regions are specified or interaction regions are automatically defined.
With interaction_region specified, inductances are extracted for any portion of a net that falls within the region. Within
an interaction_region, self inductances are extracted for all inductance nets and mutual inductances are extracted
between all inductance nets. Mutual inductances are not extracted between inductance nets in different interaction
regions.
Interaction Region File Syntax:
region_number ( xlow,ylow ) ( xhigh,yhigh ) [ layerX,layerY ]
Where:
region_number is a user-defined integer ID. Two different non-overlapping regions can have the same
region_number in which case they are treated as equivalent for mutual inductance extraction (ie, K values are
extracted between the disjointed regions).
( xlow,ylow ) ( xhigh,yhigh ) coordinates are with respect to the TOP cell, and specify a rectangle from the
lower left corner to the upper right corner.
Note: The coordinates for a region must be specified from the lower left corner to the upper right corner, or an error
will occur.
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layerX,layerY layer names are defined in the technology file.
Optionally specifies the layers to process for inductance extraction, from layerX to layerY inclusive. When the
layers are not specified for a given interaction region, Quantus assumes all layers in the design are included,
except those layers excluded from inductance extraction with the Techgen -lexclude command (see Quantus
Techgen Reference Manual ).
Note: When the layers are defined, all the layers between layerX and layerY inclusive should not be specified in the
Techgen -lexclude command, or an error will occur.
Sample Interaction Region File:
1 (-398.5,676) (-374,1000.2)
2 (-562.6,681.25) (-398.5,701.8)
3 (-686,494.4) (-660,581) M1,M4
4 (-890,450) (-840,550) M1,M3
5 (-840,450) (-790,550 )
peec_model [ true | false]
Note: peec_model is not compatible with DSPF / SPEF output.
Instructs Quantus to extract inductance using partial-element equivalent circuits (PEEC).
The number of
parasitic elements in PEEC mode will be very large and so requires the interaction_region option to limit
the area of the design being evaluated.
The peec_model will also automatically perform resistance extraction on all nets including power and
ground nets. When using peec_model do not specify the global_nets command so that Power and Ground nets
may be part of the resistance extraction (see global_nets ).
Note: The Return-Limited inductance extraction (non-PEEC) functionality is no longer supported. By default, Quantus
GUI will set the PEEC Mode option to ON (inductance –peec_model true) when extraction type is RLC or RLCK.
However, in the batch mode (CCL command file), you need to explicitly mention the following command in CCL for
inductance extraction:
inductance -peec_model true
wide_band_model [ true | false ]
This option instructs Quantus to generate a broadband interconnect model to characterize the change in resistance and
inductance due to the skin and proximity effects as frequency increases. The broadband interconnect model is accurate
from DC to over 50 GHz, and does not need any additional input from the user. The wide_band_model option is a very
efficient method for modeling high frequency effects, but does increase the total number of parasitic elements in the
output.
This feature is supported in transistor-level extraction when the output modes are extracted view, spice or xdspf.
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input_db
Command Syntax
Input Restrictions
input_db
input_db -type assura
-design_cell_name <cellName> <viewName>
<libraryName>
-design_file <file>
-directory_name <dir>
-format [DFII | GDS]
-hierarchy_delimiter <char>
input_db -type assura and all of its
options is restricted to Assura LVS
input only.
Default Delimiter:/')
-library_definitions_file <string>
-run_name <string>
-technology_library_cell_map_file
<file_name>
input_db -type pegasus or pvs
-design_cell_name <cellName> <viewName>
<libraryName>
-device_properties_file <filename>
-directory_name <dir>
-library_cell_list_file <filename>
-run_name <top_cell>
-technology_library_cell_map_file
<file_name>
input_db -type calibre
-design_cell_name <cellName> <viewName>
<libraryName>
-device_properties_file <filename>
-device_property_value <value>
input_db -type pegasus or pvs and all
of its options is restricted to
Pegasus/PVS input only
input_db -type calibre and all of its
options is restricted to Calibre input
only
Default Value: 7
-directory_name <dir>
-hierarchy_delimiter <char>
/')
-instance_property_value <value>
Default Value: 6
-library_cell_list_file <filename>
-library_definitions_file <filename>
-net_property_value <value>
Default Value: 5
-run_name <string>
-layer_map_file <filename>
-technology_library_cell_map_file
<file_name>
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input_db -type def
-bump_map_file <ubump_mapping_file_name>
-copy_def_macropin <true | false>
-def_file_list <filename>
-def_file_list_file <filename>
-design_file <filename>
-gds_file_list <filename+> | gds_file_list_file <filename>
-ignore_invalid_vias <true | false>
-lef_file_list <filename+> | -
input_db -type def and all of its
options is restricted to DEF input only.
lef_file_list_file <filename>
-libgen_library_name <library_name>
-oasis_file_list <filename+> | oasis_file_list_file <filename>
-unified_db_gds_file_list <filename+> |
-unified_db_gds_file_list_file
<filename>
input_db -type oa
-design_cell_name <cellname> <viewname>
<libname>
-design_cellview <library_name>
<cell_name> <view_name> -gds_file_list
<filename+> | -gds_file_list_file
input_db -type oa and all of its
options is restricted to OpenAccess
input only.
<filename>
-oasis_file_list <filename+> | oasis_file_list_file <filename>
-libgen_library_name <library_name>
-library_cell_name <cellname1>
<viewname1> <libname1>
[<cellname2> <viewname2>.... <libname2>
...]
-library_definitions_file <string>
-oa_cells_list <library_name1>
<cell_name1> <view_name1> ....
<library_nameN> <cell_nameN>
<view_nameN>
-oa_cells_list_file list.txt
-oa_default_rule_name <rule_name>
-retain_def_metal_fill [ true | false ]
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input_db -type metal_fill
-gds_file <filename> | -oasis_file
<filename> | -unified_db_gds_file
<filename>
-offset_x <value>
metal_fill and all of its options is
restricted for use with DEF input only.
Default Value: 0.0
-offset_y <value>
Default Value: 0.0 -orientation [ R0 |
R90 | R180 | R270 | MX | MX90 | MY |
MY90 ]
-metal_fill_top_cell <name>
-retain_def_metal_fill [ true | false ]
input_db -type gds
-design_file < gds file1 > …< gds file
N>
-offset_x <value>
Default Value: 0.0
-offset_y <value>
Default Value: 0.0
-orientation [ R0 | R90 | R180 | R270 |
MX | MX90 | MY | MY90 ]
-top_cell < top_gds_cell >
input_db -type HPB
gds and all its options is restricted for
use with gds files with RDL layers for
DEF input
input_db -type HPB is restricted to
DEF input only.
input_db -probe_text_file ed_file_name
1
The design_cell_name option is only required for Pegasus or Calibre input when the desired output is an
extracted_view or lvs_extracted_view.
2
For input type DEF the libgen_library_name is mutually exclusive with lef_file_list, lef_file_list_file, and
copy_port_to_obs.
3
For input type OA the libgen_library_name is mutually exclusive with library_definitions_file and
library_cell_name.
4
The input_db command can only be specified once to define the input database for an extraction run. However, if the
original input_db is DEF, the input_db command may be used a second time to specify a GDS file containing
metal_fill shapes.
5
For input type LVS, the cell names (macro cells, blocking cells, hierarchical cells) should not be the same as the ICT
file object names (conductor/ sub_conductor/ via/ sub_via). Quantus will exit with an error message if the same name
is specified for both the cell and ICT file object in the transistor-level flow.
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Description
The input_db command allows you to specify key characteristics of the input data, such as where the design data can be
found, where the library data can be found, and the actual format of the input data (for instance Assura data can be either
GDS or DFII format).
Options
bump_map_file ubump_mapping_file_name
Turns on micro-bump extraction with bump mapping file. To turn on micro-bump extraction for one chip (either top tier or
bottom tier), use:
input_db -bump_map_file ubump_mapping_file_name
Where, ubump_mapping_file_name is the file name that includes port pairs connected by micro-bump. In this case,
Quantus will extract resistance and total capacitance from the micro-bump by default if the design is a 3DIC design.
copy_def_macropin <true | false >
The copy_def_macropin argument specifies the copy of macro pin shapes to mid-level nets. Default is false. This option
must be specified along with the def_file_list_file option.
Note: The def_file_list_file and copy_def_macropin options do not work with input_db -def libgen_library_name option.
def_file_list <filename>
Specifies one or more lower-level DEF files, which are the child cells instantiated in the parent DEF file specified using
the -design_file command option. You can specify the lower-level DEF files in any order. This option allows you to
specify the DEF file names directly in the command file script. You can also use the input_db def_file_list_file option to specify a file containing the list of DEF file names.
def_file_list_file <filename>
New in EXT 9.1, Quantus can directly read the hierarchical DEF files. Therefore, running the MergeDEF utility to
merge the multiple DEF files to a single flat DEF file is no longer required. The hierarchical DEF feature is
supported in Quantus cell-level flow only and is supported in SP/DP, default, and advanced capacitance modes.
Note: Starting with the EXT 9.1 release, the MergeDEF utility is no longer available with Quantus.
The def_file_list_file option specifies the file containing a list of lower-level DEF files, one filename per line. These
files are for the child cells that are instantiated in the parent DEF file. The parent DEF file is specified using the design_file <filename> command. You can specify the lower-level DEF files in any order.
design_cell_name <cellName> <viewName> <libraryName>
Name of the design cell for Assura (when -format DFII is specified) or OA input as specified by the cell/view/lib.
The design_cell_name option is also required for Calibre input when the desired output is an extracted_view or
an lvs_extracted_view (see output_db ). This indicates the DFII cell name and library to write
the extracted_view created by Quantus. The viewName specified must be the layout view as it contains information
needed for the creation of the extracted_view.
design_cellview <library_name> <cell_name> <view_name>
Specifies the Open Access top cell to be extracted. You need to specify the library name, top cell name in the library,
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and the layout view name in the specified cell. This option is used for hierarchical OA designs in the cell-level flow.
design_file <file> | <gds_file1><gds_file2>... <gds_fileN>
Name of the design file for Assura when -format GDS is specified.
For GDS input, you can provide multiple GDS files. However, you must provide a top cell from the GDS input file using
the top_cell option.
device_properties_file <filename>
<filename> specifies the name of the device properties file written by Calibre or Pegasus. The device properties file
contains LVS-measured device properties. Quantus reads the device properties from the specified <filename > and
merges those properties with the device properties in the LVS extracted SPICE netlist. See Device Properties File for
details.
Note: If you do not specify the -device_properties_file option, Quantus automatically searches for the
file <run_name> .props file in the directory specified using the -directory_name < directory >option. For Pegasus, the
file < run_name >.props exists there by default. For the QCI flow, this is the query_output directory. Therefore, you may
need to be rename and move the file to that location.
device_property_value < value >
< value > specifies the PROPATTR value for devices in the Calibre AGDS data. This value is provided by users through
Calibre CCI `s GDS DEVPROP NUMBER command during AGDS generation. The default value is 7.
directory_name <dir>
This command specifies the name of the directory in which Assura, Calibre, or Pegasus has placed the output files of
the LVS run.
format DFII | GDS
Defines the input data format for Assura.
gds_file <filename> | oasis_file <filename> | unified_db_gds_file <filename>
Specifies the GDSII/OASIS filename containing the metal fill data to be input. This option is required when input_db type metal_fill is specified. Quantus can accept a hierarchical GDSII/OASIS file as input for metal fill. In this case
Quantus extracts and flattens the top-level cell in the GDSII/OASIS file and maps it to the associated cell in the design. If
multiple top-level cells are defined in the GDSII/OASIS file Quantus extracts and flattens all of them.
unified_db_gds_file <filename>
New in Quantus 20.1: You can also specify a file containing top-level hierarchical metal fill database to be input. This
option is required when input_db -type metal_fill is specified.
Note: The top metal fill option accepts only one input file. Quantus will abort if input_db -type metal_fill gds_file and -oasis_file options are specified together.
gds_file_list <filename +>
and/or
oasis_file_list <filename+>
and/or
unified_db_gds_file_list <filename+>
Specifies a GDS/OASIS file or list of GDS/OASIS files that are to be parsed to obtain library information needed for
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creating the cells and vias in the design. Multiple files should be separated by a space. The files names need not be
quoted, and do not require comma separators.
This option must be specified with the lef_file_list command (or lef_file_list_file) to add GDS information to
macro cells defined in the LEF data. When GDS data has been provided in addition to the LEF data,
the graybox command can be set to layout if desired.
oasis_file_list <filename+>
New in EXT 10.1, Quantus has been enhanced to accept files in OASIS format that manages a design better than the
GDS format.
unified_db_gds_file_list <filename+>
New in Quantus 20.1: you can specify a file containing block-level hierarchical metal fill database to be input.
gds_file_list_file <filename>
and/or
oasis_file_list_file <filename>
and/or
unified_db_gds_file_list_file <filename>
Specifies a file that contains a list of GDS files (one filename per line) that are to be parsed to obtain library information
needed for creating the cells and vias in the design. This option must be specified with the lef_file_list command
(or lef_file_list_file) to add GDS information to macro cells defined in the LEF data.
oasis_file_list_file <filename>
New in EXT 10.1, you can also specify a file that contains a list OASIS files.
unified_db_gds_file_list_file <filename>
New in Quantus 20.1: you can specify a file that contains block-level hierarchical metal fill database to be input.
Starting with the PVE 11.1.2 release, you can also comment a line in < filename > by appending a pound-sign
character "#" at the beginning of the line (tab or space before # is allowed). Anything after # is considered a comment.
You cannot use # in the middle of a line if a non-space character exists before it. You can also have multiple comment
lines in a file.
hierarchy_delimiter <char>
Character used as a delimiter to separate instance names from different levels of hierarchy in the input database. The
default hierarchy delimiter is a forward slash ("/").
Note: This should not be confused with the output_db -hierarchy_delimiter command that specifies the character to
add to the output DSPF netlist.
ignore_invalid_vias <true | false>
When Quantus reads in the design data from a LEF/DEF input, it errors out if it finds invalid via data (for example,
undefined layer in the techfile). The ignore_invalid_vias argument enables Quantus to ignore invalid via definitions
found in the LEF/DEF input files. The default value is false.
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Starting with the PVE 11.1.1 release, the input_db -ignore_invalid_vias option is replaced by the
extraction_setup -ignore_invalid_vias CCL option. The input_db -ignore_invalid_vias option will be
removed in a future Quantus release.
instance_property_value < value >
< value > specifies the PROPATTR value for instances in the Calibre AGDS data. This value is provided by users through
Calibre CCI `s GDS PLACEPROP NUMBER command during AGDS generation. The default value is 6.
layer_map_file < filename >
< filename > specifies a file containing the layer mapping between the GDS input layers and the layer names
specified in the Calibre LVS rule file.
lef_file_list <filename +>
Specifies a LEF file or list of LEF files that are to be parsed to obtain library information needed for creating the cells
and vias in the design. Multiple files should be separated by a space. The files names need not be quoted, and do not
require comma separators.
The LEF files will be parsed in the order specified, so it is suggested that you specify "technology" LEF files containing
any layer definitions before any "cell_library" LEF files.
Note: If a ROUTING or CUT layer is defined in the LEF file but not defined in the technology file, Quantus will issue a
warning. However, if a ROUTING or CUT layer is referenced or used directly by the DEF file but not defined in the
technology file, a fatal error will occur and Quantus will terminate execution.
Although LEF format supports NAMECASESENSITIVE OFF, in order to support name mapping between Quantus
SPEF output and Verilog, OA, and other applications, NAMECASESENSITIVE must be set to "ON" when importing the
LEF files directly into Quantus. The existing LibGen flow supports NAMECASESENSITIVE as OFF, however when you
want to read the LEF input directly you must change NAMECASESENSITIVE to "ON" in the LEF library files.
If you need to use GDS/OASIS to create library data because the LEF description is not sufficiently detailed, or only
GDS/OASIS data is available, then you must use the following options:
gds_file_list option (or gds_file_list_file) for GDS data
oasis_file_list option (or oasis_file_list_file) for OASIS data
When the lef_file_list or lef_file_list_file options are specified, then the graybox command should also
be specified with a value of lef_obstruction or none (see "graybox" ).
If the gds_file_list command has been specified in addition to the lef_file_list command then graybox can
be specified with a value of layout.
lef_file_list_file <filename>
Specifies a file that contains a list of LEF files (one filename per line) that are to be parsed to obtain library information
needed for creating the cells and vias in the design. The LEF files will be parsed in the order specified, so it is
suggested that you specify "technology" LEF files before any "cell_library" LEF files.
libgen_library_name <library_name>
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Quantus can read LEF library files directly, and the use of LibGen is no longer required. As a result of this,
Libgen is no longer provided in the Extraction product release. If you still desire to use LibGen with Quantus, you
will need to get it from the SEV4.1 or later release, or the ANLS6.1 or later release.
​ The libgen_library_name option specifies the name of the cell library database, created by LibGen. This variable only
applies to the LibGen flow and is not required when reading LEF data.
Note: The libgen_library_name option is mutually exclusive with the lef_file_list and lef_file_list_file options,
as well as the copy_port_to_obs option of the extraction_setup command (see "extraction_setup" ).
library_cell_list_file <filename>
Specifies the list of cells that should be output to the DSPF netlist when the input_db source is Calibre or Pegasus.
This option is required for creating cell-level DSPF output (please refer to "Creating Cell-level DSPF/SPEF or
Transistor-level DSPF/SPEF" ).
The library_cell_list_file option controls how Quantus determines which cells will be exported to the DSPF netlist.
Since Assura LVS will not be generating the runName.dcl file for Quantus with either Calibre or Pegasus input,
the library_cell_list_file option must be used instead of the Assura avParameter ?dspfCells (see the Assura
Command Reference for more information).
The library_cell_list_file option allows you to specify the cell selection for inclusion in the DSPF output. Each line
may only contain one cell name. The format of the file is to specify one cell name per line.
The library_cell_list_file file may include cells that are not found in the design. Cells that are not found in the
design will simply be ignored by Quantus when parsing the file.
library_cell_name <cell_name1> <view_name1>,<viewname2>... <library_name1> [ <cell_name2> <view_name2>
<library_name2> ...]
​ The library_cell_name specifies which view and library the specified cell data will be taken from when Quantus is
invoked. The default view is abstract. This command can be used multiple times and if a specific cell is referenced
multiple times, the last reference will be used.
Note: If library_cell_name is not specified libraries will be searched in the order they are specified in
the library_definitions_file.
cell_name
All cells that match the cell_name pattern will get their data from the specified view and library.
library_name
The library name defines which library will be used to extract the specified cell data. If the library
can not be found an error will be generated. If library_name is not specified, the library listed in the
lib.defs will be used to locate the cell data.
Note: Starting with IC version 6.1.4, the use of lib.defs file has been discontinued. If you specify a
lib.defs file using the -library_definitions_file option, Quantus will return an error. Therefore, if
you are using IC 6.1.4, specify the library definitions file as cds.lib. However, if you are using an IC
version earlier than 6.1.4 but not 5.1.x, you can still use the lib.defs file by setting the environment
variable DD_USE_LIBDEFS to YES. If you set the environment variable DD_USE_LIBDEFS to NO
(uppercase), then Quantus will honor only cds.lib irrespective of the IC version you are using.
view_name
The view name that is to be used for extracting the specified cell data.
library_definitions_file <filename>
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For DFII input format this option specifies the cds.lib file to be used for the Quantus extraction run (you can use any
name for the file, it is not required that you call it cds.lib). This will override the standard DFII search mechanism
specified by the Cadence setup search file setup.loc.
For Calibre input format, the library_definitions_file option specifies the cds.lib or lib.defs file to load. The path
to these files can be a full or a relative path.
You can also comment a line in < filename > by appending a pound-sign character "#" at the beginning of the line (tab
or space before # is allowed). Anything after # is considered a comment. You cannot use # in the middle of a line if a
non-space character exists before it. You can also have multiple comment lines in a file.
metal_fill_top_cell < name >
This option allows you to identify the top cell from the GDS metal fill input file. If no top cell is specified, Quantus will
automatically detect the top cell from the input file. However, if you do specify metal_fill_top_cell <name >, and the
specified cell does not exist, Quantus will exit with an error.
net_property_value < value >
< value > specifies the PROPATTR value for nets in the Calibre AGDS data. This value is provided by users through
Calibre CCI `s GDS NETPROP NUMBER command during AGDS generation. The default value is 5.
oa_cells_list <library_name1> <cell_name1> <view_name1> .... <library_nameN> <cell_nameN> <view_nameN>
Specifies one or more block cells for extraction. You need to specify the library name, block cell name in the library, and
the layout view name in the specified cell for each block cell. This option is used for hierarchical OA designs in the celllevel flow. For more information on the OA flow, refer to the OA input section.
oa_cells_list_file list.txt
Specifies a file containing the list of block cell names. This file has the same syntax as the -oa_cells_list option. This
option is used for hierarchical OA designs in the cell-level flow.
oa_default_rule_name < rule_name >
In earlier releases, Quantus supported only LEFDefaultRouteSpec as the default rule name. Starting with the PVE 12.1
HF2 release, you can specify any rule name using the new CCL command input_db -oa_default_rule_name.
The syntax of this command is:
input_db -type oa \
-oa_default_rule_name < rule_name >
Where, rule_name specifies the default rule name. If user-defined/system default rule is not found, then Quantus
displays an error message.
offset_x < value >
If input_db -type metal_fill or input_db -type gds is specified, Quantus will increment all X and Y coordinates of
shapes present in the GDS file by the value of offset_x and offset_y respectively. The value is specified as a floating
point number, and defaults to 0.0.
For example, if GDS coordinates for lower-left are (-300, -400) and you need to move it to (0,0), the required offset would
be (0,0) – (-300, -400), that is (300, 400).
When both offset values (offset_x and offset_y) and the orientation parameters are specified (default value R0 is used,
if orientation is not specified), Quantus applies orientation first, and then applies the offset values. This is consistent with
the LEF guideline for placing a macro in the design. This applies to both GDS layout data and metal fill data.
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When you calculate the offset values and the orientation parameters from the layout to specify them in Quantus
command file, you should follow the same rule and apply the orientation first, if any, and then apply the offset values to
obtain the right offset values and orientation parameters. Applying the offset values first might provide different results,
which may not be correct.
Note: Quantus cannot check the specified offset or orientation to ensure the input GDS file aligns with the DEF file. You
must specify correct values or you will cause unintentional shorts between the DEF and GDS data, and errors will occur
during extraction.
If the layout_scale keyword is used, you should specify the offset value after applying the scale factor values. For
example, if the offset value in the design in drawn dimensions is 100um and the value of layout_scale argument is 0.9,
then you should specify the offset value after applying the scale factor value on the original offset on the design. Here,
the offset value would be 90um.
offset_y < value >
If input_db -type metal_fill or input_db -type gds is specified, Quantus will increment all X and Y coordinates of
shapes present in the GDS file by the value of offset_x and offset_y respectively. The value is specified as a floating
point number, and defaults to 0.0.
When both offset values (offset_x and offset_y) and the orientation parameters are specified (default value R0 is used,
if orientation is not specified), Quantus applies orientation first, and then applies the offset values. This is consistent with
the LEF guideline for placing a macro in the design. This applies to both GDS layout data and metal fill data.
When you calculate the offset values and the orientation parameters from the layout to specify them in Quantus
command file, you should follow the same rule and apply the orientation first, if any, and then apply the offset values to
obtain the right offset values and orientation parameters. Applying the offset values first might provde different results,
which may not be correct.
Note: Quantus cannot check the specified offset or orientation to ensure the input GDS file aligns with the DEF file. You
must specify correct values or you will cause unintentional shorts between the DEF and GDS data, and errors will occur
during extraction.
If the layout_scale keyword is used, you should specify the offset value after applying the scale factor values. For
example, if the offset value in the design in drawn dimensions is 100um and the value of layout_scale argument is 0.9,
then you should specify the offset value after applying the scale factor value on the original offset on the design. Here,
the offset value would be 90um.
Note: offset_y must be used with offset_x as a pair, or an error will occur.
orientation [ R0 | R90 | R180 | R270 | MX | MX90 | MY | MY90 ]
Allows you to specify the orientation of the metal fill GDS file input with regard to the DEF design data. You can rotate or
mirror the GDS data to insure it aligns properly with the DEF design data.
Note: Quantus cannot check the specified offset or orientation to ensure the input GDS file aligns with the DEF file. You
must specify correct values or you will cause unintentional shorts between the DEF and GDS data, and errors will occur
during extraction.
The available arguments for the orientation option are as follows:
Argument
Meaning
DEF Equivalent1
R0
No reflection, no rotation. This is the default.
N
R90
Rotate input GDS file 90 degrees counter clockwise.
W
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R180
Rotate input GDS file 180 degrees.
S
R270
Rotate input GDS file 270 degrees counter clockwise.
E
MX
Mirror input GDS file along the X-axis.
FS
MY
Mirror input GDS file along the Y-axis.
FN
MX90
Mirror on the X-axis, and then rotate 90 degrees counter-clockwise.
FW
MY90
Mirror on the Y-axis, and then rotate 90 degrees counter-clockwise.
FE
1 The DEF equivalent is added for clarity.
probe_text_file ed_file_name
In addition to using the "probe" command during the Pegasus-LVS flow to add probe text for debugging, virtual probe
text can also be added using the -probe_text_file option. This option is independent of the Pegasus "probe"
command, and does not require any additional LVS or Virtuoso setup modifications. It is applicable to the
Assura/Pegasus/Calibre-Quantus flows.
The probe text file format contains the following fields separated by blank characters:
<probe_text> <x_coordinate_in_um> <y_coordinate_in_um> <lvs_layer_name>
X/Y coordinates should be specified with respect to top cell.
<lvs_layer_name> refers to the LVS name of the conductor layer. Suitable LVS layer names can be identified by
examining the LVS deck or the "connect" lines in "lvsfile" which can be found in the Quantus technology directory, as
shown below:
connect metal2_conn metal1_conn by Via1
For example, if INVD1 is the top cell, then the probe text file may contain the following lines:
AAA 0.025 0.5760 metal1_conn
BBB 0.055 0.5760 metal1_conn
Following is a sample line in the Spice output:
Rk17
AAA
BBB
0.9375
$METAL_1
$W=6e-08
retain_def_metal_fill [ true | false ]
The option allows you to combine the metal fill specified in the DEF/OA design data, with the metal fill from a GDS file.
In this case, Quantus will consider the metal fill specified in both the DEF/OA and GDS inputs during capacitance
extraction.
The default of this option is false, which means that Quantus will ignore DEF/OA metal fill in the presence of GDS
metal fill.
run_name <string>
Specifies the Assura, Calibre, or Pegasus name assigned to the LVS run.
​technology_library_cell_map_file <file_name>
specifies the foundry provided iCellmap file that contains simulation model to DFII cell view mappings and transfer
property information. The iCellmap file replaces the need for both the extview.rul and extview.trp files.
If the technology_library_cell_map_file option is not specified, Quantus checks the technology directory for the file
named icellmap.yaml file. If the icellmap.yaml file is not present, then Quantus uses the
existing extview.rul and extview.trp files in the technology directory.
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Note: The technology_library_cell_map_file option is applicable in Assura, Pegasus-Quantus, and QCI extracted
view flows. For Pegasus-Quantus and QCI flows, it must be used along with the output_db cdl_out_map_directory CCL option. For Assura flow, the iCellmap file is only used for transfer property information. All
simulation model to DFII cellview mappings, and cellview pin names remain in the Assura LVS extract.rul file.
Therefore, for Assura flow, it is mandatory that the extract.rul is in sync with the contents of the iCellmap file.
top_cell < top_gds_cell >
This option enables you to identify the top cell from the GDS input file. If no top cell is specified, Quantus will
automatically detect the top cell from the input file. However, if you do specify top_cell < top_gds_cell >, and the
specified cell does not exist, Quantus will exit with an error.
type assura | pegasus | calibre | def | oa | metal_fill | gds | HPB
The type option indicates the nature of the input data provided to Quantus.
assura - Specify -type assura for designs that have been processed with Assura DRC/LVS (or just Assura LVS).
pegasus/pvs - Specify -type pegasus or pvs for designs that have been analyzed with Cadence's Pegasus.
Quantus supports both PVS and Pegasus LVS.
calibre - Specify -type calibre for design input from Mentor Graphics' Calibre® LVS tool.
def - Specify -type def to input LEF/DEF design data directly into Quantus. DEF type input data also requires the
use of the lef_file_list or lef_file_list_file or the libgen_library_name options to the input_db command.
Note: If a layer is used in the input DEF file, but is not defined in the technology file, a fatal error will occur and
Quantus will terminate execution. See Quantus Techgen Reference Manual for information on defining layers in
the technology file.
oa - Specify -type oa to input OpenAccess design data directly into Quantus. OA type input data also supports
the optional use of the library_cell_name option to the input_db command. Starting with the 11.1 release, you can
also specify a compressed OA database as an input to Quantus. For information on the OA input flow, refer to OA
Input.
metal_fill - Specify -type metal_fill to import GDS/OASIS data into Quantus to be used as metal fill data for a
DEF type design input with the input_db -type def command.
​ gds - New in the 11.1 release, specify -type gds to input GDS file(s) containing RDL layers, with net names
placed as text.
This option enables the processing of RDL layers input from a GDS file. RDL-GDS input is treated as an
extension of the DEF routing and both R and C are extracted on parasitic layers.
The input_db -type gds option is used along with input_db -type def, which provides the regular DEF input
information, and the GDS input enhances it with the RDL data from GDS.
The following are the input restrictions for GDS input:
The GDS file must be fully annotated.
GDS layer map must be provided for all layers (even text layers).
RDL layers from GDS files must connect to the DEF file through either TOP PINS or COMPONENT
INSTANCE PINS.
Note: The input_db -type gds CCL option requires an XL license and an Advanced Analysis (AA)
GXL option in Quantus.
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The input_db command can only be specified once to define the input database for an extraction run. However, if
the original input_db is DEF, then additional input_db command can be used to specify an RDL GDS file (which
is an extension of DEF routing), as well as a GDS/OASIS file containing metal_fill shapes. The input_db -type
metal_fill command used by itself is not sufficient to describe a design for Quantus extraction. This command
works in conjunction with the metal_fill command (see metal_fill ) .
HPB - Specify to import GDS/OASIS data with HPB marker layers.
unified_db_gds_file <filename>
Specifies the GDSII/OASIS filename containing the metal fill data to be input when hierarchical metal fill DB is loaded.
This option is required when input_db -type metal_fill is specified.
Hierarchical Metal Fill Database Flow
The Hierarchical Fill Database Flow (HMF) provides unified metal fill database across Innovus, Pegasus, and Quantus. It
includes the following features:
For HMF flow details regarding Innovus and Pegasus, refer to the Innovus and Pegasus user manuals.
Note the following:
With HMF flow, you require either signoff mode Quantus in Innovus or standalone Quantus.
This metal fill database is supported only by Cadence tools.
In Innovus, for each design, signoff metal fill is generated by Pegasus and saved in Innovus database with a fixed name
(***.enc.dat/pvs_fill.data). To use this data, you need to specify -stream_layer_map based on Pegasus GDS layer map.
The following use models are available:
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Use Model 1: Running signoff Quantus inside Innovus
Innovus automatically generates Quantus command file and includes the required CCL options in the flow. You only need to
specify -stream_layer_map.
For details, see Innovus User Guide.
Use Model 2: Running standalone Quantus outside Innovus
Case 1: Extracting single DEF with HMF database
In the input_db -type metel_fill section, use -unified_db_gds_file option to specify the HMF database stored in the
Innovus database.
Sample CCL options:
extraction_setup \
….
-stream_layer_map_file ./stream.map
input_db -type
metal_fill \
-unified_db_gds_file
……/DBS/TOP.enc.dat/pvs_fill.data
Case 2: Extracting multiple DEF files with corresponding HMF database
In the input_db -type metal_fill, use -unified_db_gds_file to specify the top-level HMF database.
In the input_db -type def, use -unified_db_gds_file_list (or -unified_db_gds_file_list_file) to specify block-level
HMF databases.
Sample CCL options:
extraction_setup \
….
-stream_layer_map_file ./stream.map
input_db -type def \
-def_file_list_file ./deflist.txt \
-unified_db_gds_file_list
\
../../HIER/DBS/BLOCK_A.enc.dat/pvs_fill.data \
# block level HMF database
../../HIER/DBS/BLOCK_B.enc.dat/pvs_fill.data \
../../HIER/DBS/BLOCK_C.enc.dat/pvs_fill.data
input_db -type metal_fill \
-unified_db_gds_file
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layer_blocking
Command Syntax
Input Restrictions
layer_blocking
-block_assignable_partial_virtual_ground_plane <layer1> <layer2> …
ALL
-block_assignable_virtual_ground_plane <layer1> <layer2> ...
ALL
-block_substrate <layer1> <layer2> ...
DEF/OA
Description
This command blocks coupling capacitances between the specified ICT layer pairs. The <layer1> <layer2> … are ICT file
layers and not DEF/OA or LVS layers. The three CCL options have the following general format:
-block_<virtual_layer> <layer1> <layer2> …
This means the coupling capacitances between the following ICT file layer pairs are to be blocked:
<virtual_layer> <layer1>
<virtual_layer> <layer2
The <virtual_layer> does not exist either in the DEF/OA input or in the LVS DB for the Quantus cell and transistor flows,
respectively.
The assignable_virtual_ground_plane, and assignable_partial_virtual_ground_plane are defined in the ICT file as
attributes to the process object. They do not exist either in the DEF/OA input or in the LVS DB.
The shape, which is a list of rectangles, of the ICT file, assignable_partial_virtual_ground_plane is defined by the
following CCL:
extraction_setup \
-assignable_partial_virtual_ground_plane
Note: The assignable_virtual_ground_plane and assignable_partial_virtual_ground_plane options are supported in both
cell-and transistor-level flows. The block_substrate option is supported by Quantus (DEF/OA) but ignored by Quantus (LVS).
Options
block_assignable_partial_virtual_ground_plane <layer1> <layer2> …
This option is used to block the capacitance of the specified conductor layers to the partial virtual ground plane. This
option can be used to reduce the total capacitance of the conductor layers in the 3D IC extraction flow. A virtual ground
plane is the second ground plane that is at the top of the layer stack. The second ground plane is not an ICT file object,
instead it is a special property in the process object.
block_assignable_virtual_virtual_ground_plane <layer1> <layer2> …
This option is used to block the capacitance of the specified conductor layers to the virtual ground plane. This option
can be used to reduce the total capacitance of the conductor layers in the 3D IC extraction flow.
Assignable Virtual Ground Plane Blocking Illustration
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In the below illustration, the value of coupling capacitance, C6 and C7 is reduced due to the presence of the
assignable_virtual_ground_plane (G2), when the -virtual_ground_net CCL is set. Optionally, the C7’ and C6’ may
be discarded from Quantus output by the CCL option, -block_assignable_virtual_ground_plane statement. If the CCL
option is missing, C7’ and C6’ are lumped to the ground plane (G1).
For the assignable_virtual_ground_plane, and if CCL -block_assignable_virtual_ground_plane is present, the C7’
and C6’ are discarded. Otherwise, the C7’ and C6’ go to G2.
For the above example, the blocking behavior differences in the presence and absence of CCL capacitance command
option, -virtual_ground_net is illustrated in the table below.
layers M6, M7 are in -
virtual_ground_net
Missing
virtual_ground_net
Present
C6’, C7’ are discarded
C6’, C7’ are discarded
C6’, C7’ are lumped to
G1
C6’, C7’ go to G2
block_assignable_virtual_ground_plane
layers M6, M7 are not in block_assignable_virtual_ground_plane
block_substrate <layer1> <layer2> ...
This option is used to block the capacitance of the specified conductor layers to the substrate. This option can be used
to reduce the total capacitance of the conductor layers in the 3D IC extraction flow. The syntax is as follows:
-block_substrate <layer1> <layer2> ...
The block_substrate option is supported by Quantus (DEF/OA) but ignored by Quantus (LVS). This is because Quantus
(LVS) has its own Techgen blocking command, -blocking. If specified for the Quantus (DEF/OA) flow, the software will
give issue the following warning:
Warning: CCL layer_blocking -block_substrate <layer> is ignored. Make sure there is a corresponding
Techgen -blocking command.
An example Techgen blocking command that corresponds to the -block_substrate CCL is shown below.
-blocking UBMS:0.001,FOX
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log_file
Command Syntax
Input Restrictions
log_file
-abort_upon_missing_macro [ true | false ]
DEF/OA
-debug_log [ true | false ]
ALL
-dump_options [ true | false ]
ALL
-file_name < filename >
ALL
-lenient_error_reporting [ true | false ]
ALL
-max_error_messages < number >
DEF/OA
Default Value: 100
DEF/OA
-max_warning_messages < number >
Default Value: 10
-report_outside_diearea_object [ true | false ]
DEF/OA
-report_outside_diearea_object_error_limit value
DEF/OA
Default Value: 1
ALL
-strict_error_reporting [ true | false ]
Description
This command allows you to specify details of the log file, such as the file name and location, the information that will be
written to the log file.
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Options
abort_upon_missing_macro [ true | false ]
The abort_upon_missing_macro option aborts Quantus with an error if there are macro (s) that are referenced in DEF (s)
but are not defined in LEF (s). The default is false.
debug_log [ true | false ]
The debug_log option enables printing of the peak memory consumed. In addition to the peak memory consumption, the
option also prints information related to the host machine. The -debug_log option is supported in both the single
processing and distributed processing (DP) modes. In the DP mode, the option is supported in the multi-CPU mode, but
not supported in the multi-machine and LSF modes.
In the multi-CPU mode, there are many concurrent processes running at the same time. The memory consumption of
these processes are monitored at a fixed interval. For a given interval, the memory consumption of each process is
obtained and summed. The peak memory is the largest memory consumption of all intervals.
dump_options [ true | false ]
​ The dump_options option saves the current Quantus CCL file contents in the log file. It also prints them to the standard
output. The option works for both the cell-level and transistor-level flows.
file_name <filename>
The file_name option specifies the name of the log file generated by Quantus. The default log file name is qrc.log
written to the current working directory. The qrc.log file will be overwritten for each subsequent run of Quantus. To
avoid overwriting the log file with each run, you must specify the log_file -file_name command to redirect the log file
output to a different file for each run.
lenient_error_reporting [ true | false ]
In the transistor-level flow, when the -lenient_error_reporting option is set to true, the LVS DB and ictfile consistency
error checking is turned off. By default, this option is set to false.
max_error_messages <number>
​ ​ ​ The max_error_messages option sets the maximum number of non-fatal error messages issued by Quantus during a
session. When this limit is reached, the extraction run continues, but no additional errors will be reported.
The number specified must be an integer in the range of 1 through 2,147,483,647 inclusive. The default is 100.
max_warning_messages <number>
The max_warning_messages option sets the maximum number of warning messages issued by Quantus during a
session. When this limit is reached, the extraction run continues, but no additional warnings will be reported.
The number specified must be an integer in the range of 1 through 2,147,483,647 inclusive. The default is 10.
report_outside_diearea_object [ true | false ]
Controls reporting and error handling when the DEF, LEF, or GDS shapes are partially or fully outside the die
area. When this option is set to true and the -strict_error_reporting option is also set to true, Quantus exits with an
error message if shapes for either DEF, LEF, or GDS are outside the die area. The default is false. The extension of
the report file is .outside_die. This file will be saved in the output directory where the SPEF/DSPF file is saved.
report_outside_diearea_object_error_limit value
Controls the maximum number of error messages issued per DEF/LEF/GDS layer. By default, the error message limit
is 1. You can specify a maximum value to 10000000 error messages per layer. When this limit is reached, the extraction
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run continues, but no additional errors will be reported. This option must be specified with the report_outside_diearea_object option.
strict_error_reporting [ true | false ]
In the cell-level flow, the strict_error_reporting option exits Quantus with an error if it detects one of the following
conditions:
conflicting layer definitions for the same layer, which is found in multiple technology LEF files
GDSII/OASIS fill shapes are outside the die area of DEF
non-default rule definition is missing in DEF
In the transistor-level flow, the strict_error_reporting option exits Quantus with an error if it detects the following
condition:
device layer (seed) promotion is detected in the LVS output database for the Calibre flow
The default is false. If this option is set to true, Quantus exits with an error for the specified conditions. Alternatively, if
set to false, Quantus gives a warning message and the extraction run continues. This option allows you to control the
Quantus error handling for these conditions as per your requirements.
metal_fill
Command Syntax
Input Restrictions
metal_fill
metal_fill -type grounded | virtual applies to ALL
inputs. The floating | none type applies to DEF or OA
inputs only.
-enable_advanced_virtual_fill
[true | false]
-type [floating | grounded |
virtual | none]
-vmf_metal_scheme_file
<metal_scheme_file_name>
-vmf_rule_file <param_file_name>
Description
Metal fill data can be imported into the design with the input_db command either through DEF or GDS file input (see input_db
). Metal fill that is defined in the FILLS section of the input DEF file or in an input GDS file will be considered floating by default
unless otherwise specified by this command.​ ​ ​ The metal_fill command indicates how Quantus should account for the
impact of fill metal on the parasitic capacitance extraction. Metal fill can be grounded, which has a fixed potential, or floating,
which has a fixed electrical charge. Typically, grounded metal has a higher capacitance. Quantus will issue a warning if
metal_fill -type floating or -type grounded is enabled when the input design does not contain metal fill.
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Note: Metal fill can also be specified in the SPECIALNETS section of the DEF input data, with the +SHAPE FILLWIRE construct.
This type of fill metal is always considered grounded, and is not affected by the metal_fill command.You can also model
virtual fill metal, which doesn't actually exist in the design. This is done by adding metal_fill specifications to the technology
file for Quantus to use in modeling virtual metal fill during extraction. Refer to Quantus Techgen Reference Manual for
information on defining virtual metal fill for conductor layers.
Options
enable_advanced_virtual_fill true
Enables Integrated Virtual Metal fill feature. Default value is "false". The XL+AA license is needed when –
enable_advanced_virtual_fill is true.
type [ floating | grounded | virtual | none ]
floating - When you set the type option to floating, Quantus models the metal fill as floating and evaluates the
metal fill objects properly during extraction. Floating metal fill are those pieces that are not connected to electrical
nets of the design, and contribute less to the overall net capacitance but can increase the magnitude of coupled
capacitance to other nets. The default is floating. This option can be used only for the DEF or OA inputs.
grounded - When you set this option to grounded, Quantus models the metal fill shapes as grounded. Grounded
metal fill act as gray data, this allows Quantus to evaluate the metal fill objects without the need of any special
models. The metal_fill -type grounded option and the filter_cap -exclude_floating_nets true option are
mutually exclusive.
The grounded option can be used for both the DEF/OA and LVS inputs in the Quantus and Quantus FS flows. The
LVS layers that are not mapped in the layer_setup file will not be grounded.
If there are floating nets in the substrate layer, you can ground them using the ground_substrate_floating_nets true option in the transistor-level flow. For more information, refer to
ground_substrate_floating_nets.
none - specifies no metal_fill. This option disables any metal fill explicitly defined in the input data. This option
can be used only for the DEF or OA inputs.
virtual - Virtual metal fill is to be used in a design flow where metal fill is added to the design after parasitic
extractions are done (or after timing closures are achieved). In other words, the metal fill patterns are not present in
the layout at the time of extraction, so a virtual fill pattern is used to extract parasitics associated with future fill
metal. Virtual metal fill is considered floating by default.
Quantus Transistor-level Flow
In the transistor-level flow, metal_fill -type virtual creates all necessary fill patterns from the specification
defined in the technology file (see Quantus Techgen Reference Manual ). This is very accurate but increases the
extraction run time as fill metal shapes must be added to the design before capacitance extraction can occur, and
these shapes must be removed after capacitance extraction.
When metal_fill -type virtual is specified, Quantus automatically executes the filter_cap exclude_floating_nets command to eliminate the added virtual metal shapes after extraction (see filter_cap), and
the value of -exclude_floating_nets_limit is internally set to 2000. This occurs even though the exclude_floating_nets command may be expressly disabled in the command file.
Quantus Cell-level Flow
The Quantus cell-level flow supports Integrated Virtual Metal Fill (IVMF) that includes advanced modeling for the
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10nm and below color designs. To use IVMF, you need to use following CCL options:
metal_fill -type virtual \
-enable_advanced_virtual_fill true \
-vmf_metal_scheme_file
<metal_scheme_file_name> \
-vmf_rule_file
<param_file_name>
IVMF rule files include the metal scheme file and the parameter file that are required by IVMF. They can be
specified by the -vmf_metal_scheme_file and -vmf_rule_file options.
A block design may have upper PG layers that may be empty and are reserved for upper-level
power/ground/signal routing. The IVMF feature can be used to mimic the upper-level routing during block-level
extraction, and to improve extraction result accuracy by including the PG impact from upper-level routing with
IVMF for accurate block-level extraction. IVMF can be applied to an empty layer if the IVMF rule is defined for that
layer in the metal_fill -vmf_rule_file and -vmf_metal_scheme_file files.
In the IVMF rule table (-vmf_rule_file) for the empty upper PG layers, you need to specify the following:
L with a large value (for example, 100um)
W with real PG nets' width
net-fill spacing with a minimum value
fill-fill end-to-end spacing with a value set to 0 to ensure that long PG shapes are estimated correctly
fill-fill edge-to-edge spacing with real PG nets spacing
If an empty layer is covered by a pushdown blockage, you can exclude the blockage by using the
extraction_setup -ignore_pushdown_blockages true. In that case, IVMF is applied to the empty layer, and
accurate RC impact from the empty layer is reflected in the extraction results.
Note: If virtual metal is specified, any actual metal fill defined in the DEF or OA input will be ignored. This does
not affect metal fill defined as SPECIALNETS, and does not affect metal fill in LVS input (Assura, Calibre, or
Pegasus).
Added virtual metal should have little or no effect on width and spacing dependant bias or resistance extraction
because the shapes are spaced far away from conductors relative to the distances that are considered in bias
calculations.
vmf_metal_scheme_file metal_scheme_file_name
Specifies the metal scheme file. This file defines the mapping between layer name and layer type. The format of the file
is:
Layer: metal layer name in ICT file
Type: layer type (1, x, y, z, …)
Dir: routing direction
By default, Quantus will read the routing direction in the LEF as the default direction for integrated virtual metal fill
(IVMF). If both the LEF and metal scheme file are specified, the routing direction in the metal scheme file takes
precedence.
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Example of Metal Scheme File:
vmf_rule_file param_file_name
Specifies the param file. This file defines the VMF rules (size, x/y fill-fill spacing and net-fill spacing) per metal type
defined in scheme file. The format of the file is:
Type: layer type defined in scheme file
L: VMF length
W: VMF width
nf_sp: minimum net-fill spacing
ff_sl: fill-fill spacing along with length
ff_sw: fill-fill spacing along with width
The IVMF rule table is in design drawn dimension.
Example of param file:
For Quantus, XL+AA license is needed when –enable_advanced_virtual_fill is true. For IQuantus, when Innovus
IVMF is turned on, XL+AA license is needed. Similarly, for TQuantus, when Innovus IVMF is turned on, and external
VMF rule files are used, XL+AA license is needed.
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mos_diffusion_parameter_extraction
Command Syntax
Input Restrictions
mos_diffusion_parameter_extraction
LVS
-add_lvs_extracted_res [true | false]
LVS
-auto_accuracy_downgrade [true | false]
LVS
-res [ fast | moderate | accurate ]
LVS
Description
The mos_diffusion_parameter_extraction command will extract the resistance properties from the source and drain
diffusion areas of MOS and LDD devices.
Options
add_lvs_extracted_res [ true | false ]
In the Assura to Quantus flow, this option adds the NRD/NRS values (calculated by Quantus) to the corresponding
values passed on by Assura LVS to Quantus. By default, the NRD/NRS values computed by Assura LVS file are
replaced with the values calculated by the Quantus software.
Note: The NRD/NRS values are added regardless of their casing. This means that if the NRD/NRS values in the
Assura LVS file are specified in lower case and the Quantus calculated values are in upper case, the values will still be
added and displayed in the output netlist in upper case.
When you set this option to true, the NRD/NRS values are determined by adding the values calculated by Assura LVS
with the values calculated by the Quantus software. For example, consider that for a MOSFET the LVS NRD value is 0.02,
and the Quantus calculated NRD value is 0.03. In this case, the actual NRD value will sum up to 0.05. The default
behavior (false) will be to replace the NRD/NRS values from Assura LVS with the values calculated by the Quantus
software.
If the NRD/NRS values are not available (for some MOSFET devices), they are assumed to be 0 and as a result the
Quantus calculated values are used. The Quantus calculated NRD/NRS values are restricted to the
Quantus MOSFET LDD devices. Quantus does not calculate NRD/NRS for generic devices.
Note: This option is applicable only if you are using the following setting:
mos_diffusion_parameter_extraction -res { fast | moderate | accurate }
When you use this option and the mfactor feature is enabled, the Quantus software uses the following formula for
merging two parallel MOSFET devices:
NRD = 1 / (1/(NRD1_quantus+NRD1_lvs) + 1/(NRD2_quantus+NRD2_lvs)
Where:
NRD1_quantus is the NRD value of the first MOSFET
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NRD2_quantus is the NRD value of the second MOSFET
NRD1_lvs is the NRD value of the first MOSFET imported from Assura LVS
NRD2_lvs is the NRD value of the second MOSFET imported from Assura LVS
auto_accuracy_downgrade [ true | false ]
This option automatically downgrades the resistance field solver accuracy modes, specified with
the mos_diffusion_parameter_extraction -res option, to compute diffusion resistance. When auto_accuracy_downgrade is set to true, Quantus internally estimates the memory usage and downgrades accuracy
from “accurate” to “moderate”, or from “moderate” to “fast” on a case by case basis. It is possible that no accuracy
downgrade is needed if all the diffusion regions are small. The default value of this option is true.
This option is supported by the input formats Assura, Pegasus, and Calibre, and the output formats SPICE, EV, xDSPF,
and xSPEF.
res [fast | moderate | accurate]
Quantus extracts resistors for MOS and LDD source and drain regions. They are represented in the SPICE output netlist
as NRS and NRD model properties, respectively. The NRS and NRD properties are measured from the gate edge to
the metal diffusion contact edge. NRD and NRS properties are output as nrd and nrs by default.
Note: Quantus will not overwrite NRS/NRD parameters imported from Assura LVS. You must eliminate the parameters
from the LVS input if you want Quantus to calculate them.
fast - Uses standard extraction algorithm to extract source and drain resistors. This results in the fastest
performance, but may sacrifice some accuracy.
moderate - This option causes Quantus to extract resistors for MOSFET and LDD source and drain regions using
a 2D Laplace equation solver to accurately calculate the values. The Laplace solver can be executed specifying
two different levels of accuracy versus performance (moderate or accurate).
accurate - Increases the accuracy of the res option to its highest level, but also dramatically increases extraction
run time.
By default, Quantus extracts the gate resistance for all MOS and LDD devices. However, specific devices can be listed
for extraction by using the Techgen compilation option extract_mos_diffusion_res_by_device. Refer to Quantus
Techgen Reference Manual for more information.
Starting with the 15.11 release, the precision of device parameters from Quantus output as compared to the
corresponding LVS is within 0.1%, by default. That is, the default setting of the QRC_MOS_LW_PRECISION environment
variable is: QRC_MOS_LW_PRECISION =Y
This default behavior improves precision and provides better alignment between the extraction data and the LVS data
provided as input. This is applicable for all output formats. However, scenarios where the L and/or W values are very
large (W=100000 ), Quantus may report incorrect L and/or W values in the output netlist. Hence for all such scenarios,
you need to turn off the default behavior by using the “QRC_MOS_LW_PRECISION =N” environment variable.
The following changes would be observed in the printing of a MOSFET device:
Printing when QRC_MOS_LW_PRECISION =N:
XM0 source gate VSS 4 nch_18_mac L=0.1351U
+ AD=0.03214P AS=0.03214P PD=0.72208U PS=0.72208U
Printing when QRC_MOS_LW_PRECISION =Y:
XM0 source gate VSS 4 nch_18_mac L=1.35060e-07
+ AD=3.21396e-14 AS=3.21396e-14 PD=7.22082e-07 PS=7.22082e-07
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When diffusion is modeled as a conductor in the ICT file, all the LVS layers mapping to the ICT file diffusion layer are shorted
during NRD/NRS calculation triggered by CCL mos_diffusion_parameter_extraction -res. However, if you separate the
diffusion LVS layers of MOS devices into device and tap diffusion in the LVS deck, only the device diffusion is shorted. This
prevents shorting of the tap diffusion layers.
The mos_diffusion_parameter_extraction -res CCL option is not supported for the advanced node FinFET
structures. In the FinFET process, NRD/NRS cannot be defined and calculated.
The following is a snippet of the extraction rule file or lvsfile:
element generic[NMOS4_av3] NMOSW_4N_device_Device_17 net_poly1[G] net_nsd[S] net_nsd[D] NMOSW_4N_bulk[B]
The following is a snippet of the layer_setup file:
pro_layer=pdiff
ext_layer=net_welltap,net_nsd,net_subtap,net_psd
In this example, the LVS layer net_nsd will be shorted because it is used in the device line in the lvsfile. However, the
net_subtap LVS layer is not used in any device line, therefore, it is not shorted and it will assume the resistance model in the
ICT file.
output_db
Description
The output commands are grouped by the different output format types including: DSPF, SPEF, SPICE, OA database,
capacitance reports, unconnected pins' file.
output_db
-type [ dspf | spef | spice | extracted_view | lvs_extracted_view
| oa | coupling_cap_reports | promoted_feedthru | unconnected_pins | rcdb | shape_db]
The following tables defined the output_db command syntax for the -type indicated:
output_db -type dspf
Command Syntax
Input
Restrictions
output_db -type dspf
-add_bulk_terminal [ true | false]
LVS
-add_cap_prefix [ true | false ]
All
-add_explicit_vias [ true | false ]
All
-busbit_delimiter <string>
ALL
-cdl_out_map_directory <directory>
LVS
-comment_top_subckt [true | false]
LVS
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-compressed [ true | false]
ALL
-delete_x [true | false]
LVS
-device_finger_delimiter <string>
Default Delimiter:@
LVS
-disable_instances [ true | false ]
ALL
-disable_subnodes [ true | false ]
ALL
-em_extract [ true | false ]
LVS
-escape_special_character [ true | false ]
DEF/OA
–force_subcell_pin_orders [true | false]
LVS
-header_file <file>
LVS
-hierarchy_delimiter <string>
Default Delimiter: forward slash (`/')
DEF/LEF,
LVS
-include_cap_model [ true | false | comment]
LVS
-include_parasitic_cap_model [ true | false |
comment ]
LVS
-include_parasitic_res_color [ true | false ]
LVS, DEF/OA
-include_parasitic_res_conductor_bounding_box
[edge | center | multiple | false]
LVS
-include_parasitic_res_length [ true | false ]
LVS
-include_parasitic_res_model [ true | false |
comment]
LVS
-include_parasitic_res_model_by_sub_conductor [
true | false ]
LVS
-include_parasitic_res_parameters_unscaled [
true | false ]
LVS, DEF/OA
-include_parasitic_res_temp_coeff [ true |
false | comment ]
ALL
include_parasitic_res_via_bounding_box_by_layer
“all”|”<via1>” … “<viaN>”
LVS
[-include_parasitic_res_width [ true | false] |
LVS
-include_parasitic_res_width_drawn [ true |
false]]
-include_res_model [ true | false | comment]
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-map_eeq_to_master [ true | false ]
DEF/OA
-match_res_cap [ true | false]
DEF/OA
-netlist_coupling_values [ double | single |
separate ]
LVS
-output_density_tiles [ true | false ]
DEF/OA
-output_incomplete_nets [ true | false ]
DEF/OA
-output_incomplete_nets_type <incomplete net
types>
DEF/OA
-output_multi_value_rc [ true | false ]
-output_multi_value_rc [ true | false ]
DEF/OA
LVS
-output_unrouted_nets [ true | false ]
DEF/OA
-output_used_gray_cells [true | false]
DEF/OA
-output_xy [canonical_cap parasitic_cap
canonical_res parasitic_res diode mos bipolar
generic]
LVS
-parameter_name [width <string> | length
<string> |
area <string> | layer <string>]
DEF/OA
-pin_delimiter <string>
Default Delimiter: colon (:)
DEF/OA
-pin_cap_file <file>
LVS
-pin_order_file <file>
ALL
-postprocess_output_netlist <string>
ALL
-preserve_generic_mos_parameter_case [true |
false]
LVS
-probe_lvs_nets [ true | false ]
LVS
-promote_incomplete_net_pins [ true | false]
DEF/OA
-reduce_i_cards [true | false ]
LVS
-short_incomplete_net_pins [ true | false ]
All
-short_incomplete_net_pins_exclusion <filename>
LVS
-short_incomplete_nets <filename>
LVS
-short_incomplete_nets_exclusion <filename>
LVS
-short_incomplete_net_pins_conservative [ true
| false ]
LVS
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-sub_node_char <string>
LVS
-subtype [standard | extended | compatible]
ALL
-subtype compact
LVS
(Pegasus
and
Calibre)
-suppress_empty_subckts [ true | false ]
LVS
-units [micron | angstrom ]
DEF
-user_comment text
DEF/OA
1
The short_incomplete_net_pins and promote_incomplete_net_pins options are applicable only for DSPF/SPEF
outputs.
output_db -type spef
Command Syntax
Input
Restrictions
output_db -type spef
-add_bulk_terminal [ true | false ]
LVS
-add_explicit_vias [ true | false ]
All
-busbit_delimiter < string >
ALL
-cdl_out_map_directory < directory >
LVS
-comment_top_subckt [true | false]
LVS
-compressed [ true | false ]
ALL
-delete_x [true|false]
LVS
-device_finger_delimiter < string >
Default Delimiter: @
LVS
-disable_instances [ true | false ]
ALL
-disable_subnodes [ true | false ]
ALL
-em_extract [ true | false ]
LVS
-escape_special_character [ true | false ]
DEF/OA
–force_subcell_pin_orders [true | false]
LVS
-header_file < file >
LVS
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-hierarchy_delimiter < string >
Default Delimiter: forward slash (`/')
DEF/OA
-include_cap_model [ true | false
| comment ]
LVS
-include_parasitic_cap_model [ true | false
| comment ]
LVS
-include_parasitic_res_color [ true
| false ]
LVS, DEF/OA
-include_parasitic_res_length [ true
| false ]
LVS
-include_parasitic_res_model [ true | false
| comment ]
LVS
include_parasitic_res_model_by_sub_conductor
[ true | false ]
LVS
-include_parasitic_res_parameters_unscaled [
true | false ]
LVS, DEF/OA
[-include_parasitic_res_width [ true
| false ] |
LVS
-include_parasitic_res_width_drawn [ true
| false ]]
-include_res_model [ true | false
| comment ]
LVS
-map_eeq_to_master [ true | false ]
DEF/OA
-match_res_cap [ true | false ]
DEF/OA
-name_map_start_index < value >
DEF/OA
-output_density_tiles [ true | false ]
DEF/OA
-output_incomplete_nets [ true | false ]
DEF/OA
-output_incomplete_nets_type <incomplete net
types>
DEF/OA
-output_multi_value_rc [ true | false ]
-output_multi_value_rc [ true | false ]
DEF/OA
LVS
-output_triplet_rc [true | false]
DEF/OA
-output_unrouted_nets [ true | false ]
DEF/OA
-output_used_gray_cells [true | false]
DEF/OA
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-output_xy [ canonical_cap parasitic_cap
canonical_res parasitic_res
diode mos bipolar generic ]
LVS
-parameter_name [ width <string> | length
<string> |
area <string> | layer <string> ]
DEF/OA
-pin_cap_file < file >
LVS
-pin_delimiter < string >
Default Delimiter: colon (:)
DEF/OA
-pin_order_file < file >
LVS
-predefined_spef_cells_file < file >
DEF/OA
-preserve_generic_mos_parameter_case [true
| false]
LVS
-promote_incomplete_net_pins [ true
| false ]
DEF/OA
-reduce_i_cards [true | false ]
LVS
-short_incomplete_nets <filename>
LVS
-short_incomplete_nets_exclusion <filename>
LVS
-short_incomplete_net_pins [ true | false ]
All
-short_incomplete_net_pins_conservative [
true | false ]
LVS
-short_incomplete_net_pins_exclusion
<filename>
LVS
-sub_node_char < string >
LVS
-subtype [ standard | starN | extended |
compatible ]
DEF/OA
-subtype compact
LVS
(Pegasus
and
Calibre)
-suppress_empty_subckts [ true | false ]
LVS
-units < unit_string >
Default Unit: micron
ALL
-use_name_map [ true | false ]
ALL
-user_comment text
DEF/OA
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user_defined_file_name file_name1 file_name2
...
DEF/OA
output_db -type spice
Command Syntax
Input
Restrictions
output_db -type [ spice ]
Spice output
is restricted
to LVS input
only.
-add_explicit_vias [ true | false ]
-cdl_out_map_directory <directory>
-comment_top_subckt [true | false]
-compressed [ true | false ]
-device_finger_delimiter <string>
Default Delimiter: @
-em_extract [ true | false ]
–force_subcell_pin_orders [true | false]
-header_file <file>
-hierarchy_delimiter <string>
Default Delimiter: forward slash (`/')
-include_cap_model [ true | false
| comment ]
-include_parasitic_cap_model [ true | false
| comment ]
-include_parasitic_res_color [ true
| false ]
-include_parasitic_res_length [ true
| false ]
-include_parasitic_res_model [ true | false
| comment ]
include_parasitic_res_model_by_sub_conductor
[ true | false ]
-include_parasitic_res_parameters_unscaled [
true | false ]
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-include_parasitic_res_temp_coeff [ true
| false | comment ]
[ -include_parasitic_res_width [ true
| false ] |
-include_parasitic_res_width_drawn [ true
| false ]]
-include_res_model [ true | false
| comment ]
-output_self_looped_diodes [ true | false ]
-output_triplet_rc [true | false]
-output_xy [ canonical_cap parasitic_cap
canonical_res parasitic_res
diode mos bipolar generic ]
-pin_order_file [ < file > | < file +> ]
-postprocess_output_netlist <string>
-preserve_generic_mos_parameter_case [true
| false]
-sub_node_char < string >
-suppress_empty_subckts [ true | false ]
output_db -type extracted_view
Command Syntax
Input
Restrictions
output_db -type [ extracted_view |
lvs_extracted_view ]
The DFII
Extracted
View output
is restricted
to LVS input
only.
-add_explicit_vias [ true | false ]
-black_box_cell_view
<view_name>
-black_box_cell_view_file <file_name>
-cap_component < string +>
-cap_property_name < string >
-ccvs_hgain_property_name < string >
-ccvs_model_name < string >
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-ccvs_vref_property_name < string >
-cdl_out_map_directory < directory >
-em_extract [ true | false ]
-enable_cellview_check [ true | false ]
-force_subcell_pin_orders [true | false]
-hierarchical_extracted_views_directory
< string >
-hierarchical_extracted_views_prefix
< string >
-include_cap_model [ true | false
| comment ]
-ind_component < string +>
-ind_property_name < string >
-ind1_property_name < string >
-ind2_property_name < string >
-include_parasitic_cap_model [ true | false
| comment ]
-include_parasitic_res_color [ true
| false ]
-include_parasitic_res_length [ true
| false ]
-include_parasitic_res_model [ true | false
| comment ]
include_parasitic_res_model_by_sub_conductor
[ true | false ]
-include_parasitic_res_parameters_unscaled [
true | false ]
-include_parasitic_res_temp_coeff [ true
| false | comment ]
[ -include_parasitic_res_width [ true
| false ] |
-include_parasitic_res_width_drawn [ true
| false ]]
-include_res_model [ true | false
| comment ]
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-m_factor_property_name < string >
-mutual_ind_component < string +>
-mutual_ind_property_name < string >
-pin_order_file < file >
-postprocess_extracted_view < string >
-preserve_generic_mos_parameter_case [true
| false]
#New in Quantus 20.1
-replace_square_busbit_delimiter [ true
| false ]
-res_component < string +>
-res_property_name < string >
-save_fill_shapes [ true | false ]
-sub_node_char < string >
-transfer_net_expression [true | false]
-view_name < string >
-vs_model_name < string >
-vs_property_name < string >
output_db -type smart_view
Command Syntax
Input
Restrictions
output_db -type smart_view
The Smart
View output
is restricted
to LVS input
only.
-add_explicit_vias [ true | false ]
-cdl_out_map_directory < directory >
-include_parasitic_res_length [ true
| false]
include_parasitic_res_model_by_sub_conductor
[ true | false ]
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-include_parasitic_res_temp_coeff [ true
| false | comment]
[-include_parasitic_res_width [ true
| false ] |
-include_parasitic_res_width_drawn [ true
| false]]
-output_xy [ canonical_cap | parasitic_cap |
canonical_res | parasitic_res | diode | mos
| bipolar | generic ]
-pin_order_file < file >
-reduce_i_cards [ true | false ]
-short_incomplete_nets <filename>
-short_incomplete_nets_exclusion <filename>
-short_incomplete_net_pins [true | false]
-short_incomplete_net_pins_conservative [
true | false ]
-short_incomplete_net_pins_exclusion
<filename>
-subtype extended
-view_name < string >
Table: OA and Various Reports
Command Syntax
Input
Restrictions
output_db -type oa
-output_name <name>
OA output is
restricted to
OA input.
output_db -type
coupling_cap_reports
LVS
-cc_report_size <num>
-cc_report_order [ absolute |
relative ]
output_db -type
coupling_cap_reports
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output_db -type promoted_feedthru
output_db -type unconnected_pins
The output
reports are
only available
for DEF or OA
input.
output_db -type rcdb
Command Syntax
Input
Restrictions
output_db -type rcdb
rcdb output is
restricted to
DEF/OA input
-add_explicit_vias [ true | false ]
-disable_subnodes [ true | false ]
-output_density_tiles [ true |
false ]
-output_incomplete_nets [ true |
false ]
-output_incomplete_nets_type
<incomplete net types>
-output_unrouted_nets [ true |
false ]
–promote_incomplete_net_pins [ true
| false ]
–short_incomplete_net_pins [ true |
false ]
-user_comment text
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Options
add_bulk_terminal [ true | false ]
By default, Quantus does not create the instance:terminal names for backgates of standard devices in the
xDSPF/xSPEF netlist. The add_bulk_terminal option specifies that the instance:terminal names should be created
for backgate terminals that have an explicit connection to the R network.
For MOS or LDD devices, the bulk terminal is named `:b' to differentiate it from the source (:s), drain (:d), and gate (:g)
pins of the device. The add_bulk_terminal option will also apply to other devices as well (Resistor, Capacitor, Diode,
BJT...). However, in BJT devices, the bulk terminal will be named `:s' to avoid confusion, since the BJT device already
has a base terminal (:b). Starting with the EXT 10.1 release, the bulk terminal name for canonical resistors, capacitors,
and diodes is the actual pin name.
This add_bulk_terminal option is supported for flat or hierarchical extraction of transistor-level DSPF or SPEF output
only (XDSPF/XSPEF), that is when output_db -type dspf | spef is set, and there is no .dcl file present to indicate
cell-level extraction.
Note: The add_bulk_terminal option has no effect when Power and Ground nets are excluded from extraction when
the global_nets -import_from_lvs, -nets, or -nets_file commands are specified.
add_cap_prefix [ true | false ]
​ ​ This option adds a special reference designator prefix on parasitic capacitors in the output DSPF. When you set this
option to true, Quantus will add *Cg for ground capacitors and *Cc for coupling capacitors. The default is false.
add_explicit_vias [ true | false ]
The default setting of false causes the resistance for vias and contacts to be added as part of the resistance of the
metal layer interconnect which connects to the contact or via. This results in a reduction of the output netlist by
eliminating the contact parasitic resistors while preserving the overall resistance.
If add_explicit_vias is set to true, Quantus will netlist separate parasitic resistors for contacts and vias on all metal
layers in the technology file.
true - Netlist separate resistors for contacts and vias.
false - Include contact and via resistance as part of the resistance of the metal wires they are connected
to. This is the default setting.
Note: This option is automatically set by output_db -em_extract to a value based on the output format.
See em_extract for the value of the setting.
The add_explicit_vias command must be enabled when running sensitivity extraction (extraction_setup enable_sensitivity_extraction).
Note: When the .subckt replacement feature is enabled using the CCL command options, extraction_setup stitch_tsv_model or -stitch_bump_model, the -add_explicit_vias option is automatically set to true. If this option is
explicitly set to false, the software will error out with the following message:
ERROR: The “.subckt replacement” feature cannot work with “-add_explicit_vias false”
busbit_delimiter <string>
​ The busbit_delimiter option specifies the type of character to be used as the bus notation in the DSPF or SPEF
output file.
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If the argument for the -busbit_delimiter command is "[]" (square brackets), then you must prefix the brackets by the
backslash (\) character. For example:
-busbit_delimiter "\[\]"
Note: No other argument except [] requires the (\) character.
Busbit delimiter characters that are allowed are: '\[\]' '{}' '<>' '()'
Note: In the DEF/OA cell-level flow, the bus notation specified by setting the BUSBITCHARS statement in the DEF file
overrides the bus notation specified by busbit_delimiter in the Quantus command file. In the LVS input flows, both the
cell and transistor level, you must specify the actual characters used in the LVS input database as
the busbit_delimiter value so that the *|BUSBIT line in the netlist is properly set.
cdl_out_map_directory <directory>
In CDL netlists, the names of cells or devices may be modified with the addition of an "X" prefix for cell instances, or
"M","Q", or other device specific character prefix for device instances by the CDLOUT utility that creates the netlist.
When this netlist is used as an input to an LVS tool and subsequently to Quantus, the output from Quantus will include
the instance and net names from the CDL and not from the original DFII names. The "X" prefix added to cell instances
will also affect a hierarchical net name. For example the net I5/I6/net1 will be seen in the netlist as XI5/XI6/net1.
However, DSPF/SPEF output requires the original instance names, and not the modified names of the CDL netlist.
Parasitic probing of the extracted view for Calibre or Pegasus input also requires the original instance and net names.
The cdl_out_map_directory must be specified for proper back annotation to the extracted view from the Calibre or
Pegasus input netlist name space back to the schematic view name space. Quantus establishes proper mapping using
the cdl_out_map_directory if the input netlist was originally from CDLOUT.
The mapping created by the CDLOUT utility remains in mapping files in the CDLOUT run directory. This is the specified
run directory when the CDL netlist was created. The cdl_out_map_directory option indicates the location of one or
more CDLOUT run directories that should be searched for mapping files to associate the modified CDL instance name
with the original device instance name to be used in the output netlist."
The cdl_out_map_directory option is necessary whenever the schematic input file for LVS is one or more CDL netlists
created by CDLOUT from DFII schematics. This option supports cell level DSPF/SPEF creation and extracted view
creation for Pegasus or Calibre input.
In the Quantus extracted view flow, the CDLOUT run directory (output_db -cdl_out_map_directory) is required to
map the layout names back to the schematic view name space. The transfer property functionality requires that the
extracted view instance names match the schematic view instance names. Quantus checks if the .trp file actually
contains commands that result in transfer from the schematic as opposed to the .trp file which only has commands that
explicitly set or copy properties. If the .trp file does not contain the schematic transfer commands, it is not mandatory
to specify the CDL directory. However, if the .trp file contains commands to transfer device property from the
schematic to the extracted view, it is mandatory to specify the CDL directory.
While not enforced with termination, the specification of CDL output directory will still be required if net name
mappings (for example, angled to square bus brackets) have been done when generating the CDL netlist.
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comment_top_subckt [true | false]
When set to true, Quantus comments out .SUBCKT/.ENDS in the xDSPF format output for top cells in the flat extraction
flow.
The following is an example of the xDSPF output when .SUBCKT/.ENDS are commented out:
*.SUBCKT esd_top_t vccaux vccio vssio padesd sg11_res_bank sgau_res_bank
*+ segio_res_bank shpx_res_bank
*+ segio_res_bank1 shpx_res_bank1
*+ segio_res_bank2 shpx_res_bank2
*+ segio_res_bank3 shpx_res_bank3
*+ segio_res_bank4 shpx_res_bank4
*
*Net Section
*
*|GROUND_NET 0
?
?
XC1@1 sg11_res_bank vss! NCAP_25_LP nf=1 lf=5e-06 wf=1e-05
+ $X=233.685 $Y=22.26
XC1@2 sg11_res_bank vss! NCAP_25_LP nf=1 lf=5e-06 wf=1e-05
+ $X=233.685 $Y=22.26
XC1@3 sg11_res_bank vss! NCAP_25_LP nf=1 lf=5e-06 wf=1e-05
+ $X=233.685 $Y=22.26
..
..
?
?
*.ENDS
delete_x [true | false]
Starting with the PVE 12.1 release, in the Quantus Pegasus/QCI flows with GDSII input and cell-level DSPF/SPEF
output, the "X" prefix before hierarchical sub-circuit names can be removed. The "X" prefix is seen in CDL
formatted schematic netlists. EXT 15.1 onwards, this option is supported for the xDSPF and xSPEF outputs in the
Quantus Pegasus flow.
For example, in the SPEF *NAME_MAP entries shown below, the X prefixes are deleted when the CCL file includes
the following commands. Only net and instance names in the schematic net name space are modified. Layout names
with no schematic references are unchanged.
input_db -type pegasus \
-library_cell_list_file "Quantus_cell_list"
output_db \
-type spef \
-delete_x true
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output_setup \
-net_name_space "schematic"
Changed from:
*10 XLOGIC/XCONTROL_BLK/XSHIFTREG_BLK/n109
To:
*10 LOGIC/CONTROL_BLK/SHIFTREG_BLK/n109
device_finger_delimiter <string>
This option was created to enable the integration to the Ultrasim simulator to support M Factor reduction. This command
works for SPICE, DSPF, and SPEF netlists. The device_finger_delimiter character is useful when several instance
names or net names in layout are mapped to the same schematic instance name. The unique names are created by
appending this character to the instance or net name followed by a number.
The device_finger_delimiter will affect the output of merged MOS devices, as well as some net names. The
default char is `@'.
disable_instances [ true | false ]
For cell-level (LEF/DEF based) DSPF, the disable_instances option when set to true, turns off the Instance section
and results in a smaller output netlist. That is, the content of the Instance section is not printed. The Instance section
contains the list of device or subcircuit instances in the design, and their associated parameters, and is optional in the
netlists. The -disable_instances option will not have any impact if the output does not have any sub-circuit or
hierarchy. The SPEF output is flat, that is, it has no hierarchy or sub-circuit, so it will not change.
For the cell and transistor-level SPEF from the LVS input, this option controls generation of the <topcell>.dpf side file
which contains a Spice formatted instance only netlist. For the cell and transistor-level DSPF from the LVS input, this
option enables/disables printing of the Instance section at the end of the output file.
This command is set to true by default when the output type is set to dspf or spef. When you set this option to false,
the content of the Instance section is printed in the output netlist.
When the connectivity checker (for instance Gemini) is ON, then it overrides the default behavior of
disable_instances. That is, even if disable_instances is set to true, and connectivity checker is ON, you will
still see the printing of the Instances section in the xdspf netlist.
disable_subnodes [ true | false ]
When set to true for DSPF, SPEF, and RCDB output, this option indicates that subnodes should not be included and
results in a smaller output netlist. The subnodes are the"*|S"lines where the XY coordinates of a net's internal nodes
are printed. This command is enabled by default to result in a smaller netlist.
escape_special_character [ true | false ]
When you set this variable to true, Quantus inserts a backslash as a special character in the output SPEF or DSPF file.
The default is true.
When escape_special_character is set to true, Quantus produces SPEF or DSPF output that looks like this:
*4266 ublock/clk_int\!CLKINVX16\!2\!0
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When set to false, the output is as follows:
*4266 ublock/clk_int!CLK16!2!0
​ ​em_extract [ true | false ]
When the -em_extract option is set to true, the extraction options specific to EM analysis are set during a Quantus run.
For flat Quantus extracted view output, the following options are set:
output_db
-add_explicit_vias true
-include_parasitic_cap_model false
-include_parasitic_res_model comment
-include_parasitic_res_width true
-include_parasitic_res_length true
extraction_setup
-analysis em
For flat Quantus Spice/xDSPF/xSPEF output, the following options are set:
output_db
-add_explicit_vias true
-include_parasitic_cap_model true (Ignored in the xDSPF flow)
-include_parasitic_res_model comment
-include_parasitic_res_width true
-include_parasitic_res_length true
extraction_setup
-analysis em
For xDSPF/xSPEF output, the following option is set in addition to the above mentioned options:
hierarchical_extract
-split_feedthrough_pins true
For all outputs from em_extract, the following option when set overrides the default silicon width setting and
changes it to drawn width.
output_db
-include_parasitic_res_width_drawn true
For xDSPF/Smart View output, the following option is set:
output_db
-subtype extended
However, if the output_db -em_extract option is set to true, and the -subtype is already set to compatible, it is
not overwritten to extended.
To run the EMIR flow with the extracted view (Voltus-Fi Custom Power Integrity Solution-L) or the
xDPSF output (Voltus-Fi Custom Power Integrity Solution-XL), you must set the output_db -em_extract
option to true. Contact your foundry partner for the additional settings required for advanced nodes.
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For cases where diffusion is modeled as diffusion in the ICT file and not diffusion as conductor, if device
diffusion contacts share the same contact layer as tap contacts, then the em_extract option automatically
ignores vias at those tap contacts to prevent shorting of conductor layer metal resistors. This behavior is
disabled if stamp=1 or 2 is in the layer_setup file, or by using the command:
substrate_connection -remove_contact layers "none" nets "none"
force_subcell_pin_orders true|false
The –force_subcell_pin_orders option aligns the hierarchical output net list’s subcircuit IO pins with the schematic
subcircuit IO pins as specified in –pin_order_file. If the –pin_order_file subcircuit IO list contains extra pins, they are
added; and missing pins are removed. For the xDSPF, xSPEF, and SPICE flows, the topcell I/O is modified by pin_order_file by default and so is not controlled by this command. In the extracted view flow, while the pin order is
not important, the topcell I/O pins come from both the layout view and the Quantus extview.tmp output netlist.
The pin_order_file can add pins to topcell I/O, however, cannot delete pins that are already in the layout view.
The -force_subcell_pin_orders CCL command option also supports the cell-level SPEF/DSPF and Smart View
format outputs in the transistor-level flow. This CCL is only used in conjunction with the output_db pin_order_file CCL to allow changes to the I/O of subcells. To generate the SPEF/DSPF format output, the following
CCL combinations are required:
input_db -type assura|calibre|pegasus
input_db -library_cell_list_file <file_name>
output_db -pin_order_file <file_name>
extraction_setup -net_name_space schematic
output_setup -net_name_space schematic|layout
output_db -force_subcell_pin_orders true
output_db -type spef/dspf
Here, the format of the pin order file is in the SPICE format, and must be in the schematic name space.
The schematic name space requirement is for the extraction_setup command and not for the output_setup command.
Even though output_setup -net_name_space is not restricted, it is likely to be “schematic” if timing analysis is to be
done for the Quantus output.
The -force_subcell_pin_orders option is available when LVS is from Pegasus, Assura, or Calibre.
header_file <file>
Specifies a file that contains header text to be included in the DSPF or SPICE netlist output file as comments. Typically,
a timestamp, version number, and details of origin are the types of information that might be put into a header_file.
Sample of Header File
*|DSPF 1.0
*|DATE "Fri Dec 30 19:09:16 2005"
*|VENDOR "Cadence Design Systems"
*|PROGRAM "Quantus Extraction"
*|DIVIDER /
*|DELIMITER #
*|BUSBIT []
Note: The information contained in the header file replaces the standard version statement that is written to the netlist
by Quantus.
hierarchy_delimiter <string>
​ The hierarchy_delimiter option specifies the separator to be placed between the net or instance names of a
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hierarchical block in the DSPF or SPEF output file. The default character is a forward slash (`/'). Quantus supports
only the following IEEE standard hierarchy characters for the various output types:
SPEF: period ( . ), forward slash ( / ), colon ( : ), or pipe ( | ). If these characters are not specified, input_db –
hierarchy_delimiter is used. If input_db -hierarchy_delimiter is not specified, then ‘/’ is used.
DSPF: any character is permitted. If a character is not specified, input_db –hierarchy_delimiter is used.
If input_db -hierarchy_delimiter is not specified, then ‘/’ is used.
SPICE: any character is permitted. If a character is not specified, input_db –hierarchy_delimiter is used.
If input_db -hierarchy_delimiter is not specified, then ‘/’ is used.
For the SPEF and DSPF combination flow, you must specify a delimiter that is allowed for both SPEF and DSPF,
and the same delimiter has to be used for both output types.
Note: ​ The character specified by the output_db -hierarchy_delimiter option overrides the delimiter specified
by the DIVIDERCHAR statement in the input DEF file.
include_parasitic_cap_model [ false | true | comment ]
false - Parasitic capacitor models are not written to the output file.
true - Parasitic capacitor models are included in-line in the output file.
comment - Parasitic capacitor models are included as comments in the output file. This is the default setting.
Note: This option is automatically set by output_db -em_extract to a value based on the output format. See
em_extract for the value of the setting.
include_parasitic_res_model [ false | true | comment ]
false - Parasitic resistor models are not written to the output file.
true - Parasitic resistor models are included in-line in the output file.
comment - Parasitic resistor models are included as comments in the output file. This is the default setting.
Note: include_parasitic_res_model is automatically set to comment when output_db -em_extract is true. See
em_extract for the value of the setting.
include_parasitic_res_width [ true | false ]
When include_parasitic_res_width is set to `true' the width parameters for parasitic resistors are written to the output.
The width of the parasitic resistor that is reported is the silicon width: (drawn resistor width * scale_factor + (2 * bias))
Where, scale_factor is defined with the Techgen -scale command (see Quantus Techgen Reference Manual ).
Note: This option is automatically set by output_db -em_extract to a value based on the output format. See em_extract
for the value of the setting.
include_parasitic_res_width_drawn [ true | false ]
This option is similar to include_parasitic_res_width in every way with the one exception that the resistor width is
specified in the scaled drawn dimensions of the design instead of the silicon dimensions. The scaled drawn dimensions
are a result of scaling the design (using the Techgen -scale command). This command can be used to output resistor
drawn dimensions for use in EM analysis for example.
The include_parasitic_res_width option is mutually exclusive with the include_parasitic_res_width_drawn option. If
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you specify both options to the output_db command Quantus will issue a warning that only
include_parasitic_res_width_drawn will be used and will proceed with extraction.
include_parasitic_res_parameters_unscaled [ true | false ]
When set to true, prints unscaled drawn dimension for Length, Width, and Area parameters. It prints Length if include_parasitic_res_length is set to true.
When set to false, prints scaled drawn dimension for Length, Width, and Area parameters. It prints Length if include_parasitic_res_length is set to true.
The -include_parasitic_res_parameters_unscaled option can only be used when the include_parasitic_res_width_drawn option is set to true. When -include_parasitic_res_width_drawn is set to false,
the -include_parasitic_res_parameters_unscaled option is ignored.
include_parasitic_res_color [ false | true ]
When set to true, the parasitic resistor color is written in the output file. This CCL is used to activate color printing of
parasitic resistors in both the cell-level and transistor-level flows.
Note: For cell-level flows, when this option is set to true, the output_db -subtype option is automatically set to
extended.
The cell-level output netlist format is as follows:
R1 n1 n2 <value1> $LAYER=22 $M=1
R2 n3 n4 <value2> $LAYER=22 $M=2
The transistor-level output netlist format is as follows:
R1 n1 n2 <value1> $layername $M=1
R2 n3 n4 <value2> $layername $M=2
M= is the fixed keyword indicating color mask number. For more information, refer to the "Advanced Node Modeling"
chapter of Quantus Techgen Reference Manual.
include_parasitic_res_length [ true | false ]
This option specifies that the length parameter (L=n) and width parameter (W=n) should be output for parasitic resistors
on resistive metal interconnect that undergoes width changes of 10% or more. However, the default of 10% can be
changed with the extraction_setup -parasitic_res_width_change_percentage command (see "extraction_setup" ).
By default, Quantus produces a single minimum-width parasitic resistor for a variable-width wire segment. Using the
include_parasitic_res_length option, Quantus will now produce multiple parasitic resistors for the same wire
segment corresponding to each significant width change that occurs on the wire interconnect.
The width change is calculated based on the drawn width (i.e. before process bias is applied). Therefore, process bias
will not affect the number of resistors that are output when using this command. The width parameter (W=n) value that is
output in the netlist is calculated using the bias (constant or WEE).
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Since the output of include_parasitic_res_length includes the width parameter (W=n) output as well as the
length parameter (L=n), enabling this also automatically enables include_parasitic_res_width. However, if you
want the resistor width output in drawn dimensions instead, you must manually specify the
include_parasitic_res_width_drawn option.
Note: This option is automatically set by output_db -em_extract to a value based on the output format. See
em_extractfor the value of the setting.
include_parasitic_res_temp_coeff [ true | false | comment]
This feature requires the Virtuoso_QTS_Extraction_XL license and the Advanced Analysis (AA) GXL option for
Quantus.
When the include_parasitic_res_temp_coeff option is true, the temperature coefficients which are used to determine
the effect of temperature on resistance are included in the output netlist. The temperature coefficients (TC1 and TC2)
are defined in the ICT file when creating the technology file (see Quantus Techgen Reference Manual ). The behavior
of the true argument in the cell and transistor flow are:
Cell Level: TC1 and TC2 are printed as comments ( $TC1=, $TC2=).
Transistor Level: TC1 and TC2 are printed as explicit parameters (TC1= and TC2=).
The TC1 and TC2 values are imported from the ICT file by Quantus during extraction. As an example, for the M1 layer,
the ICT file defines: TC1=0.00254 TC2=0.0001. The expected printing in the xDSPF (transistor flow) and DSPF (cell
flow) output are as follows:
Quantus (cell)
Rk479578 I4/PLL/V2I/DAC_X[3]:7 I4/PLL/V2I/DAC_X[3]:8 0.946417 $M01
+ $TC1=2.54e-3 $TC2=0.0001 $L=0.246 $W=0.072 $X=241.442 $Y=229.979
Quantus (transistor)
Rk479578 I4/PLL/V2I/DAC_X[3]:7 I4/PLL/V2I/DAC_X[3]:8 0.946417
+ TC1=2.54e-3 TC2=0.0001 $M01 $L=0.246 $W=0.072 $X=241.442 $Y=229.979
In the transistor-level flow, when the include_parasitic_res_temp_coeff option is set to comment, TC1 and TC2 are
printed as comments ( $TC1=, $TC2=).
The multiple process corner mode supports temperature coefficient (TC1/TC2) printing in both the cell-level and
transistor-level flows.
In the transistor-level flow, the process corner property information (P1,P2,P3) and temperature coefficients (TC1/TC2)
are stored in the vector format for the parasitic R/C element values. During simulation, you can set the values of P1, P2,
P3 to retrieve the RC value of each process corner. For example, P1=1, P2=0, P3=0 would retrieve the P1 corner’s RC
values. P1/P2/P3 should sum up to 1.0. For example, P1=0.5, P2=0.5, P3=0 would retrieve an imaginary process
corner in between P1 and P2. By default, the process corner property names (P1,P2,P3…) for resistance are R1,R2,R3
and for capacitance are C1,C2,C3. Following is an example of the temperature coefficient print format in the vector
format:
Rxx n1 n2 ‘R1*<Rval1>+R2*<Rval2>+R3*<Rval3>’
+ TC1=’R1*<tc1_a>+R2*<tc1_b>+R3*<tc1_c>’
+ TC2=’R1*<tc2_a>+R2*<tc2_b>+R3*<tc2_c>’
+ $M01 $L=0.246 $W=0.072 $X=241.442 $Y=229.979
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Cxx n3 n4 ‘C1*<Cval1>+C2*<Cval2>+C3*<Cval3>’
...
In the transistor-level flow, multi-corner temperature coefficient printing is supported in the SPICE, xDSPF, and
extracted view output formats, and requires two XL licenses.
Following is the syntax for parameterized TC1 and TC2 coefficients in the MPC xDSPF output netlist:
*|NET net1 'Ctot_c1*C1+Ctot_c2*C2+Ctot_c3*C3'
*|I ...
*|S ...
Rg1 net1#1 net1#2 'C1*R_c1+C2*R_c2+C3*R_c3' $layer_name
TC2='C1*tc2_c1+C2*tc2_c2+C3*tc2_c3'
TC1='C1*tc1_c1+C2*tc1_c2+C3*tc1_c3'
$L=<> $W=<> $X=<> $Y=<> $lvl=<>
Cc1 net1#5 net1#6 'C1*C_c1+C2*C_c2+C3*C_c3' $lvl=<>
The CCL commands to trigger the MPC xDSPF with parameterized TC1, TC2 are:
process_technology -technology_corner
"C1" "C2" C3" \
output_db -include_parasitic_res_temp_coeff true \
When the above CCL commands are specified, TC1 and TC2 will get printed in the following format in the xDSPF file:
RM0_STI_1 vss#59051 vss#59052 'C1*6.938682+C2*6.938682+C3*6.938682' TC1='C1*0.0012+C2*0.0012+C3*0.0012'
TC2='C1*3.39e-06+C2*3.39e-06+C3*3.39e-06' $M0_STI $L=0.134 $W=0.043
When output_db -include_parasitic_res_temp_coeff comment is used then TC1 and TC2 will get printed in the
following format in xDSPF file:
RM1_86523 X65/X7/4#254 X65/X7/4#256 'C1*0.621030+C2*0.621030+C3*0.621030' $M1
$TC1='C1*0.00278137+C2*0.00278137+C3*0.00278137' $TC2='C1*-6.48998e-07+C2*-6.48998e-07+C3*-6.48998e-07'
$L=0.882 $W=0.5137
Note: In this use model, if the process_technology -temperature <> CCL is used along with output_db include_parasitic_res_temp_coeff true/comment, Quantus will error out.
To print customized process corner names inside parameterized xDSPF netlist, a separate file called
process_corner_names can be put inside each corner in Quantus technology file folder. For example, the contents of
the process_corner_file for a typical corner can be following:
C C=typ
R R=typ
Similarly, “typical_CCbest” and “typical_CCworst” can be added to each of the typical_CCbest and typical_CCworst
in the Quantus technology file folder corners. In this case, the MPC xDSPF netlist would be printed with customized
corner names as follows:
CgD2913 X1088/X24_unmatched#S vss 'typical*5.95563e-17+typical_CCbest*5.95558e17+typical_CCworst*5.95559e-17'
Rb45154 vdd vdd#6697 'typical*0.009186+typical_CCbest*0.009186+typical_CCworst*0.009186'
TC1='typical*0.00380301+typical_CCbest*0.00380301+typical_CCworst*0.00380301' TC2='typical*-5.53388e07+typical_CCbest*-5.53388e-07+typical_CCworst*-5.53388e-07' $M13 $L=1.505 $W=3.6 $X=-3.0015 $Y=1.797
This makes the xDSPF easier to read and understand in terms of which parameter corresponds to which corner instead
of default C1, C2, C3 corners that are printed when process_corner_names are not defined.
Note: When parameterized MPC xDSPF is included using dspf_include in input.scs created through ADE, Spectre,
till MMSIM18.1 ISR9 and MMSIM19.1 ISR1 release versions, does not support parsing of parameterized variables. For
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example, C1, C2, C3. Since, dspf_include is recommended for EMIR simulation in Spectre, therefore, the MPC xDSPF
netlist is currently not supported for Voltus-Fi EMIR flow. Support for MPC xDSPF in dspf_include might be added in
future Spectre release. However, Spectre currently supports parsing of MPC xDSPF when included in the input.scs
using include statement, which can be used for timing type simulation, if required.
The presence of the TC1/TC2 temperature coefficients in the output netlist or extracted view allows the downstream
simulation to consider the effects of temperature on the circuit. The expected use model is to determine the temperature
effect during simulation, in Spectre for instance, rather than in Quantus. In this case, you do not want Quantus to
consider the effect of temperature on resistance extraction using the process_technology -temperature command or
you may be double counting the effect of temperature on resistance (see "process_technology" ). Therefore, these two
command options are mutually exclusive, and an error will occur if both are specified.
For via layers TC1/TC2 must be defined as constants. However, for conductor layers TC1/TC2 can be defined as a
constant or as a function of wire width. If TC1 and TC2 are defined as constants, the printed value will be precise.
However, since Quantus may lump several wire segments of varying width into a single interconnect fragment, the TC1
and TC2 values for width dependent temperature coefficients are only an approximation.
If the resistor width parameter is not printed, the TC1/TC2 values will reflect the silicon width by default. If the width of
the parasitic resistor is included in the output at the silicon width (output_db -include_parasitic_res_width) the
temperature coefficient values will be printed based on the silicon widths.
If the width of the parasitic resistor is included in the output at the drawn width (output_db include_parasitic_res_width_drawn) the temperature coefficient values will be printed based on the drawn widths. If
layout_scale is specified in the ICT file, then the TC1 and TC2 values will reflect the scaled drawn width.
This option supports DEF/OA or LVS inputs, and supports DSPF, Spice, or Extracted View outputs. The include_parasitic_res_temp_coeff option is ignored when the SPEF output is specified. For LVS input (Assura,
Pegasus, or Calibre), this option is supported for both cell-level DSPF and transistor-level XDSPF output formats. Both
flat and hierarchical flows are supported as well.
​
Print GLOBAL_TEMPERATURE and OPERATING_TEMPERATURE in DSPF and xDSPF File Formats
In the transistor-level flow, Quantus supports printing of GLOBAL_TEMPERATURE (defines the nominal temperature for
extraction) and OPERATING_TEMPERATURE (defines the operating temperature for simulation) in the header of the DSPF
and xDSPF output. This feature is supported with the Assura, Pegasus, and Calibre LVS inputs.
The following table shows the use model and the corresponding temperature information printed in the DSPF/xDSPF
output:
Use Model
DSPF/xDSPF Output
output_db -include_parasitic_res_temp_coeff is set to true
*|GLOBAL_TEMPERATURE [ <temp_ref> | 25 ]
process_technology -temperature <temp> is not supported
output_db -include_parasitic_res_temp_coeff is set to
*|OPERATING_TEMPERATURE
<temp>
*|GLOBAL_TEMPERATURE [ <temp_ref> | 25 ]
false
process_technology -temperature <temp> is specified
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output_db -include_parasitic_res_temp_coeff is set to
false
process_technology -temperature <temp> is not specified
*|OPERATING_TEMPERATURE [ <temp_ref> | 25
]
*|GLOBAL_TEMPERATURE [ <temp_ref> | 25 ]
temp_ref is the nominal temperature, and is defined using the process command in the ICT file, as shown below:
process { temp_reference <temp_ref> }
If not specified, the default value is 25.
Notes:
If a p2lvsfile file exists in the technology directory, and the p2lvsfile contains a width-dependent TC table that is
different than the table in the ICT file, then the p2lvsfile takes precedence over the TC table specified in the ICT
file and the TC1/TC2 values that are printed in the output netlist are taken from the p2lvsfile. For getting the correct
TC extraction result based on ICT table, you need to remove TC-related contents from p2lvsfile before running
Quantus.
For DEF or OA input, this option is supported for extended DSPF output format only (output_db -type dspf subtype extended). TC1/TC2 printing will be ignored when standard DSPF (output_db -subtype standard) is
specifi