Uploaded by Ahmed Tarek

DSP48A1 FPGA Project Report: RTL, Synthesis, Implementation

Project_1_DSP48A1
Name: Ahmed Tarek Hassanien Mohamed
Group #2
1. RTL code
1.1.
reg_mux module
1.2.
DSP module
2. Testbench code
3. DO file
4. QuestaSim snippets
5. Constraint File
6. Elaboration
6.1 Messages
6.2 Schematic snippets
7. Synthesis
7.1 Messages
7.2 Utilization and Timing reports
7.3 Schematic snippets
8. Implementation
8.1 Messages
8.2 Utilization and Timing reports
8.3 Device Snippet
9. Linting snippet
No errors