Cheatsheet for CTS
Prepared by: Garima jangid
What is CTS?
Clock Tree Synthesis (CTS) is the process of
distributing the clock signal from its source (PLL or
input pad) to all the clock sinks (flip-flops, latches)
in a chip with minimal skew and controlled latency.
Objectives:
• Balance clock arrival times (minimize skew)
• Limit clock latency and transition
• Optimize clock power consumption
• Prepare a robust structure for timing
closure
CTS Flow Breakdown
Stage
Function
Clock Definition
Read clocks from SDC,
define domains
Clock Sink
Identify FFs/latches gated
Identification
by each clock
Clock Tree
H-tree, X-tree, spine,
Topology Selection hybrid, grid
Clock Buffer
Buffer/inverter insertion to
Insertion
drive sinks
Skew and Latency
Match path delays using
Balancing
balancing algorithms
Transition
Ensure signal rise/fall
Optimization
times meet library specs
CTS Routing
Create physical routing for
clock nets
Post-CTS Hold
Fix hold violations caused
Fixing
by skew reduction
Inputs to CTS
Input
Placed netlist
Clock constraints (SDC)
Power plan
Cell library (.lib)
Clock tree exceptions
(set_dont_touch, false
paths)
Description
Output from
placement step
Defines clock period,
sources, sinks
Ensures clock buffers
are powered
correctly
Provides
buffer/inverter info
Guides CTS tool
Commonly Used CTS Terms
Term
Definition
Skew
The difference in clock arrival
times between two clock sinks
(FFs or latches). High skew can
cause timing violations.
Latency
The delay from the clock
source (e.g., PLL or clock port)
to a clock sink. Includes both
source and sink latency.
Clock Latency
Total delay from the clock
source to the final clock pin of
a flip-flop (Source + Sink
latency).
Transition Time The rise or fall time of the
(Slew)
clock signal edge. It must be
within the defined limits to
avoid setup/hold violations.
Clock Tree
A physical structure composed
of buffers/inverters and wires
that distributes the clock to
sequential elements.
Clock
Standard cells used to
Buffer/Inverter replicate and strengthen the
clock signal as it fans out to
many sinks.
CTS (Clock Tree The process of inserting clock
Synthesis)
buffers and routing the clock
net to all required sinks while
minimizing skew and latency.
Clock Gate Cell A logic cell that conditionally
(ICG)
enables/disables clock
propagation to reduce power.
Used in clock gating.
Clock Domain
A group of sequential
elements (FFs) that receive
the same clock signal.
Different clock domains
require careful
synchronization.
Fanout
The number of sinks (loads)
driven by a single clock source
or buffer. High fanout needs
stronger drivers or buffer
stages.
H-Tree / X-Tree Common tree topologies used
/ Grid Tree
to balance the clock signal and
minimize skew.
Balancing
The process of ensuring equal
delay paths in the clock tree to
reduce skew.
Clock
Uncertainty
Hold Fixing
Buffer
A margin added to the timing
analysis to account for skew
and jitter. Usually set in SDC as
set_clock_uncertainty.
A delay buffer added to fix
hold time violations post-CTS.
CTS Constraints in SDC
Constraint
Purpose
create_clock
Define a clock with
name, period, and
waveform
set_propagated_clock
Enable propagation
through CTS tree
set_clock_latency
Set expected latency
for clock arrival
set_clock_uncertainty
Add margin for skew
and jitter
set_clock_transition
Limit the slew of
clock at sinks
set_dont_touch
Prevent optimization
of gating logic
set_false_path -from
Ignore invalid paths
[clk1] -to [clk2]
between
asynchronous clocks
Clock Tree Topologies
Topology
Use Case
H-Tree
Balanced clock tree, symmetric
delay; ideal for uniform
distribution
X-Tree
Like H-tree but rotated; used in
rectangular dies
Spine Tree
Central spine feeds branches;
good for row-based layouts
Grid Tree
High performance, low skew,
(Mesh)
robust for high-frequency designs
Hybrid Tree Mix of tree and mesh; widely used
in SoCs
CTS Design Metrics & Targets
Metric
Target Value (typical)
Skew
< 100 ps (≤ 50 ps preferred)
Latency
Depends on timing budget
Transition
< max_transition in .lib
(Slew)
Fanout per
< 20–24 (depends on buffer)
Buffer
Depth of
Balanced (< 20 buffer stages)
Tree
Buffer Count
Clock Power
Minimized without affecting skew
Should be <40–50% of total chip
power (depends on gating)
CTS Flow
1. Identify clock sources and sinks (FFs, latches)
2. Group sinks into clock domains
3. Select clock buffers/inverters from the library
4. Insert buffers/inverters to build a balanced tree
5. Optimize for skew, latency, power, transition
6. Connect tree to sinks and perform CTS legality
checks
7. Generate reports and validate QoR
CTS Optimization Goals
Metric
Description
Skew
Arrival time difference between
slowest and fastest sinks
Latency
Delay from source to sink
Transition
Clock slope at sink (< max limit)
Power
Minimize dynamic and leakage
power
IR Drop Safe
Avoid overloading buffers in
weak power regions
Clock Gating
Insert CTS while preserving
Aware
gating structure
CTS Buffer Insertion Strategies
Strategy
Application
Balancing Tree Equalizes paths from source to
all sinks
Non-uniform
Buffers sized by load,
Sizing
transition, and distance
Tapered Tree
Larger buffers near source,
smaller near sinks
Clustered
Group close sinks and insert
Insertion
buffers per group
Clock Gating Guidelines
• Place clock gating cells near source logic
(not FFs)
• Use integrated clock-gating cell (ICG) if
available in library
• Avoid clock gating glitches → Ensure enable
signal is stable
• Preserve gating during synthesis and CTS
• CTS should treat gated clocks as a separate
domain if not merged
CTS Reports to Analyze
Report
Insights
Skew Report
Check if skew < 100 ps
(typically)
Latency
Source → sink delays
Report
Clock QoR
Total inserted buffers, tree
Report
depth
Transition
Clock edge rate at sinks
Report
Power Report Dynamic and leakage power of
the clock network
Tool Commands (Examples)
Cadence Innovus
setCTSMode -skew 100ps -latency 300ps
clockDesign -optimizePower
reportClockTree
Synopsys ICC2
create_clock_tree
report_clock_tree
optimize_clock_tree
Common CTS Issues & Fixes
Issue
Cause
Fix
High Skew Unbalanced
Rebalance buffers,
tree
insert inverters
Clock Gate Tool
Add
Mismatch
optimized
set_dont_touch
away clock
gate
Poor
Weak driver,
Insert
Transition
long nets
intermediate
Times
buffers
Excessive
Tool overAdjust constraints,
Buffers
inserts for
use fanout control
timing
High Clock OverApply gating, use
Power
buffering,
low-power buffers
toggling
IR Drop on Buffers in
Relocate or use
Clock Path weak power
power-aware CTS
domains
Tips for CTS
•
Group sinks based on physical location
•
Enable CTS-aware placement to ease
buffer tree balancing
•
Preserve clock gating structures from
synthesis
•
•
•
•
Run early CTS trial to assess placement
quality
Avoid placing large buffers in congested
or low-power regions
Perform post-CTS hold fixing using
delay buffers
After CTS, rerun timing analysis with
propagated clocks
Output Artifacts from CTS
• Updated netlist with clock tree
• DEF/LEF with CTS buffer placements
• Skew/latency/transition reports
• Updated timing reports (setup/hold)
• Visualization of clock tree structure
Interview Questions on CTS
1. What is Clock Tree Synthesis (CTS) and why is it
important?
2. What is clock skew? What are local skew and
global skew? How does skew affect timing?
3. What is clock latency? Differentiate between
source latency, sink latency, and total latency.
4. What are the different types of clock tree
topologies? When would you use H-tree, X-tree,
or clock mesh?
5. What is the difference between an ideal clock
and a propagated clock? Why is
set_propagated_clock used?
6. How is clock gating handled in CTS? Why do we
preserve clock gating structures?
7. What are the typical constraints and targets
during CTS (skew, transition, fanout)?
8. What causes hold violations after CTS, and how
do you fix them?
9. How do you check the quality of your clock
tree? Which reports do you analyze post-CTS?
10. What is CTS-aware placement? How does it
help improve clock QoR?