ECE-UY 3124
Project #1 – Fall 2025
Class A Power Amplifier Design
Design a single-stage BJT class-A power amplifier
This project is an individual effort, similar designs will not be graded
Transistor – 2N2222 or equivalent
Transistor Specifications:
Parameter
Power Dissipation, PD
Current Gain, 
Small Signal, ro
Minimum
Nominal
100
200
infinite
Input Sinusoid Specifications:
Parameter
Minimum
Frequency for vin
Resistor Specifications:
Parameter
Resistance
Power Dissipation, PD
Minimum
1 ohm
Maximum
600 mW
300
Nominal
1 kHz
Maximum
Nominal
Maximum
1 MEGAohm
3W
Power Amplifier Performance Specifications 𝛽 200 unless otherwise noted:
Note: any of the following parameters labeled with “**” is a secondary goal and extra points if
your design achieves the goal.
Parameter
Minimum Nominal Maximum
DC Power Supply Voltage, VCC
+5 VDC
+30 VDC
DC Power Supply Current, IPS
200 mA
Load resistance, RL, capacitive coupled
50 ohm
Peak-to-Peak Current swing at RL, 𝑖 ,
, no
160 mA
clipping
2
70
Small signal current gain, 𝐴
(lower is
better)
Small signal input resistance, Rin
**Small signal gain stability, 𝐴 , over 100
300
**Power Efficiency, 
400 ohm
𝛽
+/- 10%
5%
Rev 0.0
ECE-UY 3124
Project #1 – Fall 2025
Class A Power Amplifier Design
Design Notes:
 To change the value in CircuitLab, select 2N2222 and change “B_F” to the value
required.
 Resistors can have any value at this point in the design. You don’t need to adhere to
industry standard values unless you want to (could be helpful later). If you calculate a
resistor of 2 ohms or less, then you probably don’t need this one.
 When calculating the DC operation of your circuit, it could be helpful to use VBEQ =
0.8V. At the higher ICQ values, the B-E voltage increases beyond 0.7V.
 There will be differences between your hand calculations and the PSpice results.
Enter you hand-calculated design into PSpice and slightly adjust the resistor(s) until
you achieve the required specifications in PSpice.
 When performing a transient analysis, it is best to set “maximum step size” to
0.01msec and simulate over a range of 3 msec.
PART 1: HAND CALCULATIONS
A. Submit all hand calculations for your design. It is important to show how you decided
on your resistor values and operating conditions. If you are looking for extra points on
a stable DC and/or AC design, you need to show the equations that support your
assumption for stability.
B. What is your calculated power conversion efficiency,  ? Show all the steps for this
calculation.
C. Draw (by hand) your complete schematic with the final resistor values.
D. Draw a plot of the AC and DC load lines on the same iC versus vCE graph. Clearly show
the x- and y-intercepts, with values, for each. Clearly label the Q point. Load line
calculations can assume that  = infinite ( = 1).
E. In a table, list your DC bias parameters; VCC, ICQ, VCEQ, PD, transistor?
F. In a table, and for a value of  = 200, list your calculated small signal current gain, Ai,
Input Resistance, Rin, and Output Resistance, Rout. Show complete schematic used for
calculating Rout..
G. What is your maximum peak-to-peak current at the load? Show the calculation.
Rev 0.0
ECE-UY 3124
Project #1 – Fall 2025
Class A Power Amplifier Design
H. In a table, list the resistor values and associated power dissipation for all resistors in your
design.
PART 2: PSPICE SIMULATIONS:
A. SCHEMATIC: Submit your PSpice schematic clearly showing all values for DC
voltage, DC current and DC Power for each element. All resistor values must clearly be
shown on the schematic.
B. SIMULATED DC BIAS: What are the simulated DC bias parameters, ICQ, VCEQ, VBEQ
and transistor Power Dissipation, PD, transistor? Submit a table comparing your handcalculated values to the simulated values for ICQ, VCEQ, VBEQ, and PD, transistor.
C. SIMULATED POWER SUPPLY BIAS: What is the total current delivered from the
supply, IPS? Did you achieve the specification for maximum current?
D. SIMULATED CURRENT SWING: Simulate your design in PSpice using a 1kHz
sinusoidal input, use a voltage source with a 1 kohm source resistor as shown above.
Place a current probe on the wire leading into your circuit (on the left side of the
capacitor). What is the largest peak-to-peak swing in the output current, iL, through the 50
ohm load resistance? To find the maximum swing, you should slowly increase the source
amplitude until the output current waveform begins to clip at the top or the bottom.
Unless you have a design optimized for maximum symmetrical swing, it’s most likely that
the clipping will not be symmetrical. In other words, the point of clipping in the positive
peak current will be different from the negative peak current. Submit a plot showing iL
with clipping using a  = 200. When clipping occurs, chose the smaller of the two values
and double this value, this is the peak-to-peak swing in the output current, iL. Clearly
report this peak-to-peak swing in the output current, iL. Did your design achieve the
180mA peak-to-peak swing?
E. SIMULATED EFFICIENCY: Using the peak swing in load current, iL (just below
clipping), and load resistance, 50 ohms, calculate the simulated power conversion
efficiency, ? You will need the total power supply current, IPS, from your simulation.
Show all your calculations using data recorded from your simulated plots. Compare the
hand-calculated value to the simulated value.
F. SIMULATED SMALL SIGNAL OPERATION: Using PSpice, reduce the input source
amplitude so that it is should be small enough to operate your transistor in the small signal
region. Verify that the peak AC voltage across the Base-Emitter (B-E) junction, vbe, is less
than 2.6mV peak (<<26mV). Take the difference between two voltage probes placed at
the base and the emitter. You may need to subtract off any DC offset so you only see the
sinusoidal portion of the vBE waveform. If vbe is greater than 2.6mV, decrease the source
amplitude until the B-E voltage is in the small signal range. Record the amplitude value
of the source voltage for small signal operation. Submit a plot showing of vbe for  = 200.
G. SIMULATED GAIN: Using the input source with amplitude set to the value found in part
(F), what is the small signal gain, 𝐴
, at  = 200? Submit two plots showing iS and
iL under small signal conditions using a  = 200. Edit the transistor model and change the
value for  to 100 and then to 300 , record the small signal gain for each condition. What
is the variation in the current gain, 𝐴
, when  is varied over the range from 100 to
Rev 0.0
ECE-UY 3124
Project #1 – Fall 2025
300? Submit a table showing current gain, 𝐴
Class A Power Amplifier Design
, for  = 100, 200 and 300. What is
the % variation in your gain across this range in (relative to  = 200, percent variation is
calculated using
𝑥100% )?
H. SIMULATED INPUT RESISTANCE: Using the source amplitude found in part (F), what
is the simulated input resistance, Rin, to your amplifier? Using current and voltage test
probes at the amplifier input to calculate the input resistance using PSpice by placing
cursors at the peak of each sinusoidal waveform and dividing the voltage result by the
current. Note that the placement of V/I probes on the schematic in circuit areas where
there is DC voltage and/or DC current will result in a DC offset in the simulated
measurements, if so, either move the probe or subtract the DC offset from the results.
Submit two plots showing the voltage and current waveforms used to calculate Rin
having  = 200. Submit a table comparing your hand calculation and PSpice value for
Rin. Submit a table showing PSpice values for Rin with  = 100, 200 and 300.
I. SIMULATED OUTPUT RESISTANCE: What is the output resistance, Rout, to your
amplifier? Replace the 50 ohm load with a voltage source at the output of your amplifier
(leave the coupling capacitor between the source and the circuit). Remove the input
voltage source and replace with a short (vin=0). Using current and voltage test probes at
the amplifier output, calculate the output resistance, Rout, using PSpice by placing
cursors at the peak of each waveform and dividing the voltage result by the current. The
voltage source should have a low amplitude to maintain a small signal condition. Submit
the PSpice schematic of your test circuit. Submit a plot showing vO and iO on two
separate graphs for  = 200. Submit a table showing Rout for  = 100, 200 and 300.
J. SIMULATION USING STANDARD RESISTOR VALUES: Using your PSPICE design,
substitute standard resistors into your model by rounding up or down to the nearest
values. The standard resistor values are listed in Appendix A noting there are two
columns, one for 1/2 watt and one column for 3W. Match the resistance and associated
power requirements to your design. SUBMIT the schematic with Standard Resistors.
Using =200, simulate the peak-peak current swing, small signal current gains and input
resistance. Submit a table, comparing PSpice results for VCC, ICQ, VCEQ, PD, transistor with
original resistors and the standard value resistors.
K. Submit a plot showing iL with clipping at both the positive and negative peaks using a 
= 200. Submit plots of is and iL under small signal conditions, calculate Ai. Submit plots
of iin and vin under small signal conditions, calculate Rin. Submit a table comparing the
simulated peak swing, the simulated small signal gain and input resistance for your
original design and the design with standard resistors.
L. COMPONENT BILL OF MATERIALS (BOM) FOR LAB EXPERIMENT #3: Create
the BOM, with standard resistor values (ohms), the quantities for each type of resistor and
the required power spec (½ watt or 3 watt). Include the BOM in your project submission
and also upload your BOM to Brightspace Assignments. The BOM must be received
by Tuesday, September 30 at noon. Use the BOM form posted on Brightspace.
Rev 0.0
ECE-UY 3124
Project #1 – Fall 2025
Class A Power Amplifier Design
APPENDIX A: Standard Resistor Values
1/2 watt
2.7
4.7
10
12
15
22
27
39
47
51
56
62
68
75
82
91
100
120
130
150
180
200
220
270
330
390
470
680
750
910
1k
1.2k
1.3k
1.5k
2k
3 watt
1
2
2.7
3
3.9
5.6
6.2
7.5
8.2
9.1
11
12
13
15
16
18
22
24
25
27
30
36
39
47
43
50
51
56
62
68
75
82
91
100
120
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
Rev 0.0
ECE-UY 3124
Project #1 – Fall 2025
2.2k
2.4k
2.7k
3k
3.3k
3.6k
3.9k
4.7k
5.1k
5.6k
6.8k
7.5k
9.1K
10K
11K
12K
15K
16K
18K
20K
22K
27K
30K
33K
39K
43K
47K
51K
56K
68K
82K
91.2k
100k
120k
130k
150k
200k
220k
270k
130
150
180
200
220
270
330
390
470
680
750
910
1k
Class A Power Amplifier Design
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
Rev 0.0
ECE-UY 3124
Project #1 – Fall 2025
300k
330K
470k
680k
1M
1.3M
3.3M
5.1M
9.1M
10M
Class A Power Amplifier Design
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
ohms
Rev 0.0