Section 7
PREPARED BY: TASNEEM ADEL
DMA
The processor initiates the DMA controller by sending the starting address, Number
of words in the data block and direction of transfer of data .i.e.
from I/O devices to the memory or from main memory to I/O devices.
More than one external device can be connected to the DMA controller.
DMA controller contains an address unit, for generating addresses and
selecting I/O device for transfer.
It also contains the control unit and data count for keeping counts
of the number of blocks transferred and indicating the direction of transfer
of data.
When the transfer is completed, DMA informs the processor by raising an
interrupt.
DMA Modes
Burst Mode: In this mode DMA handover the buses to CPU only after completion of whole
data transfer. Meanwhile, if the CPU requires the bus it has to stay ideal and wait for data
transfer.
Cycle Stealing Mode: In this mode, DMA gives control of buses to CPU after transfer of every
byte. It continuously issues a request for bus control, makes the transfer of one byte and
returns the bus. By this CPU doesn’t have to wait for a long time if it needs a bus for higher
priority task.
Transparent Mode: Here, DMA transfers data only when CPU is executing the instruction which
does not require the use of buses.
Problem
Show using a neat diagram how 8237 DMA can be used to connect a disk controller to
the main memory. In your diagram show all signals. Also, describe in details the steps of
the data transfer.
Solution
Solution cont.
Problem
Consider a system in which bus cycles takes 500 ns. Transfer of bus control in either
direction, from processor to I/O device or vice versa, takes 250 ns. One of the I/O device
has a data transfer rate of 50 KB/s and employs DMA. Data are transferred one byte at a time.
a.
Suppose we employ DMA in a burst mode. That is, the DMA interface gains bus mastership prior to
the start of a block transfer and maintains control of the bus until the whole block is transferred. For
how long would the device tie up the bus when transferring a block of 128 bytes?
b.
Repeat the calculation for cycle-stealing mode.
Solution
a.
For the actual transfer, the time needed is (128 bytes)/(50 KBps) = 2.56 ms. Added to this is the
time to transfer bus control at the beginning and end of the transfer, which is 250 + 250 = 500 ns.
This additional time is negligible, so that the transfer time can be considered as 2.56 ms.
b.
The time to transfer one byte in cycle stealing mode is 250 + 500 + 250 = 1000 ns= 1 μs. Total
amount of time the bus is occupied for the transfer is 128 μs. This is less than the result from part
(a) by a factor of 20.
Problem
Examination of the timing diagram of the 8237A indicates that once a block
transfer begins, it takes three bus clock cycles per DMA cycle. During the
DMA cycle, the 8237A transfers one byte of information between memory
and I/O device.
a.
Suppose we clock the 8237A at a rate of 5 MHz. How long does it take to
transfer one byte?
b.
What would be the maximum attainable data transfer rate?
c.
Assume that the memory is not fast enough and we have to insert two wait
states per DMA cycle. What will be the actual data transfer rate?
Solution
a.
At 5 MHz, on clock cycle takes 0.2 μs. A transfer of one byte therefore takes 0.6 μs.
b.
The data rate is 1/(0.6 × 10–6) = 1.67 MB/s
c.
Two wait states add an addition 0.4 μs, so that a transfer of one byte takes 1 μs. The
resulting data rate is 1 MB/s.
Thank You
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