ENG2410
Digital Design
“Sequential Circuits:
Part B”
Fall 2017
S. Areibi
School of Engineering
University of Guelph
Week #7 Topics
 Sequential Circuit Analysis
 Sequential Circuit Design
 Designing with D Flip-Flops
 Designing with JK Flip-Flops
 Designing with T Flip-Flops
 VHDL Representations
 Examples
2
Resources
 Chapter #6, Mano Sections
6.4 Sequential Circuit Analysis
 6.5 Sequential Circuit Design
 6.7 VHDL Representation of Sequential
circuits

3
Analysis of Sequential Circuits
Earlier we learned how to analyze
combinational circuits
o We will extend analysis to synchronous
sequential
o We’ll use
o
1.
2.
State tables and
State diagrams
4
Review: Flip Flops
5
Analysis of Sequential Circuits
o
The behavior of a sequential circuit is
determined from:



o
Inputs,
Outputs,
Present state of the circuit.
The analysis of a sequential circuit
consists of:

Obtaining a suitable description that
demonstrates the time sequence of inputs,
outputs and states (STATE DIAGRAM).
6
Step #1: Derive Input Equations
Can describe inputs to FF with logic equations
J A  ( XB  Y C )
K A  (YB  C )
7
Another Example
D A  ( AX  BX )
DB  A X
Y  ( A  B) X
8
Input Equations
The input equations
1.
2.
Imply the type of flip-flop from the
letter symbols,
Fully specify the combinational circuit
that drives the flip-flops.
9
Time is Implied
 Note that previous circuit used the
Present state (A, B, ..) to determine next state
 State and inputs to determine output

 Synchronous circuit
 When are transitions?
D A  ( AX  BX )
DB  A X
Y  ( A  B) X
10
Step #2: State Table
o
o
o
Similar to truth table with state added
A sequential circuit with `m’ FFs and `n’ inputs needs 2m+n rows
in state table.
Next State and output are determined using? (input equations)
D A  ( AX  BX )
DB  A X
Y  ( A  B) X
11
Step#3:
State Diagram “Mealy Model”
Input
Output
An alternative
representation to
State Table
Input
00
Output
0/0
01
1/0
Input/Output
12
Sequential Circuit Types
 Moore model –
outputs depend
on states only.
 Mealy model – outputs
depend on
inputs & states
13
State Diagram: Moore
Alternative representation for state table
Inputs
State/Output
14
Moore vs. Mealy Machine
o
Moore Machine:


o
Mealy Machine:


o
o
Easy to understand and easy to code.
Might requires more states (thus more hardware).
More complex since outputs are a function of both the state and
input.
Requires less states in most cases, therefore less components.
Choice of a model depends on the application and
personal preference.
You can transform a Mealy Machine to a Moore Machine
and vice versa.
15
State Table vs. Diagram
o
Provides same information
Table is perhaps easier to fill in from
description
 Diagram is easier for understanding and
writing code
o Analysis for sequential circuits that employs D
flip flops is easy. Why?
 Because the next state values are obtained
directly from the input equations.

16
Analysis with JK Flip Flops
For circuits with other types of flip flops such
as JK, the next state values are obtained by
following the two step procedure:
1.
2.
Obtain the binary values of each flip-flop input
equation in terms of the present state and
input variables.
Use the corresponding flip-flop characteristic
table to determine the next state.
17
Analysis with JK Flip Flops




JA = B
JB = x’
KA = Bx’
KB = A’x + Ax’ = A  x
18
JK Analysis: State Table
I.
Flip Flop Inputs
II.
JA = B
 KA = Bx’
 JB = x’
 KB = A’x + Ax’ = A  x

Use the Input
equations to
determine
the FF inputs.
Use the FF
inputs and
Table to
determine
the next
state.
JK Characteristic Table
19
JK Analysis State Table
Flip Flop Inputs
JA = B
 JB = x’
 KA = Bx’
 KB = A’x + Ax’ = A  x

20
JK Analysis: State Diagram
1
1
0
00
11
0
0
0
01
10
1
1
21
Analysis vs. Design
o
o
The analysis of sequential circuits
starts from a circuit diagram and
culminates in a state table or state
diagram.
The design of a sequential circuit
starts from a set of specifications and
we should obtain the state diagram
and finally the logic diagram.
22
Design Procedure
o
o
Design starts from a specification and results in a
logic diagram or a list of Boolean functions.
The steps to be followed are:
1.
Derive a state diagram
2.
Reduce the number of states
3.
Assign binary values to the states
4.
Obtain the binary coded state table
5.
Choose the type of flip flops to be used
6.
Use Excitation Tables to derive state table
7.
Derive the simplified flip flop input
equations and output equations
8.
Draw the logic diagram
23
Sequential Circuit Design
o
o
o
Remember that a synchronous sequential circuit is
made up of flip flops and combinational gates.
Part of the design is to choose the flip-flop
type and combinational circuit structure which,
together with the flip-flops produce a circuit
that fulfills the stated specification.
How many FLIP FLOPS?
1.
2.
3.
The number of flip-flops is determined from the
number of states in the circuit
n flip-flops can represent up to 2n binary states.
Examples:
1.
2.
3.
4.
2 states requires a single Flip Flop
4 states requires two flip flops
8 states requires three flip flops
7 states requires again three flip flops …
24
Designing with D Flip-Flops
Design a clocked
sequential circuit
that operates
according to the
state diagram. Use
D Flip Flops
25
Synthesizing Using D Flip Flops
o
o
o
The next step is to create a state table and then select two D
flip flops to represent the four states, labeling their outputs
as A and B.
There is one input, x, and one output, y, representing the
input sequence and the output value respectively.
Remember that the Excitation Table (characteristic equation)
of the D flip flop is
 Q(t + 1) = DQ
 This means that the next-state values in the state table
specify the D input condition for the flip flop.
26
Designing with D Flip-Flops
Input equations can be obtained directly from the table
using minterms:
 A(t + 1) = DA(A, B, x) = ∑m(2,4,5,6)
 B(t + 1) = DB(A, B, x) = ∑m(1,3,5,6)
27
Designing with D Flip-Flops
However, we have to minimize the
expression in a similar way used for
combinational logic design!
28
Designing with D Flip-Flops
29
Designing with D Flip-Flops
DA = AB’ + BX’
DB= A’X + B’X+ ABX’
Y = B’X
30
A Sequence Detector
Design a circuit that detects a sequence
of three ones. Use Moore Machine.
I.
Input
Create the state diagram
Output
Circuit Detects
`111’ at input
Moore Machine
31
Synthesizing Using D Flip Flops
II.
III.
IV.
The next step is to create a state table
and then select two D flip flops to
represent the four states, labeling their
outputs as A and B.
There is one input, x, and one output,
y, representing the input sequence and
the output value respectively.
The output y is `1’ only when we detect
the input sequence of `111’
32
State Table for Sequence Detector
Input equations can be obtained directly from the table
using minterms:
 A(t + 1) = DA(A, B, x) = ∑m(3, 5, 7)
 B(t + 1) = DB(A, B, x) = ∑m(1, 5, 7)
 y(A, B, x) = ∑m(6, 7)
33
Boolean Minimization
K-Maps can be used to minimize the
input equations, resulting in
o DA = Ax + Bx
o DB = Ax + B’x
o Y = AB
34
Logic Diagram of Sequence Detector
35
Sequential Circuits with different
Flip Flops (JK, T)
The design of sequential circuits other than
D type flip flops is complicated by the fact
that input equations must be derived
indirectly from the state table.
 It is necessary to derive a functional
relationship between the state table and
the input equations.
36
Excitation Table

During the design, we usually know the transition from
present to next state but we need to find the flip flop input
conditions that will cause the required transition.

We need a table that lists the required inputs for a
given change of state, called an excitation table.
37
Excitation Tables
Characteristic Table
Characteristic Table
Excitation Table
Excitation Table
38
Synthesis Using JK Flip Flops
Synthesis of circuits with JK flip flops
is the same as with D flip flops
 Except that the input equations must
be evaluated from the present-state to
the next-state transition derived from
the excitation table.
39
Example: JK Synthesis
Step #1: Obtain State Table
0
Example: No output
00
1
1
1
01
11
0
0
1
10
0
40
JK Synthesis: State Table
Present
State
Next
State
0
0
0
1
0
0
0
1
41
Cont .. Example JK Synthesis
Step #2: Use K-Maps
42
Cont .. Example JK Synthesis
Bx
00
01
11
10
0
0
0
0
1
1
X
X
X
X
A
JA = BX’
43
Cont .. Example JK Synthesis
44
Cont .. JK Synthesis Logic Diagram
45
Synthesis Using T Flip Flops
Synthesis of circuits with T flip flops is the
same as with JK flip flops … except that the
input equations must be evaluated from the
present-state to the next-state transition
derived from the T excitation table.
46
Synthesis Using T Flip Flops
Design a counter that counts from “000”
to “111” and then back to “000” again.
 Constraint: Use T Flip-Flops
47
A Counter using T Flip Flops
000
001
010
011
111
110
101
100
 Notice the only input is the clock!
48
Example: T Flip Flop Synthesis
0
49
Cont .. T Flip Flops
By using K-maps we can minimize the flip flop input equations.
1
T
A2
T
A1
T
A0
50
One Dimensional Tables
51
Two Dimensional Tables
Same thing, different layout
52
Example – Sequence Recognizer
(VHDL)
 Circuit has input: W and output: Z
 Recognizes sequence of 11 on W
 Specifically, if W has been 1 and next bit
is 1, make Z high
 Design a Moore and Mealy Machines
W
1010110111
Sequence
Recognizer
Z
53
Sequence Recognizer (Mealy)
Reset
w=1/z=0
A
B
w=0/z=0
w=0/z=0
w=1/z=1
Clk:
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
w:
0
1
0
1
1
0
1
1
1
0
1
z:
0
0
0
0
1
0
0
1
1
0
0
54
Mealy: Implementation
Reset
w=1/z=0
A
B
w=0/z=0
w=0/z=0
w=1/z=1
Clk:
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
w:
0
1
0
1
1
0
1
1
1
0
1
z:
0
0
0
0
1
0
0
1
1
0
0
55
-- (Mealy Machine of Sequence Recognizer)
library IEEE;
use IEEE.std_logic_1164.all;
entity SeqRec_Mealy is
port (reset, clk, w: in std_logic;
z: out std_logic);
end entity SeqRec_Mealy;
architecture behavioral of SeqRec_Mealy is
type statetype is (A, B); -- define new type
signal present_state, next_state: statetype;
Begin
clk_process: process(reset,clk)
begin
if reset = ‘1’ then -- Check for reset and initialize state
present_state <= A;
Elsif (rising_edge(clk)) then -- wait until the rising edge
present_state <= next_state;
end if;
end process clk_process;
end architecture behavioral;
next_out_process: process(present_state,w) is
begin
case present_state is -- depending upon current state
when A =>
-- set output signals and next state
if w = '0' then
next_state <= A;
z <= ‘0';
else
Reset
next_state <= B;
z <= '0';
end if;
when B =>
A
if w = '1' then
next_state <= B;
z <= ‘1';
w=0/z=0
else
next_state <= A;
z <= ‘0';
end if;
end case;
end process next_out_process;
w=1/z=0
B
w=0/z=0
w=1/z=1
56
Sequence Recognizer (Moore)
Reset
w=1
A/z=0
B/Z=0
w=0
w=0
w=1
w=0
C/z=1
w=1
Clk:
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
w:
0
1
0
1
1
0
1
1
1
0
1
z:
0
0
0
0
0
1
0
0
1
1
0
57
Moore: Implementation
Reset
w=1
A/z=0
B/Z=0
w=0
w=0
w=1
w=0
C/z=1
w=1
Clk
:
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
w:
0
1
0
1
1
0
1
1
1
0
1
z:
0
0
0
0
0
1
0
0
1
1
0
58
-- (Moore Machine of Sequence Recognizer)
library IEEE;
use IEEE.std_logic_1164.all;
entity SeqRec_Moore is
port (reset, clk, w: in std_logic;
z: out std_logic);
end entity SeqRec_Moore;
architecture behavioral of SeqRec_Moore is
type statetype is (A, B,C); -- define new type
signal present_state, next_state: statetype;
Begin
clk_process: process( reset, clk)
begin
if reset = ‘1’ then -- Check for reset and initialize state
present_state <= A;
Elsif (rising_edge(clk)) then -- wait until the rising edge
present_state <= next_state;
end if;
end process clk_process;
next_state_process: process( present_state, w) is
begin
case present_state is -- depending upon current state
when A =>
-- set next state
if w = '0' then
next_state <= A;
else
next_state <= B;
end if;
when B =>
if w = ‘0' then
next_state <= A;
else
next_state <= C;
end if;
when C =>
if w = ‘0’ then
next_state <= A;
else
next_state <= C;
end case;
end process next_state_process;
output_process: process( present_state) is
begin
case present_state is -- depending upon current state
when A =>
-- set output signals
z<= ‘0’;
when B =>
z<= ‘0’;
when C =>
z<= ‘1’;
end case;
end process output_process;
End architecture behavioral,
Reset
w=0
A/z=
0
w=1
w=0
B/Z=
0
w=1
w=0
C/z=1
w=1
59
T Flip Flop Analysis
 Analysis of a sequential circuit with
T flip flops follows the same
procedure outlined for JK flip flops.
 The next state values in the state
table can be obtained by using the
characteristic table or the
characteristic equation
 Q(t + 1) = T  Q = T’Q + TQ’
61
T Flip Flop Analysis Example
A
x
T
y
R
 TA = Bx
 TB = x
T
B
 Y = AB
R
CLK Reset
62
T Flip Flop Analysis State Table
 TA = Bx
 TB = x
 Y = AB
 A = Bx  A
 B(t + 1) = TB  B = x  B
 A(t + 1) = TA
63
Problem #1
 1. (Flip-Flops) a. What is the
difference between a latch and a flip
flop?
 b. Implement a JK flip-flop with a T
flip-flop and a minimal AND-OR-NOT
network. Let us assume that the
complements of J, K and Q signals
are available. Draw the logic diagram
to show your design.
64
Problem #2
65
Problem #3
a. Write state table
b. Design the system with two JK
flip-flops and a minimal AND-ORNOT network.
66
67