CHAP #06 - PART 1
MOS (Metal Oxide Semiconductor) Structure
In this lecture you will learn:
• The fundamental set of equations governing the behavior of NMOS
structure
• Accumulation, Flatband, Depletion, and Inversion Regimes
• Large signal and small signal models of the NMOS capacitor
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
MOS (Metal Oxide Semiconductor Field Effect Transistors (FETs)
Silicon MOS FET
Source
Gate
Drain
AlGaAs
InGaAs (Quantum Well)
GaAs (Substrate)
High Electron Mobility FET
100 nm
A 173 nm gate length MOS transistor
(INTEL)
22 nm gate length MOS transistors
(INTEL)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
1
A N-MOS (or NMOS) Capacitor Structure
Gate metal
contact
N+ Si Gate or Metal Gate
SiO2
x 0
+
VGB
_
x
Doping: Na
P-Si Substrate (or Bulk)
Metal contact
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Capacitor in 3D
L
Metal
W
N+N+
SiSi
Gate or
Gategate
Metal Gate
SiO2
x 0
+
VGB
_
x
P-Si substrate (or bulk)
Doping: Na
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
2
A NMOS Capacitor
N+ Si
or
Metal
Gate
SiO2
P-Si
 ox
s
 tox
Assumptions:
Doping: Na
0
x
1) The potential in the metal gate is M
If the gate is N+ Si then M  n
2) The potential deep in the P-Si substrate is  p
3) The oxide (SiO2) is insulating (zero conductivity; no free electrons and holes) and
is completely free of any charges
4) There cannot be any volume charge density inside the metal gate (it is very
conductive). But there can be a surface charge density on the surface of the metal
gate
5) Dielectric constants:
 ox  3.9 o
 s  11.7 o
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Capacitor in Equilibrium
+
Gate
- VGB  0
SiO2
P-Si
Doping: Na
 tox
0
x
Potential Plot:   x 
B  M   p
M
Potential?
B
 tox
0
Assume: B  0
p
x
We need to find the potential in equilibrium everywhere
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
3
A NMOS Capacitor in Equilibrium: Depletion Region
Step 1: Charges Flow
- VGB  0
+
Gate
SiO2
P-Si
Doping: Na
Quantum
tunneling
 tox
0
x
Step 2: Depletion region is created in the substrate near the oxide interface, and a
surface or sheet charge density is created on the metal gate
- VGB  0
+
- - - - - -
SiO2
Gate
 tox
-
- - - - - -
0
P-Si
Doping: Na
x do
Positive surface charge density (C/cm2)
x
Negative depletion charge density (C/cm3)
QG  qN a x do
  qN a
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Capacitor in Equilibrium: Charge Densities
- VGB  0
+
Gate
- - - - - -
SiO2
 tox
-
- - - - - -
P-Si
0
x do
0
x do
x
Charge density plot:
QG  qN a x do
 tox
x
 qNa
Total charge per unit area in
the semiconductor (C/cm2)
Depletion region charge
density (C/cm3)
QB  qN a x do
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
4
A NMOS Capacitor in Equilibrium: Electric Field
- VGB  0
+
Gate
- - - - - -
SiO2
 tox
-
0
- - - - - -
P-Si
x do
x
Electric field in the semiconductor:
qN a
dE x



s
s
dx
 E x x  
qN a
s
Boundary condition:
E x  x  x do   0
 x do  x 
Linearly varying
E x x  0 
E x 
 tox
x do
0
qN a
s
x do
x
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
Some Electrostatics
Consider an interface between media of different dielectric constants:
1
2


E1 E2


Suppose you know E 1 , can you find E 2 ???
Use the principle: The product of the dielectric constant and the normal
component of the electric field on both sides of an interface are related as
follows:


 2 E 2  1 E 1
Interface sheet
 QI  charge density
(C/cm2)


• Note that E 1 is the electric field JUST to the left of the interface and E 2 is the
electric field JUST to right of the interface
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
5
A NMOS Capacitor in Equilibrium: Electric Field
- VGB  0
+
Gate
- - - - - -
SiO2
 ox
 tox
-
- - - - - -
0
P-Si
s
x do
Electric field in the oxide:
dE x


0
 ox
dx
x




 qNa xdo
E x  0 
 E x  x   constant
 E x x  

 ox E x  0    s E x  0 

E x 0
qN a x do
 ox
s

 
qN a x do
ox
E x 
 tox
x do
0
x
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Capacitor in Equilibrium: Potential
- VGB  0
+
Gate
- - - - - -
SiO2
 ox
 tox
0
-
- - - - - -
P-Si
s
x do
x
Potential in the semiconductor:
qN a
d  x 
 x do  x 
 E x  x   
dx
s
 x   p 
Boundary condition:
   x  xdo   p
qN a
 x do  x 2
2 s
M
 tox
0
x do
p
x
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
6
A NMOS Capacitor in Equilibrium: Potential
- VGB  0
+
Gate
- - - - - -
SiO2
 ox
 tox
-
- - - - - -
0
s
x do
Potential in the oxide:
qN a x do
d  x 
 E x  x   
 ox
dx
 x   p
P-Si
x
Boundary condition:
2
   x  0  p  qN2ax do
s
2
qN a x do
qN a x do


x
2 s
 ox
M
 tox
0
x
p
x do
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Capacitor in Equilibrium: Potential
- VGB  0
+
Gate
- - - - - -
SiO2
 ox
 tox
M
-
- - - - - -
0
x do
0
x do
P-Si
s
x
B
 tox
Must have:
  x  t ox    p 
2
qN a x do
qN a x do

t ox  M
2 s
 ox
Therefore:
x do  
s
Cox
2
 2 
  
  s    s B
 qN a 
 Cox 
p
x
B  M   p
Oxide capacitance
(per unit area):
Cox 
 ox
t ox
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
7
A NMOS Capacitor in Equilibrium: Potential
- VGB  0
+
Gate
- - - - - -
SiO2
 ox
 tox
-
- - - - - -
0
P-Si
s
x do
x
M
B
VOX
VS
 tox
x do
0
B  VOX  VS

qNa xdo
 ox
x
p
Oxide capacitance
(per unit area)
2
2
qNa xdo
qNa xdo qNa x do
tox 


Cox
2 s
2 s
Cox 
 ox
t ox
Potential drop in
the semiconductor
Potential drop
in the oxide
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: VGB > 0
-VGB  0
+
Gate
- - - - - -
SiO2
 ox
 tox
-
- - - - - - - - - - -
P-Si
s
x do x d
0
x
All of the applied bias falls across the depletion region and the oxide
B  VGB
x do
B
 tox
xd
p
0
B  VGB  VOX  VS
qNa x d qNa x d2


Cox
Potential drop
in the oxide
2 s
x
The depletion region widens
and the oxide field increases
when VGB is positive
Potential drop in
the semiconductor
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
8
A Biased NMOS Capacitor: VGB < 0
- VGB  0
+
Gate
- - - - - -
SiO2
 ox
 tox
-
- - - - - -
0
P-Si
s
x d x do
x
All of the applied bias falls across the depletion region and the oxide
B
xd
x do
B  VGB
 tox
0
B  VGB  VOX  VS
The depletion region shortens
and the oxide field decreases
when VGB is negative
qNa x d qNa x d2


2 s
Cox
Potential drop
in the oxide
x
p
Potential drop in
the semiconductor
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: VGB < 0
- VGB  0
+
Gate
- - - - - -
SiO2
 ox
 tox
0
-
- - - - - -
P-Si
s
x d x do
x
All of the applied bias falls across the depletion region and the oxide
xd
B  VGB
 tox
x do
0
x
p
The depletion region shrinks and the oxide field also decreases for VGB < 0
xd  
s
2
  
 2 
  s    s B  VGB 
Cox
 Cox 
 qN a 
Eox 
qN a x d
 ox
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
9
A Biased NMOS Capacitor: Flatband Condition
+
Gate
- VGB  0
SiO2
P-Si
 ox
s
 tox
0
x
When VGB is sufficiently negative, the depletion region thickness shrinks to zero
This value of VGB is called the flatband voltage VFB
Potential in flatband
condition:
 tox
0
x
p
Flatband voltage can be found by letting VGB equal to VFB and setting xd equal to 0 :
2
  
 2 
  s    s B  VFB   0
Cox
C
 ox 
 qN a 
V FB B   M   p 
xd  
s
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Accumulation (VGB < VFB)
+
Gate
P-Si
SiO2
 ox
Potential:
- VGB  VFB
s
 tox
0
 tox
0
x
Charge accumulation (due to holes) on the
semiconductor surface
x
p
B  VGB
The entire potential drop for VGB < VFB falls across the oxide:
Oxide Field and Potential: Eox tox  VOX
Eox tox  VOX
 QP
 ox
 VOX  VGB  VFB
 VGB  VFB  VOX
 ox Eox  QP
Semiconductor Accumulation Charge:
tox
B  VGB  VOX
QG
 ox
QP
 QP  Cox VGB  VFB 
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
10
A Biased NMOS Capacitor: Accumulation (VGB < VFB)
- VGB  VFB
+
Gate
P-Si
SiO2
 ox
Potential:
s
 tox
0
 tox
0
x
Charge accumulation (due to holes) on the
semiconductor surface
x
p
B  VGB
Charge Density:
Total charge per unit area in the hole accumulation layer
QP  Cox VGB  VFB 
 tox
QG  Cox VGB  VFB 
0
x
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Charges
Depletion Region
Charge (C/cm2)
QB
VFB
VGB
QB  qN a x d
Accumulation
Layer Charge
(C/cm2)
xd  
s
2
  
 2 
  s    s B  VGB 
Cox
C
 ox 
 qN a 
QP
VFB
VGB
QP  Cox VGB  VFB 
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
11
A Biased NMOS Capacitor: VGB > 0
-VGB  0
+
Gate
- - - - - -
SiO2
 ox
 tox
-
- - - - - - - - - - -
P-Si
s
x do x d
0
x
All of the applied bias falls across the depletion region and the oxide
B  VGB
x do
B
 tox
xd
0
B  VGB  VOX  VS
The depletion region widens
and the oxide field increases
with VGB for VGB > VFB
qNa x d qNa x d2


2 s
Cox
x
p
Potential drop
in the oxide
Potential drop in
the semiconductor
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Depletion (VGB > VFB)
V
- GB
+
Gate
- - - - - -
SiO2
 ox
 tox
-
- - - - - -
0
 VFB
P-Si
s
xd
x
  x  0  S   p 
Surface potential s
B  VGB
 tox
VGB  VFB 
qN a x d2
2 s
p
xd
0
x
qN a x d qN a x d2

2 s
Cox
 VGB  VFB  s   p 
2 s qN a  s   p 
Cox
Potential drop in
the semiconductor
Potential drop
in the oxide
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
12
A Biased NMOS Capacitor: Surface Potential
s
VGB
p
VFB
 s   p
VGB  VFB

2  sqNa s   p
VGB  VFB  s   p 

VFB  VGB
Cox
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor
V
- GB
+
Gate
- - - - - -
SiO2
 ox
 tox
-
0
- - - - - -
 VFB
P-Si
s
xd
x
VGB  VFB  VOX  VS
VGB  VFB 
qNa xd qNa xd2

2 s
Cox
VOX
VGB  VFB  s   p 
VS
VS
Same equation written
in 3 different ways
valid for:
VFB  VGB  VTN

2  sqNa s   p

Cox
VOX
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
13
A Biased NMOS Capacitor: Electron Density (VGB > VFB)
  x  0  S
B  VGB
 tox
0
VGB  VFB  s   p 
x
p
xd

2  sqNa s   p

Cox
• As VGB is increased, S also increases
• The electron density in the semiconductor depends on the potential as:
q p q   x  p 
q   x  p 
q  x 

KT
KT
n  x   ni e KT  ni e KT e
 Nae
Electron density is the largest right at the surface of the semiconductor where
the potential is the highest
n x  0  N ae

q s  p

KT
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Threshold Condition
n  x  0  Na e

q s  p

KT
When:
  x  0   S   p
n x  0  N ae
B  VGB
 tox
0
xd

q s  p
p
KT

 Na
x
• When VGB is increased and the surface potential S reaches -p the electron
density at the surface becomes comparable to the hole density in the substrate and
cannot be ignored
• The gate voltage VGB at which S equals -p is called the threshold voltage VTN:
VTN  VFB  2 p 
2 s qN a  2 p 
Cox
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
14
A Biased NMOS Capacitor: Inversion (VGB > VTN)
- VGB  VTN
+
Gate
- - - - - -
SiO2
 ox
 tox
-
- - - - - -
0
P-Si
s
xd
x
Inversion layer charge (due to electrons)
on the semiconductor surface
• When the gate voltage VGB is increased above VTN the electron density right at
the surface increases (exponentially with the surface potential S )
• This surface electron density is called the inversion layer (assumed to be of zero
thickness in this course)
QN  Inversion layer charge density (C/cm2)
QG  qN a x d  QN
xd
0
 tox
x
 qNa
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Inversion (VGB > VTN)
B  VGB
  x  0   S   p
B  VTN
x
p
x d max
 tox
0
• When the gate voltage VGB is increased above VTN the inversion layer charge
increases so rapidly that the extra applied potential drops entirely across the oxide, and
the surface potential S remains close to -p
• Consequently, the depletion region thickness (and the depletion region charge) does
not increase when the gate voltage VGB is increased above VTN
S   p
qN a x d2

 2
2 s
p
qN a x d2 max

2 s
VTN  VFB  2 p 
2 s qN a  2 p 
Cox
qN a x d max qN a x d2 max
 VTN  VFB 

Cox
2 s
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
15
A Biased NMOS Capacitor: Surface Potential
s
 p
VGB
 p
VTN
VFB
s   p
VGB  VFB
VGB  VFB  s   p 

2  sqNa s   p

VFB  VGB  VTN
Cox
VGB  VTN
s   p
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Inversion (VGB > VTN)
- VGB  VTN
+
Gate
- - - - - -
SiO2
 ox
 tox
0
-
- - - - - -
P-Si
QN
s
x d max
x
How to calculate the inversion layer charge QN when VGB > VTN?
Start from: VGB  VFB  Vox  VS
 Eox t ox 
qN a x d2 max
2 s
VS 
qN a x d2 max
2 s
By Gauss’ law:   ox Eox  QN  qN a x d max
Therefore:
VGB  VFB  
 VGB  
QN qN a x d max qN a x d2 max


2 s
Cox
C ox
QN
 VTN
Cox
 QN  Cox VGB  VTN 
Inversion layer charge increases linearly with
the gate voltage above threshold
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
16
A Biased NMOS Capacitor: Charges
QB
Depletion Region
Charge (C/cm2)
VFB
VTN
VGB
QB  qNa x d
QB  qNa x d max
QN
Inversion Layer
Charge (C/cm2)
VFB
VTN
VGB
QN  Cox VGB  VTN 
Accumulation
Layer Charge
(C/cm2)
QP
VFB
VTN
QP  Cox VGB  VFB 
VGB
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A N-MOS (or NMOS) Capacitor Structure
Gate metal
contact
N+ Si Gate or Metal Gate
SiO2
x 0
+
VGB
_
x
P-Si Substrate (or Bulk)
Doping: Na
Metal contact
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
17
A Biased NMOS Capacitor: Charges
Gate Charge (C/cm2)
(Must be equal and opposite
to the total semiconductor
charge)
QG
VTN
VFB
VGB
Capacitance of a NMOS Capacitor:
C
C
dQG
dVGB
Cox
Cox
Accumulation
Inversion
Depletion
VGB
VTN
VFB
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
The Small Signal Capacitance of a NMOS Capacitor
• The small signal capacitance (per unit area) of the MOS capacitor is defined
as:
C
dQG
dVGB
where QG is the charge density (units: C/cm2) on the gate
(1) Accumulation (VGB < VFB):
QG  Cox VGB  VFB 

C  Cox
v gb
Cox
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
18
The Small Signal Capacitance of a NMOS Capacitor
(2) Depletion (VTN >VGB > VFB):
QG  qN a x d
C
dQG
dx d
 qN a
dVGB
dVGB
Differentiate the equation (derived earlier):
qN a x d2 qN a x d

 VGB  VFB
2 s
Cox
xd  
s
2
  
 2 
  s    s B  VGB 
Cox
 Cox 
 qN a 
1 
x
To get:  d 
qN a dx d  dVGB
  s Cox 
Define: Cb 
Finally:
s
xd
Cox
v gb
1
1
1


C Cox Cb
Cb
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
The Small Signal Capacitance of a NMOS Capacitor
(3) Inversion (VGB > VTN):
QG  qN a x d max  QN
QN  Cox VGB  VTN 
dQG
dQN
C

dVGB
dVGB
xdmax does not change with VGB above threshold
 Cox
v gb
Cox
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
19
The Small Signal Capacitance of a NMOS Capacitor
C
Cox
Cox
Accumulation
Inversion
Depletion
VGB
VTN
VFB
P-Si
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Capacitor with a Channel Contact
SiO2
N-Si
+
+
VGB
VCB
_
_
Gate metal
contact
Gate
N-Si
Inversion layer
P-Si Substrate (or Bulk)
Metal contact
• In the presence of an inversion layer, the additional contacts allow one to directly
change the potential of the inversion layer channel w.r.t. to the bulk (substrate)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
20
A Biased NMOS Capacitor: Inversion with VCB ≠0
B  VGB
  x  0   S   p  VCB
  x  0   S   p
 tox
0
x d max x d max (VCB  0)
x
p
• We had said that the surface potential S remains fixed at –p when VGB is
increased beyond VTN
• But with a non-zero VCB, the surface potential S in inversion can be changed to
(–p+ VCB)
• The new value of the depletion region width is:
qN a x d2
qN a x d2 max
 2 p  VCB 
2 s
2 s
Question: How do we now find the inversion layer charge QN when VCB is not zero?
S   p 
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Surface Potential
s
gate
+
source
drain
+
VGB
VCB
-
-
  p  VCB
VCB
 p
VGB
 p
VTN
VFB
 s   p
VGB  VFB
VGB  VFB  s   p 

2  sqNa s   p
Cox
s   p  VCB

VFB  VGB  VTN
VGB  VTN
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
21
A Biased NMOS Capacitor: Inversion with VCB ≠0
- VGB
+
Gate
- - - - - -
SiO2
 ox
-
- - - - - -
P-Si
QN
s
- VCB
+
 tox
0
x d max
x
How to calculate the inversion layer charge QN? Same way as before……..
Start from: VGB  VFB  Vox  VS
 Eox t ox 
qN a x d2 max
2 s
VS 
qN a x d2 max
2 s
By Gauss’ law:   ox Eox  QN  qN a x d max
Therefore: VGB  VFB  
 VGB  
QN qN a x d max qN a x d2 max


Cox
C ox
2 s
qN a x d max qN a x d2 max
QN
 VFB 

Cox
C ox
2 s
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Inversion with VCB ≠0
- VGB
+
Gate
- - - - - -
SiO2
 ox
-
- - - - - -
P-Si
QN
s
+
 tox
VGB  
QN
 VFB
Cox
0
x d max
- VCB
x
qN a x d max qN a x d2 max


C ox
VTN  VFB 
2 s
qN a x d max qN a x d2 max

Cox
2 s
 VFB  2 p  VCB 
 QN  Cox VGB  VTN 
2 s qN a  2 p  VCB 
Cox
Same as before but now VTN depends on VCB
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
22
NMOS Capacitor: Effect of VCB (VGB > VTN)
gate
+
gate
+
VGB
source
drain
drain
source
+
VGB
VCB
-
-
VCB >0
• Inversion charge decreases
• Depletion region expands
-
gate
+
source
drain
+
VGB
VCB
-
-
VCB <0
• Inversion charge increases
• Depletion region shrinks
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
23
CHAP #06 - PART 2
MOS (Metal Oxide Semiconductor) Structures
In this lecture you will learn:
• The fundamental set of equations governing the behavior of PMOS
capacitors
• Accumulation, Flatband, Depletion, and Inversion Regimes
• Small signal models of the PMOS capacitor
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
MOS (Metal Oxide Semiconductor Field Effect Transistors (FETs)
MOS FET
Source
Gate
Drain
AlGaAs
InGaAs (Quantum Well)
GaAs (Substrate)
High Electron Mobility FET
100 nm
A 173 nm gate length MOS transistor
(INTEL)
22 nm gate length MOS transistors
(INTEL)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
1
A P-MOS (or PMOS) Capacitor
Gate metal
contact
P+ Si Gate or Metal Gate
SiO2
x 0
+
VGB
_
x
Doping: Nd
N-Si Substrate (or Bulk)
Metal contact
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor
P+ Si
or
Metal
Gate
Assumptions:
SiO2
N-Si
 ox
s
 tox
0
Doping: Nd
x
1) The potential in the metal gate is M
If the gate is P+ Si then M   p
2) The potential deep in the p-Si substrate is  p
3) The oxide (SiO2) is insulating (near zero conductivity; no free electrons and holes)
and is completely free of any charges
4) There cannot be any volume charge density inside the metal gate (it is very
conductive). But there can be a surface charge density on the surface of the metal
gate
5) Dielectric constants:
 ox  3.9 o
 s  11.7 o
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
2
A PMOS Capacitor in Equilibrium
- VGB  0
+
Gate
SiO2
N-Si
Doping: Nd
 tox
0
x
Potential Plot:   x 
B  M  n
Assume: B  0
Potential?
 B
M
 tox
n
x
0
We need to find the potential in equilibrium everywhere
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor in Equilibrium: Depletion Region
Step 1: Charges Flow
- VGB  0
+
Gate
SiO2
N-Si
Doping: Nd
Tunnel
 tox
0
x
Step 2: Depletion region is created in the substrate and a surface or sheet charge
density on the metal gate
- VGB  0
+
SiO2
Gate
 tox
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
0
Negative surface charge density (C/cm2)
QG  qNd x do
N-Si
Doping: Nd
x do
x
Positive depletion charge density (C/cm3)
  qNd
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
3
A PMOS Capacitor in Equilibrium: Charge Densities
- VGB  0
+
Gate
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
SiO2
 tox
0
N-Si
x do
x
Charge density plot:
qNd
 tox
x do
0
x
QG  qNd x do
Total charge per unit area in
the semiconductor (C/cm2)
QB  qNd x do
Depletion region charge
density (C/cm3)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor in Equilibrium: Electric Field
- VGB  0
+
Gate
SiO2
 tox
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
0
N-Si
x do
x
Electric field in the semiconductor:
dE x
 qNd


dx
s
s
 E x x  
qNd
s
 tox
E x  x  x do   0
 x  x do 
0
Linearly varying
x do
E x 
x
E x  x  0  
qNd
s
x do
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
4
Some Electrostatics
Consider an interface between media of different dielectric constants:
1
2


E1 E2


Suppose you know E 1 , can you find E 2 ???
Use the principle: The product of the dielectric constant and the normal
component of the electric field on both sides of an interface are related as
follows:


 2 E 2  1 E 1
Interface sheet
charge density
 QI 


• Note that E 1 is the electric field JUST to the left of the interface and E 2 is the
electric field JUST to right of the interface
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor in Equilibrium: Electric Field
- VGB  0
+
Gate
SiO2
 tox
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
0
x do
Electric field in the oxide:


E x0
 E x  x   constant



   E x  0  
 

s
qNd x do
 E x  0  
qNd x do
 ox
 tox
x
 ox E x  0
dE x


0
 ox
dx
 E x x   
N-Si
s
qNd x do
 ox
 Eox
x do
0
E x 
x
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
5
A PMOS Capacitor in Equilibrium: Potential
- VGB  0
+
Gate
SiO2
 tox
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
0
N-Si
x do
x
Potential in the semiconductor:
qNd
d  x 
 x  x do 
 E x  x   
s
dx
  x   n 
   x  x do   n
qNd
 x  x do 2
2 s
n
 tox
0
x
x do
Start integrating the field – beginning
from the substrate (bulk) – to find the
potential
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor in Equilibrium: Potential
- VGB  0
+
Gate
SiO2
 tox
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
0
N-Si
x do
x
Potential in the oxide:
qNd x do
d  x 
 E x  x  
 ox
dx
  x   n
2
   x  0  n  qNd x do
2 s
2
qNd x do
qNd x do


x
2 s
 ox
n
 tox
0
x do
x
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
6
A PMOS Capacitor in Equilibrium: Potential
- VGB  0
+
Gate
SiO2
 tox
 tox
B
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
0
N-Si
x do
0
n
x
x
x do
M
Must have:
  x  t ox   n 
2
qNd x do
qNd x do

t ox  M
2 s
 ox
Therefore:
x do  
2
s
Cox
 2 
  
  s    s  B 
 qNd 
 Cox 
B  M  n
Oxide capacitance
(per unit area)
Cox 
 ox
t ox
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor in Equilibrium: Potential
- VGB  0
+
Gate
SiO2
 tox
B
 tox
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
0
0
N-Si
x do
x
x do
Eox  
M
 B  Vox  VS  Eox t ox  VS
2
qNd x do qNd x do
 B 

Cox
2 s
Potential drop
in the oxide
n
Potential drop in
the semiconductor
x
qNd x do
 ox
B  M  n
Oxide capacitance
(per unit area)
Cox 
 ox
t ox
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
7
A Biased PMOS Capacitor: VGB > 0
- VGB  0
+
Gate
SiO2
 ox
 tox
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
N-Si
s
x d x do
0
x
All of the applied bias falls across the depletion region and the oxide
 tox
B  VGB
n
0
xd
x do
x
B
 B  VGB 
qNd x d qNd x d2

2 s
Cox
Potential drop
in the oxide
Potential drop in
the semiconductor
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: VGB > 0
- VGB  0
+
Gate
SiO2
 ox
 tox
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
0
N-Si
s
x d x do
x
All of the applied bias falls across the depletion region and the oxide
B  VGB
 tox
n
0
xd
x do
x
The depletion region shrinks and the oxide field also decreases for VGB > 0
xd  
s
2
  
 2 
  s    s  B  VGB 
Cox
 Cox 
 qNd 
Eox  
qN a x d
 ox
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
8
A Biased PMOS Capacitor: Flatband Condition
+
Gate
- VGB  0
SiO2
N-Si
 ox
s
 tox
0
x
When VGB is sufficiently positive, the depletion region thickness shrinks to zero
This value of VGB is called the flatband voltage VFB
Potential in flatband
condition:
n
 tox
0
x
Flatband voltage:
2
  
 2 
  s    s  B  VFB   0
Cox
C
 ox 
 qNd 
V FB B   M  n 
xd  
s
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: Accumulation (VGB > VFB)
+
Gate
N-Si
SiO2
 ox
s
 tox
Potential:
- VGB  VFB
0
x
Charge accumulation (due to electrons) on
the semiconductor surface
B  VGB
n
 tox
0
x
The entire potential drop for VGB > VFB falls across the oxide
Charge Density:
QG  Cox VGB  VFB 
Total charge per unit area in the electron
accumulation layer
0
QN  Cox VGB  VFB 
 tox
x
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
9
A Biased PMOS Capacitor: Depletion (VGB < VFB)
- VGB  VFB
+
Gate
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
SiO2
 ox
 tox
s
xd
0
 tox
N-Si
x
n
xd
0
x
B  VGB
 B  VGB  Vox  VS
VGB  VFB
The depletion region widens
and the oxide field also
increases for VGB < VFB
qNd x d qNd x d2


2 s
Cox
Potential drop
in the oxide
Potential drop in
the semiconductor
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: Depletion (VGB < VFB)
- VGB  VFB
+
Gate
SiO2
 ox
 tox
 tox
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
0
N-Si
s
xd
n
xd
0
x
B  VGB
VGB  VFB  
x
  x  0   S  n 
qNd x d2
2 s
qNd x d qNd x d2

Cox
2 s
 VGB  VFB   s  n 
2 s qNd   s  n 
Cox
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
10
A Biased PMOS Capacitor: Hole Density
 tox
n
xd
0
x
B  VGB
  x  0   S
VGB  VFB   s  n 
2  s qNd  s  n 
Cox
• As VGB is decreased, S also decreases
• The hole density in the semiconductor depends on the potential as:
p  x   ni e

q  x 
qn q    x n 
q    x n 
KT  n e KT e
KT
KT

N
e
i
d
Hole density is the largest right at the surface of the semiconductor where the
potential is the lowest
p  x  0   Nd e
q  s n 
KT
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: Threshold Condition
 tox
n
0
x
xd
  x  0   S  n
B  VGB
p  x  0   Nd e
q  s n 
KT
N
d
• When VGB is decreased and the surface potential S reaches -n the positive hole
charge density at the surface becomes comparable to the positive charge density in
the depletion region and cannot be ignored
• The gate voltage at which S equals -n is called the threshold voltage VTP:
VTP  VFB  2n 
2 s qNd 2n 
Cox
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
11
A Biased PMOS Capacitor: Inversion (VGB < VTP)
- VGB  VTP
+
Gate
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
SiO2
 ox
 tox
0
N-Si
s
xd
x
Inversion layer charge (due to holes) on
the semiconductor surface
• When the gate voltage VGB is decreased below VTP the hole density right at the
surface increases (exponentially with the decrease in the surface potential S )
• This surface hole density is called the inversion layer (assumed to be of zero
thickness in this course)
QP  Inversion layer charge density (C/cm2)
 qNd
 tox
0
QG  qNd x d  QP
xd
x
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: Inversion (VGB < VTP)
 tox
n
0
x
x d max
B  VTP
  x  0   S  n
B  VGB
• When the gate voltage VGB is decreased below VTP the inversion layer charge increases
so rapidly that the extra applied potential drops entirely across the oxide, and the surface
potential S remains close to -n
• Consequently, the depletion region thickness (and the depletion region charge) does
not increase when the gate voltage VGB is decreased below VTP
S  n  
qNd x d2
qNd x d2 max
 2n 
2 s
2 s
2 s qNd 2n 
Cox
qNd x d max qNd x d2 max
 VTP  VFB 

Cox
2 s
VTP  VFB  2n 
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
12
A Biased NMOS Capacitor: Inversion (VGB < VTP)
- VGB  VTP
+
Gate
SiO2
 ox
 tox
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
0
N-Si
QP
s
xd
x
How to calculate the inversion layer charge QP when VGB < VTP?
Start from: VFB  VGB  Vox  VS
  Eox t ox 
qN a x d2 max
2 s
VS 
qNd x d2 max
2 s
By Gauss’ law:   ox Eox  QP  qNd x d max
Therefore:
VFB  VGB  
 VGB  
QP qNd x d max qNd x d2 max


2 s
Cox
C ox
QP
 VTP
Cox
 QP  Cox VGB  VTP 
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: Summary of Different Regimes
Flatband (VGB = VFB):
No depletion region in the semiconductor and no accumulation charge
Accumulation (VGB > VFB):
No depletion region in the semiconductor but majority carrier accumulation charge
on the surface of the semiconductor
Depletion (VTP < VGB < VFB):
Depletion region in the semiconductor but no majority carrier accumulation charge
or minority carrier inversion charge on the surface of the semiconductor
Inversion (VGB < VTP):
Depletion region in the semiconductor and minority carrier inversion charge on the
surface of the semiconductor
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
13
A Biased PMOS Capacitor: Charges
QB
Depletion Region
Charge (C/cm2)
VTP
QB  0
VFB
QB  qNd x d max  2 s qNd 2n 
VGB
2


  
 2 
 

QB  qNd x d  qNd   s   s    s VGB  VFB  
C
C
qN




ox
ox
d


QP
Inversion Layer
Charge (C/cm2)
VTP
QP  Cox VGB  VTP 
VFB
QN  0
QN  0
VGB
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: Charges
Accumulation
Layer Charge
(C/cm2)
QN
VTP
QN  0
VFB
VGB
QN  0
QN  Cox VGB  VFB 
Gate Charge
(C/cm2)
QG
VTP
VFB
VGB
QG  QP  QN  QB
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
14
The Small Signal Capacitance of a PMOS Capacitor
• The small signal capacitance (per unit area) of the MOS capacitor is defined
as:
C
dQG
dVGB
where QG is the charge density (units: C/cm2) on the gate
(1) Accumulation (VGB > VFB):
QG  Cox VGB  VFB 

C  Cox
v gb
Cox
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
The Small Signal Capacitance of a PMOS Capacitor
(2) Depletion (VTP <VGB < VFB):
QG  qNd x d
C
dQG
dx d
 qNd
dVGB
dVGB
Differentiate the equation (derived earlier):
qNd x d2 qNd x d

 VGB  VFB
Cox
2 s
 xd
1 

To get: 
qNd dx d  dVGB
  s Cox 
Define: Cb 
s
xd
v gb
Cox
Cb
1
1
1


Finally:
C Cox Cb
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
15
The Small Signal Capacitance of a PMOS Capacitor
(3) Inversion (VGB < VTP):
QG  qNd x d max  QP
QP  Cox VGB  VTP 
dQG
dQP
C

dVGB
dVGB
xdmax does not change with VGB in inversion
 Cox
v gb
Cox
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
The Small Signal Capacitance of a PMOS Capacitor
QG
Gate Charge
(C/cm2)
VTP
C
VFB
VGB
dQG
dVGB
C
Cox
Cox
Inversion
Accumulation
Depletion
VTP
VFB
VGB
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
16
A PMOS Capacitor with a Channel Contact
SiO2
Gate metal
contact
Gate
P-Si
+
+
VGB
VCB
_
_
P-Si
Inversion layer
N-Si Substrate (or Bulk)
Metal contact
• In the presence of an inversion layer, the additional contacts allow one to directly
change the potential of the inversion layer channel w.r.t. to the bulk (substrate)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: Inversion with VCB ≠0
 tox
0
x d max x d max (VCB  0)
n
x
  x  0  S  n
B  VGB
  x  0  S  n  VCB
• We had said that the surface potential S remains fixed at –n when VGB is
decreased below VTP
• But with a non-zero VCB, the surface potential S in inversion can be changed to
(–n+ VCB)
• The new value of the depletion region width is:
qNd x d2
qNd x d2 max
 2n  VCB  
2 s
2 s
Question: How do we now find the inversion layer charge QP when VCB is not zero?
 s  n  
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
17
A Biased NMOS Capacitor: Inversion with VCB ≠0
+
Gate
SiO2
 ox
- VGB  VTP
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
N-Si
QP
s
+
 tox
0
x d max
- VCB
x
How to calculate the inversion layer charge QP? Same way as before……..
Start from: VFB  VGB  Vox  VS
  Eox t ox 
qNd x d2 max
2 s
VS 
qN a x d2 max
2 s
By Gauss’ law:   ox Eox  QP  qNd x d max
Therefore:
VFB  VGB 
VGB  
QP qNd x d max qNd x d2 max


Cox
C ox
2 s
qNd x d max qNd x d2 max
QP
 VFB 

Cox
C ox
2 s
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Inversion with VCB ≠0
+
Gate
SiO2
 ox
- VGB  VTP
+ + + + +
+ + + + +
+ + + + +
+ + + + +
+ + + + +
N-Si
QP
s
+
 tox
VGB  
QP
 VFB
Cox
0
x d max
- VCB
x
qN a x d max qN a x d2 max


C ox
VTP  VFB 
2 s
qNd x d max qNd x d2 max

Cox
2 s
 VFB  2n  VCB 
 QP  Cox VGB  VTP 
2 s qNd 2n  VCB 
Cox
Same as before but now VTP depends on VCB
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
18
PMOS Capacitor: Effect of VCB (VGB < VTP)
gate
+
gate
+
VGB
source
drain
drain
source
+
VGB
VCB
-
-
VCB <0
• Inversion charge decreases
• Depletion region expands
-
gate
+
source
drain
+
VGB
VCB
-
-
VCB >0
• Inversion charge increases
• Depletion region shrinks
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
19
CHAP #06 - PART 3
NMOS Field Effect Transistor (NMOSFET or NFET)
In this lecture you will learn:
• The operation and working of the NMOS transistor
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Capacitor with a Channel Contact
metal contact
(N+ Si) Gate
N-Si
+
+
VGB
VCB
_
_
N-Si
Inversion layer
P-Si substrate
metal contact
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
1
NMOS Capacitor: Effect of VCB (VGB > VTN)
Gate
+
-
-
VCB >0
• Inversion charge decreases
• Depletion region expands
Drain
Source
+
VCB
Gate
+
Drain
Source
VGB
VGB
-
gate
+
Inversion layer charge:
QN  Cox VGB  VTN 
Drain
Source
+
VGB
VCB
-
-
Depends on VCB
VCB <0
• Inversion charge increases
• Depletion region shrinks
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Transistor
VGB  VGS  VSB
VDB  VDS  VSB
_
_
VDS
+
VGS +
Source
Drain
Gate
N-Si
N-Si
+
VSB
_
y 0
y L
y
P-Si Substrate (or Bulk)
Basic Idea: Current can be made to flow in the inversion layer by applying
a voltage across it in the horizontal direction
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
2
A Note on Voltage Symbols
VCB = VC - VB = -( VB - VC ) = - VBC
VGS = VG - VS
= VG - VB + VB - VS
= VGB - VSB
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Transistor in 3D
Metal (typically Silicide)
contacts
W
N+
Poly-Si
N+Gate
Si gate
Gate
N-Si
Source
N-Si
Drain
L
P-Si substrate
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
3
A NMOS Transistor: Circuit Symbols
+
VDS
Drain
_
Gate
+
VGS
_
+
VDS
+
VDS
Drain
_
Gate
+
VGS
_
_
Source
VSB
+
_
Source
VSB
+
Drain
_
Bulk
Bulk
Gate
+
VGS
_
Bulk
_
Source
VSB
+
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
MOS Transistor: The Gradual Channel Approximation
• The operation of the MOS transistor is best understood under the “gradual
channel approximation” which assumes that:
“Electrostatics of the MOS transistor in the horizontal direction have nothing
to do with the electrostatics in the vertical direction”
• This assumption decouples the 2-dimensional complicated problem into two
1-dimensional simpler problems – one for the vertical direction and one for
the horizontal direction.
• The electrostatics in the vertical direction
have already been worked out by us in the
context of the MOS capacitor
• In this lecture we will work out the
electrostatics in the horizontal direction
and calculate the current flow
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
4
A NMOS Transistor: Channel Potentials
_
_
VDS
+
VGS +
Source
Drain
Gate
N-Si
N-Si
+
VSB
y 0
_
y L
y
P-Si Substrate (or Bulk)
s y  L    p  VCB y  L 
 s y  0    p  VCB y  0 
  p  VDB   p  VDS  VSB
  p  VSB
Potential drop in the channel:
s y  L   s y  0   VDS
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NMOS Transistor: Current Flow
Gate
Current in the inversion channel at the location y is:
I D  W QN y  v y y 
Source
Drain
ID
y L
y 0
QN y   Inversion layer charge (C/cm2)
v y y   Drift velocity of inversion layer charge (cm/s)
VDS
ID
Drift velocity of electrons is:
-
+
VGS
v y y     n E y y 
E y y   Horizontal component of the electric field (V/cm)
Therefore:
I D  W QN y   n E y y 
Gate
Source
y 0
+
VSB
Note: positive
direction of current
is when the current
flows from the drain
to the source
Drain
E y y 
y L
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
5
NMOS Transistor: Current Flow
Let the potential in the channel from the source to the drain
end be written as:
Gate
s  y   p  VCB y 
 s y 
Source
At the source end: VCB  y  0   VSB
y L
y 0
At the drain end: VCB  y  L   VDB  VDS  VSB
Then the horizontal electric field in the channel is:
E y y   
VDS
d s  y 
d VCB y 

dy
dy
VGS
Drain
+
+
Gate
Therefore:
I D  W QN y   n
dVCB y 
dy
+
 s y 
Source
Drain
VSB
y L
y 0
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NMOS Transistor: Inversion Charge
The inversion charge in the channel is:
For VGB  VTN y 
For VGB  VTN y 
0
QN y   
  Cox VGB  VTN y 
Where the position dependent threshold voltage is:
VTN y   VFB  2 p  VCB y  
2  s qN a  2 p  VCB y 
Cox
The channel potential is “y” dependent, and therefore the threshold voltage is
also “y” dependent. Consequently, the inversion charge is also “y”
dependent
Gate
Source
y 0
Drain
y L
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
6
NMOS Transistor: Inversion Charge and FET Threshold Voltage
So:
QN y   Cox VGB  VTN y 

2 s qN a  2 p  VCB y 
 Cox VGB  VFB  2 p  VCB y  

Cox

use : VGB  VGS  VSB
and : VCB y   VCS y   VSB





2 s qN a  2 p  VCS y   VSB 
 Cox VGS  VFB  2 p  VCS y  

Cox

Ignore

2 s qN a  2 p  VSB 
QN y   Cox VGS  VFB  2 p  VCS y  

Cox

QN y   Cox VGS  VTN  VCS y 








Gate
The NMOS transistor threshold voltage is defined as:
VTN  VFB  2 p 
Drain
Source
2  s qN a  2 p  VSB 
y 0
y L
Cox
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NMOS Transistor: Inversion Charge
The inversion charge in the channel is:
VDS
QN y   Cox VGS  VTN  VCS y 
VGS
Near the source end:
+
+
Gate
VCS y  0   0
+
Drain
Source
VSB
and
QN y  0  Cox VGS  VTN 
y 0
y L
Near the drain end:
VCS y  L   VDS
and
QN y  0   Cox VGS  VTN  VDS 
Conclusions:
● Inversion layer charge is maximum near the source end and minimum near
the drain end (as shown graphically in the figure)
● When VGS < VDS + VTN , the inversion layer disappears at the drain end
● When VGS < VTN , the inversion layer disappears even at the source end
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
7
NMOS Transistor: Current Flow
Current in the inversion channel at the
location y is:
ID  W QN  y  n E y 
E y   
dVCS y 
dy
dV y 
I D  W  n Cox VGS  VTN  VCS y  CS
dy
d VCB y 
d VCS  y 

dy
dy
 W QN  y  n
Gate
Source
L
VDS
0
0
 I D dy   W  n Cox VGS  VTN  VCS  dVCS
VDS
ID
-
+
And the result is:
ID 
y L
y 0
Integrate the above equation from y=0 to y=L:
Drain
ID
VGS
+
VSB
V
W
 n Cox VGS  VTN  DS V DS
L
2 

Some interpretation is required to understand the range of validity of the
above equation. This we do next ……..
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NMOS Transistor: Current Flow
Gate
First note that:
when V DS  0
then I D  0
There can be no current when
there is no bias and no electric
field in the channel to drive the
current
Source
Drain
ID
y L
y 0
VDS
Also note that:
The inversion layer charge is maximum at the source
end and is given by:
QN y  0  Cox VGS  VTN  VCS y  0 
ID
-
+
VGS
+
VSB
 Cox VGS  VTN 
So when VGS  VTN there is no inversion charge anywhere in the channel and
therefore ID  0
Conclusion:
I D  0 only when :
VGS  VTN
AND
VDS  0
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
8
NMOS Transistor: Current Flow
Gate
Suppose now:
VGS  VTN
Source
VDS  0
and
y L
y 0
First plot the ID-VDS curve from the result:
ID 
Drain
ID
V
W
 n Cox VGS  VTN  DS V DS
L
2 

VDS
ID
-
+
VGS
ID
VGS  VTN  2.5 V
VSB
As VDS is increased the current increases
……… but then it decreases !??
VGS  VTN  2.0 V
0
+
This decrease is unphysical !
A mathematical artifact !
VGS  VTN
Note that current is maximum when:
VGS  VTN  1.5 V
VDS  VGS  VTN
0
6
VDS
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NMOS Transistor: Pinch-Off
The inversion charge in the channel near the drain end is:
Gate
QN y  L   Cox VGS  VTN  VCS y  L 
ID
Source
 Cox VGS  VTN  VDS 
y 0
Drain
y L
When VDS approaches VGS - VTN the inversion layer
charge just near the drain end approaches zero
This condition is called “pinch-off”
For VDS > VGS - VTN there is a small section of channel just near the drain end that is
almost devoid of mobile carriers (i.e. electrons). This is a highly resistive section.
Gate
SiO2
Drain
L
The channel has been
“pinched off”
y L
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
9
NMOS Transistor: Pinch-Off and Current Saturation
Gate
The channel has been
“pinched off”
SiO2
For VDS  VGS  VTN :
Drain
Channel potential: VCS y   VGS  VTN
L
Channel potential: VCS y   VDS
y L
Any increase in VDS beyond VGS - VTN completely falls across this small resistive section
For VDS > VGS - VTN , integrate the current equation from y=0 to y=L-L:
L  L
VGS VTN
0
0
 I D dy 
 ID 
 W  n Cox VGS  VTN  VCS  dVCS
W
W
 n Cox VGS  VTN  2 
 n Cox VGS  VTN  2
2 L  L 
2L
So for VDS > VGS - VTN the current is what it was when VDS was equal to VGS - VTN
Thus for large value of VDS (> VGS – VTN) the current saturates!
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NMOS Transistor: Current Flow
VTN = 1.0 V
ID Linear or triode
VGS  VTN  2.5 V
region
The ID - VDS curves for an NMOS looks like
as shown in the figure
VGS  VTN  2.0 V
VGS  VTN  1.5 V
The three curves are for different values of
VGS - VTN
VGS  VTN
0
Pinch-off
point
VDS =VGS - VTN
0

0


V 
W

I D    n Cox VGS  VTN  DS V DS
2 
L


W

 n Cox VGS  VTN  2

2L
For VGS  VTN
Cut-off
Saturation
region
VDS
5
(Cut-off region)
For 0  VDS  VGS  VTN (Linear or triode
region)
For 0  VGS  VTN  VDS (Saturation region)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
10
NMOS Transistor: Current Flow
ID
VDS  3.0 V
Linear region
ID - VGS curves for an NMOS are shown
in the figure
VDS  2.0 V
Pinch-off
Point
The three curves are for different values of
VDS
VDS  1.0 V
0
0
VTN = 1.0 V

0


V 
W

I D    n Cox VGS  VTN  DS V DS
2 
L


W

 n Cox VGS  VTN  2

2L
6
VGS
(Cut-off region)
For VGS  VTN
For 0  VDS  VGS  VTN (Linear or triode
region)
For 0  VGS  VTN  VDS (Saturation region)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NMOS Transistor: Saturation Current vs VDS
For VDS > VGS - VTN (in the saturation region)
there is a small section of the channel just
near the drain end that is almost devoid of
mobile carriers (i.e. electrons).
Gate
SiO2
Drain
L
Channel potential: VCS y   VGS  VTN
y L
Channel potential: VCS y   VDS
In saturation, for VDS > VGS - VTN , integrate the current equation from y=0 to y=L-L:
L  L
VGS VTN
0
0
 I D dy 
 W  n Cox VGS  VTN  VCS  dVCS
 ID 
W
 n Cox VGS  VTN  2 
2 L  L 

L 
W
 n Cox VGS  VTN  2  1 

2L
L 

W
 C V  VTN  2
L  n ox GS

2 L 1 

L 

ECE 315 – Spring 2005 – Farhan Rana – Cornell University
11
NMOS Transistor: Saturation Current vs VDS
For VDS > VGS - VTN (in the saturation region)
there is a small section of the channel just
near the drain end that is almost devoid of
mobile carriers (i.e. electrons).
Gate
SiO2
Drain
Channel potential: VCS y   VGS  VTN
L
Channel potential: VCS y   VDS
y L
To a very good approximation:
L
 VDS
L
L

 nVDS
L
So for 0  VGS  VTN  VDS (saturation region) :
ID 
W
 n Cox VGS  VTN  2 1  nVDS 
2L
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NMOS Transistor: Saturation Current vs VDS
For 0  VGS  VTN  VDS
ID
(In saturation region):
ID 
W
 n Cox VGS  VTN  2 1  nVDS 
2L
V DS VGS  VTN
Linear
or
triode
Saturation
Increasing
VGS
0
A better NFET current model is:
0

0


V 
W

I D    n Cox VGS  VTN  DS V DS 1  nVDS 
L
2 


W

 n Cox VGS  VTN  2 1  nVDS 

2L
VDS
For VGS  VTN
(Cut-off region)
For 0  VDS  VGS  VTN
(Linear or triode region)
For 0  VGS  VTN  VDS
(Saturation region)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
12
NMOS Transistor: The Backgate Effect or the Body Effect
VDS
VDS
ID
VGS
+
+
Gate
+
VGS
+
VSB
+
Drain
Source
VSB
y 0
y L
The NMOS transistor threshold voltage depends on the applied source to bulk
potential difference:
VTN  VFB  2 p 
2  s qN a  2 p  VSB 
 VTN  VTN VSB  0    n
n 
2  s qN a
Cox
Cox
  2 p  VSB   2 p 
= Backgate effect parameter
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NMOS Transistor: The Backgate Effect or the Body Effect
VDS
ID
+
VGS
To get rid of the body effect, one can short the bulk
(or the backgate) to the source such that VSB =0
VTN  VTN VSB  0    n
0
  2p  VSB   2p 
However, depending on the technology used, this may not always be possible……..
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
13
NMOS Transistor: Breakdown
Large fields near the drain end in saturation can
lead to breakdown
Gate
SiO2
Breakdown limits the maximum value of VDS
Drain
L
Channel potential: VCS y   VGS  VTN
Channel potential:
VCS y   VDS
ID
y L
Breakdown
Potential drop in this region:
VDS  VGS  VTN 
Field in this region:
VDS  VGS  VTN 
L
0
0
VDS
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NMOS Transistor: Velocity Saturation
The drift velocity vs field curve for almost all materials is not linear and therefore
v dn    n E
v dn  sat
Velocity saturates at high fields!
A better approximation is:
v dn  
In Silicon:
v dn   n E
v dn
does not really hold
n E
1
E
E sat
E sat
E
E sat ~ 5  10 4 V/cm
Current in the inversion channel at the location y is:
dVCS y 
dy
I D  W QN y 
 W Cox VGS  VTN  VCS 
E
1 dVCS y 
1
1
E sat
dy
E sat
 n E y 
n
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
14
NMOS Transistor: Velocity Saturation
dVCS y 
dy
 W Cox VGS  VTN  VCS 
I D  W QN y 
E
1 dVCS y 
1
1
E sat
E sat
dy
Current in the inversion channel at the location y is:
 n E y 
n
Integrate the above equation from y=0 to y=L:
VDS

1 dVCS y  
dy   W  n Cox VGS  VTN  VCS  dVCS
 I D  1 
dy
 E sat

0
0
L
Answer is (in linear region):
V
VDS
W
 n Cox VGS  VTN  DS 
L
2   VDS 

 1 

Answer is (in saturation region):
 Vsat 
ID 
ID 
n
W
Cox VGS  VTN 2
2L  VGS  VTN 
 1 

Vsat


Vsat  E sat L
Velocity saturation
decreases the
current
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
15
CHAP #06 - PART 4
PMOS Field Effect Transistor (PMOSFET or PFET)
In this lecture you will learn:
• The operation and working of the PMOS transistor
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor with a Channel Contact
metal contact
(P+ Si) Gate
P-Si
+
+
VGB
VCB
_
_
P-Si
Inversion layer
N-Si substrate
metal contact
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
1
PMOS Capacitor: Effect of VCB (VGB < VTP)
Inversion Layer Hole Charge:
Gate
QP  Cox VGB  VTP 
+
-
-
VCB <0
• Inversion charge decreases
• Depletion region expands
Drain
Source
+
VCB
Gate
+
Drain
Source
VGB
VGB
-
gate
+
VTP  y   VFB  2 n  VCB 
Drain
Source
+
VGB
VCB
-
-
2  sqNd  2 n  VCB 
Cox
VCB >0
• Inversion charge increases
• Depletion region shrinks
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Transistor
_
_
VDS +
VGS +
Source
Drain
Gate
P-Si
P-Si
+
VSB
_
y 0
y L
y
N-Si Substrate (or Bulk)
Basic Idea: Current can be made to flow in the inversion layer by applying
a voltage across it in the horizontal direction
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
2
A PMOS Transistor in 3D
Metal (typically Silicide)
contacts
W
P+
Poly-Si
N+Gate
Si gate
Gate
P-Si
Source
P-Si
Drain
L
N-Si substrate
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Transistor: Circuit Symbols
+
VDS
Drain ID
Gate
+
VGS
Bulk
Source
VSB
+
+
VDS
+
VDS
Drain ID
Gate
+
VGS
Source
Drain ID
Bulk
Gate
VSB
+
VGS
+
Bulk
Source
VSB
+
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
3
MOS Transistor: The Gradual Channel Approximation
• The operation of the MOS transistor is best understood under the “gradual
channel approximation” which assumes that:
“Electrostatics of the MOS transistor in the horizontal direction have nothing
to do with the electrostatics in the vertical direction”
• This assumption decouples the 2-dimensional complicated problem into two
1-dimensional simpler problems – one for the vertical direction and one for
the horizontal direction.
• The electrostatics in the vertical direction have already been worked out by
us in the context of the MOS capacitor
• In this lecture we will work out the electrostatics in the horizontal direction
and calculate the current flow
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
PMOS Transistor: Current Flow
Gate
Current in the inversion channel at the location y is:
I D  W QP y  v y y 
Source
Drain
ID
y L
y 0
QP y   Inversion layer charge (C/cm2)
v y y   Drift velocity of inversion layer charge (cm/s)
VDS
ID
Drift velocity of holes is:
-
+
VGS
v y y    p E y  y 
E y y   Horizontal component of the electric field (V/cm)
Therefore:
I D  W QP y   p E y y 
Gate
Source
y 0
+
VSB
Note: positive
direction of current
is when the current
flows from the drain
to the source
Drain
E y y 
y L
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
4
PMOS Transistor: Current Flow
Let the potential in the channel from the source to the drain
end be written as:
Gate
s y   n  VCB y 
 s y 
Source
At the source end: VCB  y  0   VSB
y L
y 0
At the drain end: VCB  y  L   VDB  VDS  VSB
Then the horizontal electric field in the channel is:
E y y   
VDS
d s  y 
d VCB y 

dy
dy
VGS
Drain
+
+
Gate
Therefore:
I D  W QP y   p
dVCB y 
dy
+
 s y 
Source
Drain
VSB
y L
y 0
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
PMOS Transistor: Inversion Charge
The inversion charge in the channel is:
For VGB  VTP y 
For VGB  VTP y 
0
QP y   
  Cox VGB  VTP y 
Where the position dependent threshold voltage is:
VTP y   VFB  2n  VCB y  
2  s qNd 2n  VCB y 
Cox
The channel potential is “y” dependent, and therefore the threshold voltage is
also “y” dependent. Consequently, the inversion charge is also “y”
dependent
Gate
Source
y 0
Drain
y L
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
5
PMOS Transistor: Inversion Charge and FET Threshold Voltage
So:
QP y   Cox VGB  VTP y 

2 s qNd 2n  VCB y 
 Cox VGB  VFB  2n  VCB y  
Cox

use : VGB  VGS  VSB
and : VCB y   VCS y   VSB





2 s qNd 2n  VCS y   VSB 
 Cox VGS  VFB  2n  VCS y  
Cox


2 s qNd 2n  VSB 
QP y   Cox VGS  VFB  2n  VCS y  
Cox

QP y   Cox VGS  VTP  VCS y 








Gate
The PMOS transistor threshold voltage is defined as:
VTP  VFB  2n 
Drain
Source
2  s qNd 2n  VSB 
Cox
y 0
y L
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
PMOS Transistor: Inversion Charge
The inversion charge in the channel is:
VDS
QP y   Cox VGS  VTP  VCS y 
VGS
Near the source end:
+
+
Gate
VCS y  0   0
+
Drain
Source
VSB
and
QP y  0   Cox VGS  VTP 
y 0
y L
Near the drain end:
VCS y  L   VDS
and
QP y  0   Cox VGS  VTP  VDS 
Conclusion:
Inversion layer charge is maximum near the source end and minimum near
the drain end (as shown graphically in the figure)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
6
PMOS Transistor: Current Flow
Current in the inversion channel at the
location y is:
I D  W QP y   p E y 
E y   
dVCS y 
dy
dV y 
I D  W  p Cox VGS  VTP  VCS y  CS
dy
d VCB y 
d VCS  y 

dy
dy
 W QP  y   p
Gate
Source
L
VDS
0
0
 I D dy    W  p Cox VGS  VTP  VCS  dVCS
VDS
ID
-
+
And the result is:
ID  
y L
y 0
Integrate the above equation from y=0 to y=L:
Drain
ID
VGS
+
VSB
V
W
 p Cox VGS  VTP  DS V DS
L
2 

Some interpretation is required to understand the range of validity of the
above equation. This we do next ……..
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
PMOS Transistor: Current Flow
Gate
First note that:
when V DS  0
then I D  0
There can be no current when
there is no bias and no electric
field in the channel to drive the
current
Source
Drain
ID
y L
y 0
VDS
Also note that:
The inversion layer charge is maximum at the source
end and is given by:
QP y  0   Cox VGS  VTP  VCS y  0 
ID
-
+
VGS
+
VSB
 Cox VGS  VTP 
When VGS  VTP there is no inversion charge anywhere in the channel and
therefore ID  0
Conclusion:
I D  0 only when :
VGS  VTP
AND
VDS  0
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
7
PMOS Transistor: Current Flow
Gate
Suppose now:
VGS  VTP
Source
VDS  0
and
y L
y 0
First plot the ID-VDS curve from the result:
ID  
Drain
ID
V
W
 p Cox VGS  VTP  DS V DS
L
2 

VDS
ID
-
+
VGS
ID
+
VSB
VGS  VTp  1.5 V
VGS  VTP
0
VGS  VTp  2.0 V
This decrease is unphysical !
A mathematical artifact !
VGS  VTp  2.5 V
-6
As VDS is decreased the current magnitude
increases
……… but then it decreases !?
0
VDS
Note that current magnitude is maximum
when:
VDS  VGS  VTP
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
PMOS Transistor: Pinch-Off
The inversion charge in the channel near the drain end is:
Gate
QP y  L   Cox VGS  VTP  VCS y  L 
ID
Source
 Cox VGS  VTP  VDS 
y 0
Drain
y L
When VDS approaches VGS - VTP the inversion layer
charge just near the drain end approaches zero
This condition is called “pinch-off”
For VDS < VGS - VTP there is a small section of channel just near the drain end that is
almost devoid of mobile carriers (i.e. holes). This is a highly resistive section.
Gate
SiO2
Drain
L
The channel has been
“pinched off”
y L
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
8
PMOS Transistor: Pinch-Off and Current Saturation
The channel has been
“pinched off”
Gate
SiO2
For VDS  VGS  VTP :
Drain
Channel potential: VCS y   VGS  VTP
L
Channel potential: VCS y   VDS
y L
Any decrease in VDS below VGS - VTP completely falls across this small resistive section
For VDS < VGS - VTP , integrate the current equation from y=0 to y=L-L:
L  L
VGS VTP
0
0
 I D dy  
 ID  
 W  p Cox VGS  VTP  VCS  dVCS
W
W
 p Cox VGS  VTP  2  
 p Cox VGS  VTP  2
2 L  L 
2L
So for VDS < VGS - VTP the current is what it was when VDS was equal to VGS - VTP
Thus for large negative values of VDS (< VGS – VTN) the current saturates!
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
PMOS Transistor: Current Flow
VTP =-1.0 V
Saturation region
The ID - VDS curves for an PMOS looks like
as shown in the figure
Cut-off
ID
Pinch-off point
0
VGS  VTP
The three curves are for different values of
VGS - VTP
VGS  VTp  1.5 V
VGS  VTp  2.0 V
VDS =VGS - VTP
VGS  VTp  2.5 V
-5

0


V
 W
I D  
 p Cox VGS  VTP  DS V DS
2 
L


W


 p Cox VGS  VTP  2

2L
For VGS  VTP
Linear region
VDS
0
(Cut-off region)
For 0  VDS  VGS  VTP (Linear region)
For 0  VGS  VTP  VDS (Saturation region)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
9
PMOS Transistor: Current Flow
VTP = -1.0 V
VGS
-6
0
0
ID - VGS curves for an PMOS are shown
in the figure
VDS  1.0 V
The three curves are for different values of
VDS
VDS  2.0 V
Pinch-off point
VDS  3.0 V

0


V
 W
I D  
 p Cox VGS  VTP  DS V DS
2 
L


W


 p Cox VGS  VTP  2

2L
Linear region
ID
(Cut-off region)
For VGS  VTP
For 0  VDS  VGS  VTP (Linear region)
For 0  VGS  VTP  VDS (Saturation region)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
PMOS Transistor: Saturation Current vs VDS
For VDS < VGS - VTP (in the saturation region)
there is a small section of the channel just
near the drain end that is almost devoid of
mobile carriers (i.e. holes).
Gate
SiO2
Drain
L
Channel potential: VCS y   VGS  VTP
y L
Channel potential: VCS y   VDS
In saturation, for VDS < VGS - VTP , integrate the current equation from y=0 to y=L-L:
L  L
VGS VTP
0
0
 I D dy  
 W  p Cox VGS  VTP  VCS  dVCS
 ID  
W
 p Cox VGS  VTP  2  
2 L  L 

L 
W
 p Cox VGS  VTP  2 1 

2L
L 

W
 C V  VTP  2
L  p ox GS

2 L 1 

L 

ECE 315 – Spring 2005 – Farhan Rana – Cornell University
10
PMOS Transistor: Saturation Current vs VDS
For VDS < VGS - VTP (in the saturation region)
there is a small section of the channel just
near the drain end that is almost devoid of
mobile carriers (i.e. electrons).
Gate
SiO2
Drain
Channel potential: VCS y   VGS  VTP
L
Channel potential: VCS y   VDS
y L
To a very good approximation:
L
 VDS
L
Channel length
L
modulation

   pVDS
L
So for 0  VGS  VTP  VDS (saturation region) :
ID  
10  7
1/ V
L in meters
0.1

1/ V
L in m
p 
W
 p Cox VGS  VTP  2 1   pVDS 
2L
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
PMOS Transistor: Saturation Current vs VDS
For 0  VGS  VTP  VDS
0
VDS
(In saturation region) :
ID  
0
W
 p Cox VGS  VTP  2 1   pVDS 
2L
Decreasing VGS
V DS VGS  VTP
ID
A better PFET current model is:

0


V
 W
I D  
 p Cox VGS  VTP  DS V DS 1   pVDS 
2 
L


W

 p Cox VGS  VTP  2 1   pVDS 


2L
For VGS  VTP
(Cut-off region)
For 0  VDS  VGS  VTP
(Linear region)
For 0  VGS  VTP  VDS
(Saturation region)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
11
PMOS Transistor: Backgate Effect or the Body Effect
VDS
VDS
ID
VGS
+
+
Gate
+
VGS
+
VSB
+
Drain
Source
VSB
y 0
y L
The PMOS transistor threshold voltage depends on the applied source to bulk
potential difference:
VTP  VFB  2n 
2  s qNd 2n  VSB 
Cox
 VTP  VTP VSB  0    p  2n  VSB  2n 
p 
2  s qNd
Cox
= Backgate effect parameter
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
PMOS Transistor: Backgate Effect or the Body Effect
VDS
ID
+
VGS
To get rid of the body effect, one can short the bulk
(or the backgate) to the source such that VSB =0
0
VTP  VTP VSB  0    p  2n  VSB  2n 
However, depending on the technology used, this may not always be possible……..
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
12
PMOS Transistor: Velocity Saturation
The drift velocity vs field curve for almost all materials is not linear and therefore
v dp   p E
Drift velocity saturates at high fields!
A better approximation is:
v dp 
In Silicon:
v dp   p E
v dp
does not really hold
v dp  sat
 pE
1
E
E sat
E sat
E
E sat ~ 5  10 4 V/cm
Current in the inversion channel at the location y is:
dVCS y 
dy
I D  W QP y 
 W Cox VGS  VTP  VCS 
E
1 dVCS y 
1
1
E sat
dy
E sat
p
 p E y 
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
PMOS Transistor: Velocity Saturation
dVCS y 
dy
I D  W QP y 
 W Cox VGS  VTP  VCS 
E
1 dVCS y 
1
1
E sat
E sat
dy
Current in the inversion channel at the location y is:
 p E y 
p
Integrate the above equation from y=0 to y=L:
VDS

1 dVCS y  
dy    W  p Cox VGS  VTP  VCS  dVCS
 I D  1 

dy
 E sat

0
0
L
Answer is (in linear region):
V
VDS
W
 p Cox VGS  VTP  DS 
V 
L
2 

 1  DS 
V
Answer is (in saturation region):
sat 

ID  
ID  
p
W
Cox VGS  VTP 2
VGS  VTP 
2L 
 1 

Vsat


Vsat  E sat L
Velocity saturation
decreases the
current
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
13
PMOS Transistor: Breakdown
Large fields near the drain end in saturation can
lead to breakdown
Gate
SiO2
Breakdown limits the maximum value of VDS
Drain
Channel potential: VCS y   VGS  VTP
L
Channel potential: VCS y   VDS
y L
VDS
0
0
Potential drop in this region:
VDS  VGS  VTN 
Breakdown
Field in this region:
VDS  VGS  VTN 
L
ID
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
14
CHAP #06 - PART 5
Simple FET Circuits and Small Signal Models
In this lecture you will learn:
• The operation of simple MOS FET circuits
• Small signal circuit models of the MOS FETs
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Transistor in 3D
Metal (typically Silicide)
contacts
W
N+
Poly-Si
N+Gate
Si gate
Gate
N-Si
Source
N-Si
Drain
L
P-Si substrate
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
1
A NMOS Transistor: A Review
_
_
VDS +
VGS +
Source
Drain
Gate
N-Si
N-Si
+
VSB
y 0
_
y L
y
P-Si Substrate (or Bulk)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NMOS Transistor: A Review
Increasing VGS
ID Linear region
VDS
ID
+
VGS
+
VSB
VGS  VTN
0
Pinch-off
point
VDS =VGS - VTN
0
Simplified current model (good for hand calculations):

0


V 
 
I D  k n VGS  VTN  DS V DS
2 


kn

VGS  VTN  2

2
For VGS  VTN
Cut-off
Saturation
region
VDS
Cut-off
For 0  VDS  VGS  VTN
Linear region
For 0  VGS  VTN  VDS
Saturation region
kn 
W
 n Cox
L
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
2
NMOS Transistor: A Review
Increasing VGS
ID Linear region
VDS
ID
+
VGS
+
VSB
VGS  VTN
0
Pinch-off
point
VDS =VGS - VTN
0
Better current model:

0


V 
 
ID  k n VGS  VTN  DS V DS 1  nVDS 
2 


kn

VGS  VTN  21  nVDS 

2
kn 
Cut-off
Saturation
region
VDS
For VGS  VTN
Cut-off
For 0  VDS  VGS  VTN
Linear
region
For 0  VGS  VTN  VDS
Saturation
region
W
 n Cox
L
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NFET Voltage Amplifier and Inverter
VDD
ID R
+
-
R
VOUT
ID
VIN
We need to find the relation
between the output and the
input voltage
VGS  VIN
+
VDS  VOUT
VSB  0
1) VIN  VTN
The FET is in cut-off regime and I D  0 and consequently VOUT  VDD
2) VIN  VTN
The FET is turned on and I D  0 and consequently VOUT  VDD  I D R  VDD
VDS  VGS  VTN
(Saturation)
VOUT  VIN  VTN
(Saturation)
VDS  VGS  VTN
(Linear)
VOUT  VIN  VTN
(Linear)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
3
NFET Voltage Amplifier and Inverter: A Graphical Solution
VDD
Increasing VIN
ID
R
ID
VIN
VDD
R
VOUT
+
ID 
0
VDD  VOUT
R

0


V
 

I D  k n VIN  VTN  OUT V OUT
2



kn
2

VIN  VTN 

2
0
VDD
VOUT
kn 
W
 n Cox
L
For VIN  VTN
For 0  VOUT  VIN  VTN
For 0  VIN  VTN  VOUT
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NFET Voltage Amplifier and Inverter: A Graphical Solution
R
ID
VIN
Increasing VIN
ID
VDD
VDD
R
VOUT
+
0
VOUT
Saturation
VDD
VIN  VTN
0
VDD
VOUT
Cut-off
Linear
0
0
VTN
VIN
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
4
NFET Voltage Amplifier and Inverter: Transfer Curve
1) Assume the FET is in the saturation regime:
VDD
kn
VIN  VTN 2
2
V  VOUT
I D  DD
R
ID 
R
ID
VIN
VOUT
+
Answer is:
VOUT  VDD 

VOUT
VDD
Saturation
VIN  VTN
Rk n
VIN  VTN 2
2
dVOUT
  Rkn VIN  VTN 
dVIN
But the assumption that the FET is
in saturation is only valid provided
that:
Cut-off
VDS  VGS  VTN
0
 VOUT  VIN  VTN
0
VTN
VIN
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NFET Voltage Amplifier and Inverter: Transfer Curve
2) Now assume the FET is in the linear regime:
VDD
V


I D  k n VIN  VTN  OUT V OUT
2 

R
ID
VIN
VOUT
+
ID 
VDD  VOUT
R
Answer can be found by solving the above two
equations for VOUT vs VIN
VOUT
VDD
Saturation
VIN  VTN
A high input voltage produces a low
output voltage
Cut-off
A low input voltage produces a high
output voltage
Linear
0
0
VTN
VIN
The device can therefore be used as
a logical inverter!
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
5
NFET Voltage Amplifier and Inverter: Transfer Curve
VOUT
VDD
ID
VIN
VIN  VTN
VDD
R
Saturation
Cut-off
VOUT
+
Linear
0
0 VTN
VIN
High gain region
dVOUT
In the high gain region, the slope
can be much larger than unity!
dVIN
This means a small change in the input voltage will produce a large change in the
output voltage
The circuit can therefore be used as a voltage amplifier!
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NFET Common Source (CS) Voltage Amplifier
VDD
VOUT
R
I D  id
VIN  VTN
VDD
VOUT  v out
Saturation
Cut-off
+
v in
VIN
Linear
+
0
0 VTN
Bias point
Quiescent point
What is:
v out
?
v in
VIN
Voltage gain
We need better techniques to calculate the voltage gain of such amplifier circuits
We need small signal models of the FETs!
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
6
NFET Model with Channel Length Modulation Included
We will often use the following current model:

0


V 
 
I D  k n VGS  VTN  DS V DS 1  nVDS 
2 


kn

VGS  VTN  2 1  nVDS 

2
For VGS  VTN
(Cut-off region)
For 0  VDS  VGS  VTN
(Linear region)
For 0  VGS  VTN  VDS
(Saturation region)
V DS VGS  VTN
ID
Linear
Saturation
Increasing VGS
0
0
VDS
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NFET Small Signal Model
VDD
R
IG  i g
I D  id
VDS  v ds
+
v gs
VGS
+
+
Gate
+
VBS  v bs
id Drain
ig
+
v gs
-
g mWhat
v gs goes in
g mb
v bs
here??
go 
v gs
Source
+
v bs
1
ro
+
v ds
R
-
Base
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
7
NFET Small Signal Model – Part I
VDD
i D  I D  id
R
IG  i g
VDS  v ds
+

 ID 
I D
v gs
VGS
IEEE notation!
 ID  gmv gs
v gs
VGS

 ID VGS  v gs
I D  id
+
+
VBS
gm 
I D
VGS
Transconductance
Gate i g
id
+
v gs
-
Drain
+
v ds
-
g mv gs
Source
A voltage-controlled current source
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NFET Small Signal Model – Part II
VDD

iD  ID  id  ID VGS  v gs ,VDS  v ds
R
IG  i g
I D  id
 ID 
VDS  v ds
I D
I D
v gs 
v ds
VGS
VDS
 ID  gmv gs  gov ds
+
v gs
VGS
+
+
VBS
gm 
I D
VGS
Transconductance
Gate

go 
I D
VDS
Output conductance
ig
id
+
v gs
-
g mv gs
go
Drain
+
v ds
-
Source
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
8
NFET Small Signal Model – Part III – The Complete Model
VDD

iD  ID  id  ID VGS  v gs ,VDS  v ds ,VBS  v bs
R
IG  i g
I D  id
v bs
v gs
+
+
I D
I D
I D
v gs 
v ds 
v bs
VGS
VDS
VBS
 ID  gmv gs  gov ds  gmbv bs
+
+
VGS
 ID 
VDS  v ds
gm 
VBS
I D
VGS
I D
VDS
go 
Transconductance
Gate
g mb 
Output
conductance
ig
g mv gs
Source
g mbv bs
-
v bs +
I D
VBS
Backgate
conductance
id
+
v gs
-

Drain
+
v ds
-
go
Base
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NFET Model

0


V 
 
I D  k n VGS  VTN  DS V DS 1  nVDS 
2 
 
kn

VGS  VTN  2 1  nVDS 

2
ID
V DS VGS  VTN
Linear
Saturation
Increasing VGS
0
0
For VGS  VTN
(Cut-off region)
For 0  VDS  VGS  VTN
(Linear region)
For 0  VGS  VTN  VDS
(Saturation region)
gm 
I D
VGS
go 
I D
VDS
g mb 
I D
VBS
Transconductance
Output
conductance
Backgate
conductance
VDS
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
9
NFET: Transconductance
gm 
I D
VGS
Saturation:
Linear:
gm 
gm 
I D
 k n VGS  VTN  1  nVDS   2k n I D 1  nVDS 
VGS
I D
 k nVDS 1  nVDS 
VGS
Increases only as the
square-root of the current
V DS VGS  VTN
ID
Linear
(Small gm)
To achieve large gm,
operate in the
saturation region
Saturataion
(Large gm)
Increasing VGS
0
0
VDS
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NFET: Transconductance
gm 
I D
VGS
Saturation:
Linear:
gm 
gm 
I D
 k n VGS  VTN  1  nVDS   2k n I D 1  nVDS 
VGS
I D
 k nVDS 1  nVDS 
VGS
Increases only as the
square-root of the current
g m Linear
Saturation
(Small gm) (Large gm)
Increasing VGS
0
0
VDS
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
10
NFET: Output Conductance
I D
go 
VDS
Saturation:
go 
Linear: g o 
I D
k
 n VGS  VTN 2 n  n I D
VDS
2
I D
 n I D  k n VGS  VTN  VDS 1  nVDS 
VDS
V DS VGS  VTN
ID
Linear
(Large go)
Saturation
(Very small go)
Increasing VGS
0
0
VDS
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NFET: Output Conductance
I D
go 
VDS
Saturation:
go 
Linear: g o 
go
Linear
(Large go)
I D
k
 n VGS  VTN 2 n  n I D
VDS
2
I D
 n I D  k n VGS  VTN  VDS 1  nVDS 
VDS
Saturation
(Very small go)
V DS VGS  VTN
To achieve small go,
operate in the
saturation region
Increasing VGS
0
0
VDS
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
11
NFET: Backgate Conductance
Recall that the threshold voltage depends on the source-to-bulk voltage VSB:
VTN  VTN VSB  0    n
n 
g mb 
2  s qN a
Cox
  2p  VSB   2p 
= Backgate effect (or the body effect) parameter
I D
I D VTN

VBS VTN VBS
g mb 
Saturation:
Linear:
g mb 
n
I D VTN
I VTN
 D
 gm
VTN VBS
VGS VBS
2  2 p  VBS
I D VTN
I VTN
n
 D
 gm
VTN VBS
VGS VBS
2  2 p  VBS
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
NFET Common Source (CS) Voltage Amplifier
VBS  0
VDD
v gs  v in
R
I D  id
id  gmv gs 
VOUT  v out
+
+
VIN
Gate
+
 v out   gm ro || R v gs    gm ro || R v in
 Av 
v in
v out
v
  out
ro
R
v out
  gm ro || R 
v in
Voltage gain
id Drain
+
v gs
-
g mv gs
g mbv bs
go 
v in
Source
1
ro
+
v ds
R
+
v out
-
-
Base
v bs  0
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
12
NFET Common Source (CS) Voltage Amplifier
VBS  0
VDD
v gs  v in
R
I D  id
id  gmv gs 
VOUT  v out
+
 v out   gm ro || R v gs    gm ro || R v in
 Av 
v in
+
VIN
v out
v
  out
ro
R
v out
  gm ro || R 
v in
Voltage gain
1
1 1


ro || R ro R
 ro || R 
 Av 
R
1  goR
v out
R
  gm ro || R    gm
1  goR
v in
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Note on Small Signal Modeling
When making a small signal model out of a complicated nonlinear signal
remember that:
1) All DC voltage sources in the circuit become short circuits
2) All DC current sources in the circuit become open circuits
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
13
NFET CS Amplifier: Limits of Output Voltage Swing
VIN  VTN
VDD
R
I D  id
Bias point
VOUT
VDD
VOUT  v out
Output
voltage
swing
Saturation
Cut-off
+
Linear
v in
0
+
VIN
0
VIN
VTN
Input voltage swing
Minimum output voltage and maximum input voltage:
If the output voltage becomes too small (happens when the input voltage
becomes too large), the FET will go into the linear region (in the linear region the
gain is small)
Maximum output voltage and minimum input voltage:
If the input voltage becomes too small the FET will go into cut-off
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
The Diode-Connected NFET
I
I
ID
I
+
kn
V  VTN  2 1  nV 
2
V
-
0
0
VTN
V
The gate and the drain of the FET are tied together
Since:
VDG  0
 VDS  VGS
 VDS  VGS  VTN
 The FET is always operating in saturation when not in cut-off (i.e. provided
VGS > VTN)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
14
The Diode-Connected NFET
VDD
Finding VOUT:
ID 
R
VOUT  VDS
ID
kn
VGS  VTN  2 1  nVDS 
2
kn
VOUT  VTN  2 1  nVOUT   VDD  VOUT
2
R
kn
2 VDD  VOUT
VOUT  VTN  

2
R

The above equation can be solved for VOUT
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
Including Parasitic and Overlap Capacitances
Parasitic
capacitances
Overlap
capacitances
In Saturation:
Cgs 
QG
VGS V
DS ,VSB
Cgd 
QG
VGD V
2
2
 WLCox  WCov  WC p  WLCox
3
3
 WCov  WC p  0
GS ,VSB
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
15
PFET Voltage Amplifier and Inverter
VDD
VIN
+
ID
VOUT
R
We need to find the relation
between the output and the
input voltage
ID < 0 and actual current is
flowing out of the drain
1) VGS  VIN  VDD  VTP
The FET is in cut-off regime and I D  0 and consequently VOUT  0
2) VGS  VIN  VDD  VTP
The FET is turned on and I D  0 and consequently VOUT   I D R
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
PFET Voltage Amplifier and Inverter: A Graphical Solution
VDD
VIN
VDS  VOUT  VDD
+
ID
R
VGS  VIN  VDD
VDS  VOUT  VDD
ID  
0
 VDD
0
VOUT
Decreasing

VIN - VDD
VDD
R
ID
VOUT
R

0


 VDD 
V


I D    k p VIN  VDD  VTP  OUT
 V OUT VDD 
2


k

p
VIN  VDD  VTP  2


2

For VIN  VDD  VTP
For 0  VOUT  VDD  VIN  VDD  VTP
For 0  VIN  VDD  VTP  VOUT  VDD
kp 
W
 p Cox
L
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
16
PFET Voltage Amplifier and Inverter: Transfer Curve
VDD
VIN  VDD
VIN
+
ID
0
VTP
0
Linear
VOUT
Cut-off
R
Saturation
 VDD
VOUT  VDD  VIN  VDD  VTP
VOUT  VDD
A high input voltage produces a low output voltage
A low input voltage produces a high output voltage
The device can therefore be used as a logical inverter!
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
PFET Voltage Amplifier and Inverter: Transfer Curve
VDD
VIN
High gain region
VIN  VDD
+
ID
VTP
0
0
VOUT
Linear
Cut-off
R
Saturation
VOUT  VDD  VIN  VDD  VTP
In the high gain region, the slope
VOUT  VDD
dVOUT
can be larger than unity!
dVIN
This means a small change in the input voltage will produce a large change in the
output voltage
The circuit can therefore be used as a voltage amplifier!
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
17
PFET Common Source (CS) Voltage Amplifier
VDD
v gs  v in
id  g mv gs 
+
v in
I D  id
+
VIN
R
VOUT  v out
v out
v
  out
ro
R
 v out   g m ro || R v gs
 Av 
v out
  g m ro || R 
v in
Voltage gain
Gate
+
v in
go 
id
Drain
+
v gs
-
g mv gs
g mbv bs
v bs
Source
gm 
I D
VGS
Base
go 
I D
VDS
1
ro
+
g mb 
+
v ds
R
+
v out
-
-
I D
I D VTN

VBS VTN VBS
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
The Standard CMOS Process
D
S
B
D
N
P+
P
B
P
N+
P+
N+
N
S
N well
P Substrate
The NFETs and the PFETs can be realized on the same P-substrate by making a
N-well inside the substrate for the PFETs
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
18
The Double-Well CMOS Process
D
S
B
D
N
P+
P
B
P
N+
P+
N+
N
S
isolation
isolation
N well
P Well
Epitaxial Layer (undoped)
N Substrate
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
19