1. What is the difference between bit, logic, and reg in SystemVerilog? Why was reg deprecated
in favor of logic?
bit is a 2-state data type (0 or 1), synthesizable, and doesn't support x or z.
logic is a 4-state data type (0, 1, x, z), synthesizable, and suitable for both combinational and
sequential logic.
reg is a legacy 4-state data type from Verilog, replaced by logic in SystemVerilog because reg
implied storage and caused confusion. logic is clearer and works in all contexts (combinational,
sequential).
2. Write a code snippet that demonstrates undefined behavior with logic due to x/z values, and
explain how to detect and fix it
module demo;
logic a;
initial begin
a = 1'bx;
if (a) $display("TRUE");
else $display("FALSE");
end
endmodule
This code may display either TRUE or FALSE depending on the simulator, since a is x. To
detect unknowns, use 2-state bit if unknowns are not required.
3. What are the implications of using 2-state data types instead of 4-state in terms of simulation
performance and hardware modeling?
2-state types (bit, int) improve simulation performance by reducing memory usage and
eliminating x/z propagation. However, 4-state types (logic, reg) are essential for accurate
modeling of uninitialized variables and tri-state behavior in RTL.
4. Write a module using both 2-state (bit) and 4-state (logic) signals. Show how assigning x
affects behavior in simulation
module test;
bit b;
logic l;
initial begin
b = 1;
l = 1'bx;
$display("bit = %0b, logic = %0b", b, l);
end
endmodule
Output will show bit = 1, but logic = x. The bit type can't hold x.
5. Compare signed and unsigned data types in SystemVerilog. What are the default rules?
By default, logic, bit, and reg are unsigned unless declared with signed. Integer types like int,
byte, shortint, longint are signed by default. Arithmetic operations behave differently based on
sign.
Example:
logic signed [3:0] a = -2;
logic [3:0] b = 2;
logic [4:0] res = a + b;
6. Explain the difference between int, integer, shortint, longint, and byte. Explain clearly with
examples
Type​ Width​ Signed
int​
32​
Yes
integer​32​
Yes
shortint16​
Yes
longint​64​
Yes
byte​ 8​
Yes
All are 2-state, used in testbenches or algorithmic code.
7. What are packed and unpacked arrays in SystemVerilog? How do they affect memory layout
and access?
Packed arrays are bit-level and stored contiguously. Used like vectors.
Unpacked arrays are element-level and stored separately. Used for multidimensional structures.
Example:
logic [3:0] packed_array;
logic [3:0] unpacked_array[2];
8. What is the primary difference between static and dynamic arrays?
Static arrays have a fixed size at compile time.
Dynamic arrays are created with new[] at runtime and can be resized or deleted.
9. Write a SystemVerilog code that uses a dynamic array of integers. Add methods to new,
delete, and resize elements
module dyn_arr;
int da[];
initial begin
da = new[3];
// Create array
da[0] = 10; da[1] = 20; da[2] = 30;
da = new[5](da); // Resize and copy old values
da.delete();
// Free memory
end
endmodule
10. What is a queue in SystemVerilog? How does it differ from a dynamic array in functionality
and performance?
A queue is a variable-size array with built-in methods like push_back, pop_front, and is ideal for
FIFO behavior. Dynamic arrays require manual resizing and cannot grow or shrink
automatically.
Example:
int q[$];
q.push_back(5);
q.pop_front();
11. Demonstrate use of associative array methods like first(), last(), next(), prev() in a loop
int aa[string];
initial begin
aa["a"] = 1; aa["b"] = 2;
string key = aa.first();
while (key != "") begin
$display("%s = %0d", key, aa[key]);
key = aa.next(key);
end
end
12. Explain the use of typedef in defining user-defined data types. Why is it used in complex
designs?
typedef allows defining custom types, improving readability and reuse. It's essential in large
designs for standardizing interfaces and reducing code duplication.
Example:
typedef logic [7:0] byte_t;
typedef enum logic [1:0] {IDLE, READ, WRITE} state_t;
13. Define a typedef struct for a bus transaction (address, data, read/write) and initialise the
values for the same
typedef struct packed {
logic [31:0] addr;
logic [31:0] data;
logic
rw; // 1 = read, 0 = write
} bus_txn_t;
bus_txn_t txn = '{addr: 32'hABCD, data: 32'h1234, rw: 1'b1};
14. Packed vs unpacked structs. Explain the difference with an example that demonstrates byte
alignment
Packed structs are bit-contiguous and synthesizable. Unpacked structs are word-aligned and
used in testbenches.
Example:
typedef struct packed {
logic [7:0] a;
logic [7:0] b;
} packed_s;
typedef struct {
logic [7:0] a;
logic [7:0] b;
} unpacked_s;
Packed struct uses 16 bits. Unpacked may use 32 bits due to alignment.
15. What are unions in SystemVerilog? How do packed unions differ from unpacked ones in
simulation behavior?
Unions share storage between fields.
Packed unions: Bit-aligned, synthesizable, simultaneous access to all views.
Unpacked unions: Word-aligned, simulation only.
Example:
typedef union packed {
logic [15:0] word;
struct packed { logic [7:0] low, high; };
} u_t;
16. Compare structs and unions
Structs allocate storage for each field separately.
Unions allocate shared storage, only one field valid at a time.
Use structs for multiple signals, unions for reinterpreting the same bits.
17. How do enums improve code readability and safety in SystemVerilog?
Enums replace magic numbers with named states, increasing readability and preventing invalid
values.
Example:
typedef enum logic [1:0] {IDLE, READ, WRITE} state_t;
state_t state = READ;