NMOS voltage divider circuit
Title:
Date:10_10_2012
Biasing circuit of E-MOSFET of voltage divider circuit biasing . The frequency response using AC
analysis.
Theory:
The frequency response of an amplifier refers to the frequency range in which the
amplifier will operate with negligible effects from capacitors and device internal capacitance.
This range of frequencies can be called the mid-range. Frequency response is the quantitative
measure of the output spectrum of a system or device in response to a stimulus, and is used to
characterize the dynamics of the system. It is a measure of magnitude and phase of the output
as a function of frequency, in comparison to the input. In simplest terms, if a sine wave is
injected into a system at a given frequency, a linear system will respond at that same frequency
with a certain magnitude and a certain phase angle relative to the input. Also for a linear
system, doubling the amplitude of the input will double the amplitude of the output. In
addition, if the system is time-invariant, then the frequency response also will not vary with
time.
Midband:
The frequency range of interest for amplifiers
Large capacitors can be treated as short circuit and small capacitors can be treated as open circuit
Gain is constant and can be obtained by small-signal analysis
Low-frequency band:
Gain drops at frequencies lower than fL
Large capacitors can no longer be treated as short circuit
The gain roll-off is mainly due to coupling and by-pass capacitors
High-frequency band:
Gain drops at frequencies higher than fH
Small capacitors can no longer treated as open circuit
The gain roll-off is mainly due to parasitic capacitances of the MOSFETs and BJTs
Circuit Diagram
Netlist
* SPICE netlist written by S-Edit Win32 Demo 9.12
* Written on Oct 10, 2012 at 15:36:11
* Waveform probing commands
.probe
.options probefilename="File0.dat"
+ probesdbfile="C:\4,13,15\File0.sdb"
+ probetopmodule="Module0"
* Main circuit: Module0
C1 IN N1 1uF
C2 OUT Gnd 10pF
M3 OUT IN Gnd Gnd NMOS L=2u W=15u AD=66p PD=24u AS=66p PS=24u
R4 Vdd IN 60K TC=0.0, 0.0
R5 IN Gnd 60K TC=0.0, 0.0
R6 Vdd OUT 2K TC=0.0, 0.0
v7 N1 Gnd 0.0 AC 1.0 0.0
vdd vdd gnd 5
.include "C:\Documents and Settings\ELDT\Desktop\bnbp13_5v.md"
.ac dec 5 1 100meg
.print ac vdb(OUT)

End of main circuit: Module0
Output Graph
Circuit Elements
Name
No. of Element Used
NMOS……………………..1
Capacitor…………………..2
Resistor…………………….3
Voltage Source…………….2
Device Characteristics
Drain-Source Voltage
VDS
3.58375
Gate-Source Voltage
VGS
2.50000
Drain Current
ID
708.12537u
Threshold Voltage
VTH
690.47696m
GRAPHICAL DATA
Frequency(Hz)
vdb(OUT)(dB)
1.00000e+000
-1.2101e+001
1.58489e+000
-8.3210e+000
2.51189e+000
-4.8282e+000
3.98107e+002
2.5435e+000
1.00000e+003
2.5441e+000
1.58489e+003
2.5442e+000
2.51189e+004
2.5442e+000
3.98107e+004
2.5442e+000
1.58489e+005
2.5426e+000
1.00000e+006
2.4788e+000
1.58489e+006
2.3818e+000
2.51189e+006
2.1471e+000
3.98107e+007
-1.1445e+001
6.30957e+007
-1.5340e+001
1.00000e+008
- 1.9297e+001
CMOS Inverter Transfer Analysis
Title :
DC transfer characteristics of CMOS inverter .
Theory :
CMOS circuits are constructed in such a way that all PMOS transistors must have either an
input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors
must have either an input from ground or from another NMOS transistor. The composition of a
PMOS transistor creates low resistance between its source and drain contacts when a low gate
voltage is applied and high resistance when a high gate voltage is applied. On the other hand,
the composition of an NMOS transistor creates high resistance between source and drain when
a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS
accomplishes current reduction by complementing every nMOSFET with a pMOSFET and
connecting both gates and both drains together. A high voltage on the gates will cause the
nMOSFET to conduct and the pMOSFET to not conduct while a low voltage on the gates causes
the reverse. This arrangement greatly reduces power consumption and heat generation.
However, during the switching time both MOSFETs conduct briefly as the gate voltage goes from
one state to another. This induces a brief spike in power consumption and becomes a serious
issue at high frequencies.
Circuit Diagram
Netlist
* SPICE netlist written by S-Edit Win32 Demo 9.12
* Written on Oct 10, 2012 at 16:06:37
* Waveform probing commands
.probe
.options probefilename="File0.dat"
+ probesdbfile="File0.sdb"
+ probetopmodule="Module0"
* Main circuit: Module0
M1 OUT IN Gnd Gnd NMOS L=2u W=15u AD=66p PD=24u AS=66p PS=24u
M2 OUT IN Vdd Vdd PMOS L=2u W=24u AD=66p PD=24u AS=66p PS=24u
v3 IN Gnd 5.0
Vdd Vdd Gnd 5
.include "C:\Documents and Settings\ELDT\Desktop\bnbp13_5v.md"
.dc v3 0 5 0.1
.print dc v(in) v(out)
* End of main circuit: Module0
Output Graph
Circuit Elements
Name
No. of Element Used
MOSFETs …......................2
Voltage sources ……….....2
Transfer Analysis
v3(V)
v(in)(V)
v(out)(V)
0.0000e+000
0.0000e+000
5.0000e+000
1.0000e-001
1.0000e-001
5.0000e+000
2.0000e-001
2.0000e-001
5.0000e+000
1.0000e+000
1.0000e+000
4.9743e+000
1.1000e+000
1.1000e+000
4.9567e+000
1.2000e+000
1.2000e+000
4.9338e+000
1.3000e+000
1.3000e+000
4.9054e+000
2.0000e+000
2.0000e+000
4.4982e+000
2.1000e+000
2.1000e+000
4.3893e+000
2.2000e+000
2.2000e+000
4.2520e+000
2.3000e+000
2.3000e+000
4.0649e+000
2.4000e+000
2.4000e+000
3.7453e+000
2.5000e+000
2.5000e+000
2.6310e+000
3.5000e+000
3.5000e+000
1.6948e-001
3.7000e+000
3.7000e+000
1.0160e-001
3.8000e+000
3.8000e+000
7.4988e-002
3.9000e+000
3.9000e+000
5.2780e-002
4.6000e+000
4.6000e+000
6.3856e-005
4.7000e+000
4.7000e+000
1.0476e-005
4.8000e+000
4.8000e+000
1.6598e-006
4.9000e+000
4.9000e+000
2.6330e-007
5.0000e+000
5.0000e+000
4.3507e-008
CMOS Inverter Transient Analysis
Title :
Transition analysis of CMOS inverter .
Theory :
CMOS circuits are constructed in such a way that all PMOS transistors must have either an
input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors
must have either an input from ground or from another NMOS transistor. The composition of a
PMOS transistor creates low resistance between its source and drain contacts when a low gate
voltage is applied and high resistance when a high gate voltage is applied. On the other hand,
the composition of an NMOS transistor creates high resistance between source and drain when
a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS
accomplishes current reduction by complementing every nMOSFET with a pMOSFET and
connecting both gates and both drains together. A high voltage on the gates will cause the
nMOSFET to conduct and the pMOSFET to not conduct while a low voltage on the gates causes
the reverse. This arrangement greatly reduces power consumption and heat generation.
However, during the switching time both MOSFETs conduct briefly as the gate voltage goes from
one state to another. This induces a brief spike in power consumption and becomes a serious
issue at high frequencies.
Circuit Diagram
Netlist
* SPICE netlist written by S-Edit Win32 Demo 9.12
* Written on Oct 10, 2012 at 16:29:20
* Waveform probing commands
.probe
.options probefilename="cmosinvbit.dat"
+ probesdbfile="C:\4,13,15\cmosinvbit.sdb"
+ probetopmodule="Module0"
* Main circuit: Module0
M1 OUT IN Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 OUT IN Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v3 IN Gnd bit({0100101111} on=5.0 off=0.0 rt=0n ft=0n delay=0 lt=10u ht=10u)
vdd vdd Gnd 5
.include "C:\Documents and Settings\ELDT\Desktop\bnbp13_5v.md"
.tran .01u 100u
.print tran v(out) v(in)
Output Graph
Circuit Elements
Name
No. of Element Used
MOSFETs …......................2
Voltage sources ………......2
Transient Analysis
Time(s)
v(out)(V)
v(in)(V)
0.000000e+000
5.0000e+000
0.0000e+000
6.250000e-010
5.0000e+000
0.0000e+000
1.000000e-009
5.0000e+000
0.0000e+000
1.625000e-009
5.0000e+000
0.0000e+000
7.874999e-009
5.0000e+000
0.0000e+000
6.647874e-006
5.0000e+000
0.0000e+000
6.667874e-006
5.0000e+000
0.0000e+000
6.687874e-006
5.0000e+000
0.0000e+000
6.707874e-006
5.0000e+000
0.0000e+000
6.727874e-006
5.0000e+000
0.0000e+000
6.747874e-006
5.0000e+000
0.0000e+000
1.223924e-005
1.2046e-004
5.0000e+000
1.237924e-005
-1.1470e-004
5.0000e+000
1.239924e-005
1.1399e-004
5.0000e+000
1.241924e-005
-1.1312e-004
5.0000e+000
1.247924e-005
1.1087e-004
5.0000e+000
3.043219e-005
5.0000e+000
0.0000e+000
9.989924e-005
1.1366e-008
5.0000e+000
9.991924e-005
5.3051e-008
5.0000e+000
9.993924e-005
1.1709e-008
5.0000e+000
9.995924e-005
5.2712e-008
5.0000e+000