THEORY OF COMPUTATION/
AUTOMATA THEORY
Dwumfour Abdullai Aziz Slide 1
THEORY OF COMPUTATION
• Theory of computation (automata theory) is a model that
deals with the logic of computation with respect to simple
machines, called automata.
• It is the study of abstract machines and the computation
problems that can be solved using these machines.
• The Theory helps to describe and analyze the dynamic
behavior of these abstract machines (automata).
• The term Automata originated from the word “Automaton”
which is related to “Automation”.
• An automaton with a finite number of states is referred to
as finite state automaton
Dwumfour Abdullai Aziz
Slide 2
Theory of computation
Dwumfour Abdullai Aziz
Slide 3
Automaton
q An automaton consists of
states and transitions.
q States are represented
by circles, and Transitions
represented by arrows.
q An automaton takes in some
string as input and goes
through a finite number of
states and reach a final state
Dwumfour Abdullai Aziz
Slide 4
BASIC TERMINOLOGIES
Symbol (Character): is an object, which can be any alphabet,
letter or any image. E.g. 1,2,a,b,#
Alphabet (𝜮) : Alphabets are finite set of symbols. Σ={0,1},
Σ={a,b,c}, Σ={0,1,2,3,4…, 9}
String (w): finite sequence of symbols from some alphabet.
length of a string is denoted as |w|.
Given the alphabet ( ∑ )= {a, b}, string that can be generated
from ∑ are {a, b, ab, aa, bb, aba, bba, bab...}.
A string with zero occurrences of symbols is called an empty
string, represented by ε.
E.g., 0110, 11, 001 are three strings over the binary alphabet {0, 1 }
Dwumfour Abdullai Aziz
Slide 5
BASIC TERMINOLOGIES
q E.g., aab, abcb, b, cc are four strings over the alphabet {a, b,
c }.
q It is not the case that a string over some alphabet should
contain all the symbols from the alphabet. E.g., the string cc
over the alphabet {a, b, c} does not contain the symbols a
and b.
q Length of string : The number of symbols in a string w is
called its length, denoted by |w|. E.g., |0110|=4, |10|=2,
|c|=1
Dwumfour Abdullai Aziz
Slide 6
BASIC TERMINOLOGIES
q Σ* is set of all possible strings over Σ. E.g., given Σ ={a,
b}, Σ*={∈, a, b, ab, ba, aa, bb…}
q Language (L): is a set of strings, chosen from some Σ*.
language is a subset of Σ*. E.g. given Σ={a,b}
L={set of string of length 2 over Σ }; L= {aa, ab, ba, bb}
q Language can be finite or infinite
Dwumfour Abdullai Aziz
Slide 7
BASIC TERMINOLOGIES
Power of Σ
q We write Σk ( for some integer k) to denote the set of strings of
length k over Σ )
Σk ={w | w is a string over Σ |w|=k}
q
Given Σ={0,1}
Σ0 = set of all strings of length 0: Σ0 ={∈}
• Σ1 = set of all string of length 1: Σ1 = {0,1}
• Σ2 = set of all string of length 2: Σ2 = {00, 01, 10, 11}
• Σ3 = set of all string of length 3: Σ3 = {000,001,010,011,
100,101,110,111}
•
• Σn = set of all string of length n
Dwumfour Abdullai Aziz
Slide 8
BASIC TERMINOLOGIES
Cardinality
q This refers to the number of elements in a set over alphabet Σ
Consider Σ= {0,1}
Cardinality of Σ0 =0
• Cardinality of Σ1 =2
• Cardinality of Σ2 =4
• Cardinality of Σ3 =8
•
• Cardinality of Σn =2n
Dwumfour Abdullai Aziz
Slide 9
Applications of theory of computation
ü Traffic lights
ü Lifts and elevators
ü Marketing
ü Compilers
ü Vending machines
ü Cloud computing
Dwumfour Abdullai Aziz
Slide 10
Layers of computation
Undecidable
FSM: Finite State Machine
Turing Machine
CFL: Context Free Language
CFL
Turing Machine
Undecidable
FSM
Dwumfour Abdullai Aziz
Slide 11
Layers of computation
q FSM Layer: One of the simplest model of computation
with limited memory and performs low level
computations
q CFL Layer: Computationally high compared to FSM
q Turing Machine Layer : can perform higher level
computations than CFL and FSM.
q Undecidable Layer: highest level of computation.
Performs computations that cannot be accomplished
mechanically
_-->We shall focus on FSM
Dwumfour Abdullai Aziz
Slide 12
FINITE STATE MACHINE: FMS
Dwumfour Abdullai Aziz Slide 13
• A Finite State Machine (FSM), is a computational
model that can be used to simulate sequential logic,
• Finite State Machines can be used to model different
kinds of problems in diverse disciplines
• finite state machine can be described by the
following;
– possible states it can assume,
– current state,
– the input it receives, output produced
– how it changes state.
Dwumfour Abdullai Aziz
Slide 14
MODELING STATE MACHINE
The behavior of finite state machines can be modeled
using the following
ü State transition table (state table)
ü State transition diagram( state diagram)
ü State equation
Dwumfour Abdullai Aziz Slide 15
STATE TABLE
q The state table can be used to model the behavior of
the sequential circuit using the present state, input,
next state and output.
q The present state designates the state of flip-flops
before the occurrence of a clock pulse.
q The input represent the value that may cause the
change in the current state.
q The next state shows the states of flip-flops after the
clock pulse or input, and the output specifies the
value of the output variables during the state
transition.
Dwumfour Abdullai Aziz
Slide 16
State Table
Dwumfour Abdullai Aziz Slide 17
What is State Diagram?
q We have examined a general model for sequential circuits.
q In this model the effect of all previous inputs on the outputs
is represented by a state of the circuit.
q Thus, the output of the circuit at any time depends upon its
current state and the input. These also determine the next
state of the circuit.
q The relationship that exists among the inputs, outputs,
present states and next states can be modeled with the state
diagram
q In this diagram, a state is represented by a circle, and the
transition between states is indicated by directed lines (or
arcs) connecting the circles.
Slide 18
Dwumfour Abdullai Aziz
Finite state machine
Dwumfour Abdullai Aziz Slide 19
Finite state machine
Vending Machine Door
Dwumfour Abdullai Aziz Slide 20
Derive a Finite state machine for
microwave
Dwumfour Abdullai Aziz Slide 21
Number of States vs Number of flip flops
q 1 flip-flop => 2 states
q 2 flip-flops => 4 states
q 3 flip-flops => 8 states
q 4 flip-flops => 16 states
q N flip-flops => 2N states
Dwumfour Abdullai Aziz Slide 22
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Dwumfour Abdullai Aziz Slide 24
STATE DIAGRAM FOR THE VARIOUS FLIP FLOPS
Dwumfour Abdullai Aziz
Slide 25
Dwumfour Abdullai Aziz
Slide 26
STATE DIAGRAM
Dwumfour Abdullai Aziz Slide 27
CLASSIFICATIONS OF
FINITE STATE AUTOMATA
Dwumfour Abdullai Aziz Slide 28
FINITE STATE MACHINE
Dwumfour Abdullai Aziz Slide 29
FINITE AUTOMATA WITH OUTPUT
q Finite State Automata may have outputs
corresponding to each transition.
q Synchronous Sequential circuits are developed based
on two types of models
• Mealy model/ Mealy state machine
• Moore mode/Moor state machine
q The difference lies in the way the output of the
complete circuit is generated.
Dwumfour Abdullai Aziz
Slide 30
FINITE AUTOMATA WITH OUTPUT
q FSM with output is described by 6 tuples
(Q, q0, ∑, O, δ, λ)
ü Q is finite set of states
ü q0 is the initial state
ü ∑ is the input alphabet
ü O is the output alphabet
ü δ is transition function which maps Q×∑ → Q
ü ‘λ’ is the output function which maps Q×∑→ O
Dwumfour Abdullai Aziz
Slide 31
Moore Computational Model
q A Moore machine is defined as a machine in theory of
computation whose output values are determined only by its
current state.
q In Moore machine, the output is associated with each state rather
than with the transitions.
q Moore machine is described by the 6 tuples above(Q,q0,∑,O,δ,λ)
Q is finite set of states
– q0 is the initial state
–
–
∑ is the input alphabet
–
O is the output alphabet
–
δ is transition function which maps Q×∑ → Q
–
‘λ’ is the output function which maps Q→ O
Moore Model
Q={s0,s1,s2,s3}
q0= s0
∑={0,1}
O={0,1}
δ:{s0,1}->s1
{s0,0}->s0
{s1,1}->s2
{s1,0}->s0
{s3,1}->s3
{s2,0}->s0
{s3,1}->s3
{s3,0}->s0
λ:Q→O
Dwumfour Abdullai Aziz
Slide 33
s0->0 , s1->0
s2->0 , s3->1
Moore Model
q In the Moore Model , a Combinational logic block maps
the inputs and the current state into the necessary flipflop inputs to store the appropriate next state.
q The outputs are computed by a combinational logic block
whose only inputs are the flip-flops' state outputs.
q The outputs change synchronously with the state
transition and the clock edge.
Dwumfour Abdullai Aziz Slide 34
Moore Model
Dwumfour Abdullai Aziz Slide 35
Moore Machine
Dwumfour Abdullai Aziz Slide 36
Clocked Sequential Circuit of Moore Machine
Dwumfour Abdullai Aziz Slide 37
Moore Model: Features
Moore machines are characterized by;
q The Output depends only on current state.
q More number of states are required.
q There is less hardware requirement for circuit
implementation.
q They react slower to inputs(One clock cycle later).
q Synchronous output and state generation.
q Output is associated with the states.
Slide 38
Mealy Computational Model
q A Mealy Machine is defined as a machine in theory of computation
whose output values are determined by both its current state and
current inputs.
q In mealy machine, the output is given along the edge with input
symbol
q Mealy machine is described by the 6 tuples above(Q,q0,∑,O,δ,
λ)
Q is finite set of states
– q0 is the initial state
–
–
∑ is the input alphabet
–
O is the output alphabet
–
δ is transition function which maps δ: Q×∑ → Q
–
‘λ’ is the output function which maps λ : Q ×∑ → O
Mealy Model
Q={s0,s1,s2}
q0= s0
∑={0,1}
O={0,1}
δ:{s0,1}->s1
{s0,0}->s2
{s1,1}->s1
{s1,0}->s2
{s2,1}->s1
{s2,0}->s2
λ:Q×∑ → O
{s0,1}->0, {s0,0}->0
{s1,1}->1,{s1,0}->1
{s2,1}->0, {s2,0}->0
Dwumfour Abdullai Aziz
Slide 40
Mealy machine
Dwumfour Abdullai Aziz Slide 41
Clocked Sequential Circuit of Mealy
Machine
Dwumfour Abdullai Aziz
Slide 42
Clocked Sequential Circuit of Mealy Machine
Dwumfour Abdullai Aziz Slide 43
Summary of Moore vs Mealy state diagram
q In Moore machines, the output is associated with the states
q In Mealy machines the output is associated with the
transitions.
q Moore machines have more states than equivalent Mealy
machine.
q Mealy machines (generally) have less states. Mealy
machines change their output based on their current
input and present state, rather than just the present state.
q However, less states doesn't always mean simpler to
implement.
Dwumfour Abdullai Aziz Slide 44
Summary of Moore vs Mealy state diagram
q Moore machines may be safer to use, because they
change states on the clock edge
q Mealy machines are faster, because the state is
dependent on the input. Thus, the state can change
asynchronously. This comes down to predictability vs
raw speed.
q When it comes down to it, it's difficult to draw hard
lines where one machine would always be better than
the other.
Dwumfour Abdullai Aziz Slide 45
Which Machine is best???
Moore vs Mealy
q It really comes down to the specific task at hand. Does one
want to have a synchronous or asynchronous machine? Is
speed paramount? Will there be potential unstable
(bouncing) signals? Are both the inputs and present state
readily available? The answer to each of these questions
determines the type of machine that would work best.
q It's worth mentioning that for a hardware implementation,
Mealy machines require less hardware in their circuits, but
when working with an HDL and RTL scenario, the actual
amount of discrete hardware may not be terribly important
Dwumfour Abdullai Aziz Slide 46
Design of Synchronous Sequential Circuit
Step 1: The behavior of circuit is given through the State
diagram or timing diagram
Step 2: Obtain the state table from the state diagram
Step 3: Perform state reduction if possible
Step 4:Perform state assignment
Step 5: Determine number of flip flops and assign letters
Step 6: Decide on the type of flip flop to use
Step 7: Derive circuit excitation table from state table
Step 8: Obtain Boolean expression for flip flop input and circuit
output
Step 9: Implement circuit diagram
Dwumfour Abdullai Aziz Slide 47
Design a Clock Sequential circuit for
the state diagram below
Step 1: state diagram is given
0/0
00
1/1
0/0
1/0
1/0
01
10
0/1
0/0
11
1/0
Dwumfour Abdullai Aziz Slide 48
Step 2: Obtain the state table
PRESENT STATE
NEXT STATE
X=0
OUTPUT (Z)
X=1
X=0
X=1
QA
QB
Q +A
Q +B
Q +A
Q +B
0
0
0
0
0
1
0
0
0
1
1
1
0
1
0
0
1
0
1
0
0
0
1
1
1
1
1
0
1
1
0
0
Dwumfour Abdullai Aziz
Slide 49
Step 3: perform state reduction
• No state reduction is required since no redundant state
occurs.
Step 4: perform state assignment if required
A=00
B=01
The states are already assigned binary values
from the state diagram hence no need for state
assignment
C=10
D=11
Dwumfour Abdullai Aziz
Slide 50
Step 5: Determine number of flip flops and assign letters
to them
Two (2) flip flops are required since there are four(4) states.
The flip flops are;
ü Flip flop A -> QA is the state of flip flop A
ü Flip flop B -> QB is the state of flip flop B
Step 6: decide the type of flip flop to be used
We shall use the D flip flop
Dwumfour Abdullai Aziz
Slide 51
Step 7: derive the circuit excitation table from state table
PRESENT STATE
INPUT
NEXT STATE
FLIP FLOP INPUT
QA
QB
X
Q+A
Q+B
DA
DB
Z
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
0
1
0
0
0
0
1
1
1
0
1
0
1
0
0
1
1
1
1
1
1
1
0
Remember the excitation table for D flip flop
Dwumfour Abdullai Aziz
OUTPUT
Slide 52
Step 8: Obtain the Boolean expression for flip flop input
PRESENT STATE
INPUT
NEXT STATE
FLIP FLOP INPUT OUTPUT
QA
QB
X
Q+A
Q+B
DA
DB
Z
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
0
1
0
0
0
0
1
1
1
0
1
0
1
0
0
1
1
1
1
1
1
1
0
Logical Expression for DA , DB and Z in terms of QA, QB and X
Dwumfour Abdullai Aziz
Slide 53
Step 8: Obtain the Boolean expression for flip flop input
QA
QBX
Kmap for DB
Kmap for DA
00
01
11
10
0
0
0
0
1
1
1
0
1
1
DA=QAQB + QBX + QAX’
QBX
QA
0
1
00
01
11
10
0
1
1
1
0
0
1
0
DB=QA’X + QA’QB + QBX
Z=???
Step 9: Construct the clock sequential logic circuit diagram for the equations
Dwumfour Abdullai Aziz
Slide 54
State Reduction
q Any design process must consider the problem of
minimizing the cost of the final circuit.
q The two commonly used cost reductions include;
• Reducing number of flip-flops
• Reducing number of gates.
q Since m flip-flops produce 2m states, a reduction in the
number of states may (or may not) result in a reduction
in the number of flip-flops
Dwumfour Abdullai Aziz Slide 55
State Reduction
q It is therefore desirable to know when two or more
states are equivalent in all aspects.
q The process of eliminating the equivalent or redundant
states from a state table/diagram is known as state
reduction.
q reducing the number of states in a state table must
keep the external input–output requirements
unchanged.
Dwumfour Abdullai Aziz Slide 56
State Reduction
=F
Perform state reduction on the state table above
Dwumfour Abdullai Aziz Slide 57
State Reduction
=E
Dwumfour Abdullai Aziz Slide 58
State Reduction
Dwumfour Abdullai Aziz Slide 59
Perform state reduction
Dwumfour Abdullai Aziz Slide 60
Perform state reduction
=g
Dwumfour Abdullai Aziz Slide 61
Perform State Reduction
=f
=g
Dwumfour Abdullai Aziz Slide 62
Perform State Reduction
Dwumfour Abdullai Aziz Slide 63
Perform State Reduction
Dwumfour Abdullai Aziz Slide 64
Perform state reduction
This state diagram satisfies the original input–output
Specifications
it also produce the required output Sequence
for any given input sequence.
Dwumfour Abdullai Aziz Slide 65
FINITE STATE AUTOMATA
WITHOUT OUTPUT
Dwumfour Abdullai Aziz Slide 66
FINITE STATE AUTOMATA WITHOUT
OUTPUT
Dwumfour Abdullai Aziz Slide 67