co-1
1.
Explain the Verilog HDL.
2.
Describe the Verilog HDL significance in digital system design.
3.
Discuss the module in Verilog, and how is it different from a module instantiation?
4.
Draw the general block structure of simple programmable logic device.
5.
Interpret the fundamental differences between data flow modelling and behavioural
modelling in Verilog with suitable example.
6.
Discuss the Verilog code for F=ABC+AB’C+AB’C’ in Gate-level modelling.
7.
Explain the advantages and challenges of using hierarchical modelling (Functional
calling) in Verilog for large-scale digital designs.
8.
Examine the significance of Verilog module ports in shaping the interface. How do these
ports undergo declaration and what is their role in practical utilization?
9.
Extended the Verilog code for a Full Adder using a Half Adder, followed by a Testbench.
10.
Explain the structured design methodology.
11.
Explain the key features and advantages of using Verilog HDL for hardware description
12.
Extend an example of gate-level modelling in Verilog for a basic logic gate (e.g., AND
gate).
13.
Discuss the verification important in digital system design, and how is it achieved in
Verilog
14.
Compare the VHDL and Verilog HDL.
15.
Summarize the Verilog code for Half adder in data flow modelling
16.
Explore the structural model in Verilog HDL for a full subtractor, placing emphasis on
how NAND gates are utilized in the design.
17.
Explain the use of CMOS transmission gates in switch-level modelling with an example.
18.
Present a Verilog program that utilizes structured design principles to implement a Full
Subtractor
19.
Explain the Verilog code and verify a switch level a three-input static CMOS NOR gate?
20.
Explain the purpose of input and output ports in a Verilog module?
21.
Discuss the gate-level modelling in Verilog
22.
Discuss the dataflow modelling in Verilog
22.
Explain the significance of input and output ports in the context of Verilog modules with
an example.
23.
Discuss the Verilog code for full adder in Behavioural modelling
24.
Explain in the terms “Hardware Encapsulation” and “Hardware modelling” with suitable
example using Verilog HDL.
25.
Present a clear flow graph and elucidate the TOP-down design methodology,
emphasizing its practical application in hardware modeling with Verilog HDL.
26.
Elaborate on the use of the Structured Implicit model in a Verilog program for an 8x1
MUX, providing a detailed explanation
27.
Expalin the CMOS transmission gates with diagram
Co-2
28.
Draw the general block structure of simple programmable logic device.
29.
Explain the gate array design
30.
Describe a significant advantage of employing cell-based design methodologies.
31.
Explain the structure of a Ripple carry adder with neat diagrams.
32.
Describe the fundamental characteristics of programmable logic devices (PLDs).
33.
Implement a diagram of an Array multiplier with labeled components in a digital design
tool, illustrating its practical application, and explain how the tool interprets and
executes the design
34.
Describes the short notes on data-path subsystem.
35.
Discribes the Asynchronous counter.
36.
Interpret the operational principles of one/zero detectors and standard logic gates in the
context of real-world scenarios, illustrating how their distinctive characteristics
contribute to specific advantages or limitations.
37.
Infer the importance of verification in the design flow process.
38.
State is the sea of gate design
39.
Define full custom design
40.
Explain the structure of a carry look ahead adder with neat diagrams.
41.
Estimate PLDs offer flexibility in digital system design.
42.
Expand the structure of an array multiplier and offer a detailed explanation of the
necessary design.
43.
Explain the differences between logical shifting and arithmetic shifting.
44.
Describes the synchronous counter.
45.
Delve into the interpretation of comparators and their integral role in enabling precise
and efficient comparison operations within data path subsystems
46.
Explain the importance of verification in the design flow process
47.
Define the programmable logic in digital design
48.
Infer the term "design flow" refer to in digital design
49.
Classify binary counters and explain each in detail
50.
Explain the concept behind cell-based design.
51.
Describes the types of the multipliers in detail.
52.
Illustrate the structure of a carry save adder through well-defined diagrams, emphasizing
clarity and accuracy
53.
Explain the diffrences between synchronous and asynchronous counters
54.
Elaborate on the distinctions between magnitude and equality comparators, providing
insights into how each type serves specific functions in the context of digital designs.
co-3
1.
Explain the classifications of timing controls in digital circuits.
2.
State the meant by controllability
3.
Discuss the Verilog code to find the first bit with a value 1 in Flag = 16'b
0010_0000_0000_0000.
4.
Describe the 4-bit BCD ripple counters with neat diagram.
5.
Infer a 3-bit binary counter using T flip-flop.
6.
Discover a top -level module “Stimulus”. Define Reg_in (4 bit) and Clk (1 bit) as register
variables and Reg_out (4 bits) as wire. Instantiate the module “shift -reg” in “stimulus”
block and connect the ports by ordered list. Declare A (4 bit) and clock (1 bit) as inputs
and B (4 bit) as output in “shift -reg” module. (No need to show internals). Write a
Verilog code for the above.
7.
Explain about Linked State Machines.
8.
Utilize your expertise in sequential systems to calculate the minimum count of flip-flops
necessary for implementing a machine with a reduced state table containing 12 rows.
9.
Discuss With an example explain about one Hot design Method using ASMs.
10.
Explain the state assignment.
11.
Infer the short notes on Timing controls and delay in Verilog
12.
State the Formal verification procedure.
13.
Discuss the guidelines for construction of state graph
14.
Explain briefly about FSM module Develop a Verilog code for melay model for 4 states.
Assume present state, next state, and output.
15.
Utilize the knowledge of Verilog HDL to derive the code for a 4-bit carry look-ahead
adder along with a well-crafted test bench.
16.
Describes the code for 3 to 8 decoder using Verilog HDL and test bench
17.
Illustrate the application capabilities in Verilog HDL by showcasing the code
implementation for a 4-bit up counter, accompanied by a thorough test bench
18.
Explain the Verilog HDL code for 4-bit Ripple carry adder with test bench.
19.
Define a finite state machine with the help of proper diagram.
20.
Describe a Mod-6 Synchronous counter by using JK Flip-flop
21.
Explain its classification of a finite state machine.
22.
Explain the FSM architecture cantered around shift registers.
23.
Describe With an example explain about one Hot design Method using ASMs.
24.
Describes the Verilog description of 4-bit ripple carry adder at gate level abstraction,
with a neat block diagram. Also, write stimulus block.
25.
Utilize the knowledge on digital design to showcase the outcomes of the following
operations: i) a & b ii) a && b iii) &a iv) a >> 1 v) a >>> 1 vi) y = {2{a}} vii) a ^ b viii) z = {a,
b}.
26.
Explain the code for 4-bit carry save adder using Verilog HDL and test bench.
27.
Illustrate the application capabilities in digital circuit design by explaining the principles
of Mealy and Moore models and comparing them, particularly focusing on Mealy circuit
characteristics.
Co-4
28.
Explain how asynchronous behaviour differs from synchronous operation, highlighting
key characteristics
29.
Define the asynchronous behaviour in the context of digital circuits.
30.
Explain why the analysis of asynchronous circuits is crucial during the design process.
31.
Explain two advantages of the asynchronous design methodologies in comparison to
synchronous approaches
32.
Compare the synchronous & Asynchronous counters.
33.
Demonstrate the knowledge on digital system components by explaining the role of
arbiters and their importance in resolving conflicts and distributing resources in digital
circuits.
34.
Describes the asynchronous BCD counter using JK flip- flops.
35.
Demonstrate the various types of hazards in sequential circuit design and the methods
to eliminate them. Give suitable examples.
36.
Sketch and Explain the Skew and Jitter.
37.
Define the synchronous behaviour in the context of digital circuits.
38.
Define the term "synthesis" with respect to asynchronous circuits.
39.
Explain the importance of analysing asynchronous circuits during the design process.
40.
Discuss about static 0 and 1 hazard
41.
Demonstrate the steps for the design of asynchronous sequential circuit
42. Illustrate an asynchronous circuit that has two inputs x1 and x2 and one output z. the
circuit is required to give an output whenever the input sequence (0,0), (0,1) and (1,1) received
but only in that order.
43.
Explain an original circuit that exhibits a dynamic hazard.
44.
Utilize the knowledge on state assignment techniques to create an efficient plan with
minimal states, and deduce the expressions for next state and output based on the flow
table illustrated in the Figure.
45. Devising a hazard-free, minimum-cost POS (Product of Sums) implementation for the
function f(x1, ..., x4) = πM(0, 2, 3, 7, 10) + D(5, 13, 15).
46. Static hazard & Dynamic hazard.
47. Define state reduction in the context of asynchronous sequential circuits.
48. Define hazards in the context of digital circuits.
49. types of asynchronous circuits and explain each.
50. Differentiate between state Assignment Synchronous circuit and state assignment
asynchronous circuit.
51. Prepare a hazard-free minimum-cost implementation of the function. f (x1, · · · , x4)
=Σm(0, 4, 11, 13, 15) + D(2, 3, 5, 10) Design an asynchronous sequential circuit has two inputs
X2 and X1 and one output Z. When X1=0, the output Z is 0. The first change in X2 that occurs
while X1 is 1 will cause output Z to be 1. The output Z will remain 1 until X1 returns to 0.
52. Explain the types of asynchronous circuits and explain each.
53. Preparing an optimal state assignment with the least number of states and deriving the
corresponding next state and output expressions from the flow table in the provided figure.
54. Describes the state assignment in the context of asynchronous circuit design.