Digital Logic Design
Chapter Two:
Logic Gates and Boolean Algebra
Digital Logic Gates and Families
DIGITAL LOGIC GATES
 The logic gate are the fundamental building blocks from which all other
logic circuits and digital systems are constructed.
 Digital (logic) circuits operate in the binary mode where each input and
output voltage is either a 0 or a 1
 This characteristic of logic circuits allows us to use Boolean algebra as a tool
for the analysis and design of digital systems.
 Boolean algebra is a relatively simple mathematical tool that allows us to
describe the relationship between a logic circuit’s output(s) and its Inputs as
an algebraic equation (a Boolean expression).
 A Boolean variable is a quantity that may, be equal to either 0 or 1.
 Thus, Boolean 0 and 1 do not present actual numbers but instead represent
the state of a voltage variable, or what is called its logic level.
 Truth Table:- A truth table lists all possible combinations of input binary
variables and the corresponding outputs of a logic system.
 The number of possible input combinations will equal to 2n for an n-input
truth table.
3
Cont..
 There are three basic logic gates, namely the OR gate, the AND gate and the NOT
gate.
 Other logic gates that are derived from these basic gates are the NAND gate, the
NOR gate, the EXCLUSIVEOR gate and the EXCLUSIVE-NOR gate.
A. THE INVERTER(NOT Gate)
 A NOT gate is a one-input, one-output logic circuit whose output is always the
complement of the input.
 The inverter changes one logic level to the opposite level. In terms of bits, it
changes a 1 to a 0 and a 0 to a 1.
 Standard logic symbols for the inverter are shown in Figure below.
 The NOT operation on a logic variable X is denoted as
 This operation is summarized using truth table as shown below.
4
B. The OR Gate
 An OR gate is a logic circuit with two or more inputs and one output.
 Figure below is the logic symbol for a two-input OR gate.
Fig. symbol of OR gate
Fig. truth table of OR gate
 The OR gate operates in such a way that its output is HIGH (logic’ 1) if either input A
or B or both are at a logic 1 level, otherwise the output will be LOW
 The operation is summarized using truth table for two inputs variables.
 Addition in Boolean algebra involves variables whose values are either binary 1 or
binary 0.
 The basic rules for Boolean addition are as follows:
 Expression:-If one input variable is A, if the other input
variable is B, and if the output variable is X, then the Boolean expression is:
X=A+B
 For instance, the function of a 3-input OR gate can be expressed as X = A + B + C.
and so on.
5
C. THE AND GATE
 An AND gate is a logic circuit having two or more inputs and one output.
 Figure below is the logic symbol for a two-input AND gate (a).
FIGURE (a) AND gate symbol. (b) Truth table for the AND operation;
 The AND gate is a circuit that operates in such a way that its output is HIGH only
when all its inputs are HIGH. For all other cases the AND gate output is LOW.
 The operation is summarized using truth table for two inputs variables in above
table (b).
 Boolean multiplication follows the same basic rules governing
binary multiplication.
 Expression:- If one input variable is A, the other input variable is B, and
the output variable is X, then the Boolean expression is X=AB
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D. THE NAND GATE
 The NAND gate is a popular logic element because it can be used as a universal
gate: that is, NAND gates can be used in combination to perform the AND, OR, and
inverter operations.
 The term NAND is a contraction of NOT-AND and implies an AND function with a
complemented (inverted) output.
 The standard logic symbol for a 2-input NAND gate is shown below.
 A NAND gate produces a LOW output only when
all the inputs are HIGH. When any of the inputs is LOW, the output will be HIGH.
 The operation is summarized using truth table above.
 The truth table in above table shows that the NAND gate output is the exact inverse
of the AND gate for all possible input conditions.
 NAND gate operation is logically expressed as
 In general, the Boolean expression for a NAND gate with more than two inputs can
be written as
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E. The NOR Gate
 The NOR gate, like the NAND gate, is a useful logic element because it can also be
used as a universal gate;
 The term NOR is a contraction of NOT-OR and implies an OR function with an
inverted (complemented) output.
 The standard logic symbol for a 2-input NOR gate and its equivalent OR gate
followed by an inverter are shown in figure below.
 A NOR gate produces a LOW output when any of its inputs is HIGH.
Only when all of its inputs are LOW is the output HIGH.
 The truth table is shown as above.
 The output of a two-input NOR gate is logically expressed as
 In general, the Boolean expression for a NOR gate with more than two inputs can
be written as:
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F. EXCLUSIVE-OR Gate
 Standard symbols (a) and the truth table (b) for an exclusive-OR (XOR) gate are
shown in Figure below.
 The XOR gate has only two inputs.
 The output of an exclusive-OR gate is HIGH only when the two inputs are at
opposite logic levels.
 The output of a two-input EX-OR gate is expressed by
 Example:- How do you implement three-input and four-input EX-OR logic functions
with the help of two-input EX-OR gates?(a)
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G. The Exclusive-NOR Gate
 Standard symbols (a) for an exclusive-NOR (XNOR) gate are shown in Figure below
 Like the XOR gate, an XNOR has only two inputs.
 The bubble on the output of the XNOR symbol indicates that its output is opposite
that of the XOR gate.
 When the two input logic levels are opposite, the output of the exclusive-NOR gate
is LOW.
 The truth table is shown above.
 The output of a two-input EX-NOR gate is expressed by:
 Example:-How do you implement a three-input EX-NOR function using only twoinput EX-NOR gates?
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Timing Diagrams
 A timing diagram ¡s a graphical method of showing the exact output behavior of a
logic circuit for every possible set of input conditions.
 It is often used to describe the operation of digital devices because its visual
characteristics are much easier to understand than a word explanation.
 Example 1:- If two waveforms, A and B, are applied to the AND gate inputs as in
Figure below, what is the resulting output waveform?
A
B
x
X
 If two waveforms, A and B, are applied to the AND gate inputs as in Figure below,
what is the resulting output waveform?
A
B
Digital logic design by Nigatu A
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Timing Diagrams
 Example 3:- For the situation depicted in Figure below, determine the waveform at
the OR gate output and AND gate output?
 Example 4:-Determine the output waveform of a NAND gate, a NOR gate, a XOR
gate and a X-NOR having the inputs shown in Figure below.
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Digital Logic Families(ICs families)
 An integrated circuit (abbreviated IC) is a small silicon semiconductor crystal, called
a chip, containing the electronic components for the digital gates.
 The various gates are interconnected inside the chip to form the required circuit.
 The chip is mounted in a ceramic or plastic container, and connections arc welded
to external pins to form the integrated circuit.
 The number of pins may range from 14 in a small IC package to 64 or more in a
larger package.
 Each IC has a numeric designation printed on the surface of the package for
identification.
 Vendors publish data books that contain descriptions and all other information
about the ICs that they manufacture.
 Levels of Integration:-Digital ICs are often categorized according to their circuit
complexity as measured by the number of logic gates in a single package.
 The differentiation between those chips that have a few internal gates and those
having hundreds or thousands of gates is made by a customary reference to a
package as being either a small-, medium-, large-. Or very large -scale integration
device.
13
Cont.…
 Small-scale integration (SSI): Devices contain several independent gates in a single package.
 The number of gates is usually fewer than 10 and is limited by the number of pins
available in the IC.
 Medium-sale integration (MSI): Devices have a complexity of approximately 10 to100 gates in a single package.
 They usually perform specific elementary digital operations such as decoders, adders, or
multiplexers.
 Large-scale integration (LSI): Devices contain between 100 and a few thousand gates in a single package.
 They include digital systems such as processors, memory chips, and programmable logic
devices.
 Very large-scale integration (VLSI): Devices contain thousands of gates within a single package.
 Examples are large memory arrays and complex microcomputer chips.
 Because of their small size and low cost, VLSI devices have revolutionized the computer
system design technology, giving the designer the capabilities to create structures that
previously were uneconomical.
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Boolean Algebra and Logic
Simplification
BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION
Boolean Operation and Expression
 Boolean algebra is the mathematics of digital systems.
 Boolean algebra is a means for expressing the relationship between a
logic circuit’s inputs and outputs.
 Variable, complement, and literal are terms used in Boolean
algebra.
 A variable is a symbol used to represent a logical quantity.
 Any single variable can have a 1 or a 0 value.
 The complement is the inverse of a variable and is indicated by a bar
over a variable (over bar) or by a prime.
 Example, the complement of the variable A is A’. If A = 1, then A =0.
If A = 0, then A’ = 1.
 A literal is a variable or the complement of a variable.
Literal is may be variable may be complement or may be both.
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Laws Of Boolean Algebra
 The basic laws of Boolean algebras are
 The commutative laws for addition and multiplication,
 The associative laws for addition and multiplication, and
 The distributive law.
Commutative Laws
 The commutative law of addition for two variables is written as
 Using logic circuit,
 The commutative law of multiplication for two variables is
 Using logic circuit,
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Associative Laws
 The associative law of addition is written as follows for three
variables:
 Using logic circuit,
 The associative law of multiplication is written as follows for three
variables:
 Using logic circuit,
 The distributive law:- is written for three variables as follows:
 Using logic circuit,
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Rules of Boolean Algebra
 The following table lists 12 basic rules that are useful in manipulating and
simplifying Boolean expressions.
 Rules 1 through 9 will be viewed in terms of their application to logic gates.
 Rules 10 through 12 will be derived in terms of the simpler rules.





Rule 1. A + 0 = A :- A variable ORed with 0 is always equal to the variable.
Rule 2. A + 1 = 1 :- A variable ORed with 1 is always equal to 1.
Rule 3. A . 0 = 0 :- A variable ANDed with 0 is always equal to 0.
Rule 4. A . 1 = A :- A variable ANDed with 1 is always equal to the variable.
Rule 5. A + A =A:- A variable ORed with itself is always equal to the variable.
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Cont…
 Rule 11. A + A’B = A + B :- This rule can be proved as follows:
 Rule 12. (A + B)(A + C) = A + BC :- This rule can be proved as follows:
 Ex:- show the above both rules using truth table.
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Duality
 The duality principle:- It states that every algebraic expression deducible from the
postulates of Boolean algebra remains valid if the operators and identity elements
are interchanged.
 This means one expression can be obtained from the other in each pair by
interchanging every element.
 That is, we simply interchange OR and AND operators and replace 1‘s by 0’s and 0’s
by 1 ‘s.
 Example observe the following table at a and b:
Digital logic design by Nigatu A
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DEMORGAN'S THEOREMS
 One of DeMorgan's theorems is stated as follows:
 The complement of a product of variables is equal to the sum of the
complements of the variables,
 The formula for expressing this theorem for two variables is
(XY)’ = X’ + Y’
 Using logic circuit,
 DeMorgan's second theorem is stated as follows:
 The complement of a sum of variables is equal to the product of the
complements of the variables.
 The formula for expressing this theorem for two variables is
(X + Y) = X’Y’
 Using logic circuit,
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Cont…
 As stated, DeMorgan's theorems also apply to expressions in which there
are more than two variables.
 The following examples illustrate the application of DeMorgan's theorems
to 3-variable and 4-variable expressions.
 Example:-a) Apply DeMorgan's theorems to the expressions (XYZ)’ and (X + Y + z)’
soln:- (XYZ)’ = X’ + Y’ + Z’
(X + Y + Z) = X’Y’Z’
b) Apply DeMorgan's theorem to the expression (X’ + Y’)’ + Z’
 Each variable in DeMorgan's theorems as stated in above can also represent
a combination of other variables.
 Example:- Apply DeMorgan's theorems
a) [(AB + C)’(A + BC)]’
b) [(A + BC’)’ + D(E + F’)’]’
 Ex:23
Boolean Expression for a Logic Circuit
 A Boolean function is an expression formed with binary variables, the two binary
operators OR and AND, and unary operator NOT, parentheses, and an equal sign.
 To derive the Boolean expression for a given logic circuit, begin at the left-most
inputs and work toward the final output, writing the expression for each gate.
 For the example circuit in Figure below, the Boolean expression is determined as
follows:
 Example:-drive the output Boolean expression for the following ckt
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Implementing logic circuits from Boolean expression
 When the operatíon of a circuit is defined by a Boolean expression, we can draw a
logic-circuit diagram directly from that expression,
 Example:- Draw a logic circuit for the following expressions
X = (A + B)(B’ + C)
 EX:- Draw a logic circuit for the following Boolean function.
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SIMPLIFICATION USING BOOLEAN ALGEBRA
 A literal is a primed or unprimed variable.
 When a Boolean function is implemented with logic gates, each literal in the
function designates an input to a gate, and each term is implemented with a gate.
 The minimization of the number of literals and the number of terms results in a
circuit with less equipment.
 The number of literals in a Boolean function can be minimized by algebraic
manipulations, and Unfortunately, there are no specific rules to follow that will
guarantee the final answer.
 The only method available is a cut-and-try procedure employing the postulates, the
basic theorems, and any other manipulation method that becomes familiar with
use.
 Example:-Using Boolean algebra techniques, simplify this expression:
a) F = AB + A(B +C) + B(B + C)
b) F = AB’ + A(B + C)’ + B(B +C)’
c) F = [AB’(C + BD) + A’B’]C
d) F = [AB(C + (BD)’) + (AB)’]CD
e) F = AB + (AC)’ + AB’C(AB + C).
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CANONICAL AND STANDARD FORMS
 All Boolean expressions, regardless of their form, can be converted into either of
two standard forms:
i.
The sum-of-products form(SOP) or
ii. The product-of-sums form(POS).
 Standardization makes the evaluation, simplification, and implementation of
Boolean expressions much more systematic and easier.
 Product Term:- A term consisting of the product of literals (variables or their
complements). For example, ABC’ is a product term.
 Sum of Products (SOP):-When two or more product terms are summed by Boolean
addition, the resulting expression is a sum-of-products (SOP).
 Some example are,
 Also, an SOP expression can contain a single-variable term, as in A + AB’C + BC’D.
 In an SOP expression a single over bar cannot extend over more than one variable;
however, more than one variable in a term can have an over bar.
27
Cont…
 The domain of a general Boolean expression is the set of variables contained in the
expression in either complemented or uncomplemented form.
 For example, the domain of the A’B + AB’C is the set of variables A, B, C and the
domain of the expression ABC + CDE + BCD is the set of variables A, B, C, D, E.
Conversion of a General Expression to SOP Form
 Any logic expression can be changed into SOP form by applying Boolean algebra
techniques.
 For Example:-the expression A(B + CD) can be converted to SOP form by applying
the distributive law:
a) A(B + CD)
b) AB + B(CD + EF)
c) (A + B)’(B + C + D)
d) ((A + B)’ + C)’
• Note:-An SOP expression is equal to 1 only if one or more of the
product terms in the expression is equal to 1.
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The Standard SOP form




A standard SOP expression is one in which all the variables in the domain appear in each
product term in the expression.
Example:a) ABC + A’B’C + ABC’ +A’BC standard SOP
b) AB’C + A’B’C’ + AC’
not standard SOP
Standard SOP expressions are important in constructing truth tables, and in the Karnaugh
map simplification method, which is covered next section.
Any nonstandard SOP expression (referred to simply as SOP) can be converted to the
standard form using Boolean algebra.
Converting Product Terms to Standard SOP



This can be done by using rule 6(A + A’ = 1), A variable added to its complement equals 1.
STEP 1:- Multiply each nonstandard product term by a term made up of the sum of a missing
variable and its complement(A + A’).
STEP 2:- Repeat Step I until all resulting product terms contain all variables in the domain in
either complemented or uncomplemented form.
 Example:- Convert the following Boolean expression into standard SOP form:
a) F = AB’C + A’B’ + ABC’D
b) F = AB + AC’ + B’C + B
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Cont…


Sum Term:- :- A term consisting of the sum of literals (variables or their complements), For
example, A + B + C’ is a sum term.
When two or more sum terms are multiplied, the resulting expression is a product-of-sums
(POS).
Some examples are:



.
In a POS expression, a single overbar cannot extend over more than one variable;
For example, a POS expression can have the term

The Standard POS Form



A standard POS expression is one in which all the variables in the domain appear in each sum
term in the expression.
For example, a)
standard POS form
b)
not standard POS form
Any nonstandard pas expression (referred to simply as POS) can be converted to the standard
form using Boolean algebra.
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Converting a Sum Term to Standard POS
 This can be done by using Boolean algebra rule 8 (A . A’ = 0), A variable multiplied
by its complement equals 0.
 Step 1. Add to each nonstandard product term a term made up of the product of
the missing variable and its complement.
 Step 2. Apply rule 12 A + BC = (A + B)(A + C)
 Step 3. Repeat Step 1 until all resulting sum terms contain all variables in the
domain in either complemented or uncomplemented form.
 Example:-Convert the following Boolean expression into standard POS form:
a)
b)
c)
 Note:- A POS expression is equal to 0 only if one or more of the sum terms in the
expression is equal to .
 example:- Determine the binary values of the variables for which the following
standard POS expression is equal to 0:
a)
b)
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CANONICAL AND STANDARD FORMS
 Minterm:- it is a product term containing all n variables of the function in either
true or complemented.
 That is, Miniterms(m) = Standard Product Terms
 Each minterm is obtained by an AND operation of the variables in their true form or
complemented form.
 These product terms are called the standard products or minterms.
 In the minterm, a variable will possess the value 1 if it is in true form, whereas, it
contains the value 0 if it is in complemented form.
 Maxterms:-it is a sum term containing all n variables of the function in either true
or complemented form.
 That is, Maxterms(M) = Standard Sum-terms
 Each maxterm is obtained by an OR operation of the variables in their true form or
complemented form.
 Note that, in the maxterm, a variable will possess the value 0, if it is in true form,
whereas, it contains the value 1, if it is in complemented form.
 For a three-variable function, eight minterms and maxterms are listed in the
following table in Figure below.
32
Cont…
 Note that each maxterm is the complement of its corresponding minterm, and vice
versa.
33
Cont…
 A Boolean function may be expressed algebraically from a given truth table by
forming a minterm for each combination of the variables that produces a 1 in the
function, and then taking the OR of all those terms.
 Similarlly, A Boolean function may be also expressed algebraically from a given
truth table by forming a maxterm for each combination of the variables that
produces a 0 in the function, and then taking the AND of all those terms.
 For example:-let see the following table for two function f1 and f2.
34
Cont….
 Miniterms :- function f1 is 1, for minterms 001, 100 and 111
 Therefore:
f1 = m1 + m4 + m7
f1 = 001 + 100 + 111, using binary representation.
Now using variables, f1 = x’y’z + xy’z’ + xyz
 Maxterms:- function f2 is 0, for maxterms 000, 010, 011, 101 and 110
 Therefere,
f1 = M0.M2.M3.M5.M6
f1 = (000)(010)(011)(101)(110) using binary
Now using variables,
f1 = (x + y + z) (x + y’ + z) (x + y’ + z’) (x’ + y + z’) (x’ + y’ + z)
 Similarly, it may be easily verified that for function f2 is 1 for:
 Miniterms: f2 = 011 + 101 + 110 + 111
f2 = m3 + m5 + m6 + m7
f2 = x’yz + xy’z + xyz’ + xyz
 Maxterms:- function f2 is 0 for:
f2 = M0.M1.M2.M4
f2 = (000)(001)(010)(100)
f2 = (x + y + z) (x + y + z’) (x+ y’ + z) (x’ + y + z)
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 From these demonstrate that,
 Any Boolean function can be expressed as a sum of minterms (by ‘sum” is
meant the ORing of terms). And
 Any Boolean function can be expressed as a product of Maxterms (by ‘product”
is meant the ANDing of terms)
 Boolean functions expressed as a sum of minterms or product of maxterms are said
to be in CANONICAL form(standard forms).
Canonical Sum of Minterms
 We have seen that any Boolean function can be expressed as a sum of minterms.
 Sum of minterms can be expressed in a compact form by listing the corresponding
decimal-equivalent codes of the minterms containing a function value of 1.
 For example, from the above truth table, f1 is 1 for m1, m4 and m7 and,
f2 is 1 for m3, m5, m6 and m7.
 So that using decimal representation.
f1(x, y, z) = ∑(1, 4, 7) and f2(x, y, z) = ∑(3, 5, 6, 7)
 where ∑ represents the summation of minterms corresponding to decimal codes.
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Canonical product of Maxterms
 Similarly, products of maxterms can be expressed in a compact form by listing the
corresponding decimal-equivalent codes of the maxterms containing a function
value of 0.
 For example:- in above truth table, f1 is 0 for M0, M2, M3, M5, and M6
and,
f2 is 0 for M0, M1, M2, and M4
 Therefore, using decimal representation,
f1(x, y, z) = ∏(0, 2, 3, 5, 6)
f2(x, y, z) = ∏(0, 1, 2, 4)
Where ∏ represents the product of maxterms corresponding to decimal codes.
 Therefore, we can express Boolean function by different representation ways if it is
in standard forms:
 Binary representation
 Variable representation
 Decimal representation
37
Cont…
 Example 1: - Express the Boolean function F(A,B, C) = A + B ‘C
a) In a sum of minterms (in decimal notation) and
b) In a product of maxterms (in decimal notation)
 Solution:a) first the function should be converted to standard miniterms forms
 When it is rearranged, the function become
F(A, B, C) = A’B’C + AB’C’ + AB’C + ABC’ + ABC
F(A, B, C) = 001 + 100 + 101 + 110 + 111
F(A, B, C) = m1 + m4 + m5 + m6 + m7
F(A, B, C) = ∑ (1, 4, 5, 6, 7)
b) the function should be standard maxterms, when it is converted,
F(A, B, C) = (A + B + C) (A + B’ + C) (A + B’ + C’)
F(A, B, C) = (000)(010)(011)
F(A, B, C) = M0.M2.M3
F(A, B, C) = ∏(0, 2, 3)
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Example
 Example 2: - Express the Boolean function variable expansion:
i.
In a sum of minterms (in decimal notation) and
ii. In a product of maxterms (in decimal notation)
a) F(A,B,C) =A+BC
b) F(x, y, z) = xy + x’z
c) F3(A, B, C, D) = (AB + CD)(A’B’ + C’D’)
d) F1(x, y, z) = y’ + xy + x’yz’
e) F (A, B, C, D) = AB + ACD
f) F(A,B,C) =(A+B’)(B+C)(A+C’)
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Conversion between Canonical Forms
 The complement of a function expressed as the sum of minterms equals the sum of
minterms missing from the original function.
 This is because the original function is expressed by those minterms that make the
function equal to 1, whereas its complement is a 1 for those minterms that the
function is a 0.
 As an example, consider the function
40
Cont…
 To convert from one canonical form to another, interchange the symbols ∑ and ∏
and list those numbers missing from the original form.
 In order to find the missing terms, one must realize that the total number of
minterms or maxterms is 2n, where n is the number of binary variables in the
function.
 A Boolean function can be converted from an algebraic expression to sum of
miniterms and product of maxterms by using a binary expansion methods
 Consider, for example, the Boolean expression
F(x, y, z) = xy + x’z
Solution
 In xy, z is missed and, in x’z, y is missed so that, z can be 0 or 1 and y can be 0 or 1
 In binary forms, F(x, y, z) = xy + x’z
F(x, y, z) = 110 + 001
111 + 011
 From this, sum of minterms is F(x, y, z) = ∑(1, 3, 6, 7)
 Since there are a total of eight minterms or maxterms in a function of three
variable, we determine the missing terms to be 0, 2, 4, and 5.
 The function expressed in product of maxterm is
41
F(x, y, z) = ∏(0, 2, 4, 5)
Example
 Example 2: - Express the Boolean function using numerical expansion
i.
In a sum of minterms (in decimal notation) and
ii. In a product of maxterms (in decimal notation)
a) F(A,B,C) =A+BC
b) F(x, y, z) = xy + x’z
c) F3(A, B, C, D) = (AB + CD)(A’B’ + C’D’)
d) F1(x, y, z) = y’ + xy + x’yz’
e) F (A, B, C, D) = AB + ACD
f) F(A,B,C) =(A+B’)(B+C)(A+C’)
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THE KARNAUGH MAP(k-map)
 A Karnaugh map provides a systematic method for simplifying Boolean expressions
and, if properly used, will produce the simplest SOP or POS expression possible,
known as the minimum expression.
 As you have seen, the effectiveness of algebraic simplification depends on your
familiarity with all the laws, rules, and theorems of Boolean algebra and on your
ability to apply them.
 The Karnaugh map, on the other hand, provides a "cookbook" method for
simplification.
 The purpose of a Karnaugh map is to simplify a Boolean expression.
 A Kamaugh map is similar to a truth table because it presents all of the possible
values of input variables and the resulting output for each value.
 The Karnaugh map is an array of cells in which each cell represents a binary value
of the input variables.
 Karnaugh maps can be used for expressions with two, three, four and five variables.
 The number of cells in a Karnaugh map is equal to the total number of possible
input variable combinations as is the number of rows in a truth table.
 For three variables, the number of cells is 23 = 8.
 For four variables, the number of cells is 24 = 16.
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The 3-Variable Karnaugh Map
 The 3-variable Karnaugh map is an array of eight cells. as shown in Figure below
 In this case, A, B, and C are used for the variables although other letters could be
used.
 Binary values of A and B are along the left side (notice the sequence) and the
values of C are across the top.
 The value of a given cell is the binary values
of A and B at the left in the same row
combined with the value of C at the top in
the same column.
 For example, the cell in the upper left corner
has a binary value of 000 and the cell in the
lower right corner has a binary value of 101.
 Figure ( b) shows the standard product
terms that are represented by each cell in
the Karnaugh map.
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The 4-Variable Karnaugh Map
 The 4-variable Karnaugh map is an array of sixteen cells, as shown in Figure (a).
 Binary values of A and B are along the left side and the values of C and D are across
the top.
 The value of a given cell is the binary values of A and B at the left in the same row
combined with the binary values of C and D at the top in the same column.
 For example, the cell in the upper right corner has a binary value of 00 I 0 and the
cell in the lower right corner has a binary value of 1010.
Digital logic design by Nigatu A
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Cell Adjacency
 The cells in a Karnaugh map are arranged so that there is only a single-variable
change between adjacent cells.
 Adjacency is defined by a single-variable change.
 In the 3-variable map the 010 cell is adjacent to the 000 cell, the 011 cell, and the
110 cell.
 The 010 cell is not adjacent to the 001 cell, the 111 cell, the 100 cell, or the 101
cell.
 Cells that differ by only one variable are adjacent.
 Cells with values that differ by more than one variable are not adjacent.
 Physically, each cell is adjacent to the cells that are immediately next to it on any of
its four sides.
 A cell is not adjacent to the cells that diagonally touch any of its corners.
 Also, the cells in the top row are adjacent to the corresponding cells in the bottom
row and the cells in the outer left column are adjacent to the corresponding cells in
the outer right column.
 Although the same rules for adjacency apply to Karnaugh maps with any number of
cells.
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KARNAUGH MAP SOP MINIMIZATION
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Mapping a Standard SOP Expression
For an SOP expression in standard form, a I is placed on the Karnaugh map for each
product term in the expression.
Each 1 is placed on a cell corresponding to the value of a product term.
When an SOP expression is completely mapped, there will be a number of 1s on
the Karnaugh map equal to the number of product terms in the standard SOP
expression.
The cells that do not have a 1 are the cells for which the expression is 0.
Usually, when working with SOP expressions, the 0s are left off the map.
The following steps show the mapping process.
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Cont…
 Example1:- Map the following standard SOP expression on a Karnaugh map:
F(A, B, C) = A’B’C + A’BC’ + ABC’ + ABC
SOLUTION:- convert to binary represantation
F(A, B, C) = A’B’C + A’BC’ + ABC’ + ABC
F(A, B, C) = 001 + 010 + 110 + 111
 Example 2:-Map the following sum of mininterms expression on a Karnaugh map:
F(x, y, z) = ∑ (2, 3, 4, 5)
 SOLUTION: - convert to binary
F(x, y, z) = m2 + m3 + m4 + m5
F(x, y, z) = 010 + 011 + 100 + 101
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 Example 3:- Map the following standard SOP expression on a Karnaugh map:
F(A, B, C, D) = A’B’C’D + A’B’CD + A’BC’D’ + AB’CD’ + ABC’D’ +ABC’D + ABCD
 SOLUTION:- Convert to binary forms
F(A, B, C, D) = 0001 + 0011 + 0100 + 1010 +
1100 + 1101 + 1111
F(A, B, C, D) =∑ (1, 3, 4, 10, 12,13,15)
Mapping a Nonstandard SOP Expression
 A Boolean expression must first be in standard form before you use a K-map.
 If an expression is not in standard form, then it must be converted to standard form
by numerical expansion.
 Map the following SOP expression on a Karnaugh map:
F(A, B, C) = A’ + AB’ + ABC’
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CONT…
SOLUTION: The SOP expression is obviously not in standard form because each product term
does not have three variables.
 The first term is missing two variables, the second term is missing one variable, and
the third term is standard.
 First expand the terms numerically as follows:
So, F(A,B,C) = ∑(0, 1, 2, 3, 4, 5, 6)
Map each of the resulting binary
values by placing a I in the
appropriate cell of the 3-variable
Karnaugh map in Figure below.
Example:
a)
b)
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Karnaugh Map Simplification of SOP Expressions
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After an SOP expression has been mapped, a minimum SOP expression is obtained by
grouping the Is and determining the minimum SOP expression from the map.
Grouping the 1s:- The goal is to maximize the size of the groups and to minimize the number
of groups. Rules:
Step 1:- A group must contain either 1, 2, 4, 8, or 16 cells, which are all powers of two. In the
case of a 3-variable map, 2 3 = 8 cells is the maximum group.
Step 2:- Each cell in a group must be adjacent to one or more cells in that same
group. but all cells in the group do not have to be adjacent to each other.
Step3:- Always include the largest possible number of 1s in a group in accordance with rule 1
Step 4:- Each I on the map must be included in at least one group. The Is already in a group
can be included in another group as long as the overlapping groups include non common 1s.
 Example:-Group the Is in each of the Karnaugh maps in Figure below.
Digital logic design by Nigatu A
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Determining the Minimum SOP Expression from the Map
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The following rules are applied to find the minimum product terms and the minimum SOP
expression:
Step 1. Group the cells that have 1s. Each group of cells containing 1s creates one product
term composed of all variables that occur in only one form (either uncomplemented or
complemented) within the group.
Variables that occur both uncomplemented and complemented within the group are
eliminated.
Step 2. Determine the minimum product term for each group.
Step3 . When all the minimum product terms are derived from the Karnaugh map, they are
summed to form the minimum SOP expression.
Example:-Determine the product terms for the Karnaugh map in Figure below and write the
resulting minimum SOP expression.
Digital logic design by Nigatu A
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cont…
 Example 4.1. Simplify the Boolean function by using SOP K-MAP minimization
a) F (A, B, C) = A’BC + AB’C’ + AB’C’ + AB’C
b) F (A, B, C) = A’B’C + A’BC + A’BC’ + AB’C + ABC.
c) F (A, B, C) = ∑(0, 2, 4, 5, 6).
d) F(A, B, C, D) = ABCD + AB’C’D’ + AB’C + AB
e) F(W, X,Y, Z) = ∑(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)
f) F (W, X,Y, Z) = ∑(3, 4, 5, 7, 9, 13, 14, 15)
g) F (W, X, Y, Z) =∏(0, 1, 4, 5, 6, 8, 9, 12, 13, 14)
"Don't Care" Conditions
 Sometimes a situation arises in which some input variable combinations are not
allowed.
 For example, recall that in the BCD code covered in Chapter 2, there are six invalid
combinations: 1010, 1011, 1100, 1101, 1110, and 1111.
 Since these unallowed states will never occur in an application involving the BCD
code, they can be treated as "don't care" terms with respect to their effect on the
output.
 That is, for these "don't care" terms either a 1 or a 0 may be assigned to the
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output: it really does not matter since they will never occur.
 The "don't care" terms can be used to advantage on the Karnaugh map.
 Figure below shows that for each "don't care" term, an X is placed in the cell.
 When grouping the 1s, the X can be treated as 1 s to make a larger grouping or as
0s if they cannot be used to advantage.
 The larger a group, the simpler the resulting term will be.
 Example:- Obtain the minimal sum of the products for the function
a) F (A, B, C, D) = ∑(1, 3, 7, 11, 15) + d(0, 2, 5)
b) F(A,B,C,D)= ∑(0,2,3,5,7,8, 13) + d(1,6, 12)
c) F(A,B,C,D)= ∑(1,7,9,1O, 12, 13, 14, 15) + d(4, 5, 8)
d) F(A, B, C, D) = ∑(2, 8, 11, 15)+ d(3, 12, 14)
e) F (W, X, Y, Z) = ∑(0, 2, 6, 11, 13, 15) + d (1, 9, 10, 14)
f) F (A, B, C, D) = ∑(0, 8, 10, 11, 14) + d (6)
g) F (A, B, C, D) = ∑(2, 8, 11, 15) + d (3, 12, 14)
h) F (W, X, Y, Z) = ∑(0, 2, 6, 11, 13, 15) + d (1, 9, 10, 14)
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KARNAUGH MAP POS MINIMIZATION
 The approaches are much the same except that with POS expressions, 0s
representing the standard sum terms are placed on the K-map instead of 1s.
 For a POS expression in standard form, a 0 is placed on the K-map for each sum
term in the expression.
 Each 0 is placed in a cell corresponding to the value of a sum term.
 When a POS expression is completely mapped, there will be a number of 0s on the
K-map equal to the number of sum terms in the standard POS expression.
 The cells that do not have a 0 are the cells for which the expression is 1.
 Usually, when working with POS expressions, the 1s are left off.
 The following steps and the illustration in Figure below show the mapping process.
 Step 1. Determine the binary value of each sum term in the standard POS expression.
This is the binary value that makes the term equal to 0.
 Step 2. As each sum term is evaluated, place a 0 on the K-map in the corresponding cell.
 Example:-Map the following standard POS expression on a K-map:
a)
b)
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Karnaugh Map Simplification of POS Expressions
 The process for minimizing a POS expression is basically the same as for an SOP
expression except that you group 0s to produce minimum sum terms instead of
grouping 1s to produce minimum product terms.
 The rules for grouping the 0s are the same as those for grouping the 1s.
 EXAMPLE:- Use a K-map to minimize the following standard POS expression:
a) F(A, B, C) =
b) F (X, Y, Z) =
c) F(A, B, C, D) = ∏(2, 8, 11, 15)
d) F (W, X, Y, Z) = ∏(0, 2, 6, 11, 13, 15)
e) F (A, B, C, D) = ∑(0, 8, 10, 11, 14)
f) F (A, B, C, D) = ∏(2, 8, 11, 15) + d (3, 12, 14)
g) F (W, X, Y, Z) = ∑(0, 2, 6, 11, 13, 15) + d (1, 9, 10, 14)
 Example2:- Using the Karnaugh map method, simplify the following functions,
obtain their sum of the products form, and product of the sums form. Realize them
with basic gates.
(a) F(W,X,Y,Z)= ∑(1,3,4,5,6,7,9, 12, 13)
(b) F(W,X,Y,Z)= ∏(1,5,6,7,11, 12, 13,15)
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FIVE-VARIABLE KARNAUGH MAPS
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Boolean functions with five variables can be simplified using a 32-cell Kamaugh map.
Actually, two 4-variable maps (16 cells each) are used to construct a S-variable map.
A Kamaugh map for five variables (ABCDE) can be constructed using two 4-variable maps
with which you are already familiar.
Each map contains 16 cells with all combinations of variables B, C, D, and E.
One map is for A = 0 and the other is for A = I, as shown in Figure below.
Cell Adjacencies
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You already know how to determine adjacent cells within the 4-variable map.
The best way to visualize cell adjacencies between the two 16-cel1 maps is to imagine that
the A = 0 map is placed on top of the A = I map.
Each cell in the A = 0 map is adjacent to the cell directly below it in the A = I map.
Digital logic design by Nigatu A
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Cont…
 Example:- for the below k-map, Combining these terms into the simplified SOP
expression yields:
X = DE’ + B’CE + A’BD’ + BC’ D’E
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Cont…
 Example:-
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