Interview Experience
Qualcomm - Hardware
30th Nov, 2023 (1 hour)
1. Questions on MTech project.
2. Draw four variable k-map. Which coding you have used for this and why? Ans: gray code
since one bit change.
3. Why are we so concerned about low power VLSI? Ans: cost effective. Then they said how
much cost will be increased!! It’s not that much. Then I answered wrt battery backup. They
were satisfied.
4. Tell some techniques for low power design. Refer Physical design lectures by ISG Sir.
5. Write a Verilog code to swap 2 numbers. Refer Verilog lectures by ISG Sir.
6. Design a FSM for detecting a sequence 1101. I designed a mealy machine.
7.
Why can’t we simply use the above logic to detect 1101. Ans: The one I designed needs 2 flip
flops (4 states) but above design needs 4 flip flops.
8. A real-life problem that you would like to solve. Since my MTP involves a solution related to
diabetes. They were keen to know some more if I have in my mind.
9. Explain restoring divider. I have mentioned this in my course project and hence the question.
They were not only interested in the algorithm but also the logic behind it as why we are
doing so and so.
10.
Find setup time and hold time for above Circuit.
RESULT – Not selected. I was the last one to be interviewed. Though answered 90% of the question
correctly, got positive feedback but they already selected students as per target. Sequence in which
you go for interview matters a lot as some companies keep giving parallel offers while others are still
left to be interviewed and this sequence is pre decided on a criteria not known to me.
Texas Instruments - Digital
1st Dec, 2023
(Technical : 30-40 mins)
1. Very brief discussion on MTP.
2. Design a Counter of your choice. I designed a synchronous binary up counter. [ If they don’t
mention anything, always draw the one with less disadvantages so that you can defend your
answer if they ask next why you chose this. Same applies with mealy and moore, draw the
one that is best suited for your design]
3. Write a Verilog code for the counter designed.
4. What is the difference between Verilog and VHDL.
5. What is FIFO? Find depth of FIFO if read time = x ns, write time = y ns, data burst size = z. I
don’t remember the exact values but if you know FIFO you can solve that, it was easy one, no
tricks involved.
6. Write a Verilog code for Fibonacci series.
RESULT – Not selected though answered each and every question correctly. Out of 24 students
shortlisted, TI didn’t select anyone for digital profile and this happened previous year too.
Micron
1st Dec, 2023
Round 1 (Technical) (20 mins)
Detailed discussion on MTech project.
Round 2 (Technical) (1 hour)
1. Draw a transistor-based D Latch.
2. Explain the working of circuit drawn.
3. What will be the setup time, hold time and propagation delay of the circuit.
4. Write a Verilog code for D latch.
5. Brief discussion on MTech project.
6. Write a test bench for a part of your code in MTech project. My MTP code was in Verilog.
7. Explain Restoring divider. I mentioned this as my course project.
8. Draw a CMOS inverter and its VTC.
9. At which point of VTC, the short circuit current will be maximum.
10. Draw a graph of this short circuit current vs Vin.
11. Draw Vin and Vout waveform for this.
12.
We get a spike at the output waveform. Why it is so? Ans: Associated with parasitic
capacitances.
Round 3 (HR) (10-15 mins)
1. Ready to relocate to Hyderabad or not was the priority one question for him.
2. Discussion about my family.
3. What do you know about Micron?
RESULT – SELECTED!
Preparation Guidance – Digital Profile
1. Verilog lectures by ISG Sir (NPTEL) (Up to lecture 24 is enough if you have time shortage)
2. Digital IC Design by Jankiraman (NPTEL)
3. Physical Design lectures by ISG Sir (NPTEL)
4. DIGI Q Pdf
5. FIFO
6. Clock Domain Crossing
7. STA by Yash Jain available on YouTube
8. ASIC Design Flow
9. Various lectures from Technical Bytes YouTube channel, such as clock frequency divider etc
10. COA
11. Any one programming language
12. Puzzles
13. Few frequently asked codes.
14. Do course work like ADIC, CAD, DVLSI and Nanoelectronics wisely.
15. MTech Project.
Few Tips
1. You can never be 100% prepared but always be prepared with the important topics and
whatever you mention in your CV.
2. Do mention at least one course project.
3. For written tests: Revise your Gate notes. Do previous year’s screening questions (most of
the time its repeated)
4. Always explain your answers during the interview.
5. Stay calm during the placement phase, many ups and downs will be there.
You are enrolled in VLSI at IIT Kharagpur, so the depth of the iceberg is already done, now
only the tip is left.
All the best guys!!
RESHMA BHAGAT