3/1/24 Digital Circuits ECE 212 Lecture 3 CMOS Inverter – Static Characteristics Mohamed Dessouky Integrated Circuits Laboratory Ain Shams University Cairo, Egypt Mohamed.Dessouky@eng.asu.edu.eg Digital Circuits – ECE212 – S24 1 Reminder: NMOS and PMOS Transistors W L +ve VGS +ve VTH + −− −− + L -ve VGS -ve VTH L • nMOS is ON when a +ve voltage is applied between the gate-source. • pMOS is ON when a -ve voltage is applied between the gate-source. M. Dessouky Digital Circuits – ECE212 – S24 2 1 3/1/24 CMOS Inverter Operation + −VDD 0 + pull-up to VDD OFF PMOS _ _ PMOS 0 VDD + NMOS VDD + pull-down to GND 0 _ NMOS OFF _ ππ = VDD, QN ο ON, QP ο OFF, π0 = 0 (pull-down) ππ = 0, QN ο OFF, QP ο ON, π0 = VDD (pull-up) ∴ π0 = πΰ΄₯π Digital Circuits – ECE212 – S24 M. Dessouky 3 Inverter: Cross-Section and Top View V DD SiO2 Insulator p+ p+ n+ V n+ PMOS NMOS Lp=Lmin Ln=Lmin DD M2 PMOS Gates from polysilicon Vin Metal lines Lp Vout Ln for connections M1 Wn=Wp NMOS Inverter top view - Layout M. Dessouky Inverter Schematic Digital Circuits – ECE212 – S24 4 2 3/1/24 Definition: The ο’ ratio • Define ο’= (W L ) p (W L )n (design parameter) • In digital circuits, we often choose minimum transistor lengths for lower transistor resistance and maximum speed Lp Lp = Ln = Lmin ο ο’ = Wp Wn • Is the main designer optimization parameter • Since all transistor parasitic capacitance is proportional to W οCdp ο» ο’Cdn οCgp ο» ο’Cgn Ln Wn=Wp Digital Circuits – ECE212 – S24 M. Dessouky 5 Definition: The r ratio • Define the resistance ratio of identically-sized PMOS and NMOS (ο’ =1) • Remember Req ο» π= π πππ π πππ 3 VDD ο¦ 7 οΆ ο§1 − ο¬VDD ο· 4 I DSAT ο¨ 9 οΈ Lp I DSAT ο΅ W 1L , ο π πΌπ·ππ΄π = ππΆππ₯ π − πππ» 2 2 πΏ π·π· ∴π= π πππ ππ = = mobility ratio ο» 3 to 3.5 π πππ ππ • Therefore, r is a constant, technology parameter • In general: • In order to have π πππ = π πππ, then choose π½ = π M. Dessouky Ln π πππ ππ ππ π = = π πππ ππ ππ π½ Wn=Wp Digital Circuits – ECE212 – S24 6 3 3/1/24 DC Voltage Transfer Characteristics • Static Plot of Vout vs. Vin • Vin varies from 0 to VDD • Input is changed slowly, and output is measured after all transients are settled (DC). • Obtained analytically by equating the nMOS and pMOS transistor currents in different regions of operation. • Solve graphically? High Vout Low Vin Low High Digital Circuits – ECE212 – S24 M. Dessouky 7 Load Line – Resistor load • Find dc bias point: πΌπ· , ππ·π , ππ·πΊπ • Load line equation: ππ·π· = π π· πΌπ· + ππ·π • Solve Graphically. • Output does not reach ground!! vout ππ·π· − π π· πΌπ· VGS ππ· ππ·π· π π· ππ· slope= VDS vin 1 π π· slope= − ππ·π· ππ π π· πΌπ· ππ·π Resistor IV characteristics M. Dessouky πππ’π‘ 1 π π· ππ·π π π· πΌπ· Transistor πΌπ· , ππ·π characteristics Digital Circuits – ECE212 – S24 8 4 3/1/24 Transfer Characteristics – Transistor load • Replace the resistor with a fixed-gate pMOS • Trace πππ’π‘ vs. πππ , or the DC Voltage Transfer Characteristics • πππ = ππΊπ1 and πππ’π‘ = ππ·π1 • Output does not reach ground!! ID Vi4 M1 OFF M2 Lin. M1 Vi4 M2 Vi1 Vi3 Vi3 Vi2 Vo4 Vi2 M1 Sat. M2 Sat. Vi3 Vi2 Vi1 M1 Sat. M2 Lin. Vi1 M1 Lin. M2 Sat. Vi4 VVo2o1 VDDVDS Vo3 Voltage Transfer characteristics Digital Circuits – ECE212 – S24 M. Dessouky 9 Inverter Transfer Characteristics • Connect the PMOS gate to πππ . • Trace πππ’π‘ vs. πππ , or the DC Voltage Transfer Characteristics • πππ = ππΊπ1 = ππ·π· − ππΊπ2 • πππ’π‘ = ππ·π1 Vin1 M2 M1 Vin2 Vin3 Vin4 Vin5 Vin5 Vin1 M1 Sat. M2 Lin. Vin2 Vin4 Vin3 Vin4 Vin5 M. Dessouky Vin3 Vin2 Vin2 Vin1 Vin1 Digital Circuits – ECE212 – S24 M1 Lin. M2 Sat. Vin3 M1 OFF M2 Lin. M1 Sat. M2 Sat. Vin4 M1 Lin. M2 OFF Vin5 Transfer characteristics 10 5 3/1/24 Inverter Switching Voltage • Vinv is the input voltage at which Vin = Vout • Interception with Vout = Vin straight line. • Analytically, equate both currents in sat. 1 ππ ππ πΆππ₯ π − πππ»π 2 2 πΏ πΊππ ππ 1 2 = ππ πΆππ₯ ππΊππ − πππ»π 2 πΏ With ππΊππ = πππ , ππΊππ = πππ − ππ·π· M1 Sat. M2 Lin. M1 Lin. M2 Sat. Vin = Vout Solve for πππ ππ·π· − πππ»π + πππ»π πΤπ½ ππππ£ = π 1 + πΤπ½ π π • At π½ = ππππ = 1, π • • π ππππ£ = ππ·π· 2 π >1 π½ M1 OFF M2 Lin. π =1 π½ M1 Sat. M2 Sat. π <1 π½ M1 Lin. M2 OFF π π At π½ > 1, stronger nMOS, ππππ£ < π·π· 2 π ππ·π· At π½ < 1, stronger pMOS, ππππ£ > 2 Digital Circuits – ECE212 – S24 M. Dessouky 11 Intermediate (Forbidden) Zone 1 • • • • • • 2 πππ» : (inv. 1) min output voltage that is considered HIGH πππΏ : (inv. 1) max output voltage that is considered LOW ππΌπ» : (inv. 2) min HIGH input voltage to guarantee a LOW output (πππΏ ) ππΌπΏ : (inv. 2) max LOW input voltage to guarantee a HIGH output (πππ» ) Defined by unity gain points Inputs between ππΌπΏ and ππΌπ» are said to be in the indeterminate region or forbidden zone and do not represent legal digital logic levels M. Dessouky Digital Circuits – ECE212 – S24 12 6 3/1/24 Noise Margin 1 2 π <1 π½ • Allows you to determine the allowable noise voltage on the input of a gate (inverter 2) so that the output will not be corrupted. • How much noise can be added to the worst-case output of inverter 1 (πππΏ or πππ» ), so that inverter 2 sees a valid worst-case input (ππΌπΏ or ππΌπ» )? • LOW Noise Margin: πππΏ = ππΌπΏ − πππΏ • HIGH Noise Margin: πππ» = πππ» − ππΌπ» π • Note that π½ = 1 maximizes both noise margins at the same time. Why? Digital Circuits – ECE212 – S24 M. Dessouky 13 Power and Energy • Power is drawn from a voltage source attached to the VDD pin(s) of a chip. • Instantaneous Power: • Energy: P(t ) = I (t )V (t ) T E = ο² P(t )dt 0 • Average Power: M. Dessouky T E 1 Pavg = = ο² P(t )dt T T0 Digital Circuits – ECE212 – S24 14 14 7 3/1/24 Power in Circuit Elements • Instantaneous power delivered by a voltage source: PVDD (t ) = I DD (t )VDD • Power dissipated in a resistor: PR ( t ) = VR2 ( t ) = I R2 ( t ) R R • Energy stored in a capacitor: ο₯ ο₯ EC = ο² I ( t )V ( t ) dt = ο² C 0 0 dV V ( t ) dt dt VC = C ο² V ( t )dV = 12 CVC2 0 M. Dessouky Digital Circuits – ECE212 – S24 15 15 Digital Power Dissipation Sources • Ptotal = Pdynamic + Pstatic • Dynamic power: Pdynamic = Pswitching + Pshortcircuit – Switching load capacitances – Short-circuit current during transitions • Static power is consumed even when chip has no transition. – Leakage draws power from nominally OFF devices M. Dessouky Digital Circuits – ECE212 – S24 16 16 8 3/1/24 Charging a Capacitor • When the gate output rises – Energy stored in capacitor is 2 EC = 12 CLVDD – But energy drawn from the supply is ο₯ ο₯ EVDD = ο² I ( t )VDD dt = ο² CL 0 0 dV VDD dt dt VDD 2 = CLVDD ο² dV = CLVDD 0 – Half the energy from VDD is dissipated in the pMOS transistor as heat, other half stored in capacitor • When the gate output falls – Energy in capacitor is dumped to GND – Dissipated as heat in the nMOS transistor M. Dessouky 17 Digital Circuits – ECE212 – S24 17 Switching Power VDD iDD(t) fsw =1/T C πswitching = πΈππ·π· πΆππ·π· 2 = = πΆππ·π· 2 πsw π π • If a gate switched only ο‘% of the time πswitching = πΌπΆππ·π· 2 πsw • ο‘ is defined as the activity factor M. Dessouky Digital Circuits – ECE212 – S24 18 18 9 3/1/24 Short Circuit Power During input transition • When transistors switch, both nMOS and pMOS networks may be momentarily ON at once • Leads to a blip of “short circuit” current. • < 10% of dynamic power if rise/fall times are comparable for input and output • We will generally ignore this component Digital Circuits – ECE212 – S24 M. Dessouky 19 19 Static Power Gate-leakage current sub-threshold current • Static gates during idle time, i.e. no transitions • Pstatic = (Isub + Igate + Ijunct)VDD – Subthreshold leakage – Gate leakage – Junction leakage • Important for large digital systems with high number of gates • Increases with temperature M. Dessouky Digital Circuits – ECE212 – S24 20 10
